FPGA可编程逻辑器件芯片EP4S40G5H40C2N中文规格书

PLLs & Clock Networks
Figure2–32.Regional Clocks
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-regional
clock by driving two regional clock network lines in adjacent quadrants
(one from each quadrant). This allows logic that spans multiple
quadrants to utilize the same low skew clock. The routing of this clock
signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single
quadrant. Internal logic-array routing can also drive a dual-regional
clock. Clock pins and enhanced PLL outputs on the top and bottom can
drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on
the left and right can drive vertical dual-regional clocks, as shown in
Figure2–33. Corner PLLs cannot drive dual-regional clocks.
A compensated delay element on each DQS pin automatically aligns
input DQS synchronization signals with the data window of their
corresponding DQ data signals. The DQS signals drive a local DQS bus in
the top and bottom I/O banks. This DQS bus is an additional resource to
the I/O clocks and is used to clock DQ input registers with the DQS
signal.
The Stratix II device has two phase-shifting reference circuits, one on the
top and one on the bottom of the device. The circuit on the top controls
the compensated delay elements for all DQS pins on the top. The circuit
on the bottom controls the compensated delay elements for all DQS pins
on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock,
which must have the same frequency as the DQS signal. Clock pins
CLK[15..12]p feed the phase circuitry on the top of the device and
clock pins CLK[7..4]p feed the phase circuitry on the bottom of the
device. In addition, PLL clock outputs can also feed the phase-shifting
reference circuits.
Figure 2–56 illustrates the phase-shift reference circuit control of each
DQS delay shift on the top of the device. This same circuit is duplicated
on the bottom of the device.EP2S90484-pin Hybrid FineLine BGA 84
00780-pin FineLine BGA 188
401,020-pin FineLine BGA 3618
841,508-pin FineLine BGA 3618
84EP2S130780-pin FineLine BGA 188
401,020-pin FineLine BGA 3618
841,508-pin FineLine BGA 3618
84EP2S1801,020-pin FineLine BGA 3618
841,508-pin FineLine BGA
361884Notes to Table 2–14:
(1)Check the pin table for each DQS/DQ group in the different modes.
Table 2–14.DQS & DQ Bus Mode Support (Part 2 of 2)
Note (1)Device
Package Number of ×4Groups Number of ×8/×9 Groups Number of ×16/×18 Groups Number of ×32/×36 Groups
f See the Configurin
g Stratix II & Stratix II GX Devices chapter in volume 2
of the Stratix II Device Handbook or the Stratix II GX Device Handbook for
more information about configuration schemes in Stratix II and
Stratix II GX devices.
Device Security Using Configuration Bitstream Encryption
Stratix II FPGAs are the industry’s first FPGAs with the ability to decrypt
a configuration bitstream using the Advanced Encryption Standard
(AES) algorithm. When using the design security feature, a 128-bit
security key is stored in the Stratix II FPGA. To successfully configure a
Stratix II FPGA that has the design security feature enabled, it must be
configured with a configuration file that was encrypted using the same
128-bit security key. The security key can be stored in non-volatile
memory inside the Stratix II device. This non-volatile memory does not
require any external devices, such as a battery back-up, for storage.PPA
MAX II device or microprocessor and flash device v
JTAG Download cable (4)
MAX II device or microprocessor and
flash device Notes for Table 3–5:
(1)
In these modes, the host system must send a DCLK that is 4× the data rate.(2)
The enhanced configuration device decompression feature is available, while the Stratix II decompression feature is not available.(3)
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.(4)The supported download cables include the Altera USB Blaster universal serial bus (USB) port download cable,
MasterBlaster serial/USB communications cable, ByteBlaster II parallel port download cable, and the
ByteBlasterMV parallel port download cable.
Table 3–5.Stratix II Configuration Features (Part 2 of 2)
Configuration
Scheme
Configuration Method Design Security Decompression Remote System Upgrade。