PCM3060资料

BurrĆBrown Products
from Texas
Instruments
FEATURES
APPLICATIONS
DESCRIPTION
PCM3060
SLAS533–MARCH2007 24-BIT,96/192-kHz ASYNCHRONOUS STEREO AUDIO CODEC
–Digital De-Emphasis:32,44.1,48kHz for
DAC
•24-Bit Delta-Sigma ADC and DAC
–Power Down:ADC/DAC Independently •ADC,DAC Asynchronous Operation
–Asynchronous/Synchronous Control for •Stereo ADC:
ADC/DAC Operation
–High Performance:(Typical,48kHz)
•External Reset and Power-Down Pin:–THD+N:–93dB
–ADC/DAC Simultaneously –SNR:99dB
•Audio Interface Mode:
–Dynamic Range:99dB
–ADC/DAC Independent Master/Slave –Sampling Rate:16–96kHz
•Audio Data Format:
–System Clock:256,384,512,768f S
–ADC/DAC Independent –Full Scale Input:3Vp-p
–I2S,Left-Justified,Right-Justified –Antialiasing Filter Included
•Dual Power Supplies:
–1/64Decimation Filter:
–5-V for Analog and3.3-V for Digital –Pass-Band Ripple:±0.05dB
•Package:TSSOP-28
–Stop-Band Attenuation:–65dB
–On-Chip High-Pass Filter:0.91Hz at
f S=48kHz
•DVD-RW
•Stereo DAC:•Digital TV
–High Performance:(Typical,Differential,•Digital Set-Top Box
48kHz)
•Audio-Visual Applications
–THD+N:–94dB
–SNR:105dB
–Dynamic Range:104dB The PCM3060is a low-cost,high-performance,–Sampling Rate:16–192kHz single-chip,24-bit stereo audio codec with
single-ended analog inputs and differential analog –System Clock:128,192,256,384,
outputs.
512,768f S
The stereo24-bit ADC employs a64-times –Differential Voltage Output:8Vp-p
delta-sigma modulator.It supports16–96kHz –Single-Ended Voltage Output:4Vp-p
sampling rates and a16/24-bit digital audio output –Analog Low-Pass Filter Included word on the audio interface.
–4×/8×Oversampling Digital Filter:The stereo24-bit DAC employs a64-or128-times –Pass-Band Ripple:±0.04dB delta-sigma modulator.It supports16–192kHz
sampling rates and a16/24-bit digital audio input –Stop-Band Attenuation:–50dB
word on the audio interface.
–Zero Flags
The PCM3060supports fully independent operation •Flexible Mode Control
of the sampling rate and audio interface for the ADC –3-Wire SPI,2-Wire I2C Compatible Serial and DAC.
Control Interface
Each audio interface supports I2S,left-justified,and –Hardware Control Mode
right-justified formats with16/24-bit words.•Multiple Functions via SPI or I2C Interface:
–Digital Attenuation and Soft Mute for ADC
and DAC
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright©2007,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
DESCRIPTION(CONTINUED)
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
PCM3060
SLAS533–MARCH2007
This integrated circuit can be damaged by ESD.Texas Instruments recommends that all integrated circuits be handled with appropriate precautions.Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure.Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
The PCM3060can be software-controlled through a3-wire SPI-compatible or2-wire I2C-compatible serial interface,which provides access to all functions including digital attenuation,soft mute,de-emphasis etc.
The PCM3060can be also used in hardware mode,which provides three basic functions.
The PCM3060is fabricated using a highly advanced CMOS process and is available in a small28-pin TSSOP package.
The PCM3060is suitable for various sound processing applications for DVD-RW,digital TV,STB,and other AV equipment.
over operating free-air temperature range(unless otherwise noted)(1)
VALUE UNIT
V CC–0.3to6.5 Supply voltage V
V DD–0.3to4 Ground voltage differences AGND1,AGND2,DGND,SGND±0.1V
RST,MS,MC,MD,SCKI1,SCKI2,DIN–0.3to6.5V Digital input voltage BCK1,BCK2,LRCK1,LRCK2,DOUT–0.3to(V DD+0.3V)<4V
ZEROL,ZEROR,MODE–0.3to(V DD+0.3V)<4V Analog input voltage V IN L,V IN R,V COM,V OUT L+,V OUT L–,V OUT R+,V OUT R––0.3to(V CC+0.3V)<6.5V Input current(any pins except supplies)±10mA
T A Ambient temperature under bias–40to125°C
T stg Storage temperature–55to150°C
T J Junction temperature150°C Lead temperature(soldering)260,5s°C Package temperature(IR reflow,peak)260°C (1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
over operating free-air temperature range(unless otherwise noted)
MIN NOM MAX UNIT V CC Analog supply voltage 4.55 5.5V
V DD Digital supply voltage 2.7 3.3 3.6V Digital input interface level TTL compatible
Sampling frequency,LRCK1,LRCK21696/192kHz Digital input clock frequency
System clock frequency,SCKI1,SCKI2 2.04836.864MHz Analog input level3Vpp
AC-coupled5kΩAnalog output load resistance
DC-coupled10kΩAnalog output load capacitance50pF Digital output load capacitance20pF Operating free-air temperature–252585°C
2Submit Documentation Feedback
ELECTRICAL CHARACTERISTICS
PCM3060 SLAS533–MARCH2007
All specifications at T
A =25°C,V
CC
=5V,V
DD
=3.3V,f
S
=48kHz,SCKI1=SCKI2=512f
S
,24-bit data(unless otherwise
noted).
PCM3060PW
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
DIGITAL INPUT/OUTPUT
DATA FORMAT
Audio data interface format I2S,LJ,RJ
Audio data word length16,24Bits
Audio data format MSB-first,2s-complement
Sampling frequency,ADC164896
f S kHz
Sampling frequency,DAC1648192
System clock frequency128,192,256,384,512,768f S 2.04836.864MHz
INPUT LOGIC
V IH(1)2V DD
V IL(1)0.8 Input logic level VDC
V IH(2)(3)2 5.5
V IL(2)(3)0.8
I IH(2)V IN=V DD±10
I IL(2)V IN=0V±10
Input logic currentµA
I IH(1)(3)V IN=V DD65100
I IL(1)(3)V IN=0V±10
OUTPUT LOGIC
V OH(4)I OUT=–4mA 2.8
Output logic level VDC
V OL(4)(5)I OUT=4mA0.5
REFERENCE OUTPUT
V COM output voltage0.5V CC V
V COM output impedance712.518kΩ
Allowable V COM output
±1µA source/sink current
ADC CHARACTERISTICS
Resolution1624Bits
ANALOG INPUT
Full scale input voltage V IN L,V IN R=0dB0.6V CC Vp-p
Center voltage0.5V CC V
Input impedance10kΩ
Antialiasing filter response–3dB300kHz
DC ACCURACY
Gain mismatch,
Full-scale input,V IN L,V IN R±2±8%of FSR channel-to-channel
Gain error Full-scale input,V IN L,V IN R±2±8%of FSR
Bipolar zero error HPF bypass,V IN L,V IN R±0.5±2%of FSR
(1)BCK1,BCK2,LRCK1,LRCK2(in slave mode,Schmitt-trigger input with50-kΩtypical internal pulldown resistor)
(2)SCKI1,SCKI2,DIN,MS/ADR/IFMD,MC/SCL/FMT,MD/SDA/IFMD(Schmitt-trigger input,5-V tolerant).
(3)RST(Schmitt-trigger input with50-kΩtypical internal pulldown resistor,5-V tolerant).
(4)BCK1,BCK2,LRCK1,LRCK2(in master mode),DOUT,ZEROL,ZEROR
(5)MD/SDA/IFMD(in I2C mode,open drain LOW output)
3
Submit Documentation Feedback
PCM3060
SLAS533–MARCH 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data (unless otherwise noted).
PCM3060PW PARAMETER
TEST CONDITIONS
UNIT
MIN
TYP MAX DYNAMIC PERFORMANCE (6)(7)
V IN =–1dB,f S =48kHz –93–85
THD+N
Total harmonic distortion +noise dB V IN =–1dB,f S =96kHz –93
f S =48kHz,A-weighted 9599Dynamic range
dB f S =96kHz,A-weighted 101f S =48kHz,A-weighted 9599SNR Signal-to-noise ratio dB f S =96kHz,A-weighted 101f S =48kHz 9296Channel separation
dB (between L-ch and R-ch)f S =96kHz
98f S 1=48kHz,f S 2=44.1kHz 92
96Crosstalk from DAC
dB
f S 1=96kHz,f S 2=44.1kHz
98
DIGITAL FILTER PERFORMANCE
0.454
Pass band Hz f S
0.583
Stop band Hz
f S
Pass-band ripple <0.454f S ±0.05
dB Stop-band attenuation >0.583f S
–65
dB Group delay time 17.4/f S s 0.019f S HPF frequency response
–3dB Hz
/1000
DAC CHARACTERISTICS
Resolution
16
24
Bits
ANALOG OUTPUT
Single-ended 0.8V CC Output voltage Vp-p Differential 1.6V CC Single-ended 0.5V CC Center voltage V Differential 0.48V CC
AC-coupled 5Load impedance
k ΩDC-coupled 10
f =20kHz
–0.02dB LPF frequency response
f =44kHz –0.07–3dB
300kHz
DC ACCURACY
Gain mismatch,±1±4%of FSR channel-to-channel Gain error ±2±6%of FSR Single-ended
±1±2
Bipolar zero error
%of FSR
Differential (V OUT X+–V OUT X–)
±1
(6)f IN =1kHz,using System Two audio measurement system by Audio Precision,RMS mode with 20-kHz LPF and 400-Hz HPF.(7)
f S =96kHz:SCKI1=SCKI2=256f S ,f S =192kHz:SCKI1=512f S at f S =48kHz and SCKI2=128f S at f S =192kHz.
4
Submit Documentation Feedback
PCM3060 SLAS533–MARCH2007
ELECTRICAL CHARACTERISTICS(continued)
All specifications at T A=25°C,V CC=5V,V DD=3.3V,f S=48kHz,SCKI1=SCKI2=512f S,24-bit data(unless otherwise noted).
PCM3060PW
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX
DYNAMIC PERFORMANCE(SINGLE-ENDED)(8)(9)(10)
V OUT=0dB,f S=48kHz–93–85
THD+N Total harmonic distortion+noise V OUT=0dB,f S=96kHz–94dB
V OUT=0dB,f S=192kHz–94
f S=48kHz,EIAJ,A-weighted99103
Dynamic range f S=96kHz,EIAJ,A-weighted103dB
fS=192kHz,EIAJ,A-weighted103
f S=48kHz,EIAJ,A-weighted100104
SNR Signal-to-noise ratio f S=96kHz,EIAJ,A-weighted104dB
f S=192kHz,EIAJ,A-weighted104
f S=48kHz97101
Channel separation f S=96kHz101dB
f S=192kHz101
f S1=48kHz,f S2=44.1kHz97101
Crosstalk from ADC f S1=48kHz,f S2=88.2kHz101dB
f S1=48kHz,f S2=176.4kHz101
DYNAMIC PERFORMANCE(DIFFERENTIAL)(8)(9)(11)
V OUT=0dB,f S=48kHz–94
THD+N Total harmonic distortion+noise V OUT=0dB,f S=96kHz–95dB
V OUT=0dB,f S=192kHz–95
f S=48kHz,EIAJ,A-weighted104
Dynamic range f S=96kHz,EIAJ,A-weighted104dB
f S=192kHz,EIAJ,A-weighted104
f S=48kHz,EIAJ,A-weighted105
SNR Signal-to-noise ratio f S=96kHz,EIAJ,A-weighted105dB
f S=192kHz,EIAJ,A-weighted105
f S=48kHz103
Channel separation f S=96kHz103dB
f S=192kHz103
f S1=48kHz,f S2=44.1kHz103
Crosstalk from ADC f S1=48kHz,f S2=88.2kHz103dB
f S1=48kHz,f S2=176.4kHz103
DIGITAL FILTER PERFORMANCE SHARP ROLLOFF
0.454
Pass band Hz
f S
0.546
Stop band Hz
f S
Pass-band ripple<0.454f S±0.04dB
Stop-band attenuation>0.546f S–50dB
(8)f S=96kHz:SCKI1=SCKI2=256f S,f S=192kHz:SCKI1=512f S at f S=48kHz and SCKI2=128f S at f S=192kHz.
(9)f OUT=1kHz,using System Two audio measurement system by Audio Precision,RMS mode with20-kHz LPF and400-Hz HPF.
(10)Assumed5-kΩAC-coupled second-order LPF and115-dB or higher-performance buffer.
(11)Assumed10-kΩDC-coupled second-order LPF and115-dB or higher-performance differential to single-ended converter.
5
Submit Documentation Feedback
PCM3060
SLAS533–MARCH 2007
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data (unless otherwise noted).
PCM3060PW PARAMETER
TEST CONDITIONS UNIT
MIN
TYP
MAX DIGITAL FILTER PERFORMANCE
SLOW ROLLOFF
0.308
Pass band Hz f S
Stop band 0.73f S
Hz
Pass-band ripple <0.308f S ±0.5dB Stop-band attenuation
>0.73f S
–35
dB DIGITAL FILTER PERFORMANCE
Group delay time 20/f S s De-emphasis error
±0.1
dB
POWER SUPPLY REQUIREMENTS V CC 4.55 5.5Voltage range
VDC V DD
2.7
3.3 3.6f S =48kHz/ADC,f S =48kHz/DAC 2530
mA f S =96kHz/ADC,f S =96kHz/DAC
25mA f S 1=48kHz/ADC,f S 2=192kHz/DAC 25mA I CC
f S =48kHz/ADC,power down/DAC 12mA Power down/ADC,f S =48kHz/DAC
13mA Full power down
(12)(13)
780µA
Supply current
f S =48kHz/ADC,f S =48kHz/DAC 912mA f S =96kHz/ADC,f S =96kHz/DAC 16mA f S 1=48kHz/ADC,f S 2=192kHz/DAC 13mA I DD
f S =48kHz/ADC,power down/DAC 5mA Power down/ADC,f S =48kHz/DAC 5mA Full power down (12)
150µA
f S =48kHz/ADC,f S =48kHz/DAC 160190
f S =96kHz/ADC,f S =96kHz/DAC 180f S 1=48kHz/ADC,f S 2=192kHz/DAC 170Power dissipation mW
f S =48kHz/ADC,power down/DAC 77Power down/ADC,f S =48kHz/DAC 82Full power down (12)(13)
4.4
TEMPERATURE RANGE
Operation temperature
–25
85
°C θJA
Thermal resistance
105
°C/W
(12)Halt SCKI1,SCKI2,BCK1,BCK2,LRCK1,LRCK2
(13)AC-coupled configuration.If DC-coupled configuration is used,DC current flow to external load is added and it depends on external load
resistance.
6
Submit Documentation Feedback
PIN ASSIGNMENTS
V
MODE
MS/ADR/IFMD
V R
IN
V L
IN
V
CC
AGND1
AGND2
V R+
OUT
V
COM
V R–
OUT
V L+
OUT
SGND
V L–
OUT
RST
PCM3060
PW (TSSOP) PACKAGE
(TOP VIEW)
P0043-03
PCM3060
SLAS533–MARCH2007
7 Submit Documentation Feedback
PCM3060
SLAS533–MARCH 2007
Table 1.TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME PIN AGND123–ADC analog ground AGND222–DAC analog ground
BCK15I/O (1)Audio data bit clock input/output for ADC BCK210I/O (1)Audio data bit clock input/output for DAC DGND 8–Digital ground
DIN 12I (2)Audio data digital input for DAC DOUT 3O Audio data digital output for ADC
LRCK14I/O (1)Audio data left/right clock input/output for ADC LRCK211I/O (1)Audio data left/right clock input/output for DAC
MC/SCL/FMT 1I (2)Mode control,clock for SPI,clock for I 2C,format for H/W mode (5)MD/SDA/DEMP 2I/O (3)Mode control,data for SPI,data for I 2C,de-emphasis for H/W mode
This pin provides four operation modes according to its input connection.Connected directly to V DD :SPI mode.Connected to VDD through 220-k Ωpullup resistor:H/W mode,single-ended MODE 28I
(4)
V OUT X.Connected to DGND through 220-k Ωpulldown resistor:H/W mode,differential V OUT X.Connected directly to DGND :I 2C mode.
MS/ADR/IFMD 27I (2)Mode control,select for SPI with low active,address for I 2C,I/F mode for H/W mode RST 15I
(5)
Reset and power-down control input,active-low SCKI16I (2)System clock input for ADC SCKI29I (2)System clock input for DAC SGND 16–Shield analog ground
V CC 24–ADC,DAC analog power supply,5-V V COM 21–ADC,DAC voltage common decoupling V DD 7–Digital power supply,3.3-V V IN L 25I Analog input to ADC,L-channel V IN R 26I Analog input to ADC,R-channel
V OUT L–19O Analog output from DAC,L-channel –in differential mode,must be open in single-ended mode V OUT L+20O Analog output from DAC,L-channel +in differential mode,L-channel in single-ended mode ZEROL 14O Zero flag,L-channel ZEROR 13O Zero flag,R-channel
V OUT R–17O Analog output from DAC,R-channel –in differential mode,must be open in single-ended mode V OUT R+18
O
Analog output from DAC,R-channel +in differential mode,R-channel in single-ended mode
(1)Schmitt-trigger input/output with 50-k Ωtypical internal pulldown resistor (2)Schmitt-trigger input,5-V tolerant
(3)Schmitt-trigger input,5V tolerant for SPI,H/W mode and Schmitt-trigger input/open drain LOW output,5-V tolerant for I 2C (4)V DD /2biased,quad-state input
(5)
Schmitt-trigger input with 50-k Ωtypical internal pulldown resistor,5-V tolerant
8
Submit Documentation Feedback
V OUT L–V OUT R+
V OUT L+V OUT R–V IN R V IN L
V COM V CC ZEROR SCK2LRCK2
BCK1BCK2SGND AGND2V DD DGND
LRCK1
DOUT DIN
SCK1AGND1MD/SDA/DEMP
MS/ADR/IFMD RST MC/SCL/FMT MODE
ZEROL
B0229-01
PCM3060
SLAS533–MARCH 2007
BLOCK DIAGRAM
9
Submit Documentation Feedback
TYPICAL PERFORMANCE CURVES OF ADC INTERNAL FILTER
DIGITAL FILTER
−160
−140−120−100−80−60−40−200A m p l i t u d e − d
B
G001
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
A m p l i t u d e − d B
G002
ANALOG
FILTER
f − Frequency − kHz
1
10
100
10k
1k
G004
−50
−45−40−35−30−25−20−15−10−50A m p l i t u d e − d B
G003
PCM3060
SLAS533–MARCH 2007
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data,
unless otherwise noted.
DECIMATION FILTER,STOP-BAND CHARACTERISTICS
DECIMATION FILTER,PASS-BAND CHARACTERISTICS
HIGH-PASS FILTER CHARACTERISTICS
ANTIALIASING FILTER CHARACTERISTICS
Figure 4.
10
Submit Documentation Feedback
TYPICAL PERFORMANCE CURVES OF DAC INTERNAL FILTER
DIGITAL FILTER
−160
−140−120−100−80−60−40−200
A m p l i t u d e − d B
Normalized Frequency [×f S ]G005
−0.5
−0.4
−0.3
−0.2
−0.1
0.0
0.1
A m p l i t u d e − d B
G006
ANALOG FILTER
−10
−9−8−7−6−5−4−3
−2−100
2
4
6
8
10
12
14
16
18
20
A m p l i t u d e − d B
f − Frequency − kHz
G007
−50
−40
−30
−20
−10
A m p l i t u d e − d B
SLAS533–MARCH 2007
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data,
unless otherwise noted.
INTERPOLATION FILTER,STOP BAND
INTERPOLATION FILTER,PASS BAND
(SHARP-ROLL OFF)
(SHARP-ROLL OFF)
Figure 5.DE-EMPHASIS FILTER CHARACTERISTICS
(f S =44.1kHz)
LOW-PASS FILTER CHARACTERISTICS
Figure 7.
TYPICAL ADC PERFORMANCE CURVES
−25
025*******
T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − d B
T A − Free-Air Temperature − °C
G009
−25
025*******
D y n a m i c R a n g e a n d S N R − d B
T A − Free-Air Temperature − °C
G010
4.50
4.75
5.00 5.25 5.50
V CC − Supply Voltage − V G011
4.50
4.75
5.00 5.25 5.50
V CC − Supply Voltage − V
G012
SLAS533–MARCH 2007
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data,
unless otherwise noted.
THD+N at –1dB vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
Figure 9.
Figure 10.
THD+N at –1dB vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
Figure 11.Figure 12.
TYPICAL DAC PERFORMANCE CURVES
−25
025*******
T A − Free-Air Temperature − °C G013
T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − d B
−25
025*******
D y n a m i c R a n g e a n d S N R − d B
T A − Free-Air Temperature − °C
G014
4.50
4.75
5.00 5.25 5.50
V CC − Supply Voltage − V G015
4.50
4.75
5.00 5.25 5.50
V CC − Supply Voltage − V
G016
SLAS533–MARCH 2007
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data,
unless otherwise noted.
THD+N vs TEMPERATURE
DYNAMIC RANGE and SNR vs TEMPERATURE
Figure 13.
Figure 14.
THD+N vs SUPPLY VOLTAGE
DYNAMIC RANGE and SNR vs SUPPLY VOLTAGE
Figure 15.Figure 16.
TYPICAL PERFORMANCE CURVES
ADCs OUTPUT SPECTRUM
f − Frequency − kHz
−140
−120−100−80−60−40−2000
5
10
15
20
A m p l i t u d e − d
B
G017
f − Frequency − kHz
−140
−120−100−80−60−40−2000
5
10
15
20
A m p l i t u d e − d
B
G018
DAC OUTPUT SPECTRUM
f − Frequency − kHz
−140
−120−100−80−60−40−2000
5
10
15
20
A m p l i t u d e − d
B
G019
f − Frequency − kHz
−140
−120−100−80−60−40−200
A m p l i t u d e − d B
G020
SLAS533–MARCH 2007
All specifications at T A =25°C,V CC =5V,V DD =3.3V,f S =48kHz,SCKI1=SCKI2=512f S ,24-bit data,
unless otherwise noted.
OUTPUT SPECTRUM (–1dB,N=32768)
OUTPUT SPECTRUM (–60dB,N=32768)
Figure 17.Figure 18.
OUTPUT SPECTRUM (0dB,N=32768)
OUTPUT SPECTRUM (–60dB,N=32768)
Figure 19.Figure 20.
DEVICE DESCRIPTION
ASYNCHRONOUS OPERATION
SYSTEM CLOCK
H
L
T0005-14
System Clock (SCK1, SCK2)
SLAS533–MARCH 2007
The PCM3060supports complete asynchronous operation between the ADC and DAC by receiving two independent system clocks on SCKI1and SCKI2.
Also,the PCM3060supports synchronous operation between ADC and DAC by receiving one common system clock on either SCKI1or SCKI2and controlling the system clock configuration through register 67or 72in serial mode control.
The PCM3060requires two system clocks for operating the ADC and DAC blocks independently,or it requires one common clock for synchronous ADC and DAC operation.
The system clock for the ADC of the PCM3060must be 256,384,512,or 768f S ,where f S is the audio sampling rate for the ADC,16to 96kHz.
The system clock for the DAC of the PCM3060must be 128,192,256,384,512,or 768f S ,where f S is the audio sampling rate for the DAC,16to 192kHz.
Table 2lists the typical system clock frequencies,f SCKI1and f SCKI2for common audio sampling rates,and Figure 21shows the timing requirements for the system clock inputs.
Table 2.System Clock Frequencies for Common Audio Sampling Clock Frequencies
SAMPLING SYSTEM CLOCK FREQUENCY,f SCKI1,f SCKI2[MHz]
FREQUENCY
128f S (1)192f S (1)256f S 384f S 512f S 768f S (kHz)
16 2.048 3.072 4.096 6.1448.19212.28832 4.096 6.1448.19212.28816.38424.57644.1 5.64888.467211.289616.934422.579233.868848 6.1449.21612.28818.43224.57636.86488.211.289616.934422.579233.8688See (2)See (2)9612.28818.43224.57636.864See (2)See (2)176.4(1)22.579233.8688See
(2)
See (2)See (2)See (2)192(1)
24.576
36.864
See (2)
See (2)
See (2)
See (2)
(1)This combination of sampling clock frequency and system clock frequency is supported only for the DAC.(2)
This system clock frequency is not supported for the given sampling clock frequency.
SYMBOL PARAMETERS MIN MAX UNIT t (SCY)System clock cycle time 25ns t w(SCH)System clock high time 0.4t (SCY)ns t w(SCL)
System clock low time 0.4t (SCY)ns
System clock duty cycle
40%
60%
Figure 21.System Clock Input Timing
SLAS533–MARCH2007
POWER-ON RESET AND EXTERNAL RESET SEQUENCE
The PCM3060has both an internal power-on reset circuit and an external reset circuit.The sequences for both resets are shown in the following.
Figure22illustrates the timing of the internal power-on reset.Initialization(reset)is done automatically at the time when V DD exceeds2.2V typical.
Internal reset is released1024SCKIx(x=1,2)after power on if the H/W control mode is selected and RST is kept HIGH;then the PCM3060begins normal operation.If the S/W control mode is selected and RST is kept HIGH,internal reset is released1024SCKIx after the reset of ADPSV and DAPSV through serial control port; then the PCM3060begins normal operation.If RST is kept LOW,internal reset is held and the reset sequence is frozen until RST is changed from LOW to HIGH.V OUT L and V OUT R from the DAC are forced to the V COM(=0.5 V CC)level as V CC rises.If synchronization is maintained among SCKIx,BCKx,and LRCKx,V OUT L and V OUT R go into the fade-in sequence after t DACDLY1=2048/f S from internal reset release.Then V OUT L and V OUT R provide outputs corresponding to DIN after t DACDLY2=1616/f S from the start of fade-in.Similarly,DOUT from the ADC is enabled and goes into the fade-in sequence after t ADCDLY1=2048/f S from internal reset release,and then DOUT provides an output corresponding to V IN L and V IN R after t ADCDLY2=1936/f S from the start of fade-in.If synchronization is not held,the internal reset is not released and operation mode is kept on reset and power-down state.After resynchronization,the DAC begins its fade-in sequence,and the ADC also begins fade-in operation after internal initialization and an initial delay.
Figure23is the timing chart of the external reset.The RST pin initiates external forced reset when RST is held LOW for at least t RST=2048/f S;it resets the device places it in the power-down state,which is the lowest-power dissipation state in the PCM3060.
When RST transitions from HIGH to LOW while SCKIx,BCKx,and LRCKx are synchronized,V OUT L and V OUT R are forced to the V COM(=0.5V CC)level after the fade-out sequence lasting t DACDLY2=1616/f S,and DOUT is forced to ZERO after t ADCDLY2=1936/f S fade-out sequence.After that,the internal reset becomes LOW,the PCM3060resets and enters into the power-down state,finally all registers and memory except mode control registers are reset.To resume into normal operation,changing RST to HIGH again is required,and the sequence shown in Figure22is performed.It is possible to halt SCKIx,BCKx and LRCKx during the power-down state,but all clocks must be resumed prior to starting the power-up sequence.The same fade-in/-out sequence of V OUT L/R and DOUT can be obtained by setting the ADPSV and DAPSV bits through serial mode control port.
POWER-ON RESET AND EXTERNAL RESET SEQUENCE (Continued)
V DD
RST
0.5V CC
DOUT
MODE
SCKIx,BCKx,LRCKx
ADPSV DAPSV
Internal Reset
V L+/–V R+/–
OUT OUT (V =DD V DD 3.3 V typ.)(=2.7 V min)
T0097-02
SLAS533–MARCH 2007
NOTE:Release from the power-save mode is required if the software control mode is selected.
Figure 22.DAC Output and ADC Output for Power-On Reset
V DD
0V
RST
0.5V CC
DOUT
MODE
SCKIx,BCKx,LRCKx
ADPSV DAPSV
Internal Reset
V L+/–V R+/–
OUT OUT (V =DD 3.3 V typ.)
T0098-02
SLAS533–MARCH 2007
(1)
ADPSV and DAPSV control V OUT L/R and DOUT,respectively,with fade-in/out the same as for RST.
Figure 23.DAC Output and ADC Output for External Reset
PCM AUDIO INTERFACE
Audio Interface Mode and Timing
DOUT
0.5V DD
1.4V
1.4V
DIN
1.4V
BCK1/2(Input )
LRCK1/2(Input )
T0247-01
SLAS533–MARCH 2007
The digital audio data can be interfaced in either slave or master mode,and this interface mode is selectable using the serial mode control described in the Mode Control section.
The interface mode is also selectable independently for the ADC and the DAC.DIN is always input to the PCM3060and DOUT is always an output from the PCM3060.Slave mode is the default mode for both the ADC and the DAC.
In slave mode,BCK1/2and LRCK1/2are inputs to the PCM3060,and BCK1/2must be either 64f S or 48f S .DIN is sampled on the rising edge of BCK2,and DOUT is changed on the falling edge of BCK1.The default timing specification is shown in Figure 24.
In master mode,BCK1/2and LRCK1/2are outputs from the PCM3060.BCK1/2and LRCK1/2are generated by the PCM3060from SCKI1/2,and BCK1/2is fixed at 64f S .DIN is sampled on the rising edge of BCK2,and DOUT is changed on the falling edge of BCK1.The detailed timing specification is shown in Figure 25.
SYMBOL DESCRIPTION
MIN TYP MAX UNIT t (BCY)BCK1/2cycle time 75ns t w (BCH)BCK1/2high time 35ns t w
(BCL)
BCK1/2low time
35ns t (LRS)LRCK1/2set-up time to BCK1/2rising edge 10ns t (LRH)LRCK1/2hold time to BCK1/2rising edge 10ns t (DIS)DIN setup time to BCK1/2rising edge 10ns t (DIH)DIN hold time to BCK1/2rising edge 10ns
t (DOD)
DOUT delay time from BCK1/2falling edge
15
70ns
NOTE:Load capacitance of output is 20pF.
Figure 24.Audio Data Interface Timing (Slave Mode:BCK1/2and LRCK1/2Work as Inputs)
DOUT
0.5V DD
0.5V DD
0.5V DD
DIN
1.4V
1.4V
BCK1/2(Output )
SCKI1/2(Input )
LRCK1/2(Output )
T0248-01
Audio Interface Format
SLAS533–MARCH 2007
SYMBOL PARAMETERS MIN TYP MAX UNIT
t (BCY)BCK1/2cycle time 1/64f S t w(BCH)BCK1/2high time 0.4t (BCY)0.5t (BCY)0.6t (BCY)t w(BCL)BCK1/2low time
0.4t (BCY)
0.5t (BCY)
0.6t (BCY)
t (LRD)LRCK1/2delay time from BCK1/2falling edge 030
ns t (DIS)DIN setup time to BCK1/2rising edge 10ns t (DIH)DIN hold time to BCK1/2rising edge 10ns
t (DOD)DOUT delay time from BCK1/2falling edge 030ns t (BCD)
BCK1/2delay time from SCKI1/2rising edge (1)
10
40
ns
NOTE:Load capacitance of output is 20pF.
(1)
This specification applies for SCKI1/2when the frequency is less than 25MHz.
Figure 25.Audio Data Interface Timing (Master Mode:BCK1/2and LRCK1/2work as Outputs)The PCM3060supports the following four interface formats in both slave and master modes,and they are selectable independently for the ADC and DAC using serial mode control.
24-bit I 2S format
24-bit left-justified format 24-bit right-justified format 16-bit right-justified format All formats are provided in MSB-first,2s complement data format.。