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模块化生产加工单元实训

设备故障诊断与维修综合实训项目技术总结目录第一章、任务描述 (3)1. 意义 (3)2. 任务 (4)3. 实施 (5)第二章调研 (5)1. 国内外概况 (5)2. 调研结论 (6)3. 技术参数 (7)第三章、方案设计 (8)1、机械结构方案 (8)2、气动方案 (9)3.2.1 传感器的简介以及分类 (9)3.2.2传感器工作原理及应用 (10)3.2.3 气动部件的选用 (14)3.2.4气动部件的简要分析 (17)3、控制设计 (17)第四章、技术设计 (18)1、气动元件选型 (18)2、电气元件选型 (21)3、重要部件描述 (23)第五章、硬件设计 (24)1、I/O地址表 (24)2、电源 (25)第六章、软件设计 (26)1、顺序功能图 (26)2、PLC程序图................................................................................................. 错误!未定义书签。

第七章、调试 (46)1、测试设计 (46)2、过程 (46)3、故障 (46)第八章、体会 (47)1、存在的问题 (47)2、致谢 (48)第一章、任务描述1.意义模块化生产培训系统(MPS，Modular Production training System)是一种模拟自动化生产加工单元。

它可以大量代替单调往复或高精度的工作，用以满足前沿产品和自动化设备更新的需要。

基于MPS 装置即模块化加工系统，其典型应用就是物料分拣过程，所涉及的内容包括传感器技术，自动控制原理，气动和电气控制，电气安装和机械安装以及PLC人机界面。

一个适合的物料分拣系统可以减轻工人的劳动强度，提高分拣的质量，提高劳动生产率。

通过MPS控制系统的研究与开发，进一步熟悉电子、机械、气动、传感器和PLC等方面的知识，达到了知识巩固与提高的目的，有增强了学生的动手能力。

LP2525规格书

⏅ഇ㘨ᖋড়ᖂ⬉ᄤ᳝䰤݀ৌ -6
LP2525
催ᬜㅔ֓行㒓ϝッᓣᓔ݇⬉⑤᥻ࠊ䲚៤⬉䏃
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UMD-PP99-037 hep-ph9810442 Gaugino Mass without Singlets

October 21, 1998
Gaugino Mass without Singlets
hep-ph/9810442 v2 22 Oct 1998
CERN-TH/98-337 LBNL-42419 UCB-PTH-98/50 UMD-PP99-037 hep-ph/9810442
Gian F. Giudicey, Markus A. Lutyz, Hitoshi Murayama , and Riccardo Rattazziy yTheory Division, CERN Geneva, Switzerland z Department of Physics, University of Maryland College Park, Maryland 20742, USA Department of Physics, University of California Berkeley, California 94720, USA
This work was supported in part by the U.S. Department of Energy under Contracts DE-AC0376SF00098, in part by the National Science Foundation under grants PHY-95-14797 and PHY-9802551, and by the Alfred P. Sloan Foundation.
1 Introduction
Supersymmetry (SUSY) is arguably the most attractive mechanism to stabilize the hierarchy between the fundamental scale (e.g. the Planck scale M 1018 GeV) and the electroweak scale (MW 100 GeV). However, superpartners of the standardmodel particles have not been observed up to energies of order MW , so SUSY must be broken at or above the weak scale. The phenomenology of SUSY depends crucially on the mechanism of SUSY breaking and the way that SUSY breaking is communicated to the observable sector. Communication of SUSY-breaking e ects by supergravity (SUGRA) interactions is in some ways the most attractive scenario. In models of this type, SUSY is broken in a hidden sector and gravitational-strength interactions communicate SUSY breaking to the observable sector. The main advantage of this scenario lies in its theoretical appeal: the key ingredients are either present of necessity (e.g. SUGRA) or very wellmotivated (e.g. hidden sectors are generically present in string theories). The main disadvantage of this scenario is that at present there is no convincing explanation for the degeneracy of squark masses required to avoid large avor-changing neutral current e ects. In the context of string theory and SUGRA models with singlets, there are also cosmological problems related to the existence of uncharged elds with almost at potentials and interactions suppressed by powers of the Planck scale. In order to explain the origin of the SUSY breaking scale (and hence the weak scale) the most attractive scenario is that SUSY is broken dynamically 1, 2, 3]. In recent years, it has been found that this occurs in many asymptotically-free supersymmetric gauge theories. In these models, dimensional transmutation generates the hierarchy between the SUSY breaking scale SUSY and the Planck scale, and the SUSY-breaking masses are of order 2 =M . The most important challenge of SUSY constructing phenomenologically viable models of dynamical SUSY breaking in the hidden sector is generating su ciently large gaugino masses 3, 4]. In models without gauge singlets in the hidden sector, the gaugino mass is conventionally believed to be extremely suppressed, at most of order 3 =M 2 ' 1 keV. There have been a variSUSY ety of solutions discussed in the literature 5, 6, 7], all of which involve gauge singlets with SUSY-breaking VEV's, and require more or less complicated model-building. It is not at all clear whether any of these solutions can work in the context of string theory, where one singlet eld, the dilaton, couples to all gauge kinetic terms. Obtaining realistic gaugino masses in string theory therefore appears to require a large F component for the dilaton (in addition to the usual dilaton stabilization problem),

QM-045 SPC 程序 -L20

SPC程序文件编号：QP-045版次号：第A/0版生效日期：2020-06-20编写部门：质量部文件变更履历表文件名称：SPC程序编号：1 目的本程序是为了了解和改善过程，通过对过程能力的分析/评估，使其成为量化资料，为设计、制造过程的改进提供依据和参考。

2 适用范围本程序适用于本公司顾客要求和需做过程控制(PpK、CpK、)的所有统称3.1 SPC：指统计过程控制。

3.2 CpK ：是稳定过程的能力指数。

它是- -项有关过程的指数，计算时需同时考虑过程数的趋势及该趋势接近于规格界限的程度。

3.3 PpK：一指初期过程的能力指数。

它是一项类似于CpK的指数，但计算时是以新产品的初期过程性能研究所得的数据为基础。

4 职责和权限研发中心负责统计过程控制的监督、管理工作;技术员、操作工或QC/试验员负责统计过程控制的数据搜集和分析。

5 内容作业流程5.1 研发中心、生产部依据《过程控制管理程序》中的内容，对公司所有新的制造过程关键和重要过程建立新产品、通用产品的统计过程控制，并对其进行过程研究，以验证过程能力，为过程控制提供附加的输入，由生产部、品保部和研发中心共同实施和执行。

5.2为确保公司统计过程控制的体系得到有效运作，技术部应按《控制计划管理程序》规定制订和编制统计过程控制体系所需要的过程流程图，其内容包括:测量技术、抽样计划、接收准则、当不能满足接收准则时的反应计划等。

5.3当公司有新的制造过程产生时，技术部依顾客要求、公司对产品和过程特性的重要性来确定生产过程中的关键、重要过程，并将其在相应的控制计划中予以明确规定。

技术开发部对公司所有关键和重要过程确定新产品通用产品的产品/过程特殊特性5.4当公司对所有关键和重要过程确定新产品、通用产品的产品/过程特殊特性后，由技术部根据公司对产品和过程进行统计过程控制执行的能力决定关键、重要过程的管理项目并将其在相应的控制计划中予以明确规定，经副总经理批准后，生产部、品管部门和技术开发部实施并执行5.5当公司决定关键、重要过程的管理项目后，由技术部根据顾客对产品特性的要求并结合公司实际的过程生产能力制定关键、重要过程的管理项目的管理标准，并将其在相应的控制计划、产品图样、检验标准、操作标准中予以明确规定,经总经理或管理者代表审查核准后，由生产部和质量检验部门实施和执行。

How to Order

5 to 40mA
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switch 3-wire type
D-Y59A
28 VDC or less
40mA or less
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24 VDC Relay, PLC IC circuit, Relay, PLC
Refer to applicable auto switch list — Page 182.
PLC: Programmable Logic Controller
20 76
93 117 135 66 37 10 10 10
Hale Waihona Puke 275169 10 19 9 36 10.5 8.5 83
25 82.5 98.5 117.5 135 66.5 37.5 12 13 16
32
51 68.5 10 19 9 42 11.5 9 93
Bore size
HA
J
K
L
MM ML NN OA OB OL
25, 50, 75, 100, 125, 150, 175, 200, 250, 300, 350, 400
12/16
20/25/32/40/50/63
1.5MPa
1.0MPa
0.12MPa
0.1MPa
–10°C to 60°C (With no condensation)
50 to 400mm/s
Bore size
WA
30st or Over 30st and Over 100st and Over 200st and less up to 100st up to 200st up to 300st
Over 300st
12 20 40 110 200 –

MPIA252012-1R5M-LF

f 0.80 Typ.
g 2.50 Typ.
h
h 2.00 Typ.
3.2 Material List
No. 1 2 3 4
Item Core Wire Terminal Electrode Magnetic Glue
Material Metal Enameled Copper Wire Ag/Ni/Sn/Cu Epoxy resin and magnetic powder
适用范围 Scope．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 3 品名构成 Product Identification．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 3 形状、尺寸和材料 Appearance, Dimensions and Material．．．．．．．．．．．．．．．．．．．．．． 3 测试条件 Testing Conditions．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 4 电气特性 Electrical Characteristics And Test Instruments．．．．．．．．．．．．．．．．．．．．．． 4 工作条件 Condition of work．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 4 信赖性试验 Reliability and Test Condition．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 5-6 焊接条件 Recommended Soldering Conditions．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 7-8 包装 Package Information．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．．． 8-9

2520资料

Application Note AN-1062IRPLMB1E - 25W 230VAC Small Size BallastUsing IR2520DBy Cecilia ContentiTable of ContentsPage Overview (1)Features (2)Electrical Characteristics (2)IR2520D Ballast Control IC (2)Circuit Description (3)Miniballast 1 Bill of Materials (4)Functional Description (5)Fault Conditions (6)Open Filaments Protection (7)Low AC Line Protection (8)Miniballast Layout (9)Design Tip: Auto Restart Option (11)Different Procedure to Adapt the Design (12)Small sizes ballasts (often called Matchbox ballasts) are becoming very common in Europe to drive a wide range of lamps with power between 18W and 26W like PLC 18W, PLT 18W, TC-L 18W, TC-L 24W, TC-F18W, TC-F 24W, TC-DEL/TEL 26W, T5 24W, T8 18W, T5C 22W and TR 22W. Limiting the maximum power to 25W the design does not need to conform to THD and PF requirements and this allows saving the PFC stage reducing the components count and maintaining a very small size.Topics CoveredOverview FeaturesElectrical Characteristics IR2520D Ballast Control IC Circuit DescriptionMiniballast Circuit Diagram Functional Description Fault Conditions Miniballast LayoutDesign Tip: AUto-restart Option Design Procedure to adapt the design to different lamp types1. OverviewSmall sizes ballasts (often called Matchbox ballasts) are becoming very common in Europe to drive a wide range of lamps with power between 18W and 26W like PLC 18W, PLT 18W, TC-L 18W, TC-L 24W, TC-F 18W,TC-F 24W, TC-DEL/TEL 26W, T5 24W, T8 18W, T5C 22W and TR 22W. Limiting the maximum power to 25W the design does not need to conform to THD and PF requirements and this allows saving the PFC stage reducing the components count and maintaining a very small size.The MINIBALLAST1 is an electronic ballast for driving 26W compact fluorescent lamps from 220VAC. The circuit provides all of the necessary functions for preheat, ignition and on-state operation of the lamp and also includes the EMI filter and the rectification stage. The ballast size is 36mmx55mm.The circuit is built around the IR2520D Ballast Control IC. The IR2520D provides adjustable preheat time,adjustable run frequency to set the lamp power, high starting frequency for soft start and to avoid lamp flash,fault protection for open filament condition and failure to strike, low AC line protection and auto-restart after line brownout conditions. The IR2520D is a low-cost solution with only 8 pins and allows the componentcount for the complete solution to be reduced down to 19 components.- 25W 230VAC small size ballast using IR2520DByCecilia Contenti 12AN10622. FeaturesProgrammable run frequency Programmable preheat timeOpen filaments and no-lamp protectionFailure to Strike and deactivated-lamp protection Low AC line protection3. Electrical CharacteristicsInput Power: 24W @ 220VACInput Current: 168mArms @ 220VAC Starting Frequency: 100KHz Average Run Frequency: 40KHz Ballast turn-on voltage: 120VAC Ballast turn-off voltage: 70VAC4. IR2520D Ballast Control ICThe IR2520D is intended for driving CFL and TL lamps in CFL or matchbox (small size ballasts)applications. The IR2520D integrates all of the necessary functions for preheat, ignition and on-state operation of the lamp, plus, lamp fault protection and low AC-line protection, together with a complete high and low-side 600V half-bridge driver. The IR2520D has only 8 pins and fits into a standard SOIC8 or DIP8 package. The IR2520D has been designed to overcome the disadvantage of discrete self-oscillating solutions while maintaining low cost.In the CFL market, the self-oscillating bipolar transistor solution is still more popular than a ballast control IC plus FETs solution due to lower cost. This approach is very simple in nature but has disadvantages including:DIAC or additional circuit required for starting,additional free-wheeling diodes required operating frequencies determined by bi-polar tran-sistor storage time and toroid saturation (not easy todesign, very dependent on tolerances in production and difficult to set the frequencies precisely),unreliable “always hot” PTC thermistor used for preheat that often fails in the field,no protection against lamp non-strike or open filaments conditions,no smooth frequency ramping during ignition, capacitive mode operations,high crest factor in the lamp current.These can result in high susceptibility to components and load tolerances and/or catastrophic failure of ballast output stage components and a short lamp life. The IR2520D includes adaptive zero-voltage switching (ZV, adaptive run frequency for zero-volt-age switching), internal crest factor and non-zero voltage switching (ZVS) protection, as well as an in-tegrated bootstrap diode. The heart of this IC is a voltage controlled oscillator (VCO) with externally programmable minimum frequency and a 0-5VDC analog voltage input. One of the biggest advantages of the IR2520 is that it uses the VS pin and the RDSon of the low-side half-bridge MOSFET for over-current protection and to detect non-ZVS conditions. An internal 600V FET connects the VS pin to the VS sens-ing circuitry and allows for the VS pin to be accu-rately measured during the time when pin LO is high, while withstanding the high DC bus voltage during the other portion of the switching cycle when the high-side FET is turned on and VS is at the DC bus potential. This eliminates the need for a high-precision current sensing resistor that is typically used to detect over current. Please refer to the IR2520D datasheet for further information on the IR2520D including electrical parameters, state diagram and complete functional description.As a result of the IR2520 features, the MINIBALLAST1circuit using the IR2520D is a complete matchbox solution that offers better reliability and longer lamp life than self oscillating solutions while reducing component count and ballast size.AN10625. Circuit DescriptionThe schematic for MINIBALLAST1 is shown in figure 5.1. The BOM with the components values is shown in table 5.2.The ballast incorporates a fuse, EMI filter, input recti-fier, bus capacitor, half-bridge, control and output stage. The output stage is the classical resonant circuit consisting of an inductor, LRES, and a capaci-tor, CRES. The circuit is built around the IR2520D Ballast Control IC. The IR2520 provides adjustable preheat time, adjustable run frequency to set the lamp power, high starting frequency (about 2.5 times fmin) to avoid lamp flash, capacitive mode protection for open filament condition and current crest factor protection for failure to strike or no lamp conditions.The AC line input voltage is rectified to provide a bus voltage of approximately 300 volts. The start up resistor, Rsupply (in the reference design we have 2 resistors, Rsupply and Rsupply 2 in series), is sized such that they can supply the micro-power current during under-voltage lockout (UVLO). When VCC exceeds the UVLO+ threshold, the IR2520 begins to oscillate and the charge pump circuit (CSNUB, DCP1 and DCP2) supplies the current to VCC that causes the internal 15.6V zener clamp to regulate.The IR2520 Ballast Control IC controls the frequency of the half-bridge programming the right parameters on the lamp to provide lamp preheat, lamp ignition, running mode, low AC line protection and lamp/ ballast fault protection.Fig. 5.1) MINIBALLAST1 Circuit Diagram34AN1062TABLE 5.2) MINIBALLAST1 Bill Of Materials.Lamp type: Spiral CFL 26W, Line Input Voltage: 190-240 VAC. Note: Different lamp types may require BOM changes.AN10626. Functional DescriptionFigure 6.1 shows the voltage across the lamp and the current in the resonant inductor LRES during Startup, Preheat, Ignition and Run Mode.Fig. 6.1:Voltage across the lamp(yellow waveform) and current in the resonant inductor (green waveform) during Startup, Preheat, Ignition and Run ModeWhen power is turned on, the IR2520D goes into Under Voltage Lockout (UVLO) mode.The UVLO mode is designed to maintain a very low (<200uA) supply current and to guarantee that the IC is fully functional before the high- and low-side out-put drivers are activated. During UVLO, the high- and low-side driver outputs (LO and HO) are both low and pin VCO is pulled down to COM for resetting the starting frequency to the maximum.Once VCC reaches the startup threshold (UVLO+), the IR2520D turns on and the half-bridge FETs startto oscillate. The IC goes into Frequency Sweep Mode.At startup, VCO is 0V and the frequency is very high (about 2.5 times fmin). This minimizes voltage spikes and lamp flash at startup. The frequency ramps down towards the resonant frequency of the high-Q ballast output stage, causing the lamp voltage and lamp current to increase. During this time, the filaments of the lamp are pre-heated to the emission tempera-ture to guarantee a long lamp life. The frequency keeps decreasing until the lamp ignites. If the lamp ignites successfully, the IR2520D enters RUN Mode. If the minimum frequency has been chosen below or very close to the resonant frequency, the IC will work near resonance and will adjust the frequency continuously to maintain ZVS at the half-bridge and to minimize the losses in the FETs. If the minimum frequency has been chosen higher than the reso-nant frequency the IR2520D will work at the mini-mum frequency.Figure 6.2 shows the current across the resonant inductor and the voltage across the lamp filamentsat the startup.Figure 6.2:Voltage across the lamp filaments (yellow) and current in the resonant inductor (green) at the startup.56AN1062Figure 6.3 shows the VS (HB) Voltage, the lamp voltage and the lamp current during Run Mode.Figure 6.3:VS (HB) Voltage (blue), Lamp Voltage (yellow) and the Lamp Current (green) during Run Mode.7. Fault ConditionsIn case of fault conditions such as open filaments,failure to strike, deactivated lamp or no lamp, the IR2520D will go into Fault Mode. In this mode the oscillator is latched off. To reset the IC back to pre-heat mode, VCC must be recycled below and above the UVLO thresholds. Resetting the mains does this.In case of low AC line, the IR2520D will automati-cally increase the frequency to maintain ZVS. In this way, the ballast will work at a lower power during a low AC line condition and will operate at the proper power again when the line increases again.7.1. Failure To Strike/ Deactivated Lamp Protection This protection relies on the crest factor protection together with the non-ZVS circuit of the IR2520D, bothenabled when the voltage in pin VCO reaches 4.6V.In order to detect failure to strike conditions, the IR2520D performs an internal crest factor measure-ment for detecting excessive dangerous currents or inductor saturation that can occur during a lamp non-strike fault condition or deactivated lamp condition.The IR2520D measures the VS pin during the entire on-time of the low-side MOSFET. Should the peak current exceed the average current by a factor of 4during the on-time of LO, the IC will enter Fault Mode and both gate driver outputs will be latched ‘low’.Performing the crest factor measurement provides a relative current measurement that cancels tem-perature and/or tolerance variations of the RDSon of the low-side half-bridge MOSFET and does not need to be programmed differently for different lamp types. During normal operation, the current will increase until the lamp ignites. After lamp ig-nition the current will decrease down to the nomi-nal current. Should a lamp non-strike condition occur where the filaments are intact but the lamp does not ignite, the lamp voltage and output stage current will increase during the ignition ramp until excessive currents occur or the resonant induc-tor saturates. The non-ZVS circuit or the crest factor circuit will detect this condition and the IC willenter Fault Mode and both gate driver outputs will be latched ‘low’. This will prevent damaging of the half-bridge MOSFET s.Fig. 7.1 shows the inductor current and the lamp voltage in case of failure to strike condition together with the VCO pin voltage. At initial turn-on of the bal-last, the frequency will ramp down from fmax, through resonance, to fmin. If the lamp does not ignite, the inductor current will saturate and high-voltages will occur across the lamp as the frequency sweeps through resonance. The voltages and currents in the output stage will decrease as the frequency contin-ues to decrease to the capacitive side of resonance.The voltages and currents will be low but hard-switch-ing will occur (non-ZVS). When the frequency reachesAN1062fmin (VCO > 4.6V), the non-ZVS and crest-factor pro-tection will be activated and the frequency will in-crease again to try and maintain ZVS. The frequency will sweep back through resonance (from the ca-pacitive side) and the crest-factor protection will shut-down the IC on the first event when the inductor satu-rates to a level where the crest factor exceeds 3 (see Fig. 7.1).Fig. 7.2 shows pin LO, pin VS and the current in the resonant inductor during shutdown, with a shorter time scale. The final shortened pulse of LO just be-fore shutdown (Fig. 7.2) occurs due to the internal 1us blank time of the crest-factor detection during each turn-on rising edge of LO (to provide immunityto noise and transients).Fig. 7.1:4 is the current in the resonant inductor, 2 is the lampvoltage, 3 is the voltage in pin VCOFig. 7.2:4 is the current in the resonant inductor, 2 is pin VS (HB Voltage), 3 is pin LO7.2. Open Filaments ProtectionThe open filament protection relies on the non-ZVS circuit of the IR2520D, enabled when pin VCO reaches 4.6V. Should an open filament lamp fault occur, hard-switching will occur at the half-bridge and the non-ZVS circuit inside the IR2520 will detect this condition, increase the frequency each cycle and shut down when VCO decreases below 1V; both gate driver outputs will be latched ‘low’. This will prevent hard-switching and damaging of the half-bridge MOSFET s.Fig. 7.3 shows the pin VCO and pin VS at the shut-down with open filament. As you can see, at startup pin VCO charges from 0V up to 4.6V, at 4.6V the non-ZVS circuit is enabled, CVCO discharges and the frequency increases. When the voltage on pin VCO decreases below 1V we have latched shutdown.78AN1062Fig. 7.4 shows pin VCO and pin VS (HB Voltage) at the shutdown with a shorter time scale. The FMIN pin can be used as trigger as this pin transitions from 5V to COM when the IC enters fault mode orUVLO-.Fig. 7.3:3 is the voltage in pin VCO and 2 is pin VSFig. 7.4:1 is the voltage in pin FMIN, 3 is the voltage in pin VCO,2 is pin VS7.3. Low AC line ProtectionAs you can see from figure 7.5, varying the AC line from 220V to 130VAC the ZVMCS circuit of the IR2520increases automatically the frequency to maintain ZVS.When the mains voltage decreases, the resonant frequency increases, becoming close to the run frequency. This will cause non-ZVS. The IR2520will detect non-ZVS and increase the frequency continuously as long as non-ZVS is detected. This will protect the half-bridge MOSFETs against hard-switching. 9AN1062Figure 7.5:VS PIN for AC line 220V (on the top) and AC line 130V (on the bottom)8. MINIBALLAST LayoutThe Layout of the Reference Kit MINIBALLAST1 is shown in Fig. 8.1.The critical components are CVCC, CVCO, RFMIN and CBOOT. They must be placed as close as possible to the pins of the IR2520D. The ground of CCVO, RFMIN and CVCC need to be connected to pin COM of the IR2520D and this ground pathmust be connected to the power ground at a single point10AN1062Figure 8.1: MINIBALLAST1 Layout 11AN10629. Design Tip: Auto-restart OptionThe design can be modified to include re-lamp/auto-restart option as shown in Fig. 9.1.The resistors Rsupply must be moved across the upper lamp filament and the lamp connected to the bus voltage, instead than to ground. When the lampFig. 9.1: Circuit Modification to include auto-restart optionis replaced, Rsupply together with the upper filament of the lamp provide a path from the DC bus to supply the micro-power current to the IR2520 and to restart the IR2520 as soon as VCC exceeds the UVLO+threshold. Rsupply need to be able to handle high voltage. If using SMD components, 2 resistors are needed.12AN106210. Design Procedure to adapt the design to different lamps typesThe design with the IR2520D is very simple because it only has 2 control pins: VCO (0-5VDC oscillator voltage input) and FMIN (minimum frequency set-ting). To modify the design for a higher lamp power,you will need to modify RFMIN, CVCO, LRES and CRES. Make sure that FET s and inductors are rated to the current you need with the new lamp and that VCC is stable. To modify the design to a lower lamp power, you will need to decrease RFMIN and only in some case to modify also CVCO, LRES and CRES.In most cases you can use FET s and inductors with lower current ratings.Pin FMIN is connected to ground through a resistor (RFMIN). The value of this resistor programs the mini-mum frequency (fmin) of the IC and the starting fre-quency of the IC (2.5xfmin). The IR2520 will work in run mode at the minimum frequency unless non-ZVS is detected. Generally, to work with constant fre-quency, the minimum frequency needs to be chosen above the resonant frequency of the low-Q R-C-L circuit. In this case, one can increase the value of RFMIN to decrease the frequency and increase the lamp power, or, decrease the value of RFMIN to in-crease the run frequency and decrease the lamp power.Pin VCO is connected to ground through a capacitor (CVCO). The value of this capacitor programs the time the frequency needs to ramp down from 2.5times fmin (fmax) to fmin.One can increase the capacitor value to increase the preheat time, or, decrease the capacitor value to de-crease the preheat time.The suggested design procedure is as follows:1)Use the BDA software to calculate LRESand CRES.Select the input configuration without PFC,select the IR2156 IC and select single lamp current mode configuration. Select the new lamp in the database or add the lamp pa rameters by hand selecting the “Advanced”option.Calculate the operating point and chose the right values of L and C that satisfy:1.1)Run frequency (best working range) 40-50KHz 1.2) C as small as possible to minimizelosses (suggested value 4.7nF)1.3)L values you have available2)While measuring LO, apply 15V from pinVCC to pin COM and adjust the value of RFMIN to obtain the right minimum fre-quency (it is suggested set fmin = run fre-quency obtained with the BDA software).Increase RFMIN to decrease the minimum frequency or decrease RFMIN to increase the minimum frequency.3)Apply the AC input and check preheat, igni-tion and run states of the lamp.3.1) If the lamp ignites during preheat, the preheat current is too small or the starting volt age across the lamp is too big, increase the value of CRES to decrease the voltage across the lamp during preheat and startup while increasing the preheat current. LRES may need to be decreased to maintain the same power and the same frequency.3.2) If the IC works at a frequency > fmin, increase CRES or LRES to decrease the reso nant frequency avoiding hard-switching, or,decrease the value of the snubber capaci tor CSNUBBER (a CSNUBBER minimum value of 680pF is suggested to make sure VCC stays above the UVLO-).AN1062 3.3) If VCC drops, increase the value ofCSNUBBER or CVCC4)Adjust the value of RFMIN to have the rightpower on the lamp (increase RFMIN to in-crease power or decrease RFMIN to de-crease power) and the value of CVCO to setthe correct preheat time (increase CVCO toincrease the preheat time and decreaseCVCO to decrease the preheat time).5)Test the ballast over the entire input rangeand make sure that the frequency does notchange dramatically in your working range.Select the value of RSUPPLY to have startupat the correct AC line voltage. Increase thevalue of RSUPPLY to start the IC at higherAC voltages and decrease the value ofRSUPPLY to start the IC at lower AC volt-ages.6)Test your lamp life (number of starts). A gooddesign should guarantee at least 5,000starts. To increase the number of starts, in-crease CRES or the preheat time (CVCO)WORLD HEADQUARTERS:233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105/ Data and specifications subject to change without notice. 3/2/200413。

备件目录 9853 6558 20f Spare Parts Catalogue COP 2560EX

Atlas CopcoSpare Parts CatalogueHydraulic Rock Drills COP 2560EXNo. 9853 6558 20fAtlas Copco Rock Drills AB Örebro, Sweden©Atlas Copco Rock Drills AB, 2009, All rights reservedAtlas Copco Rock Drills AB SE-70191 Örebro, SwedenUse Atlas Copco genuine parts only.Any damage or mailfunction caused by the use of unauthorized parts is not covered by warranty or product liability.This publication refers only to the mentioned product.When ordering spare parts, please state part number (not the ref no) and the quantity.Använd alltid Atlas Copco originaldelar.Skador och driftstörningar orsakade av ej godkända reservdelar täcks ej av garanti och produktsäkerhetsåtaganden.Denna publikation gäller endast för nämnda produkt.Vid beställning av reservdelar, var god ange detaljnummer (ej ref nr) samt antal.© Copyright 2009, Atlas Copco Rock Drills AB, SwedenAny unauthorized use or copying of the contents or any part thereof is prohibited.This applies in particular to trademarks, model denominations, part numbers and drawings.Obehörigt utnyttjande eller kopiering av innehållet eller del därav är förbjudet.Detta gäller speciellt varumärken, modellbeteckningar, reservdelsnummer och ritningar.Table of Content / Innehållsförteckning1. ROCK DRILL / BERGBORRMASKIN (5)2.CROSS REFERENCE LIST (47)34ROCK DRILL / BERGBORRMASKIN LIST OF CONTENTSPart no DetaljnrDescription Benämning See pageSe sidaRemarksAnmärkning –ROCK DRILL BERGBORRMASKIN73115 2900 80– ACCUMULATOR– ACKUMULATOR153115 2700 80– ACCUMULATOR– ACKUMULATOR173115 2615 90– RETURN ACCUM.– RETURACKUMULAT.193115 3473 85– HYDRAULIC MOTOR– HYDRAULMOTOR21MSQ 250 SH3115 3473 86– HYDRAULIC MOTOR– HYDRAULMOTOR23MSQ 315 SH3115 9153 90– O-RING SET– O-RINGSSATS25COP 1638-25603115 9158 90– SEAL KIT– TÄTNINGSSATS273115 9153 90– – O-RING SET– – O-RINGSSATS25COP 1638-25603115 9158 93– SEAL KIT– TÄTNINGSSATS293115 9158 96– OVERHAUL KIT– RENOVERINGSSATS313115 9158 93– – SEAL KIT– – TÄTNINGSSATS293115 9159 94– OVERHAUL KIT– RENOVERINGSSATS333115 9158 90– – SEAL KIT– – TÄTNINGSSATS273115 9153 90– – – O-RING SET– – – O-RINGSSATS25COP 1638-25603115 9159 95– OVERHAUL KIT– RENOVERINGSSATS373115 9159 94– – OVERHAUL KIT– – RENOVERINGSSATS333115 9158 90– – – SEAL KIT– – – TÄTNINGSSATS273115 9153 90– – – – O-RING SET– – – – O-RINGSSATS25COP 1638-2560–– ASSEMBLY TOOL– MONTERINGSVERKT39–– ASSEMBLY TOOL– MONTERINGSVERKT413115 3425 80– – CHARGIN DEVICE– – LADDN.UTRUSTN.43FOR ACCUMULATORS –– ASSEMBLY TOOL– MONTERINGSVERKT455ROCK DRILL / BERGBORRMASKIN68311 1256 01 005DROCK DRILL / BERGBORRMASKIN7(Sheet 1 of 6)Ref no Part no DetaljnrQty AntalDescriptionBenämning See page Se sidaRemarks Anmärkning23115 3456 801CYLINDER COMPL.CYLINDER KOMPL.INCL. POS 3,5-10,11,123–1CYLINDERCYLINDER50259 0311 001THREAD INSERT GÄNGINSATS HELI-COIL M 20X2 X 1,5 D 60259 0011 004THREAD INSERT GÄNGINSATS HELI-COIL M 14 X 1,5 D 70259 2061 003THREAD INSERT GÄNGINSATS HELI-COIL M 16 X 1,5 D 83115 2401 001PLUG RÖRPROPP90686 6447 042PLUGPROPPM 22X1,5 - STEEL 5.8100661 1034 002SEAL WASHER TÄTNINGSBRICKA 22,7 / 30 X 2 TREDO 113115 1165 004STUD PINNSKRUV 123115 2112 001GUIDESTYRNING143115 2972 801SEAL HOUSE COMP TÄTN. HUS KOMPL FRONTINCL.POS 15-1715–1SEAL HOUSING TÄTNINGSHUS 163115 2053 002SEAL KIT TÄTNINGSSATS170663 6136 001O-RINGO-RING59,5 X 3 70 SHORE 193115 2973 001PISTON GUIDE KOLVSTYRNING 213115 3426 001PISTONKOLV243115 2976 801SEAL HOUSE COMP TÄTN. HUS KOMPL REAR 25–1SEAL HOUSING TÄTNINGSHUS 263115 2869 002SEAL KIT TÄTNINGSSATS270663 6135 001O-RINGO-RING54,5 X 3 70 SHORE 293115 3094 001PISTON GUIDE KOLVSTYRNING 313115 1765 001VALVE PISTON VENTILKOLV 323115 2077 031VALVE COVER VENTILGAVEL 333115 2076 051VALVE COVERVENTILGAVEL340147 1438 034SCREW, HEX HEAD SKRUV, SEXKANT M 14 X 30 - 8.8 FZB 353115 3293 001REG. PLUG REGLERPROPP 363115 3214 001NUTBOTTENMUTTER 373115 1697 002SEAL WASHER TÄTNINGSBRICKA GM 1000383115 3245 001SEAL RING TÄTNINGSRING450663 6135 011O-RING O-RING 54,5 X 3 90 SHORE 460663 6135 011O-RINGO-RING54,5 X 3 90 SHOREB0040503ROCK DRILL / BERGBORRMASKIN8470663 2133 011O-RING O-RING 39,2 X 3 90 SHORE 480663 2133 011O-RINGO-RING39,2 X 3 90 SHORE 523115 2583 841INTERM. COMPL.MELLANDEL,KOMPL INCL. POS 53-60,66-72533115 2583 451INTERMED. PART MELLANDEL INCL. POS 54-6054–1INTERMED. PART MELLANDEL550686 6442 001PLUGPROPPG 1/4 TYPE B - STEEL 5.8560661 1020 001SEAL WASHER TÄTNINGSBRICKA 13,7 / 20,6 X 2,1 - FZ ST TREDO 1/4570259 2061 004THREAD INSERT GÄNGINSATS HELI-COIL M 16 X 1,5 D 580259 0068 002THREAD INSERT GÄNGINSATS HELI-COIL M 12 X 1,5 D 593115 1746 061NOZZLE MUNSTYCKE M8X8, D=1,7603115 2401 001PLUG RÖRPROPP 663115 3474 001LINER FODER 673115 2084 001BUSHING BUSSNING680335 3500 101LOCK RING LÅSRING 80 X 3,2 DIN 7993 B 690663 2105 961O-RING O-RING 89,5 X 3 90 SHORE 700663 2104 941O-RING O-RING99,5 X 3 90 SHORE 713115 1746 062NOZZLE MUNSTYCKE M8X8, D=1,7720196 1318 001SET SCREW STOPPSKRUV M 8 X 8 SK6SS DIN 916763115 2384 001VALVE SEAT VENTILSÄTE 773115 2383 001VALVE CONE VENTILKÄGLA780663 2129 011O-RINGO-RING29,2 X 3 90 SHORE 793115 2114 001CONNECT. PLATE ANSLUTN.PLATTA800211 1960 842SCREW SKRUV MC6S M 12 X 35 -12.9810663 2100 622O-RING O-RING24,2 X 3 90 SHORE 823115 2988 002SEAL RING TÄTNINGSRING830663 6143 001O-RING O-RING94,5 X 3 70 SHORE 843115 1879 001SEAL KIT TÄTNINGSSATS 853115 1880 001SEAL KITTÄTNINGSSATS 863115 3441 001DAMPING PISTON DÄMPKOLV870686 9110 001PROTECTION PLUG SKYDDSPROPP 9,3 / 10,9 X 9923115 3483 001BACK HEADBAKSTYCKE(Sheet 2 of 6)Ref no Part no DetaljnrQty AntalDescription BenämningSee page Se sidaRemarks Anmärkning8311 1256 01 005DROCK DRILL / BERGBORRMASKIN9930663 6138 001O-RINGO-RING69,5 X 3 70 SHORE 940147 1481 033SCREW, HEX HEAD SKRUV, SEXKANT M 16 X 60 - 8.8 FZB 953115 2945 001VENTILATOR VENTILATOR 1033115 3434 001GEAR HOUSING VÄXELHUS 1040686 4201 032PLUG PROPP1050653 9038 002GASKETPACKNING10 / 13,5 X 1 -11 4010 141063115 3436 011SEAL RETAINER TÄTNINGSHÅLLARE 1073115 3313 001SEAL KIT TÄTNINGSSATS1080335 2173 001CIRCLIP SPÅRRING SGH 110 X 4 DIN 4721093115 0273 001WASHER BRICKA1100663 6144 001O-RINGO-RING99,5 X 3 70 SHORE 1163115 3432 801ROT.CHUCK,COMPL BORRHYLSA,KOMPL 1173115 3432 001ROT.CHUCK BORRHYLSA 1183115 3433 001BUSHINGBUSSNING1190515 8000 151THR.NEEDLE CARR AX.NÅLRULLKRANS 30 47 34 46 2 16300 700001204090 0203 001THR.NEEDLE CARR AX.NÅLRULLKRANS 35 52 39 51 2 15500 360001210509 0222 001ROLLER BEARING RULLAGER 85 / 130 X 291220509 0121 291ROLLER BEARING RULLAGER 100 140 25 20 1,5 1190001233115 0274 001GEAR WHEELKUGGHJUL1240516 1504 011NEEDLE BEARING NÅLLAGER 22 / 34 X 161253115 0823 001WASHERBRICKA1260516 1538 001NEEDLE BEARING NÅLLAGER 28 / 45 X 171273115 3437 001BEARING SLEEVE LAGERHYLSA1280666 6000 591RADIAL LIP SEAL RADIALTÄTNING 32 44 8 - D 9 0013 3930 91293115 3438 001BEARING SLEEVE LAGERHYLSA 130**** **** 001SHAFT AXEL131**** **** 001DRIVERMEDBRINGARE 132**** **** 001ROT.CH.BUSHING BORRBUSSNING 133**** **** 001SIDE BOLT SIDOBULT134**** **** 002SEAL RING TÄTNINGSRING135**** **** 001O-RING O-RING 56,7 X 3 70 SHORE 136**** **** 002O-RING O-RING 13,3 X 2,4 70 SHORE 1373115 0297 011SHIMSHIMS0,10 MM(Sheet 3 of 6)Ref no Part no DetaljnrQty AntalDescriptionBenämningSee page Se sidaRemarks AnmärkningB0040503ROCK DRILL / BERGBORRMASKIN10138**** **** 021SHIM SHIMS 0,15 MM 139**** **** 031SHIMSHIMS0,5 MM1413115 3435 001EXTENSION PIECE FÖRL.STYCKE INCL. POS 1421420686 3115 221PLUG PROPP D 8 NPTF 1/41430663 6151 001O-RING O-RING134,5 X 3 70 SHORE 1443115 3314 001SEAL KIT TÄTNINGSSATS1453176 6344 001NIPPLENIPPELUNF 3/4 - G 3/81463176 5677 001HOSE ASSEMBLY SLANGLEDNING 10 X 1000 R2AT 1473176 6548 001NIPPLE NIPPEL UNF 3/41483176 6512 001NIPPLENIPPELUNF 3/4 - G 3/81513115 2871 531EXTRACTOR UPPSLAGARE152**** **** 801COVER COMPL.LOCK KOMPL.INCL. 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NIPPLE T-SKARVNIPPEL1103115 3425 801CHARGIN DEVICE LADDN.UTRUSTN.Page43FOR ACCUMULATORS 1203115 1632 001CONTROL MANOM.KONTROLLMANOM.130**** **** 001MANDREL DORN1403091 0455 901EXTRACTOR AVDRAGARE150**** **** 101ASSEMBLY TOOL MONT.VERKTYG REAR DAMPING SEAL 1603115 3374 201ASSEMBLY TOOL MONT.VERKTYG REAR DAMPING SEALB0039310CHARGIN DEVICE / LADDN.UTRUSTN.3115 3425 8042FOR ACCUMULATORSCHARGIN DEVICE / LADDN.UTRUSTN.3115 3425 80Ref no Part noDetaljnrQtyAntalDescription Benämning See pageSe sidaRemarksAnmärkning –1EXPLODED VIEW SPRÄNGBILD9851 2518 011DESCRIPTION BESKRIVNING9852 1797 011INSTRUCTIONS INSTRUKTION13115 3425 011O-RING O-RING FÖR FLASKANSLUTNING23115 3425 021BOTTLE CONNECT FLASKANSLUTNING TO NITROGEN DIN1033115 3425 031HOSE SLANG1/8' L=2000MM43115 3425 041MANOMETER MANOMETER63MM SS 0-400BAR53115 3425 051MANOMETER MANOMETER63MM SS 0-250BAR63115 3425 061MANOMETER MANOMETER63MM SS 0-25BAR73115 3425 071REGULATOR REGULATOR RS200/1 200BAR83115 3425 081NEEDLE VALVE NÅLVENTIL FÖR EVAKUERING93115 3425 091HOSE SLANG COMPLETE WITH CONNECTIONS1/8' L=2500MM103115 3425 101CONNECTION ANSLUTNING TILL MEMBRAN I SS11–1LABEL SET DEKALSATS12–1HOSE SLANG133115 3425 171GASKET PACKNING143115 3425 181SET SCREW STOPPSKRUV153115 3425 191HEX.SOCKET KEY HÅLNYCKEL 6KANT163115 0262 001VALVE VENTIL COMPLETE173310 4076 002CAP HUVFOR ACCUMULATORSASSEMBLY TOOL / MONTERINGSVERKT44ASSEMBLY TOOL / MONTERINGSVERKTRef no Part noDetaljnrQtyAntalDescription Benämning See pageSe sidaRemarksAnmärkning33115 2409 801PRESSING TOOL PRESSVERKTYG 43115 2410 801PRESSING TOOL PRESSVERKTYG 53115 2411 001PRESSING TOOL PRESSVERKTYG 63115 2412 001PRESSING TOOL PRESSVERKTYG 73115 2422 001PRESSING TOOL PRESSVERKTYG 83115 2423 001GUIDE RING STYRRING46CROSS REFERENCE LISTPart no Detaljnr Description RefnoSee pageSe sida0102 0460 00PIN18811 0102 0460 00PIN831 0102 0476 00PIN18911 0147 1328 03SCREW, HEX HEAD2319 0147 1401 03SCREW, HEX HEAD3334 0147 1438 03SCREW, HEX HEAD3434 0147 1438 03SCREW, HEX HEAD347 0147 1481 03SCREW, HEX HEAD2033 0147 1481 03SCREW, HEX HEAD949 0196 1318 00SET SCREW19011 0196 1318 00SET SCREW728 0211 1960 84SCREW1733 0211 1960 84SCREW808 0259 0011 00THREAD INSERT67 0259 0068 00THREAD INSERT588 0259 0311 00THREAD INSERT57 0259 2061 00THREAD INSERT578 0259 2061 00THREAD INSERT77 0291 1128 19LOCK NUT2419 0335 2130 00CIRCLIP24911 0335 2130 00CIRCLIP1833 0335 2173 00CIRCLIP1033 0335 2173 00CIRCLIP1089 0335 2176 00CIRCLIP1333 0335 2176 00CIRCLIP15510 0335 2177 00CIRCLIP231 0335 2177 00CIRCLIP531 0335 2177 00CIRCLIP16610 0335 3500 10LOCK RING16330335 3500 10LOCK RING688 0371 1100 02LIFTING EYE12 0462 7010 34ASSEMBLY TOOL7539 0509 0121 29ROLLER BEARING1133 0509 0121 29ROLLER BEARING1229 0509 0222 00ROLLER BEARING1219 0509 0222 00ROLLER BEARING1233 0515 8000 15THR.NEEDLE CARR1199 0516 1504 01NEEDLE BEARING1433 0516 1504 01NEEDLE BEARING1249 0516 1538 00NEEDLE BEARING1269 0516 1538 00NEEDLE BEARING1533 0653 9038 00GASKET1059 0653 9038 00GASKET1427 0661 1020 00SEAL WASHER568 0661 1026 00SEAL WASHER15610 0661 1034 00SEAL WASHER107 0661 1038 00SEAL WASHER1319 0661 1038 00SEAL WASHER1727 0661 2014 00BACK-UP RING829 0661 2014 00BACK-UP RING18411 0663 2100 54O-RING19511 0663 2100 54O-RING19411 0663 2100 54O-RING19311 0663 2100 54O-RING19611 0663 2100 62O-RING818 0663 2100 62O-RING25 0663 2101 66O-RING17210 0663 2101 66O-RING17010 Part noDetaljnrDescription RefnoSee pageSe sida0663 2101 66O-RING 250663 2101 66O-RING 171100663 2104 94O-RING 250663 2104 94O-RING 7080663 2105 96O-RING 6980663 2105 96O-RING 250663 2109 37O-RING 250663 2110 00O-RING 250663 2110 00O-RING 7150663 2115 00O-RING 250663 2120 00O-RING 13690663 2120 00O-RING 250663 2126 01O-RING 198110663 2128 00O-RING 11270663 2128 00O-RING 250663 2128 00O-RING 9190663 2129 01O-RING 7880663 2129 01O-RING 250663 2133 00O-RING 8270663 2133 01O-RING 4880663 2133 01O-RING 4780663 2133 01O-RING 250663 2134 00O-RING 250663 2143 00O-RING 250663 2144 00O-RING 250663 2145 01O-RING 250663 6121 00O-RING 6150663 6121 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CWP25-CG中文资料

1IXYS reserves the right to change limits, test conditions and dimensions ContentsPage Symbols and Definitions 2Nomenclature2General Information 3A ssembly Instructions4FRED, Rectifier Diode and Thyristor Chips in Planar Design5IGBT ChipsV CESI CG-Series, Low V CE(sat) B2 Types 600 ...1200 V7 ... 20 A 6G-Series, Fast C2 Types600 V 7 ... 20 A 6S-Series, SCSOA Capability, Fast Types 600 V10 ... 20 A 6E-Series, Improved NPT³ technology1200 ... 1700 V20 ... 150 A7MOSFET ChipsV DSSR DS(on)HiPerFET TM Power MOSFET70 ...1200 V 0.005 ... 4.5 Ω8-10PolarHT TM MOSFET, very Low R DS(on)55 ... 300 V 0.015 ... 0.135 Ω11P-Channel Power MOSFET-100 ...-600 V 0.06 ... 1.2 Ω12N-Channel Depletion Mode MOSFET 500 ...1000 V30 ... 110 Ω12Layouts13-17Bipolar ChipsV RRM / V DRMI F(AV)M / I T(AV)M Rectifier Diodes 1200 ... 1800 V 12 ... 416 A 18-19FREDs600 ... 1200 V 8 ... 244 A 20-21Low Leakage FREDs 200 ... 1200 V 9 ... 148 A 22-23SONIC-FRD TM Diodes 600 ... 1800 V 12 ... 150 A 24-25GaAs Schottky Diodes 100 ... 600 V 3.5 ... 25 A 26-27Schottky Diodes8 ... 200 V 28 ... 145 A 28-31Phase Control Thyristors 800 ... 2200 V 15 ... 540 A 32-33Fast Rectifier Diodes1600 ... 1800 V10 ... 26 A34Direct Copper Bonded (DCB), Direct Alu Bonded (DAB) Ceramic SubstratesWhat is DCB/DAB?35DCB Specification362© 2004 IXYS All rights reservedSymbols and DefinitionsC ies Input capacitance of IGBT C iss Input capacitance of MOSFET-di/dt Rate of decrease of forward current I C DC collector current I D Drain currentI FForward current of diodeI F(AV)M Maximum average forward current at specified T h I FSM Peak one cycle surge forward current I GT Gate trigger current I R Reverse currentI RM Maximum peak recovery current I TForward current of thyristorI T(AV)M Maximum average on-state current of a thyristor at specified T hI TSM Maximum surge current of a thyristor R DS(on)Static drain-source on-state resistance R thjc Thermal resistance junction to case r TSlope resistance of a thyristor or diode (for power loss calculations) T case Case temperature T h Heatsink temperaturet fiCurrent fall time with inductive load T j , T (vj)Junction temperatureT jm , T (vj)m Maximum junction temperature t rrReverse recovery time of a diode V CE(sat)Collector-emitter saturation voltage V CES Maximum collector-emitter voltage V DRM Maximum repetitive forward blocking voltage of thyristorV DSS Drain-source break-down voltage V F Forward voltage of diode V R Reverse voltageV RRM Maximum peak reverse voltage of thyristor or diodeV T On-state voltage of thyristorV T0Threshold voltage of thyristors or diodes (for power loss calculation only)Chip and DCB Ceramic Substrates Data book Edition 2004Published by IXYS Semiconductor GmbH Marketing CommunicationsEdisonstraße 15, D-68623 Lampertheim© IXYS Semiconductor GmbH All Rights reserved As far as patents or other rights of third parties are concerned, liability is only assumed for chips and DCB parts per se, not for applications, processes and circuits implemented with components or assemblies. Terms of delivery and the right to change design or specifications are reserved.NomenclatureIGBT and MOSFET DiscreteIXSD 40N60A (Example)IX IXYSDie technology E NPT 3 IGBTF HiPerFETTM Power MOSFETG Fast IGBTS IGBT with SCSOA capability T Standard Power MOSFET D Unassembled chip (die)40Current rating, 40 = 40 A N N-channel type PP-channel type60Voltage class, 60 = 600 Vxx MOSFETA Prime RDS(on) for standard MOSFET Q Low gate charge dieQ2Low gate charge die, 2nd generation P PolarHTTM Power MOSFET L Linear Mode MOSFET IGBT--No letter, low VCE(sat)A Or A2, std speed type B Or B2, high speed typeCOr C2, very high speed type W-CWP 55-12/18(Thyristor Example)WPackage typeC Chip functionC = Silicon phase control thyristor W Unassembled chip PProcess designatorP = Planar passivated chip cathode on top55Current rating value of one chip in A 12/18Voltage class, 12/18 = 1200 up to 1800 VDiode and Thyristor ChipsC-DWEP 69-12(Diode Example)C Package typeD Chip functionD = Silicon rectifier diode W Unassembled chipEPProcess designatorEP = Epitaxial rectifier diodeN = Rectifier diode, cathode on top P = Rectifier diode, anode on topFN = Fast Rectifier diode, cathode on top FP = Fast Rectifier diode, anode on top69Current rating value of one chip in A -12Voltage class, 12 = 1200 V 001947 TS2/765/17557Registration No.:0019473IXYS reserves the right to change limits, test conditions and dimensions General Informations for ChipsWhen mounting Power Semiconductor chips to a header, ceramic substrate or hybrid thick film circuit, the solder system and the chip attach process are very important to the reliability and performance of the final product. This brochure provides several guidelines that describe recommended chip attachment pro-cedures. These methods have been used successfully for many years at IXYS.Available forms of chip packingsIXYS offers various options.Please order from one of the following possibilities:Packaging Options Delivery formC-...*Chips in tray (Waffle Pack);Electrically testedT-...*Chips in wafer, unsawed;Bipolar = 5" (125 mm ∅) wafer;Electrically tested, rejects are inked W-...*Chips in wafer on foil, sawed;Bipolar = 5" (125 mm ∅) wafer;Electrically tested, rejects are inked...* must be amended by the exact chip type designation.Packing, Storage and HandlingChips should be transported in their original containers. All chip transfer to other containers or for assembly should be done only with rubber-tipped vacuum pencils. Contact with human skin (or with a tool that has been touched by hand) leaves an oily residue that may adversely impact subsequent chip attach or reliability.At temperatures below 104°F (40°C), there is no limitation on storage time for chips in sealed original packages. Chips removed from original packages should be assembled immediately. The wetting ability of the contact metallization with solder can be preserved by storage in a clean and dry nitrogen atmosphere.The IGBT and MOSFET Chips are electrostatic discharge (ESD) sensitive. Normal ESD precautions for handling must be observed.Prior to chip attach, all testing and handling of the chips must be done at ESD safe work stations according to DIN IEC 47(CO) 701.Ionized air blowers are recommended for added ESD protection.Contamination of the chips degrades the assembly results.Finger prints, dust or oily deposits on the surface of the chips have to be absolutely avoided.Rough mechanical treatment can cause damage to the chip.Electrical TestsThe electrical properties listed in the data sheet presume correctly assembled chips. Testing ofnon-assembled chips requires the following precautions:-High currents have to be supplied homogeneously to the whole metallized contact area.-Kelvin probes must be used to test voltages at high currents-Applying the full specified blocking or reverse voltage may cause arcing across the glass passivated junction termination, because the electrical field on top of the passivation glass causes ionization of the surrounding air. This phenomenon can be avoided by usinginert fluids or by increasing the pressure of the gas surrounding the chip to values above 30 psig (2 bars).General Rules for AssemblyThe linear thermal expansion coefficient of silicon is very small compared to usual contact metals. If a large area metallized silicon chip is directly soldered to a metal like copper, enormous shear stress is caused by temperature changes (e.g. when cooling down from the solder temperature or by heating during working conditions) which can disrupt the solder mountdown.If it is found that larger chips are cracking during mountdown or in the application, then the use of a low thermal expansion coefficient buffer layer, e.g. tungsten, molybdenum or Trimetal ®, for strain relief should be considered. An alternative solution is to soft-solder these larger chips to DCB ceramic substrates because of their matching thermal expansion coefficients.4© 2004 IXYS All rights reservedMOS/IGBT ChipsRecommended Solder SystemIXYS recommends a soft solder chip attach using a solder composition of 92.5 % Pb, 5 % Sn and 2.5 % Ag. The maximum chip attach temperature is 460°C for MOSFET and 360°C for HiPerFET TM and IGBT.Wire BondingIt is recommended to use wire of diameter not greater than 0.38 mm (0.015") for bonding to the source emitter and gate pads. Multiple wires should be used in place of thicker wire to handle high drain or emitter currents. See tables for number of recommended wire bonds. At smaller gate pads 0.15 mm is recommended.Thermal Response TestingTo assure good chip attach processing, thermal response testing per MIL STD 750, Method 3161 or equivalent should be performed.Bipolar ChipsAssemblingIXYS bipolar semiconductor chips have a soft-solderable, multi-layer metallization (Ti/Ni/Ag) on the bottom side and, on top, either the same metallization scheme or an alumunium layer sufficiently thick for ultrasonic bonding. Note that the last layer of metal for soldering is pure silver.Regardless of their type all chips possess the same glass passivated junction termination system on top of the chip. For that reason they can be easily chip bonded or they can all be simply soldered to a flat contacting electrode in accordance to the General Rules on Page 3. All kinds of the usual soft solders with melting points below 660°F (350°C) can be used thanks to their pure silver top metal.Solders with high melting points are preferable due to their better power cycling capability, i.e. they are more resistant to thermal fatigue.Soldering temperature should not exceed 750°F (400°C). The maximum temperature should not be applied for more than five minutes.As already mentioned above the electrical properties quoted in the data sheets can only be obtained with properly assembled chips.This is only possible when all contact materials to be soldered together are well wetted and the solder is practically free of voids.A simple means to achieve good solder connections is to use a belt furnace running with a process gas containing at least 10 %Hydrogen in Nitrogen.Other approved methods are also allowed, provided that the above mentioned temperature-time-limits are not exceeded and temperature shocks above 930°F/min (500 K/min) are avoided.We do not recommend the use of fluxes for soldering!Ultrasonic Wire BondingChips provided with a thick aluminium layer are designed for ultrasonic wire bonding. Wire diameters up to 500 µm can be used dependent on chip types. Setting wires in parallel and application of stitch bonding lead to surge current ratings comparable to soldered chips.CoatingAlthough the chips are glass passivated, they must be protected against arcing and environmental influences. The coating material that is in contact with the chip surface must have the following properties:- elasticity (to prevent mechanical stress)- high purity, no contamination with alkali metals - good adhesion to metals and glass passivation.Assembly Instructions5IXYS reserves the right to change limits, test conditions and dimensionsFRED, Rectifier Diode and Thyristor Chips in Planar DesignFast Recovery Epitaxial Diodes (FRED)Power switches (IGBT, MOSFET, BJT, GTO) for applications in electronics are only as good as their associated free-wheeling diodes. At increasing switching frequencies, the proper functioning and efficiency of the power switch, aside from conduction losses,is determined by the turn-off behavior of the diode (characterized by Q rr , I RM and t rr - Fig. 1.Rectifier Diode and Thyristor ChipsThe figures 3 a-c show cross sectional views of the diode and thyristor chips in the passivation area. All thyristor and diode chips (DWN, DWFN,CWP) are fabricated using separation diffusion processes so that all junctions terminate on the topside of the chip. Now the entire bottom surfaces of all chips are available for soldering onto a DCB or other ceramic substrate without a molybdenum strain buffer. The elimination of the strain buffer and its solder joint reduces thermal resistance and increases blocking voltage stability. The junction termination areas are passivated with glass, whose thermal expansion coefficient matches that of silicon. All silicon chips increasingly use planar technology with guard rings and channel stoppers to reduce electric fields on the chip surface.The contact areas of the chips have vapor deposited metal layers which contribute substantially to their high power cycle capability. All chips are processed on silicon wafers of 5" diameter and diced after a wafer sample test which auto-matically marks chips not meeting the electrical specification.The chip geometry is square or rectangular.Fig. 3a-cCross sections of Chips in the passivation area a) Diode chip, type DWN, DWFN b) Diode chip, type DWP, DWFP c) Thyristor chip, type CWPThe reverse current character-istic following the peak reverse current I RM is another very im-portant property. The slope of the decaying reverse current di rr /dt results from design para- meters (technology and dif-fusion of the FRED chip Fig. 2. In a circuit this current slope, in conjunction with parasitic induc-tances (e.g. connecting leads, causes over-voltage spikes and high frequency interference vol-tages.The higher the di rr /dt ("hard recovery" or "snap-off" behavior) the higher is the resulting additional stress for both the diode and the paralleled switch. A slow decay of the reverse current ("soft recovery" behavior), is the most desirable characteristic, and this is designed into all FRED. The wide range of available blocking voltages makes it possible to apply these FRED as output rectifiers in switch-mode power supplies (SMPS) as well as protective and free-wheeling diodes for power switches in inverters and welding power supplies.MetalizationFig. 1:Current and voltage during turn-on andturn-offswitching of fast diodesFig. 2:Cross section of glassivated planar epitaxial diode chip with seperation diffusion (type DWEP)Epitaxie Sch ich t n -Sub stra t n+KathodeAnodeGuard ringSubstrate n+Epitaxy layer n-CathodeAnode Glasspassivation p n n +GlasspassivationGuard ring Metalization Fig. 3b)MetalizationChannel-stopperGlasspassivationGuard ring EmitterFig. 3c)Fig. 3a)18© 2004 IXYS All rights reservedRectifier DiodesTypeV RRMVDWN 5800 -DWP 51200DWN 21200 -DWN 91800DWN 17 DWP 17DWN 21DWP 21DWN 35DWP 35DWN 50DWP 50DWN 75DWP 75DWN 110DWP 110DWN 340DWN 1081600 -1Mounted on DCB19© 2004 IXYS All rights reservedDWNDWPRectifier DiodesTypeDWN 5DWP 5DWN 2•DWN 9•DWN 17 •DWP 17•DWN 21•DWP 21•DWN 35•DWP 35•DWN 50•DWP 50DWN 75•DWP 75•DWN 110•DWP 110•DWN 340•DWN 108•s o l d e r a b l e20© 2004 IXYS All rights reserved FRED - F ast R ecovery E pitaxial DiodesTypeV RRMVDWEP 27-02200DWEP 37-02DWEP 77-02DWEP 8-06600DWEP 12-06DWEP 15-06DWEP 23-06DWEP 25-06DWEP 35-06DWEP 55-06DWEP 75-06DWEP 3-101000DWEP 10-10DWEP 18-10DWEP 20-10DWEP 30-10DWEP 50-101 Mounted on DCB21© 2004 IXYS All rights reserved FRED - F ast R ecovery E pitaxial DiodesTypeDWEP 27-02•DWEP 37-02•DWEP 77-02••DWEP 8-06•DWEP 12-06••DWEP 15-06••DWEP 23-06••DWEP 25-06••DWEP 35-06••DWEP 55-06•DWEP 75-06••DWEP 3-10•DWEP 10-10•DWEP 18-10•DWEP 20-10•DWEP 30-10••DWEP 50-10•s o l d e r a b l eb o n d a b l e22© 2004 IXYS All rights reservedLow Leakage Fast Recovery Epitaxial DiodesTypeV RRM VDWLP 4-02200DWLP 15-02DWLP 15-02B DWLP 25-02DWLP 4-03300DWLP 8-03DWLP 15-03DWLP 15-03A DWLP 23-03DWLP 23-03A DWLP 55-03DWLP 75-03DWLP 8-04400DWLP 15-04DWLP 23-04DWLP 55-04DWLP 75-04DWLP 150-04DWLP 4-066001Mounted on DCB23© 2004 IXYS All rights reservedLow Leakage Fast Recovery Epitaxial DiodesTypeDWLP 4-02•DWLP 15-02•DWLP 15-02B •DWLP 25-02•DWLP 4-03•DWLP 8-03•DWLP 15-03•DWLP 15-03A •DWLP 23-03•DWLP 23-03A •DWLP 55-03••DWLP 75-03•DWLP 8-04•DWLP 15-04•DWLP 23-04•DWLP 55-04••DWLP 75-04••DWLP 150-04••DWLP 4-06•s o l d e r a b l eb o n d a b l e24© 2004 IXYS All rights reserved SONIC-FRD TMDiodesTypeV DWHP 8-06 F in design DWHP 15-06 F 600DWHP 23-06 FDWHP 56-06 F DWHP 69-06 F DWHP 150-06 F in design DWHFP 15-12 F 1200DWHFP 23-12 F DWHFP 56-12 F DWHFP 56-12 S DWHFP 69-12 F DWHFP 69-12 S DWHFP 150-12 S DLFP 55-17 S 1700DLFP 68-17 S DLFP 150-17 S DLFP 200-17 S 1Mounted on DCB25© 2004 IXYS All rights reserved SONIC-FRD TMDiodesTypeDWHP 8-06 F DWHP 15-06 F DWHP 23-06 F DWHP 56-06 F DWHP 69-06 F DWHP 150-06 F DWHFP 15-12 F DWHFP 23-12 FDWHFP 56-12 F DWHFP 56-12 SDWHFP 69-12 F DWHFP 69-12 S DWHFP 150-12 S DLFP 55-17 S DLFP 68-17 S DLFP 150-17 S DLFP 200-17 S s o l d e r a b l e26© 2004 IXYS All rights reservedGaAs Schottky DiodesTypeV RRMVDWGS04-01A 100DWGS10-01C DWGS04-018A 180DWGS04-018CDWGS10-018ADWGS10-018C DWGS20-018A DWGS20-018C DWGS04-025A 250DWGS04-025C DWGS10-025A DWGS10-025C DWGS20-025A DWGS20-025C DWGS04-03A 300DWGS04-03C DWGS10-03A27© 2004 IXYS All rights reservedGaAs Schottky DiodesD W GS04-01A D W GS10-01CD W GS04-018A D W GS04-018C D W GS10-018A D W GS10-018C D W GS20-018A D W GS20-018C D W GS04-025A D W GS04-025C D W GS10-025A D W GS10-025C D W GS20-025A D W GS20-025C D W GS04-03A D W GS04-03C D W GS10-03A s o l d e r a b l e28© 2004 IXYS All rights reservedSchottky DiodesTypeV RRMVDWS 39-08D DWS 9-15B 15DWS 19-15B DWS 29-15B DWS 7-30B 30DWS 17-30B DWS 27-30B DWS 37-30B DWS 217-30B DWS 3-45B 45DWS 4-45A DWS 13-45B DWS 14-45A DWS 23-45B DWS 24-45A DWS 33-45B 1Mounted on DCB29© 2004 IXYS All rights reservedSchottky DiodesTypeDWS 39-08D •DWS 9-15B •DWS 19-15B •DWS 29-15B •DWS 7-30B •DWS 17-30B •DWS 27-30B•DWS 37-30B •DWS 217-30B •DWS 3-45B •DWS 4-45A •DWS 13-45B •DWS 14-45A •DWS 23-45B ••DWS 24-45A •DWS 33-45B ••s o l d e r a b l eb o n d a b l e30© 2004 IXYS All rights reservedSchottky DiodesTypeV RRMVDWS 5-60A 60DWS 15-60BDWS 25-60BDWS 35-60B DWS 25-80B 80DWS 36-80A DWS 2-100A 100DWS 12-100A DWS 22-100A DWS 32-100A DWS 1-150A 150DWS 11-150A DWS 21-150A DWS 31-150A DWS 1-180A 1801 Mounted on DCB31© 2004 IXYS All rights reservedSchottky DiodesTypeDWS 5-60A •DWS 15-60B •DWS 25-60B •DWS 35-60B •DWS 25-80B •DWS 36-80A •DWS 2-100A •DWS 12-100A •DWS 22-100A •DWS 32-100A ••DWS 1-150A •DWS 11-150A •DWS 21-150A •DWS 31-150A •DWS 1-180A •s o l d e r a b l eb o n d a b l e32© 2004 IXYS All rights reservedPhase Control ThyristorsTypeV DRM V RRMVCWP 7-CG 800 -CWP 81200CWP 8-CG CWP 35CWP 16-CG 1200 -CWP 21-CG 1600 -CWP 22-CG CWP 24CWP 25-CG CWP 411200 -CWP 501800CWP 55CWP 71CWP 130CWP 180CWP 341CWP 3471Mounted on DCB33© 2004 IXYS All rights reservedPhase Control Thyristors...-CG typesTypeCWP 7-CG ••CWP 8••CWP 8-CG•CWP 35••CWP 16-CG ••CWP 21-CG ••CWP 22-CG ••CWP 24••CWP 25-CG ••CWP 41••CWP 50••CWP 55••CWP 71••CWP 130••CWP 180••CWP 341•CWP 347•s o l d e r a b l eb o n d a b l e34© 2004 IXYS All rights reservedDWFN DWFPFast Rectifier DiodesTypeV RRMVDWFN 2-16/181600 -DWFN 9-16/181800DWFN 17-16/18DWFP 17-16/18DWFN 21-16/18DWFN 35-16/181 Mounted on DCBTypeo l d e r a b l e。

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6P25-P中文资料

0
10
20
30
40
50
60
Ambient Temp. (Deg. C)
NOTE: The ambient temperature is as measured at approx. 1/4” away on the back side of the unit, with the probe end at approx. center (vertical & horizontal). For thermal performance, the unit was mounted on a 4”x4” PCB (with ground plane) & enclosed in a box so that it operates in a controlled environment.
Vin = 5.0V, Vo = 3.3V, Io = 6A, TA = +25°C, Cin = 100μF, Cout = 0.)
Efficiency (%)
Efficiency v/s Ambient Temp.
95.00
92.00
89.00
86.00
83.00
80.00
-40
-30
-20
-10
less than 5%.
Page 2
6-PAK 8/2001 REV F
元器件交易网
Programming
The 6-PAK™ is programmed through the Control SIP. All connected Power Boosters follow the Control SIP programming. To program the 6-PAK™ for Vout<3.3, connect a resistor across the TRIM and Vo pins. For Vout>3.3, resistor is connected across TRIM and GND.

Wang HC,Meng AP,Li JQ,Sima YK2005A karyotypic study on Manglietia (Magnoliaceae) from China

CARYOLOGIA Vol.58,no.2:189-199,2005A Karyotypic Study on Manglietia(Magnoliaceae)from China Heng-Chang Wang1,Ai-Ping Meng1,Jian-Qiang Li1*and Yong-Kang Sima21Department of Taxonomy and Systematics,Wuhan Botanical Garden,the Chinese Academy of Sciences,Wuhan Hubei430074,P.R.China.2Yunnan Laboratory for Conservation of the Rare,Endangered&Endemic Forest Plants,State Forestry Adminis-tration/Yunnan Academy of Forestry,Kunming Yunnan650204,P.R.China.Abstract—Twenty species of Manglietia and one species of Manglietiastrum from China are cytologically investi-gated,of which12are reported for the first time.All the studied species are diploid(2n=38).Chromosomes are me-dium-small to small with gradually decreased sizes.The interphase nucleus and the prophase chromosomes of all species are categorized as the complex chromocenter type and the interstitial type respectively.Karyotype is mainly of2B or in rare condition,2A or1A.The metacentric(m)and submetacentric(sm)chromosomes are found to form the main part of chromosome complement while the subtelocentric(st)chromosomes were rare or absent.It seems that karyotypic variation at the diploid level is the predominant feature of chromosome evolution in Manglietia.Nev-ertheless,karyomorphological differences are disordered and show no significant correlation with the morphological variation and the circumscription of the sampled taxa.Key words:China,karyomorphology,Manglietia,Manglietiastrum.INTRODUCTIONManglietia is a genus of the family Magno-liaceae endemic to Asia.It is mainly distributed in tropical and subtropical Asian regions from the eastern Himalayas to southern China and Malay-sia.Its main center of diversity is in China.Man-glietia is mainly characterized with the number of ovules4-12(-16),while its ally Magnolia with 2(-4).(Dandy1927;1964;1974;1978;Gagnepain 1938;Nooteboom1985;1993;1998;2000;Chen and Nooteboom1993;Law1984;1996;2000). Baillon(1866)thought it would not be natural to divide Manglietia from Magnolia only on the basis of their different numbers of ovules and proposed to include the former in the latter.Praglowski (1974)pointed out the similarity between Mangli-etia and Magnolia Subgen.Magnolia in pollen morphology.Recently,according to three main taxonomical characters,i.e.sylleptic branching, flowers appearing after leaves and anthers in-trorsely dehiscent,Gong et al.(2003)treated Manglietia as a synonym of Magnolia.Another way,Baranova(1972)and Tucker(1977)ob-served unique morphological characteristics of w(1984;1996;2000)and Law et al.(1995)pointed out that Manglietia plants pos-sessed comprehensive morphological characters as well as a special distribution pattern.Whilst disagreeing with the lumper concept of Baillon (1866),Canright(1955)and Keng(1978)on Manglietia,Law appeared to support the pro-posal of Dandy(1927;1964;1974)that Mangli-etia should be treated as a separate genus.Mo-lecular evidences from a number of researchers (Shi2000;Ueda et al.2000;Azuma et al.2000; 2001;Kim et al.2001)have revealed that Mangli-etia is a monophyletic group.Recently,Figlar and Nooteboom(2004)combined molecular and morphological considerations and propose a new taxonomy of Magnolioideae(Magnoliaceae).Ac-cording to the system,Magnolioideae contains only one genus,Magnolia.To account for the vari-ability that resulted in the recognition of several to many genera in the past,Magnolia is subdivided into three subgenera:1.Magnolia with eight sec-tions and seven subsections;2.Yulania with two sections and six subsections;3.Gynopodium with two sections.Thus for Manglietia:Magnolia sub-genus Magnolia section Manglietia.Delimitation of Manglietia has been change-able.Chen and Nooteboom(1993)mainly adopted the outline of Nooteboom(1985).They*Corresponding author:fax++86-027-********;e-mail: lijq@(The author contributes equally to the paper)transferred Manglietiastrum from Magnolia to Manglietia ,and according to them there are 25Manglietia species in the world and 18in w (1996)thought there were over 30species in the world and 22in China,and he recognized Manglietiastrum as a distinct genus (Law 1979;1984;1995;1996;1997;2000).Based on a com-prehensive literature review,Frodin and Gov-aerts (1996)listed 29Manglietia species and five varieties in the world and 22species and three va-rieties in China.In addition,new species are con-tinually published (Wei 1993;Zheng 1995A;Shui and Chen 2003).According to Figlar and Nooteboom (2004),there are about 29species in Magnolia section Manglietia.Though chromosome numbers and shape are just one of a multiple of characters that can be used in the classification of taxa,they sometimes are an important tool in investigations of plant systematics and diversification (Stebbins 1971;Hong 1990;Stace 2000).Manglietia has been cy-tologically studied by a number of researchers (Darlington and Wylie 1955;Fedorov 1974;Okada 1975;Biswas 1979;Biswas and Sharma 1984;Singhal and Gill 1984;Goldblatt 1984;1985;1988;1990;Chen et al.1985;1989;2003;Li et al.1997;Chen et al.2000).All these studies have found a consistent basic chromosome number of x =19throughout Magnoliaceae and that all entities of Manglietia are diploid.How-ever,most of the investigations have only reported chromosome and there is a paucity of data fromkaryotypic studies of the genus,with only eight entities described by Li et al.(1997),Chen et al.(2003)and Meng et al.(2004).Karyotypic evi-dence is often important in infrageneric taxonomy as well as systematics.In this paper the karyotypes of 20species from China,including the indig-enous and cultivated,from temperate to tropical and deciduous to evergreen are described and analyzed aim to (1)provide comprehensive cyto-logical data for further taxonomical study in Man-glietia ;(2)examine its patterns of chromosome variation if present.MATERIALS AND METHODMaterials.-In China,several botanical gar-dens and institutes,including the South China Botanical Garden,the Chinese Academy of Sci-ences (CAS),Kunming Botanical Garden (CAS),Wuhan Botanical Garden (CAS)and Yunnan Academy of Forestry (YAF),have built up their particular conservation bases of Magnoliaceae through introduction and cultivation from the original localities in China and abroad.This has enabled us to carry out the cytological studies of Manglietia to be reported in this paper,which is performed from March to May,2004,under ex-pert guidance of the above botanical gardens and with their careful confirmation to the species of Manglietia (see Acknowledgements).Table 1listsTable 1—Sampling localities,original localities,vouchers of Species of Manglietia .Taxon Sampling Lo.Original Lo.Voucher Taxon Sampling Lo.Original Lo.Voucher M.megaphylla YAF Xichou,Yunnan Meng 019M.yuyuanensis WBG Ruyuan,Guangdong He 001M.rufibarbata KBG Xichou,Yunnan Meng 016M.patungensis Badong,Hubei Badong,HubeiHe 002M.grandis KBG Xichou,Yunnan Meng 006M.forrestii KBG Southwestern Yunnan Meng 003M.crassipes KBG Jinxiu,Guangxi Meng 008M.fordiana YAF Jingdong,Yunnan Meng 030M.moto KBG Beijiang,Guangdong Meng 018M.conifera SCBG Xinyi,Guangdong Wang 035M.chingii KBG Pingbian,Yunnan Meng 004M.glauca KBG Indonesia Meng 014M.aromatica KBG Malipo,Yunnan Meng 020M.ovoidea KBG Maguan,Yunnan Meng 022M.hookeri KBG Jingdong,Yunnan Meng 002M.deciduas KBG Yichun,Jiangxi Meng 033M.duclouxii KBG Yanjin,Yunnan Meng 034M.maguanica YAF Maguan,Yunnan Meng 029M.insignisWBGSouthwest of Hunan He 003Manglietiastrum sinicumKBGXichou,YunnanMeng,010M.pachyphylla SCBGConghua,GuangdongWang 011Notes:KBG =Kunming Botanical Garden;SCBG =South China Botanical Garden;WBG =Wuhan Botanical Garden;YAF =Yunnan Academy of Forestry.190heng-chang,meng,li and simathe information of collection.All the voucher specimens are now deposited in the herbarium of Wuhan Botanical Garden(HIB).Though Figlar and Nooteboom(2004)have changed the names of Manglietia,for the convenient purpose of spe-cific recognition,we still adopt the scientific names listed in the bibliographic checklist of Magnoliaceae by Frodin and Govaerts(1996).Methods.-All chromosome observations are made from shoot apices at mitotic metaphase.The shoot apices are first pretreated in a mixture of saturated aqueous solution of p-Dichlorobenzene and a small amount of bromonaphthalene for2-3 hours;then fixed with Carnoy fluid(1:3glacital acetic acid/absolute alcohol)at about4°C for30 min,macerated in1N HCL at60°C for nine min-utes,stained with1%acetoorcein and then squashed for observation.The authors have made permanent slides of these squashed specimens. Measurements are done in10well-spread met-aphases of not less than five individuals of each species.The cytological classification of the rest-ing and prophase chromosomes follows Tanaka’s categories(1971;1977).The symbols for the de-scription of chromosomes follow Levan et al. (1964).The symmetry of karyotype is classified according to Stebbins(1971).RESULTS AND DISCUSSIONWe present karyotypes of20species of Man-glietia plus one species of Manglietiastrum from China,of which12species are reported here for the first time.Table2gives the chromosome num-bers and summarizes the main karyomorphologi-cal features of these species.The interphase nu-cleus(Plate I,Fig.1)and the prophase chromo-somes(Plate I,Fig.2)of all these species are cat-egorized as the complex chromocenter type and the interstitial type,respectively.The selected photographs of the chromosome morphology at metaphase are illustrated in plate I-II,Figs.3-21 and the karyotypic idiograms in plate III-IV, Figs.1-21.They confirm that all species are dip-loid with2n=38.From the results in Table2,the following observations may be made:1)the chro-mosome shape and size of each species are differ-ent each other but generally consistent among in-dividuals from different populations;2)the chro-mosomes are not longer than5µm in absolute length and can be generally classed into the cat-egory of medium-small to small chromosome ac-cording to Lima-De-faria(1949).In the chromo-some complements chromosomes change their size gradually;3)the ratio of the longest to the shortest chromosome length ranges from1.72(M. conifera)to2.50(M.rufibarbata),but most of the data are near around2.00,a breakpoint to classify whether karyotype is A-type or B-type;4)karyo-type asymmetry is mainly of2B or in rare condi-tion,2A or1A;5)the metacentric(m)and sub-metacentric(sm)chromosomes appear to form the main part of chromosome complement while the subtelocentric(st)chromosomes are rare or absent.Karyomorphological differences within Manglietia are therefore exhibited in some de-tailed parameters including karyotypic formula, number of m,sm and st chromosomes,ratio of the longest to the shortest chromosome length,pres-ence or absence of satellites and so on.Although it is common that in some taxa karyotypes of metaphase chromosomes are di-verse in different populations or even in different individuals,at present investigation,karyotype ofTable2—Comparison of karyotype characteristics of20species of Manglietia Bl.Plus one species of Manglietias-trum Law from ChinaTaxon KF(2n=38)L/S NC KA Taxon KF(2n=38)L/S NC KAM.megaphylla30m+8sm 2.1232B M.yuyuanensis32m+2m*+4sm 2.0522B M.rufibarbata22m+14sm+2sm* 2.5032B M.patungensis32m+2m*+4sm 2.1512B M.grandis20m+16sm+2sm* 2.0052B M.forrestii18m+20sm 2.0422B M.crassipes22m+16sm 2.0422B M.fordiana16m+22sm 2.2372B M.moto26m+12sm 1.9532A M.conifera34m+4sm 1.7201A M.chingii22m+14sm+2st 1.9662A M.glauca22m+10sm+6st 2.1762B M.aromatica16m+22sm 2.1272B M.ovoidea20m+16sm+2sm* 1.9562A M.hookeri34m+4sm 2.1022B M.deciduas16m+22sm 2.1152B M.duclouxii20m+18sm 2.1842B M.maguanica28m+10sm 1.8322AM.insignis32m+4sm+2sm* 2.4912B Manglietias-trum sinicum12m+26sm 1.972A M.pachyphylla26m+12sm 1.8532ANotes:*=chromosome with satellite,L/S=ratio of the longest chromosome to the shortest,NC=number of chromosomes with arm ratio2,KA=karyotype asymmetry.a karyotypic study on manglietia(magnoliaceae)from china191Plate I.Fig.1—Interphase of Manglietia glauca representing the similar interphase nuclei pattern in Manglietia and Manglietiastrum ;Fig.2.Prophase of M.glauca representing the similar prophase nuclei pattern in Manglietia and Manglietiastrum ;Figs.3-12.Metaphase nuclei of ten Manglietia species.Fig.3.M.megaphylla ;Fig.4.M.grandis ;Fig.5.M.crassipes ;Fig.6.M.rufibarbata ;Fig.7.M.moto ;Fig.8.M.aromatica ;Fig.9.M.chingii ;Fig.10.M.hookeri ;Fig.11.M.duclouxii ;Fig.12.M.yuyuanensis .Scale bar =5µm.192heng-chang,meng,li and simaPlate II.Figs.13-22—Metaphase nuclei of ten Manglietia species.Fig.13.M.pachyphylla ;Fig.14.M.patungensis ;Fig.15.M.insignis ;Fig.16.M.forrestii .Fig.17.M.fordiana ;Fig.18.M.conifera ;Fig.19.M.glauca ;Fig.20.M.ovoi-dea ;Fig.21.M.decidua ;Fig.22.M.maguanica ;Fig.23.Manglietiastrum sinicum.Scale bar =5µm.a karyotypic study on manglietia (magnoliaceae)from china 193Plate III.Figs.1-11—Karyomorphology of eleven Manglietia species .Fig.1.M.megaphylla ;Fig.2.M.rufibarbata ;Fig.3.M.grandis ;Fig.4.M.crassipes ;Fig.5.M.moto ;Fig.6.M.chingii ;Fig.7.M.aromatica ;Fig.8.M.hookeri ;Fig.9.M.duclouxii ;Fig.10.M.patungensis;Fig.11.M.pachyphylla .Scale bar =5µm.194heng-chang,meng,li and simaeach Manglietia species is relatively stable among individuals/populations.We have observed not less than five individuals of two to four popula-tions for all the analyzed species.There are only slight chromosomal parameters variation oc-curred between individuals,which does not change the karyomorphology or karyotypic for-mula of them.The main karyotypic differences exist in interspecific rather than in infraspecific level.This seems to imply that in natural condi-Plate IV.Figs.12-21.Karyomorphology of nine Manglietia species.Fig.12.M.insignis ;Fig.13.M.yuyuanensis .Fig.14.M.forrestii .Fig.15.M.fordiana ;Fig.16.M.conifera ;Fig.17.M.glauca ;Fig.18.M.ovoidea ;Fig.19.M.decidua ;Fig.20.M.maguanica .Fig.21.Manglietiastrum sinicum.Scale bar =5µm.a karyotypic study on manglietia (magnoliaceae)from china 195tion species differentiation of Manglietia group has long been evolved and hybridization or recip-rocal chromosome translocation occurred few fre-quently.We have noticed that the sampled Man-glietia species can be distinguished by some minor but comprehensive morphological characters ei-ther in field or in cultivated locality.It seems that like Stebbins(1971)pointed out a minute chro-mosome structural change produced obvious morphological divergence.Despite Manglietia’s placement in various ranks(Dandy1927;1964; 1974;1978;Gagnepain1938;Nooteboom1985; 2000;Chen and Nooteboom1993;Law1996; 2000;Figlar and Nooteboom2004),we think that people should be more cautious in species treatment within the group.It is difficult to discuss the phylogenetic rela-tionship within Manglietia based on cytological evidence.Though diverse karyomorphological characters occurred among the observed species, and according to the traditional cytotaxonomical standard of Stebbins(1971),species that has high chromosomal asymmetry is in general more ad-vanced,it is not safe to indicate any possible evo-lutionary line in Manglietia.For example,M.de-cidua is the sole completely deciduous species, which is restricted in Yichun County,Jiangxi Province of China.In Manglietia the species is dis-tributed mostly northward(27°83t-28°5t N, 113°54t-114°37t E)(Yu1994).Deciduous seems to be an advanced character that adapted to the se-vere cold environment comparing to the ever-green.Some authors also divided Manglietia into two sections(TieŸp1980;Zheng1995B).Never-theless,the karyotype of M.decidua belongs to the relatively primitive2A type.In general karyomor-phological differences(see Table2)are disor-dered and show no significant correlation with the morphological variation and the circumscription of these taxa.Inferred from ndh F sequences,Kim et al.(2001)indicated Manglietia(they selected12 species)to form a well-supported monophylum. However,within the Manglietia clade,bootstrap values are weak,which implies that phylogenetic relationship within the group is still uncertain and need to be elucidated further.Previous reports and the present study indi-cate that all Manglietia members are diploid, while in Magnolia,in addition to diploidy,there exist triploidy,tetraploidy,pentaploidy and hexa-ploidy(Yashui1937;Jankai-ammal1952; Biswas1979;Biswas and Sharma1984;Chen et al.1985;1989;Chen et al.1989;Wu1995;Li et al.1998;Zhang et al.2002;Li and He2003)(see Table3).This seems to imply that chromosome variation at various ploidy levels occurred fre-quently in Magnolia.While in Manglietia,as ana-lyzed above,the intrachromosomal variation rep-resents a major evolutionary line at the diploid level.Magnolia has a more broad distribution pat-tern and morphological divergence range than Manglietia and is usually recognized as polyphyletic(Shi2000;Azuma et al.2000;2001; Kim et al.2001;Li and Conran2003).Obviously,Table3—List of previously published polyploid species in Magnolia(FRODIN and GOVERTS,1996)and Parak-meria(Law,1996).Species Chromosome ReferencesM.acuminata(L.)L76JANAKI AMMAL1952M.acuminata var.subcordata(Spach)Dandy76JANAKI AMMAL1952M.biondii Pamp.76CHEN et al.1985M.campbellii Hook.f.et Thoms.114JANAKI AMMAL1952;CHEN et al.1985Magnolia cylindrical E.H.Wilson76WU1995M.dawsoniana Rehder&E.H.Wilson114JANAKI AMMAL1952M.denudata Desr.114YASUI1937;JANAKI AMMAL1952;CHEN et al.1989;LIand HE2003M.denudata Desr.76CHEN et al.1985;LI et al.1998aM.grandiflora Desr.114JANAKI AMMAL1952;BISWAS1979;BISWAS andSHARMA1984;CHEN et al.1985;LI et al.1998M.liliiflora Desr.76JANAKI AMMAL1952;BISWAS1979;CHEN et al.1985;LI et al.1998M.sargentiana Rehder&E.H.Wilson114JANAKI AMMAL1952;CHEN et al.1985M.schiedeana Schltl.114JANAKI AMMAL1952M.sprengeri Pamp.114JANAKI AMMAL1952;M.×soulangeana Soul.-Bod.76CHEN et al.1989Parakmeria lotungensis(Chun et C.Tsoong)Law114CHEN et al.1985;ZHANG et al.2002P.omeiensis Cheng76CHEN et al.1985P.yunnanensis Hu114CHEN et al.1989Notes:Parakmeria=Magnolia section Gynopodium Dandy(NOOTEBOOM1985;FIGLAR and NOOTEBOOM2004)196heng-chang,meng,li and simasome infrageneric re-identification within Magno-lia is necessary.However,in light of contribution of cytological evidence to the existing taxonomy, it is not logical to place Manglietia in the present hierarchical scheme(Law,1996;etc),especially out of context with the rest of the family,because there are some similarities between the cytological character of Manglietia and other genera of Mag-noliaceae(Li et al.1997;1998A;1998B;1998C; Chen et al.2003).We think the recent new sys-tem of Figlar and Nooteboom(2004)on Mag-nolioideae is no doubt generally reasonable but will face a process of test and acceptance by other workers.Additionally Manglietiastrum sinicum(Law 1979)has been observed this time.Nooteboom (1985)reduced the taxon to Magnolia and Chen and Nooteboom(1993)transferred it to Mangli-etia.Manglietiastrum can be distinguished from Manglietia morphologically.They thought this could warrant its status as a section of Manglietia. Some recent morphological cladistic analyses(Xu et al.2000;Li and Conran2003)and molecular phylogenetic evidences(Shi et al.2000;Kim et al. 2001)seem to indicate that Manglietiastrum is as-sociated with Parakmeria(=Magnolia section Gy-nopodium Dandy(Nooteboom1985;Figlar and Nooteboom2004))and Pachylarnax.Through a systematical observation of the prefoliation fea-tures in Magnoliaceae.Sima et al.(2001)found prefoliation of the whole family could be classi-fied into three types:Magnolia-type,Pachylarnax-type and Liriodendron-type.All the Manglietia be-long to Magnolia-type,and three genera,Pachyly-larnax,Manglietiastrum and Parakmeria belong to the Pachylarnax-type.Figlar and Nooteboom (2004)reduce Pachylarnax and Manglietiastrum to Magnolia subgenus Gynopodium section Man-glietiastrum.Although the chromosome param-eters of Manglietiastrum sinicum fall to the ranges of those of the whole Manglietia,the resolution of the cytological disposition of Manglietiastrum is rather poor cytologically.At this stage of a detailed investigation of karyomorphology of Manglietia it is neither possi-ble nor realistic to attempt to suggest satisfactory relationship either within the group or with other genera.In many cases it would seem that there is a complex reticulation of‘advanced’and‘primitive’cytological characters in Magnoliaceae and karyo-morphology alone cannot really be considered to contribute any single linear trend in the systematic relationship of Manglietia as a whole.Eventually, to try and determine relationship,with other Mag-nolious members even with other families,it will be necessary to compare and integrate the results of this investigation with the large amount of data collected by other workers.Acknowledgements—We wish to thank Gong Xun,Yue Zhong-shu of Kunming Botanical Garden, Xia Nian-he of South China Botanical Garden,Zhang Bing-kun of Wuhan Botanical Garden for providing plant materials for cytological studies;Gu Zhi-jian of Kunming Institute of Botany for experiment guidance. We are also great grateful to the anonymous referee. This study was financially supported by grants from the Chinese Academy of Sciences(KSCX2-SW-104),the State Key Basic Research and Development Plan of P. R.China(G2000046806),and the Wuhan Botanical Garden,CAS(01035108,01035123).REFERENCESAzuma H.,Thien L.B.and Kawano S.,2000—Mo-lecular phylogeny of Magnolia based on chloroplast DNA sequence data(trnK intron,psbA-trnH and atpB-rbcL intergenic space regions)and floral scent chemistry.In:w et al.(eds.),“Proceedings of the International Symposium of the family Mag-noliaceae”Pp.205-209.Science Press,Beijing. Azuma H.,Garcia-franco J.G.,Rico-gray V.and Th-ien L.B.,2001—Molecular phylogeny of the Mag-noliaceae:the biogeography of tropical and temperate disjunctions.Amer.J.Bot.88(12):2275-2285. Baillon H.E.,1866—Me´moire sur la Famille des Mag-noliace´es.Adansonia7:66.Baranova M.,1972—Systematic anatomy of the epi-dermis in the Magnoliaceae and some related fami-lies.Taxon21(4):447-469.Biswas B.K.,1979—Chromosome studies in the family Magnoliaceae.Proc.Indian Sci.Congr.Assoc.(III,C)66:77.Biswas B.K.and Sharma A.K.,1984—Chromosome studies in the family Magnoliaceae.Cytologia49: 193-200.Canright J.E.,1955—The comparative morphology and relationships of the Magnoliaceae.IV wood and nodal anatomy.J.Arn.Arb.36:119-140.Chen B.L.and Nooteboom H.P.,1993—Notes on Magnoliaceae III:the Magnoliaceae of China.Ann.Missouri Bot.Gard.80:1030-1051.Chen R.Y.,Chen Z.G.,Li X.L.and Song W.Q.,1985—Chromosome numbers of some species in the fam-ily Magnoliaceae in China.Acta Phytotax.Sin.23(2):103-105.Chen R.Y.,Zhang W.and Wu Q.A.,1989—Chromo-some numbers of some species in the family Magno-liaceae in Yunnan of China.Acta Bot.Yunnan.11: 234-238.Chen R.Y.,Song W.Q.,Li X.L.,Li M.X.,Liang G.L., An Z.P.,Chen C.B.,Qi Z.X.and Sun Y.Z.(eds.), 2003—Chromosome atlas of major economic plantsa karyotypic study on manglietia(magnoliaceae)from china197genome in China.Tomus III:395-406.Science Press,Beijing.Chen Z.Y.,Huang X.X.and Wang R.J.,2000—Chro-mosome data of Magnoliaceae.In:w et al.(eds.),“Proceedings of the International Sympo-sium of the family Magnoliaceae”Pp.192-201.Sci-ence Press,Beijing.Chen Z.Y.,Law Y.W.,Chen S.J.and Huang S.F., 1989—The chromosome numbers of Magnoliaceae.Acta Bot.Austro Sin.4:67-74(in Chinese).Dandy J.E.,1927—The genera of Magnoliaceae.Kew Bull.257-263.Dandy J.E.,1964—Magnoliaceae.In:J.Hutchinson (ed.),“The Genera of Flowering Plants”I:50-57.Clarendon,Oxford.Dandy J.E.,1974—Magnoliaceae.In:J.Praglowski (ed.),“World pollen spore flora”,vol.3:1-5.Almqvist and Wiksell press,Stockholm.Dandy J.E.,1978—Revised survey of the genus Magno-lia together with Manglietia and Michelia.Pp.29-37 In:N.C.Treseder(ed.),“Magnolias”.Faber and Faber,London.Darlington C.D.and Wylie A.P.(eds.),1955—Chromosome atlas of flowering plants.George Allen &Unwin,London.Fedorov A.(ed.),1974—Chromosome numbers of flowering plants.Science Publishers,Koenigstein city,Otto Koeltz.Figlar R.B.and Nooteboom H.P.,2004—Notes on Magnoliaceae IV.Blumea.49:87-100.Frodin D.G.and Govaerts R.(eds.),1996—World Checklist and Bibliography of Magnoliaceae.Whit-stable Litho Printer Ltd,Britain.Gagnepain F.,1938—Magnoliaceae.In:P.H.Le-comte(ed.),Fl.Indo-Chine,Suppl.1:29-59.Mas-son&Cie,Paris.Goldblatt P.(ed.),1984—Index to plant chromosome numbers1979∼1981.Missouri Bot.Gard.Goldblatt P.(ed.),1985—Index to plant chromosome numbers1982∼1983.Missouri Bot.Gard.Goldblatt P.(ed.),1988—Index to plant chromosome numbers1984∼1985.Missouri Bot.Gard.Goldblatt P.(ed.),1990—Index to plant chromosome numbers1986∼1987.Missouri Bot.Gard.Gong X.,Shi S.H.,Pan Y.Z.,Huang Y.L.and Yin Q., 2003—An observation on the main taxonomic char-acters of subfamily Magnolioideae in China.Acta Bot Yunnan.25(4):447-456.Hong D.Y.(ed),1990—Plant cytotaxonomy.Sciences Press,Beijing.Jankai-ammal E.K.,1952—The race history of magno-lias.Indian J.Gen.P.Bre.12(2):182-192.Keng H.,1978—The delimitation of the genus Magno-lia(Magnoliaceae).Gard.Bull.Singapore31:127-131.Kim S.,Park C.W.,Kim Y.D.and Suh Y.,2001—Phylogenetic relationships in family Magnoliaceae in-ferred from ndhF sequences.Amer.J.Bot.88(4): 717-728.Law Y.H.,1979—A new genus of Magnoliaceae from China.Acta Phytotax.Sin.17:w Y.H.,1984—A preliminary study on the systemat-ics of Magnoliaceae.ActaPhytotax.Sin.22(2):89-109.Law Y.H.,1996—Magnoliaceae.In:C.Y.Wu(ed.), Flora Reipublicae Popularis Sinicae,vol.30(1):151-191.Science Press,Beijing.Law Y.H.,1997—Woonyoungia Law,A new genus of Magnoliaceae from China.Bull.Bot.Res.(Harbin) 17(4):353-356.Law Y.H.,2000—Studies on the phylogeny of Magno-liaceae.In:w et al.(eds.),“Proceedings of the International Symposium of the family Magno-liaceae”Pp.3-13.Science Press,Beijing.Law Y.H.,Xia N.H.and Yang H.Q.,1995—The ori-gin,evolution and phytogeography of Magnoliaceae.J.Trop.Subtrop.Bot.3(4):1-12.Levan A.,Fredge K.and Sandberg A.A.,1964—No-menclature for centromeric position on chromo-somes.Hereditas52:201-220.Li J.Q.and He Z.C.,2003âMeiosis observation and chromosome configuration analysis of Magnolia denudata.Acta Phytotax.Sin.41(4):362-368.Li J.and Conran J.G.,2003—Phylogenetic relation-ships in Magnoliaceae subfam.Magnolioideae:a mor-phological cladistic analysis.P.Syst.Evol.242: 33-47.Li X.L.,Song W.Q.,An Z.P.and Chen R.Y.,1997—The karyotype comparison among some species of Manglietia in China.Acta Sci.Nat.Uni.Nankai.30(4):109-112.Li X.L.,Song W.Q.,An Z.P.and Chen R.Y.,1998a—Karyotype analysis of some species of Magnolia in China.Acta Bot.Yunnan.20(2):204-206.Li X.L.,Song W.Q.,An Z.P.and Chen R.Y.,1998b—Karyotype analysis of Michelia(Magnoliaceae)in China.Acta Phytotax.Sin.36(2):145-149.Li X.L.,Song W.Q.,An Z.P.and Chen R.Y.,1998c—Karyotype comparison between genera in Magno-liaceae.Acta Phytotax.Sin.36(3):232-237.Lima-de-faria A.,1949—Genetics,origin and evolu-tion of kinetochores.Hereditas,35:422-444.Meng A.P.,He Z.C.,Li J.Q.and Wang H.C.,2004—Karyomorphology of three Manglietia(Magno-liaceae)species.Acta Bot.Yunnan.26(3):317-320. Nooteboom H.P.,1985—Notcs on Magnoliaceae.Blunea31:65-121.Nooteboom H.P.,1993—Magnoliaceae.In:K.Kubit-ski(ed.),The families and genera of vascular plants Vol.II:391-401.Flowering plants.Spinger−Ver-lag,New York.Nooteboom H.P.,1998—The tropical Magnoliaceae and their classification.In:D.Hunt.(ed.),Magno-lias and their allies.Pp:71-78.Divid Hunt,Mil-borne Port,UK.Nooteboom H.P.,2000—Different looks at the classi-fication of the Magnoliaceae.In:w et al.(eds.),“Proceedings of the International Sympo-sium of the family Magnoliaceae”Pp.14-25.Sci-ence Press,Beijing.198heng-chang,meng,li and sima。

MB20微型一体化可编程逻辑控制器选型手册

32个有
无
13us（基本指令）梯形图、流程图
10条
47条
2*RS232（非隔离）
9个
176mm（L）*80mm(W)*66mm(H)
使用温度-10-55℃，保存温度-10-70℃ 5％-95％无凝结
符合GB/T 2423.10-1995、GB/T2423.11-97标准
AC500V,1min
5MΩ以上
30038400mb20微型一体化智能可编程逻辑控制器选型手册mb40智能可编程逻辑控制器模块型谱模块插箱型号应用mb40chs806mb40chs81010槽模件底板10mb40chs81414槽模件底板14电源模块型号应用电源输入类型电源输出类型mb40psm129无交采或同期模件24v205v50wmb40psm149使用交采或同期模件24v205v50w12v50wmb40psm125无交采或同期模件24v205v25wmb40psm145使用交采或同期模件24v205v25w12v15wcpu模块型号应用主频以太网测点数开入开出模入模出mb40cpu301单机系统66mhz512512128128mb40cpu511单机单网系统300mhz以上10m100m204820481024256mb40cpu512双机双网系统300mhz以上10m100m204820481024256mb40cpu521单机双网系统300mhz以上10m100m204820481024256及功能模块型号应用通道数信号类型mb40dim212数字量输入1624vdcmb40dim214数字量输入3224vdcmb40iim214soe量输入3224vdcmb40dom212数字量输出1624vdcmb40dom214数字量输出3224vdcmb40aim211电流型模拟量输入020ma420mamb40aim221电压型模拟量输入05v15vmb40aim212电流型模拟量输入16020ma420mamb40aim222电压型模拟量输入1605v15vmb40aom211模拟量输出020ma420ma05v15vmb40cpm418rs232rs485串口通讯波特率

25-21 SMD LED 数据手册说明书

SMD B25-21/BHC-ZP2Q2TY/2AFeatures․Package in 8mm tape on 7〞diameter reel.․Compatible with automatic placement equipment.․Compatible with infrared and vapor phase reflow solder process. ․Mono-color type. ․Pb-free.․The product itself will remain within RoHS compliant version. ․Compliance with EU REACH․Compliance Halogen Free .(Br <900 ppm ,Cl <900 ppm , Br+Cl < 1500 ppm).Description․The 25-21 SMD LED is much smaller than lead frame type components, thus enable smaller board size, higher packing density, reduced storage space and finally smaller equipment to be obtained.․Besides, lightweight makes them ideal for miniature applications. etc.Applications․Backling in dashboard and switch․Telecommunication: indicator and backlighting in telephone and fax. ․Flat backlight for LCD, switch and symbol. ․General use.InGaN Blue Water ClearReverse Voltage V R 5 V Forward Current I F10 mAeak Forward Current(Duty 1/10 @1KHz)I FP100 mA Power Dissipation Pd40 mW Electrostatic Discharge ESD HBM150 V Operating Temperature T opr-40 ~ +85 ℃Storage Temperature Tstg -40 ~ +90 ℃Soldering Temperature Tsol Reflow Soldering : 260 ℃ for 10 sec. Hand Soldering : 350 ℃ for 3 sec.Electro-Optical Characteristics (Ta=25℃)Luminous Intensity Iv 57 ----- 112 mcd I F =5mAViewing Angle 2θ1/2 ----- 60 ----- deg Peak Wavelength λp ----- 468 ----- nmDominant Wavelength λd 465.0 ----- 475.0 nm Spectrum Radiation Bandwidth △λ ----- 25 ----- nm Forward Voltage V F 2.60 ---- 3.00 V Reverse CurrentI R----------50μAV R =5VNote:1.Tolerance of Luminous Intensity: ±11%2.Tolerance of Dominant Wavelength ±1nm3. Tolerance of Forward Voltage: ±0. 05VP2 57 72 mcdI F =5mAQ1 72 90 Q290112Bin Range of Dominant WavelengthX 465.0 470.0 nm I F =5mAY470.5475.028 2.60 2.70 VI F =5mA29 2.70 2.80 30 2.80 2.90 312.903.00Note:1.Tolerance of Luminous Intensity: ±11%2.Tolerance of Dominant Wavelength ±1nm3. Tolerance of Forward Voltage: ±0. 05VTypical Electro-Optical Characteristics CurvesPackage DimensionNote: Tolerances unless mentioned ±0.1mm. Unit = mmLabel Explanation‧CPN: Customer ’s Product Number ‧P/N: Product Number ‧QTY: Packing Quantity‧CAT: Luminous Intensity Rank‧HUE: Chromaticity Coordinates & Dom. Wavelength Rank ‧REF: Forward Voltage Rank ‧LOT No: Lot NumberReel DimensionsNote: The tolerances unless mentioned is ±0.1mm ,Unit = mmCarrier Tape Dimensions: Loaded quantity 2000 PCS per reelPrecautions For Use1. Over-current-proofCustomer must apply resistors for protection, otherwise slight voltage shift will cause bigcurrent change ( Burn out will happen ).2. Storage2.1 Do not open moisture proof bag before the products are ready to use.2.2 Before opening the package: The LEDs should be kept at 30℃or less and 90%RH or less.2.3 After opening the package: The LED's floor life is 1 year under 30℃or less and 60% RH or less.If unused LEDs remain, it should be stored in moisture proof packages.2.4 If the moisture absorbent material (silica gel) has faded away or the LEDs have exceeded thestorage time, baking treatment should be performed using the following conditions.3.3 When soldering, do not put stress on the LEDs during heating.3.4 After soldering, do not warp the circuit board.4.Soldering IronEach terminal is to go to the tip of soldering iron temperature less than 350℃for 3 seconds within once in less than the soldering iron capacity 25W. Leave two seconds and more intervals, and do soldering of each terminal. Be careful because the damage of the product is often started at the time of the hand solder.5.RepairingRepair should not be done after the LEDs have been soldered. When repairing is unavoidable, a double-head soldering iron should be used (as below figure). It should be confirmed beforehand whether the characteristics of the LEDs will orApplication RestrictionsHigh reliability applications such as military/aerospace, automotive safety/security systems,and medical equipment may require different product. If you have any concerns, please contact Everlight before using this product in your application. This specification guarantees the quality and performance of the product as an individual component. Do not use this product beyond the specification described in this document.。

EN25P20-50GIP资料

FEATURES• Single power supply operation - Full voltage range: 2.7-3.6 volt• 2 Mbit Serial Flash- 2 M-bit/256 K-byte/1024 pages - 256 bytes per programmable page• High performance - 100MHz clock rate• Low power consumption - 5 mA typical active current- 1 μA typical power down current• Uniform Sector Architecture: - Four 64-Kbyte sectors• Software and Hardware Write Protection:- Write Protect all or portion of memory via software- Enable/Disable protection with WP# pin • High performance program/erase speed - Byte program time: 7µs typical - Page program time: 1.5ms typical - Sector erase time: 800ms typical - Chip erase time: 3 Seconds typical• Minimum 100K endurance cycle• Package Options- 8 pins SOP 150mil body width - 8 contact VDFN- All Pb-free packages are RoHS compliant • Commercial and industrial temperature RangeGENERAL DESCRIPTIONThe EN25P20 is a 2M-bit (256K-byte) Serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.The EN25P20 is designed to allow either single Sector at a time or full chip erase operation. The EN25P20 can be configured to protect part of the memory as the software protected mode. The device can sustain a minimum of 100K program/erase cycles on each sector.EN25P20 2 Mbit Uniform Sector, Serial Flash MemoryFigure.1 CONNECTION DIAGRAMS8 - LEAD SOP 8 - CONTACT VDFN Figure 2. BLOCK DIAGRAMSIGNAL DESCRIPTIONSerial Data Input (DI)The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK) input pin.Serial Data Output (DO)The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin. Serial Clock (CLK)The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI Mode")Chip Select (CS#)The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. When CS# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. After power-up, CS# must transition from high to low before a new instruction will be accepted.Hold (HOLD#)The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low, while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored (don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.Write Protect (WP#)The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Usedin conjunction with the Status Register’s Block Protect (BP0, BP1) bits and Status Register Protect (SRP) bits, a portion or the entire memory array can be hardware protected. Table 1. PIN NamesNameSymbol PinCLK Serial Clock InputDI Serial Data InputDO Serial Data OutputEnableCS# ChipProtectWP# WriteHOLD# HoldInputVcc Supply Voltage (2.7-3.6V)Vss GroundMEMORY ORGANIZATIONThe memory is organized as:bytesz 262,144z Uniform Sector ArchitectureFour 64-Kbyte sectorsz1024 pages (256 bytes each)Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or Bulk Erasable but not Page Erasable.Table 2. Block Sector ArchitectureSector SECTOR SIZE (KByte) Address range3 64 30000h3FFFFh–2 64 20000h2FFFFh–1 64 10000h1FFFFh–0 64 00000h0FFFFh–OPERATING FEATURESSPI ModesThe EN25P20 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure 3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK. Data output on the DO pin is clocked out on the falling edge of SCK.Figure 3. SPI ModesPage ProgrammingTo program one data byte, two instructions are required: Write Enable (WREN), which is one byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the internal Program cycle (of duration tPP).To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on the same page of memory.Sector Erase and Bulk EraseThe Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied, the bytes of memory need to have been erased to all 1s (FFh). This can be achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of duration tSE or tBE). The Erase instruction must be preceded by a Write Enable (WREN) instruction.Polling During a Write, Program or Erase CycleA further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE or BE) can be achieved by not waiting for the worst case delay (tW, tPP, tSE, or tBE). The Write In Progress (WIP) bit is provided in the Status Register so that the application program can monitor its value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.Active Power, Stand-by Power and Deep Power-Down ModesWhen Chip Select (CS#) is Low, the device is enabled, and in the Active Power mode. When Chip Select (CS#) is High, the device is disabled, but could remain in the Active Power mode until all internal cycles have completed (Program, Erase, Write Status Register). The device then goes in to the Stand-by Power mode. The device consumption drops to I CC1.The Deep Power-down mode is entered when the specific instruction (the Enter Deep Power-down Mode (DP) instruction) is executed. The device consumption drops further to I CC2. The device remains in this mode until another specific instruction (the Release from Deep Power-down Mode and Read Device ID (RDI) instruction) is executed.All other instructions are ignored while the device is in the Deep Power-down mode. This can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent Write, Program or Erase instructions.Status Register. The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions.BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle.WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions.SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode. In this mode, the non-volatile bits of the Status Register (SRP, BP1, BP0) become read-only bits.Write ProtectionApplications that use non-volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. To address this concern the EN25P20 provides the following data protection mechanisms:z Power-On Reset and an internal timer (t PUW) can provide protection against inadvertent changes while the power supply is outside the operating specification.z Program, Erase and Write Status Register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution.z All instructions that modify data must be preceded by a Write Enable (WREN) instruction to set the Write Enable Latch (WEL) bit . This bit is returned to its reset state by the following events:– Power-up– Write Disable (WRDI) instruction completion or Write Status Register (WRSR) instruction completion or Page Program (PP) instruction completion or Sector Erase (SE)instructioncompletion or Bulk Erase (BE) instruction completion orz The Block Protect (BP1, BP0) bits allow part of the memory to be configured as read-only. This is the Software Protected Mode (SPM).z The Write Protect (WP#) signal allows the Block Protect (BP1, BP0) bits and Status Register Protect (SRP) bit to be protected. This is the Hardware Protected Mode (HPM).z In addition to the low power consumption feature, the Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the Release from Deep Power-down instruction).Table 3. Protected Area Sizes Sector OrganizationMemory ContentBP1 Bit BP0BitProtected SectorsAddresses Density(KB)Portion1 1 All ( Sector 0 to 3) 000000h-03FFFFh 256KB All sectors1 0 Sector2 to3 020000h-03FFFFh 128KB Upper 1/20 1 Sector 3 030000h-03FFFFh 64KB Upper 1/40 0 None None None NoneHold FunctionThe Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any Write Status Register, Program or Erase cycle that is currently in progress.To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low (as shown in Figure 4.).The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides with Serial Clock (CLK) being Low.If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts after Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock (CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in Figure 4.). During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI) and Serial Clock (CLK) are Don’t Care.Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the moment of entering the Hold condition.If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of resetting the internal logic of the device. To restart communication with the device, it is necessary to drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from going back to the Hold condition.Figure 4. Hold Condition WaveformINSTRUCTIONSAll instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP) instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.In the case of multi-byte commands of Page Program (PP), and Release from Deep Power Down (RES ) minimum number of bytes specified has to be given, without which, the command will be ignored.In the case of Page Program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. In the case of SE, exact 24-bit address is a must, any less or more will cause the command to be ignored.All attempts to access the memory array during a Write Status Register cycle, Program cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle continues unaffected.Table 4. Instruction SetInstruction Name Byte 1CodeByte 2 Byte 3 Byte 4 Byte 5 Byte 6 n-Bytes Write Enable 06hWrite Disable 04hRead Status Register 05h (S7-S0)(1)continuous(2)Write StatusRegister01h S7-S0Read Data 03h A23-A16 A15-A8 A7-A0 (D7-D0) (Next byte) continuousFast Read 0Bh A23-A16 A15-A8 A7-A0 dummy (D7-D0) (Next Byte)continuous Page Program 02h A23-A16A15-A8 A7-A0 D7-D0(Next byte)continuous Sector Erase D8h A23-A16A15-A8 A7-A0Bulk Erase C7hDeep Power-down B9hRelease from DeepPower-down, and read Device ID dummy dummydummy(ID7-ID0)(4)Release from DeepPower-downABhManufacturer/ Device ID 90h dummy dummy00h (M7-M0)(ID7-ID0)(5)Read Identification 9Fh (M7-M0) (ID15-ID8) (ID7-ID0)Notes:1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data being read fromthe device on the DO pin.2. The Status Register contents will repeat continuously until CS# terminate the instruction.3. All sectors may use any address within the sector.4. The Device ID will repeat continuously until CS# terminate the instruction.5. The Manufacturer ID and Device ID bytes will repeat continuously until CS# terminate the instruction.00h on Byte 4 starts with MID and alternate with DID, 01h on Byte 4 starts with DID and alternate with MID.Table 5. Manufacturer and Device IdentificationOP Code (M7-M0) (ID15-ID0) (ID7-ID0)ABh11h90h 1Ch 11h9Fh 1Ch 2012hWrite Enable (WREN) (06h)The Write Enable (WREN) instruction (Figure 5)sets the Write Enable Latch (WEL) bit. The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.The Write Enable (WREN) instruction is entered by driving Chip Select (CS#) Low, sending the instruction code, and then driving Chip Select (CS#) High.Write Disable (WRDI) (04h)The Write Disable instruction (Figure 6) resets the Write Enable Latch (WEL) bit in the Status Register to a 0. The Write Disable instruction is entered by driving Chip Select (CS#) low, shifting the instruction code “04h” into the DI pin and then driving Chip Select (CS#) high. Note that the WEL bit is automatically reset after Power-up and upon completion of the Write Status Register, Page Program, Sector Erase, and Bulk Erase instructions.Read Status Register (RDSR) (05h)The Read Status Register (RDSR) instruction allows the Status Register to be read. The Status Register may be read at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible to read the Status Register continuously, as shown in Figure 7.Table 6. Status Register Bit Locations SRP 0 0 0 BP1 BP0 WEL BUSYThe status and control bits of the Status Register are as follows:BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted.BP1, BP0 bits. The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if, both Block Protect (BP1, BP0) bits are 0.Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing this will ensure compatibility with future devices.SRP bit. The Status Register Protect (SRP) bit is operated in conjunction with the Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect (SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the Status Register (SRP, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution.Status Register ProtectReserved Bits Block Protect BitsWrite Enable LatchBusyWrite Status Register (WRSR) (01h)The Write Status Register (WRSR) instruction allows new values to be written to the Status Register. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded and executed, the device sets the Write Enable Latch (WEL).The Write Status Register (WRSR) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code and the data byte on Serial Data Input (DI).The instruction sequence is shown in Figure 8.. The Write Status Register (WRSR) instruction has no effect on S6, S5, S1 and S0 of the Status Register. S6 and S5 are always read as 0. Chip Select (CS#) must be driven High after the eighth bit of the data byte has been latched in. If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch (WEL) is reset.The Write Status Register (WRSR) instruction allows the user to change the values of the Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-only, as defined in Table 3.. The Write Status Register (WRSR) instruction also allows the user to set or reset the Status Register Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered.Read Data Bytes (READ) (03h)The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency f R, during the falling edge of Serial Clock (CLK).The instruction sequence is shown in Figure 9.. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.The Read Data Bytes (READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.Read Data Bytes at Higher Speed (FAST_READ) (0Bh)The device is first selected by driving Chip Select (CS#) Low. The instruction code for the Read Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (CLK). Then the memory contents, at that address, is shifted out on Serial Data Output (DO), each bit being shifted out, at a maximum frequency F R, during the falling edge of Serial Clock (CLK).The instruction sequence is shown in Figure 10.. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. The whole memory can, therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ) instruction. When the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely.The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving Chip Select (CS#) High. Chip Select (CS#) can be driven High at any time during data output. Any Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress.Page Program (PP) (02h)The Page Program (PP) instruction allows bytes to be programmed in the memory. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).The Page Program (PP) instruction is entered by driving Chip Select (CS#) Low, followed by the in-struction code, three address bytes and at least one data byte on Serial Data Input (DI). If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (CS#) must be driven Low for the entire duration of the sequence.The instruction sequence is shown in Figure 11. If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes are guaranteed to be programmed correctly within the same page. If less than 256 Data bytes are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page.Chip Select (CS#) must be driven High after the eighth bit of the last data byte has been latched in, otherwise the Page Program (PP) instruction is not executed.As soon as Chip Select (CS#) is driven High, the self-timed Page Program cycle (whose duration is t PP) is initiated. While the Page Program cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.A Page Program (PP) instruction applied to a page which is protected by the Block Protect (BP1, BP0)bits (see Table 3.a and Table 3.b) is not executed.Sector Erase (SE) (D8h)The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).The Sector Erase (SE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code, and three address bytes on Serial Data Input (DI). Any address inside the Sector (see Table 2.a and Table 2.b) is a valid address for the Sector Erase (SE) instruction. Chip Select (CS#) must be driven Low for the entire duration of the sequence.The instruction sequence is shown in Figure 12.. Chip Select (CS#) must be driven High after the eighth bit of the last address byte has been latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Sector Erase cycle (whose duration is t SE) is initiated. While the Sector Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP1, BP0) bits (see Table 3.a and Table 3.b) is not executed.Bulk Erase (BE) (C7h)The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write Enable (WREN) instruction must previously have been executed. After the Write Enable (WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).The Bulk Erase (BE) instruction is entered by driving Chip Select (CS#) Low, followed by the instruction code on Serial Data Input (DI). Chip Select (CS#) must be driven Low for the entire duration of the sequence.The instruction sequence is shown in Figure 13.. Chip Select (CS#) must be driven High after the eighth bit of the instruction code has been latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (CS#) is driven High, the self-timed Bulk Erase cycle (whose duration is t BE) is initiated. While the Bulk Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.The Bulk Erase (BE) instruction is executed only if all Block Protect (BP1, BP0) bits are 0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.。

Signatures of Technicolor Models with the GIM Mechanism

Models of weak interactions based on the technicolor idea [1] need a mechanism which communicates the symmetry breaking to the quarks and leptons. One way of coupling the technifermions to the quarks and leptons is the introduction of extended-technicolor (ETC) interactions [2], which generate fermion masses. However, simple extended-technicolor models suﬀer unacceptable ﬂavor-changing neutral currents. More limitations on viable technicolor theories are imposed by measurements of the electroweak parameters[4]. An interesting solution to these problems are models which incorporate the GlashowIliopoulous-Maiani (GIM) mechanism [5]. The ﬁrst technicolor models that used GIM mechanism to avoid unacceptably large ﬂavor-changing neutral currents were the composite technicolor standard models [6]. These models realize the GIM mechanism by separating the ETC interactions into several ETC groups. There are separate ETC groups for the lefthanded fermion ﬁelds, the right-handed up quarks, and the right-handed down quarks. Such construction introduces a large global symmetry associated with quark ﬂavor. This ﬂavor symmetry is the essence of the GIM mechanism. Breaking of the global symmetry is responsible for the fermion masses and the quark mixing—the existence of the Kobayashi-Maskawa matrix. However, the composite technicolor models presented in Ref. [6] were toy models of weak interactions, since the models did not incorporate leptons. Realistic technicolor models with the GIM mechanism were described in Refs. [7] and [8]. We will refer to these models as technicolor-GIM models (TC-GIM). Not only do the TC-GIM models avoid trouble with the ﬂavor-changing neutral currents, but they also limit the number of technifermion doublets to one, thereby avoiding conﬂict with precise electroweak measurements [4]. A noticeable feature of these models is the presence of exotic light fermions. From the point of view of a model builder, the most diﬃcult task is to create a model with an appropriate pattern of breaking ﬂavor and gauge symmetries. The symmetry breaking is achieved by introducing numerous heavy fermion ﬁelds and gauge bosons. The light fermions that were mentioned before exist in the TC-GIM models only to cancel certain anomalies. In QCD-like models the light fermions seem to be a necessary ingredient. Since the light fermions are a necessary feature of TC-GIM models, their signatures are the best place to test and study this kind of models. In this paper we explore the phenomenological consequences of the light fermion sector. The light fermions transform under the ETC groups and also some additional conﬁning interactions. The scale of conﬁning interactions, depending on a particular model, can be from tens to hundreds of GeV. Below the conﬁnement scale, there are pseudo-Goldstone bosons (PGBs) in the particle spectrum whose constituents are the light fermions. The PGBs are the lightest exotic particles in the spectrum of the TC-GIM models. While present experiments put a lower bound on the scale of the conﬁning interactions, future experiments 1

BGF802-20

Fig.9
GSM EDGE rms EVM as a function of load power; typical values.
2003 Jun 13
5
Philips Semiconductors
Product speciﬁcation
CDMA800 power module
BGF802-20
DISCRETE SEMICONDUCTORS
DATA SHEET
M3D737
BGF802-20 CDMA800 power module
Product speciﬁcation Supersedes data of 2003 Feb 24 2003 Jun 13
Philips Semiconductors
2003 Jun 13
2
Philips Semiconductors
Product speciﬁcation
CDMA800 power module
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VS PD PL Tstg Tmb DC supply voltage input drive power load power storage temperature operating mounting base temperature PARAMETER − − − −30 −20 MIN. 30 100 30 +100 +90
EVM (%) − − 0.4
GSM EDGE Notes
1. IS95 CDMA (Pilot, paging, sync and traffic codes 8−13). 2. ACPR 750 kHz at 30 kHz resolution bandwidth. 3. ACPR 1.98 MHz at 30 kHz resolution bandwidth. 4. ACPR 400 kHz at 30 kHz resolution bandwidth.