Exception Handling in Embedded Systems--Cortex-M0 & 68000

ID: 10374498Name: Tianyi ZhouException Handling in ProcessorsProcessors have been developing for 50 years and exception handling mechanisms, one of the most fundamental parts in computer systems, have also been improved. Nowadays, in different processors, there are different approaches to handle exceptions.To begin with, what is exception handling? Exception handling is the software code that is utilized to deal with unexpected events raised during the execution of a program, to display error messages, and sometimes to provide informative detail regarding processes [1]. For instance, when you are downloading a large important document, an error may be displayed and stops the application in use. With exception handling added to application, it is assured that the exception will be handled in an orderly way and the work completed will not be lost. In addition, a detailed error message can also be set to inform users of information such as an address where the document is saved temporarily [2]. As for the sorts of exceptions usually dealt with, it can be a hardware interrupt, a software interrupt, an asynchronous interrupt, a synchronous interrupt, a signal, a trap or a system call [3]. Therefore, considering the wide range of unexpected events it treats, exception handling should be the last part to be ignored when designing a complete system. The detailed exception-handling procedure of processors called ARM Cortex-M0 and 68000 will be discussed in the following.The Cortex-M0 processor is a kind of ARM. It is a 32-bit Reduced Instruction Set Computing (RISC) processor with a single bus interface and the instruction set it used is called Thumb [4]. Among many features it contains, built-in Nested Vectored Interrupt Controller (NVIC) is an impressive one which allows interrupt configuration and coding of exception handler easy. The exception handling mechanism named vectored interrupt, supported by NVIC, is an essential element in Cortex-M0 design. What’s more, fault handling exception is able to catch a variety of sources of errors [4]. Before figuring out the procedure of how to handle exceptions, we need to study the exception types first. Generally, ARM exceptions can be considered in three groups: the exceptions generated as the direct effect of executing an instruction, the ones generated as a side-effect of an instruction and the ones generated externally, unrelated to the instruction flow [1]. The exceptions in the Cortex-M0 processor typically have seven types, which are nonmaskable interrupt (NMI), hard fault, supervisor call (SVCall), pendable service call (PendSV), systick, and all other interrupts [4]. Table 1. shows a detailed list of exceptions. Furthermore, three fixed highest priority levels and four programmable levels are supported in the Cortex-M0 processor. Each exception has a priority level that assures whether the exception willbe carried out or if it will stay in a pending state [4].Table 1 List of Exceptions in the Cortex-M0 ProcessorWhen it comes to the specific process of handling exceptions in Cortex-M0 processor, there are three limitations to accept exception requests. First, for interrupt and SysTick interrupt requests, the interrupt has to be enabled. Second, the processor is not running an exception handler of the same or a higher priority. Last, the exception is not blocked by the PRIMASK interrupt masking register [4]. If the conditions above are satisfied, an exception takes place. With entering an exception, three steps happen: the stack point stacks and update, the processor fetches the vector and updates it to the PC as well as the registers’ update[4]. The purpose of the first stacking step is to guarantee an interrupted program to be resumed correctly by saving some parts of the current state of the processor before the program execution switches to the exception handler. What’s more, t he eight registers, R0 to R3, R12, R14, the return address and the program status register, are put to the stack automatically and in order (Figure 1) [4].Figure 1 Order of register stacking during the exception sequenceAfter the stacking has been completed, the stack pointer is updated and the processor then fetches the exception vector from the vector table [4]. The vector table, shown in Figure 2,is the beginning of the memory space that contains exception vectors for available exceptions in the system, as well as the starting value of the main stack pointer (MSP) [4]. Obviously, some of the spaces in the vector table are not used because the Cortex-M0 only has a few system exceptions, but they will be used on other ARM processors. The vector is then updated to the PC. As the exception handlerbegins to execute, several registers are updated. For example, the value of LR is updated to the corresponding EXC_RETURN value and the IPSR is updated to the exception number of the currently serving exception [4].Figure 2 Vector TableWhen an exception return instruction is completed, the exception exit sequence turns to begin with the following two steps. First is the unstacking of registers. The purpose of this step is to restore registers to the state they were in before the exception was taken by read and restore the register values that were stored on to the stack [4]. Due to the uncertain stack frame, the processor first checks the value of the EXC_RETURN. If the value equals zero, it triggers the unstacking from the main stack, or from the process stack. There is a detailed flow chart shown in Figure 3. When the exception return process has finished, the system fetches instructions from the restored return address in the program counter [4]. Execution of the interrupt program is resumed then.Moreover, if an exception is in a pending state when another exception handler has been completed, a tail-chain scenario will occur that means all registers need not be restored from the stack and pushed back to the stack again [4]. Late arrival, another optimization mechanism in the Cortex-M0, increases the speed of processing higher-priority exceptions by dealing with them first instead of the lower-priority ones [4].Figure 3 Unstacking at the exception exitAfter the exception handling of the ARM Cortex-M0 has been introduced, it is time to present another processor, 68000. Motorola 68000 is a 32-bit microprocessor that has a powerful exception processing system. First of all, the MC68000 provides two privilege states, supervisor and user, and each state has its own stack pointer and stack. The relation between the two states and exceptions is shown in Figure 4. Exceptions can be external (hardware-initiated) or internal (software-initiated) (Figure 5)Figure 4 the relation between states and exceptionsFigure 5 Exception taxonomyThere are two types of Interrupts, a kind of hardware-initiated exceptions in the 68000 microprocessor, vectored interrupts and auto-vectored interrupts. Vectored interrupts are intended for peripherals that can provide an 8-bit vector number, stored in register in the peripheral (IVEC), to the 68000. It is important that programmers have responsibility for initializing the device with the vector number. Auto-vectored interrupts are intended for earlier peripherals designed for 8-bit processors that cannot provided a vector during an IACK cycle. Furthermore, the exception processing has three steps as the ARM Cortex-M0 does. First, an exception request occurs when instruction is being executed. When the request is allowed, there are three tasks need to be done: saving PC and SR to the Supervisor Stack, determining the address of the exception handler, jumping to the exception handler routine after finishing execution of instruction and executing the exception. Finally, when exception is finished, it is time to restore PC and SR from the Supervisor Stack and then to resume program execution after returning from exception handler routine. Besides these tasks, the 68000 also uses Vector Table to determine the address of the exception handler. The detailed exception handling procedure is shown in Figure 6.Figure 6 Exception processing flowchartTo summarize, the exception handling mechanism known as a vectored interrupt is used in both ARM Cortex-M0 and 68000. It allows that ―the exception vectors for different interrupts are separated and the starting-of-interrupt-service routines are located automatically without software intervention [4].‖In this case, it provides a very efficient approach to handling exceptions that are used widely in processors.Reference[1] Steve Furber, Addison-Wesley. ―ARM system-on-chip architecture‖. 2000.[2] Josh Juneau,Matt Arena. ―Oracle and PL/SQL Recipes -- A Problem-solution Approach‖. ISBN-13 (electronic): 978-1-4302-3208-7, 2010.[3] Peak Christopher G.,Scheinberg,Martin,Sokol, Jr.,Joseph. ―Processing exceptions from 64-bit application program executing in 64-bit processor with 32-bit OS kernel by switching to 32-bit processor mode‖. United States Patent, 7451298. Peak, et al. November 11, 2008.[4] Joseph Yiu. ―The Definitive Guide to the ARM Cortex-M0‖.Academic Press, March 1, 2011. Web ISBN-13:978-0-12-385478-0[5] Ricardo Gutierrez-Osuna, Wright State University. ―Lecture 9: Exception processing‖. Microprocessor-based System Design。