PPC440SPE-RGB533C中文资料

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440SP中文资料

Part Number 440SPRevision 1.23 - Sept 26, 2006 PowerPC 440SP Embedded ProcessorData Sheet Features•PowerPC‚ 440 processor core operating at up to 667MHz with 32-KB I- and D-caches (with parity checking)•On-chip 256-KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory•Selectable Processor:Bus clock ratios (Refer to the Clocking chapter in the PPC440SP Embedded Processor User’s Manual for details)•Supports up to 4 GB (2 Chip Selects) of 64-bit/32-bit SDRAM with ECC–DDR1 266-333-400–DDR2 400-533-667•Three DDR PCI-X interfaces (32-bit or 64-bit) up to 133 MHz (DDR 266) with support forconventional PCI•XOR Accelerator with DMA controller•Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives •I2O Messaging Unit with two DMA controllers •External Peripheral Bus (24-bit Address, 8-bit Data) for up to three devices•One Ethernet 10/100/1000 Mbps half- or full-duplex interface. Operational modes supported are MII and GMII.•Programmable Interrupt Controller supports interrupts from a variety of sources.•Programmable General Purpose Timers (GPT)•Three serial ports (16750 compatible UART)•Two IIC interfaces•General Purpose I/O (GPIO) interface available •JTAG interface for board level testing •Processor can boot from PCI memoryDescriptionDesigned specifically to address high-end embedded applications for storage, the PowerPC 440SP Embedded Processor (PPC440SP) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation.This chip contains a high-performance RISC processor core, a DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three DDR PCI-X bus interfaces, an Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.Technology: CMOS Cu-11, 0.13mm Package: 29mm, 783-ball, 1mm pitch, Flip Chip-Plastic Ball Grid Array (FC-PBGA)Power (estimated): Less than 6W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5VPowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006Data SheetContentsOrdering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Device Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84PowerPC 440SP Embedded ProcessorRevision 1.23 - Sept 26, 2006Data SheetFiguresFigure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Figure 2. PPC440SP Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Figure 3. 29mm, 783-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Figure 5. Input Setup and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Figure 7. DDR SDRAM Simulation Signal Termination Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Figure 9. DDR SDRAM Read Data Path. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Figure 11. DDR SDRAM Read Cycle Timing Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82TablesTable 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72Table 15. I/O Specifications—533MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 18. DDR SDRAM Clock to Write DQS Timing—TDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 20. DDR SDRAM I/O Read Timing—T SD and T HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006Data SheetOrdering and PVR InformationFor information about the availability of the following parts, contact your local AMCC sales office.Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only.The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC440SP Embedded Processor User’s Manual for details about accessing these registers.Note: Raid-enabled versions (Product Feature = R) require a RAID key license.Figure 1. Order Part Number KeyProduct Name Order Part Number(see Notes:)Package Rev Level PVR Value JTAG ID PPC440SP PPC440SP-xpCfffC29mm, 783 FC-PBGAC0x532218910x12056049Notes:1.x = Product FeatureA = RAID6 not enabled R = RAID6 enabled2.p = Module Package TypeF = leaded FC-PBGAN = lead free FC-PGBA (RoHS compliant)3. C = Chip Revision Level C 4.fff = Processor Frequency533 = 533MHz 667 = 667MHz5. C = Case Temperature Range of -40°C to +100°CAMCC Part NumberPPC440SP-RNC667CPackageProcessor Speed Product FeatureRevision LevelCase Temperature Range Note: The example part number above is a RAID6-enabled, lead-free package, at Chip Revision Level C, capable of running at 667 MHz, and is shipped in tray packaging.PowerPC 440SP Embedded ProcessorRevision 1.23 - Sept 26, 2006Data SheetPPC440SP Functional Block DiagramFigure 2. PPC440SP Functional Block DiagramThe PPC440SP is a System on a chip, which uses IBM ® CoreConnect Bus™ Architecture.Implemented with the Crossbar option, the IBM CoreConnect buses provide:•128-bit Data, 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data paths (10.6GB/sec total)•32-bit OPB interfaces up to 83.33MHz, 333MB/sAddress MapsThe PPC440SP incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various processor accessible address regions. The second address map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the PPC440SP processor through the use of mtdcr and mfdcr instructions.UART2UART1IIC1Processor Core DCR Bus32KB On-chip Peripheral Bus (OPB)GPIO AcceleratorBridgeDDR2 SDRAM External Bus ControllerControllerClock,Control,ResetPower MgmtJTAG Timers MMUUnit OPB Interrupt ControllerUniversal I-Cache32KB D-CacheXOR/DMA PPC440DDR PCI-XMALEthernet DCRsGPT L2 Cache/SRAM10/100/Low Latency (LL) SegmentHigh Bandwidth (HB) SegmentController Processor Local Bus (PLB)Trace ArbiterPLBI2O/DMA Host Local 64 bits 64 bits Local 32 bitsMemory PCI0PCI1PCI21000MII,GMII(EBC)(DMA0 and DMA1)(DMA2)Queue IIC0UART0(EMAC)PowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006Data SheetTable 1. System Memory Address Map (Sheet 1 of 2)Function Sub Function Start Address End Address SizeLocal Memory (LL)1DDR SDRAM0000 0000 0000 00000000 0000 FFFF FFFF4GB SRAM0000 0001 0000 00000000 0001 0003 FFFF256KB Reserved0000 0001 0004 00000000 0001 000F FFFFInternal PLB Interfaces (LL)I2O Registers0000 0001 0010 00000000 0001 0010 00FF256B DMA 0 Registers0000 0001 0010 01000000 0001 0010 01FF256B DMA 1 Registers0000 0001 0010 02000000 0001 0010 02FF256B I20/DMA Buffers0000 0001 0010 03000000 0001 0010 0FFF 3.25KB Reserved0000 0001 0010 10000000 0001 001F FFFFXOR/DMA20000 0001 0020 00000000 0001 0020 3FFF16KB Reserved0000 0001 0020 40000000 0001 EFFF FFFFInternal OPB Peripherals (LL)Reserved0000 0001 F000 00000000 0001 F000 01FFUART00000 0001 F000 02000000 0001 F000 02078B Reserved0000 0001 F000 02080000 0001 F000 02FFUART10000 0001 F000 03000000 0001 F000 03078B Reserved0000 0001 F000 03080000 0001 F000 03FFIIC00000 0001 F000 04000000 0001 F000 041F32B Reserved0000 0001 F000 04200000 0001 F000 04FFIIC10000 0001 F000 05000000 0001 F000 051F32B Reserved0000 0001 F000 05200000 0001 F000 05FFUART20000 0001 F000 06000000 0001 F000 06078B Reserved0000 0001 F000 06080000 0001 F000 06FF248B GPIO Controller Registers0000 0001 F000 07000000 0001 F000 077F128B Reserved0000 0001 F000 07800000 0001 F000 07FFEthernet Controller Registers0000 0001 F000 08000000 0001 F000 08FF256B Reserved0000 0001 F000 09000000 0001 F000 09FFGeneral Purpose Timers0000 0001 F000 0A000000 0001 F000 0B3F320B Reserved0000 0001 F000 0B400000 0001 F7FF FFFFEBC Memory0000 0001 F800 00000000 0001 FFBF FFFF124MB Additional Boot ROM60000 0001 FFC0 00000000 0001 FFDF FFFF2MBBoot ROM2, 30000 0001 FFE0 00000000 0001 FFFF FFFF2MB Reserved0000 0002 0000 00000000 0007 FFFF FFFFLocal Memory Alias (HB)Aliased DDR SDRAM0000 0008 0000 00000000 0008 FFFF FFFF4GBPowerPC 440SP Embedded ProcessorRevision 1.23 - Sept 26, 2006Data SheetDDR PCI-X Space (HB)Reserved 0000 0009 0000 00000000 0009 07FF FFFF PCIX0 I/O 0000 0009 0800 00000000 0009 0800 FFFF 64KB PCIX1 I/O 0000 0009 1800 00000000 0009 1800 FFFF 64KB PCIX2 I/O0000 0009 2800 00000000 0009 2800 FFFF64KBPCIX0 Addressing Config. Regs 0000 0009 0EC0 00000000 0009 0EC0 00078B PCIX1 Addressing Config. Regs 0000 0009 1EC0 00000000 0009 1EC0 00078B PCIX2 Addressing Config. Regs 0000 0009 2EC0 00000000 0009 2EC0 00078BPCIX0 Core Config. Regs 0000 0009 0EC8 00000000 0009 0EC8 0FFF 4KB PCIX1 Core Config. Regs 0000 0009 1EC8 00000000 0009 1EC8 0FFF 4KB PCIX2 Core Config. Regs0000 0009 2EC8 00000000 0009 2EC8 0FFF4KBPCIX0 Simple Message Passing 0000 0009 0EC8 11000000 0009 0EC8 11FF 256B PCIX1 Simple Message Passing 0000 0009 1EC8 11000000 0009 1EC8 11FF 256B PCIX2 Simple Message Passing0000 0009 2EC8 11000000 0009 2EC8 11FF256BPCIX0 Special Cycle 0000 0009 0ED0 00000000 0009 0EDF FFFF 1MB PCIX1 Special Cycle 0000 0009 1ED0 00000000 0009 1EDF FFFF 1MB PCIX2 Special Cycle 0000 0009 2ED0 00000000 0009 2EDF FFFF 1MBReserved 0000 0009 2EE0 00000000 0009 2EFF FFFF PCI Memory 0000 0009 2F00 00000000 0009 FFBF FFFF 3.3GBReserved0000 0009 FFC0 00000000 0009 FFDF FFFF PCI Boot ROM (PCI Memory)0000 0009 FFE0 00000000 0009 FFFF FFFF 2MB PCI Memory0000 000A 0000 00000000 000F FFFF FFFF 24GBReserved 40000 0010 0000 000003FF FFFF FFFF FFFF Reserved 50400 0010 0000 000007FF FFFF FFFF FFFF DDR PCI-X Space (HB)PCI Memory0800 0000 0000 0000FFFF FFFF FFFF FFFF15.7EBNotes:1.DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.2.The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.3.When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at 9 FFE0 0000 (128 KB).4.Never decoded.5.Unpredictable results on Read and Write operations.6.Accessed by means of EBC Peripheral Bank Configuration RegistersTable 1. System Memory Address Map (Sheet 2 of 2)FunctionSub FunctionStart Address End Address SizePowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006Data SheetTable 2. DCR Address Map (4KB of Device Configuration Registers)Function Start Address End Address SizeTotal DCR Address Space10003FF1KW (4KB)1By function:Reserved00000B12W Clocking Power On Reset00C00D2W System DCRs 00E00F2W Memory Controller 0100112W External Bus Controller0120132W Reserved01401F12W SRAM02002F16WL2 Controller03003F16W Memory Queue04004F16W Reserved05005F16WI2O/DMA06007F32WPLB08008F16WPLB to OPB Bridge Out09009F16W Reserved0A00AF16W Reserved0B00B12W Reserved0B20BF14W Interrupt Controller 00C00CF16W Interrupt Controller 10D00DF16W Power Management0E00E78W Reserved0E817F152W Ethernet MAL1801FF128W Reserved2003FF512WNotes:1.DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).PowerPC 440SP Embedded ProcessorRevision 1.23 - Sept 26, 2006Data SheetPowerPC 440 Processor CoreThe PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture.Features include:•Up to 667MHz operation•PowerPC Book E architecture •32KB I-cache, 32KB D-cache–Parity on Data and Tag address - checking of parity with error injection •Three logical regions in D-cache: Locked, Transient, and Normal •D-cache full-line flush capability•41-bit virtual address, 36-bit (64GB) physical address •Superscalar, out-of-order execution •Seven-stage pipeline•Three execution pipelines •Dynamic branch prediction •Memory management unit–64-entry, full associative, unified TLB with parity –Separate instruction and data micro-TLBs–Storage attributes for write-through, cache-inhibited, guarded, and big or little endian •Debug facilities–Multiple instruction and data range breakpoints –Data value compare–Single step, branch, and trap events –Non-invasive real-time trace interface •24 DSP instructions–Single cycle multiply and multiply-accumulate –32 x 32 integer multiplyInternal BusesThe PowerPC 440SP Embedded Processor features three standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the DDR PCI-X bridge connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores.The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB segment allows PLB masters DMA, XOR, and PCI to exchange large blocks of data with SDRAM and PCI without interfering with the low latency PLB masters.Bus features include:•PLB–128-bit Data implementation of the PLB architecture –Separate and simultaneous read and write data paths –64-bit address–Simultaneous control, address, and data phases –Four levels of pipelining–Byte enable capability supporting unaligned transfersPowerPC 440SP Embedded Processor Revision 1.23 - Sept 26, 2006Data Sheet–32- and 64-byte burst transfers–166MHz, maximum 5.2GB/s (simultaneous read and write)–Processor:Bus clock ratios of N:1 and N:2•OPB–Dynamic bus sizing: 32-, 16-, and 8-bit data path–32-bit address–83.33MHz, maximum 333MB/s•DCR–32-bit data path–10-bit addressOn-Chip SRAM/L2 CacheFeatures include:•Four banks of 64KB each for a total of 256KB•Configurable as either L2 cache or SRAM•Memory cycles supported:–Single beat read and write, 1 to 16 bytes–Quadword Read and Write burst for 12-bit master–Guarded memory accesses on 4KB boundaries•Sustainable 2.6GB/s peak bandwidth at 166MHz•Use as an L2 cache improves processor performance and reduces the PLB load–Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by software–Data Array and Tag Array parity–Unified data and instruction cache–Four-way set associative–36-bit addressing–Full LRU replacement algorithm–Write through, look aside•Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet coreDDR PCI-X InterfaceThe DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. There are three separate interfaces supporting 32- and 64-bit PCI-X buses in DDR mode. All three interfaces can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.Features include:•PCI-X2.0–Split transactions–Frequency to 266MHz–32- and 64-bit address/data bus–ECC supported for 266MHz Mode 2 only•PCI 2.3 backward compatibility–Frequency to 66MHz–32- and 64-bit bus•Can be the PCI Host Bus Bridge or an Adapter Device PCI interface•Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter•Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts•Simple message passing capability•Asynchronous to the PLBPowerPC 440SP Embedded ProcessorRevision 1.23 - Sept 26, 2006Data Sheet•PCI Power Management Version 1.1•PCI arbitration function with PCI-X Mode 2 support (optional)•PCI register set addressable both from on-chip processor and PCI device sides •Ability to boot from PCI-X bus memory •Error tracking/status•Supports initiation of transfer to the following address spaces:–Single beat I/O reads and writes–Single beat and burst memory reads and writes–Single beat configuration reads and writes (Type 0 and Type 1)–Single beat special cycles•PCI-X initialization sequence support (frequency & mode determination)•Support for unexpected split completions •Outbound transaction split discard timers •Vital Product Data (VPD) support •PCI-to-PCI opaque bridgeDDR1/DDR2 SDRAM Memory ControllerThe DDR2 SDRAM memory controller supports industry standard 184-pin DIMMs, SO-DIMMs, and other discrete devices. Global memory timings, address and bank sizes, and memory addressing modes are programmable. The DDR2 SDRAM controller interfaces to the PLB through a Memory Queue (MQ) function that includes six high-speed 1KB FIFO buffers.Features include:•Registered and non-registered industry standard DIMMs •DDR1 266-333-400•DDR2 400-533-667•64-and 32-bit memory interfaces with optional 8-bit ECC (SEC/DED)• 5.32GB/s peak bandwidth for the 64-bit interface • 2.66GB/s peak bandwidth for the 32-bit interface•Two chip (bank) select signals supporting two external banks •CAS latencies of 2, 3, 4, 5, 6, and 7 supported•Page mode accesses (up to 32 open pages) with configurable paging policy •Look-ahead request queue with programmable depth of four commands.•Optional optimized command scheduling (activate/precharge non-conflicting banks while accessing the current bank)•Up to 4GB in two external banks•Programmable address mapping and timing •Hardware and software initiated self-refresh•Sync DRAM configuration by means of mode register and extended mode register set commands •Power management (self-refresh, suspend, sleep)•Low Latency & High Bandwidth PLB ports•Selectable PLB read response (immediate or deferred)•Programmable Low Latency & High Bandwidth arbitration schemes•High Bandwidth port has four 1KB read buffers and two1KB write buffers •Low Latency port has four 128B read buffers and two 128B write buffersExternal Peripheral Bus Controller (EBC)Features include:•Support 2MB Boot ROM•Up to three ROM, EPROM, SRAM, Flash memory, and slave peripherals supported •Burst and non-burst devices •8-bit data bus。

芝麻坊 4 系列电脑电源说明书

Serie 4, Forno da incasso, 60 x 60cm, AcciaioHBA514BR0Accessori integrati1 x Griglia combinata, 1 x Leccarda universale smaltataAccessori opzionaliHEZ317000 Teglia per pizza, HEZ327000 Pietra per pane e pizza, HEZ333001 Coperchio per leccarda extra profonda, HEZ530000 2 leccarde slim 455x188x39 mm (LxPxA), HEZ531000 Leccarda bassa 455x375x30 mm (LxPxA), HEZ531010 Leccarda antiaderen455x375x30mm (LxPxA), HEZ532000 Leccarda profonda 455x375x38 mm (LxPxA), HEZ532010 Leccarda antiaderen 455x400x38mm (LxPxA), HEZ533000 Leccarda profonda 455x375x81 mm (LxPxA), HEZ538000 Guide telescopiche clip a 1 livello, HEZ629070 Teglia per grigliare adatta a pirolisi, HEZ633001 Coperchio per tegame professionale, HEZ633070 Tegame professionale, HEZ634000 Griglia combinata 455x375x31 mm (LxPxA), HEZ636000 Leccarda in vetro 455x364x30 mm (LxPxA), HEZ638000 Guide telescopiche clip a 1 livello, HEZ660050 Accessory, HEZ664000 Griglia combinata455x375x59 mm (LxPxA), HEZ915003 Pirofila in vetro con coperchio 5,4 l., HEZG0AS00 Cavo di collegamento 3m Cottura HotAir 3D: risultati perfetti di cottura grazie alla distribuzione omogenea del aria al interno della cavità, che consente di cucinare fino a 3 livelli allo stesso tempo.• Display digitale LED rosso: facile e comodo da utilizzare.• Cleaning Assistance: pulizia più semplice del forno grazie al nuovo sistema che è perfetto per un tipo di sporco leggero e non incrostato.Dati tecniciTipologia costruttiva del prodotto: .....................................Da incasso Sistema di pulizia: ....................................................................Idrolisi Dimensioni del vano per l'installazione (AxLxP): 585-595 x 560-568 x 550 mmDimensioni (AxLxP): ............................................595 x 594 x 548 mm Dimensioni del prodotto imballato (AxLxP): .......675 x 690 x 660 mm Materiale del cruscotto: ...................................................acciaio inox Materiale porta: ..........................................................................vetro Peso netto: ..............................................................................29.3 kg Volume utile: .................................................................................71 l Metodo di cottura: .Grill a superficie grande, Aria calda delicata, aria calda, Riscaldamento statico, Funzione pizza, riscaldamento inferiore, grill ventilatoMateriale della cavità: .................................................................Altro Regolazione della temperatura: ..........................................Meccanico Numero di luci interne: (1)Lunghezza del cavo di alimentazione elettrica: .....................120.0 cm Codice EAN: (4242005033683)Numero di vani - (2010/30/CE): (1)Classe di efficienza energetica: .........................................................A Energy consumption per cycle conventional (2010/30/EC): ........0.97 kWh/cycleEnergy consumption per cycle forced air convection (2010/30/EC):0.81 kWh/cycleIndice di efficienza energetica (2010/30/CE): ..........................95.3 % Potenza: ..................................................................................3400 W Corrente: .....................................................................................16 A Tensione: .............................................................................220-240 V Frequenza: ...........................................................................60; 50 Hz Tipo di spina: ..........................................................................Schuko Accessori inclusi: .......1 x Griglia combinata, 1 x Leccarda universale smaltataSerie 4, Forno da incasso, 60 x 60cm, AcciaioHBA514BR0Cottura HotAir 3D: risultati perfetti di cottura grazie alla distribuzione omogenea del aria al interno della cavità, che consente di cucinare fino a 3 livelli allo stesso tempo.Caratteristiche principali- 7 programmi di cottura: MultiCottura HotAir 3D, Riscaldamento superiore e inferiore, Grill ventilato, Grill a superficie grande, Funzione pizza, Riscaldamento inferiore- Display digitale LED rosso- Volume cavità: 71 l- Regolazione della temperatura da 50 °C a 275 °C- Cleaning AssistanceAltre caratteristiche- Riscaldamento rapido- Orologio elettronico con impostazione inizio e fine cottura- Illuminazione interna alogenaAccessori- Accessori: 1 griglia combinata, 1 leccarda universale profonda smaltataEtichetta energetica- Assorbimento massimo elettrico: 3.4 kW- Classe di efficienza energetica (acc. EU Nr. 65/2014): A(in una scala di classi di efficienza energetica da A+++ a D)- Consumo energetico per ciclo durante funzionamento convenzionale:0.97 kWh- Consumo energetico per ciclo durante funzionamento ventilato:0.81 kWh- Numero di cavità: 1 Tipo di alimentazione: elettrica Volume della cavità:71 lSerie 4, Forno da incasso, 60 x 60cm, Acciaio HBA514BR0。

MICROMASTER 440通用变频器

目录1 MICROMASTER 440 变频器的参数.................................................................... ................................... 1-1 1.1 MICROMASTER 440 变频器的系统参数.................简介.......................................................................1-2 1.2 快速调试(P0010=1)..... ................... ....................................................................................................1-4 1.3 命令和驱动数据组一概览........ ............. ......................... ......................................................................1-51.4 参数的说明......................................... .................................................................................................1-62 功能框图.............................................. .................................................................................................... 2-13 二进制互联连接（BiCo）功能................................................................................................................ 3-1 3.1 概述..................................................................................................................................................... 3-2 3.2 怎样进行BiCo 设置？......................................................................................................................... 3-2 3.3 BiCo 控制字和状态字的用法................................................................................................................. 3-43.4 BiCo 的连接............................................................ ............................................................................. 3-54 通讯....................................................................... .................................................................................. 4-1 4.1 采用的串行通讯接口............................................................................................................................ 4-2 4.2 串行通讯的工作情况............................ ................................................................................................. 4-2 4.2.1 概述.................................................................................................................................................... 4-2 4.2.2 RS485 的排障..................................................................................................................................... 4-3 4.3 采用通用的串行接口协议................................................................................ ................... ...................4-3 4.3.1 通讯报文的结构............................................................ ...................................................................... 4-4 4.3.2 USS 协议有关信息的详细说明........................................... .............................................................. 4-4 4.3.3 有效的数据字符.................................................................... .............................................................. 4-5 4.3.4 USS 的任务和应答.............................................................................................................................. 4-7 4.3.5 PKW 举例：..................................................................... .................................................................4-10 4.3.6 PZD 区域（过程数据区）................................................... .................................................................4-12 4.3.7 任务报文（主站→MICROMASTER4）................................................................................................4-12 4.3.8 应答报文（MICROMASTER4→主站）............................. ..................................................................4-13 4.3.9 MICROMASTER4 有关USS 通讯的参数设置.................. ..................................................................4-15 4.3.10 基本设定................................................................................................................... ........................4-16 4.3.11 一般的高级设置.................................................................................................................................4-16 4.3.12 较复杂的高级设置.............................................................................................................................4-17 4.3.13 与早期MICROMASTER 产品的兼容性....... . ...................................................................................4-17 4.3.14 读出和写入参数............................................... .................................................................................4-18 4.3.15 广播方式............................................................................................................................................4-19 4.3.16 通过USS 利用BiCo（二进制互联连接）...... . ....................................................................................4-19 4.4 PROFIBUS....................................................... . .................................................................................. 4-20 4.4.1 概况............................................................... . .................................................................................. 4-20 4.4.2 PROFIBUS 的使用........................................ .................................................................................... 4-20 4.5 PROFIBUS 模板............................................. . .................................................................................... 4-214.5.1 PROFIBUS 模板的特点................................. . .................................................................................. 4-215 高级操作板（AOP）..................................................... . .......................................................................... 5-1 5.1 警告和说明........................................................................ .................................................................... 5-4 5.1.1 特殊键的功能...................................................................................................................................... 5-4 5.2 应用举例............................................................................... . .............................................................. 5-5 5.2.1 采用AOP 控制单台变频器.......................................................... ....................................................... 5-55.2.2.3 网络控制－PC 方式.................................................................................................................... 5-7 5.2.3 参数的“读出”.............................................................. ................................................................. 5-8 5.2.4 参数的“下载”.................................................................. ............................................................... 5-9 5.2.5 AOP 的参数.................................................................... . ..................................................................5-10 5.2.6 从站方式和DriveMonitor 的操作................ . ....................................................................................5-10 5.2.7 MM3 参数的读出..................................... . .........................................................................................5-11 5.2.8 定时器的操作........................................... . .........................................................................................5-11 5.3 AOP 开始工作........................................................................................................................................5-14 5.3.1 接通电源和初始化............. . ...............................................................................................................5-14 5.3.2 语言文本的选择...................................... . ..........................................................................................5-15 5.3.3 开机“帮助”............................... . .....................................................................................................5-15 5.3.4 常规的操作屏幕.............................. . ..................................................................................................5-15 5.3.5 主菜单（机旁操作方式）.................................... . ..............................................................................5-16 5.3.6 请求等待................................................................ ............................................................................5-17 5.4 操作菜单................................................................................................................................................5-17 5.4.1 机旁操作方式下的操作........................................................................................................................5-17 5.4.1.1 通讯故障..........................................................................................................................................5-18 5.4.1.2 显示变频器的状态............... ............................................................................................................5-18 5.4.1.3 变频器类型的检验..................... ......................................................................................................5-18 5.4.2 主站方式下的操作................ . ............................................................................................................5-18 5.4.2.1 广播操作方式........................................... . .....................................................................................5-19 5.4.2.2 通讯故障..........................................................................................................................................5-19 5.5 选择操作方式.........................................................................................................................................5-19 5.5.1 机旁操作方式........................................................................................................... ......................... 5-20 5.5.2 主站方式................................................................................................................... ......................... 5-20 5.5.3 内部方式................................................................................................................... .........................5-20 5.5.4 从站方式.............................................................................................. ............................................. 5-20 5.5.5 PC 方式..................................................................................................... ........................................ 5-21 5.6 参数的访问............................................................................................................................................ 5-21 5.6.1 标准访问级的参数....................................................................... ...................................................... 5-21 5.6.2 功能键的使用................................................................................ .................................................... 5-22 5.6.2.1 屏幕显示滚动功能................................................................ .......................................................... 5-22 5.6.2.2 修改参数数值的某一位数字................................................ ............................................................ 5-22 5.6.2.3 跳转功能.......................................................................................................................................... 5-22 5.6.3 专家级参数................................................................................. ....................................................... 5-23 5.6.3.1 下标参数.............................................................................. ........................................................... 5-23 5.6.4 AOP 存储的参数组................................................................... ......................................................... 5-24 5.6.5 工程设计.................................................................................... ........................................................ 5-24 5.7 AOP 设定和组态.................................................................................................................................... 5-25 5.7.1 设定菜单..................................................................... ....................................................................... 5-25 5.7.1.1 背景亮度......................................................................................................................................... 5-25 5.7.1.2 屏幕对比度............................................................. ....................................................................... 5-26 5.7.1.3 用大字符显示.................................................................................................................................. 5-265.7.1.7 参数组的名称..................................................................................... ........................................... 5-27 5.7.1.8 设定时间/日期.......................................... ..................................................................................... 5-28 5.7.1.9 AOP 复位....................................................................................................................................... 5-28 5.8 故障指示............................................................................................................................................... 5-29 5.8.1 故障屏幕...................................................................................... ..................................................... 5-29 5.8.2 报警屏幕............................................................................................................................................ 5-30 5.8.3 多重故障................................................................................. .......................................................... 5-30 5.8.4 多重报警................................................................................. .......................................................... 5-30 5.8.5 故障和报警同时发生............................................................... .......................................................... 5-31 5.8.6 变频器的故障码....................................................................... ......................................................... 5-31 5.8.7 变频器的报警码........................................................................................ ........................................ 5-315.8.8 变频器的故障/ 报警记录（P0947）.............................................................................................. 5-316 编码器模板.............................................................................................................................................. 6-1 6.1 前言...................................................................................................................................................... 6-2 6.2 一般情况............................................................................................................................................... 6-3 6.3 安装...................................................................................................................................................... 6-4 6.3.1 准备工作................................................................................... ........................................................ 6-4 6.3.1.1 变频器的准备工作........................................................................................................................... 6-4 6.3.1.2 编码器模板的准备工作.......................................................... ......................................................... 6-5 6.3.2 接线方法的举例.................................................................................................................................. 6-8 6.4 调试................................................................................................................................................................. 6-9 6.4.1 TTL 编码器............................................................. ...........................................................................6-10 6.4.2 HTL 编码器................................................................... .....................................................................6-11 6.4.3 外接电源......................................................................... ...................................................................6-11 6.4.4 编码器模板的参数化........................................................ ..................................................................6-12 6.5 故障的排除............................................................................................................................................6-14 6.5.1 LED 指示灯............................................................ ...........................................................................6-14 6.5.2 故障码....................................................................... ........................................................................6-156.6 编码器模板的技术规格................................................... ......................................................................6-157 MICROMASTER 440 变频器的制动电阻..................................... ...........................................................7-1 7.1 技术数据...................................................................................... .........................................................7-2 7.2 安装.......................................................................................................................................................7-2 7.3 接线.......................................................................................................................................................7-2 7.4 制动电阻的接线和外形尺寸...................................................................................................................7-37.5 制动电阻的选型........................................................... .........................................................................7-48 选件安装图............................................................................................................................................... 8-1插图图4-1 典型的RS485 多站接口.................................................................................................................... 4-3 图4-2 通讯报文的结构................................................................................................................................. 4-4 图4-3 地址（ADR）的位号......................................................................................................................... 4-4图6-1 编码器模板的外观........................................................................................ .................................... 6-3 图6-2 变频器的铭牌........................................................................................................... ........................ 6-4 图6-3 选件的安装顺序........................................................................................................ ....................... 6-5图6-4 屏蔽接线端和PE 端子.......................................................................................... ......................... 6-5 图6-5 编码器模板上的LED 指示灯................................................................................. ......................... 6-6 图6-6 编码器模板的DIP 开关................................................................................................ .................... 6-7 图6-7 TTL 编码器的接线(5V DC) ................................................................................ ............................ 6-8 图6-8 HTL 编码器的接线(18V DC) .................................................................................. ........................ 6-8 图6-9 具有外接电源的编码器............................................................................................. ........................ 6-9 图6-10 编码器模板的安装方法....................................................................................... ............................ 6-9 图6-11 编码器模板上的LED 指示灯..........................................................................................................6-14表格表3-1 BiCo 的连接（r0019 至r0054）..................................... ................................................................. 3-5 表3-2 BiCo 的连接（r0055 至r1119）....................................... ............................................................. 3-6 表3-3 BiCo 的连接（r1170 至r2050）.......................................... .......................................................... 3-7 表3-4 BiCo 的连接（r2053 至r2294）............................................ ........................................................ 3-8 表4-1 任务识别标记ID 的定义............................................................ ....................................................... 4-7 表4-2 应答识别标记ID 的定义............................................................ ....................................................... 4-8 表4-3 对应答识别标记ID 的错误数值=“任务不能执行”的定义............... .................................................. 4-9 表4-4 PZD 区的结构..................................................................................... ..............................................4-12 表4-5 变频器的控制字（STW）................................................................ ................................................4-12 表4-6 变频器的状态字（PZD）.................................................................. ...............................................4-13 表4-7 实际例子........................................................................................ ....................................................4-14 表4-8 比较表（MICROMASTER4/早期生产的MIsCROMASTER 变频器）. ............................................4-18 表4-9 PROFIBUSSUB-D 插座的插针功能分配.............................................. ............................................ 4-23 表4-10 与数据传输速率相应的最大电缆长度................................................. ............................................ 4-23 表4-11 插头/座和电缆的订货号........................................................................ ............................. ........... 4-23 表4-12 技术数据.............................................................................................. ........................... .............. 4-24 表4-13 有关PROFIBUS 的订货资料................................................................... ...................................... 4-241 MICROMASTER 440 变频器的参数1.1 MICROMASTER 440 变频器的系统参数简介“参数说明”的编排格式如下。

Kuppersbusch BP 6550.0S-CN烤箱说明书

目录1. 图标的说明 (5)2. 运输与包装 (6)3. 安全须知 (7)3.1 连接与操作 (7)3.2 开启与操作 (7)3.3 烤箱 (8)3.4 家长须知 (9)3.5 首次使用 (9)3.6 环境保护 (9)3.7 能源信息 (10)3.8 用户须知 (10)4. 清洁与保养 (11)4.1 产品表面 (11)4.2 烤箱门的清洁（不包括微波炉、微烤一体机） (13)4.3 高温热解自清洁的烤箱（部分型号） (14)5. 首次使用前的注意事项 (14)5.1 重要建议 (15)6. 配件 (16)6.1 可伸缩滑动搁架 (16)6.2 滑出式搁架 (17)6.3 烤箱配件的更换 (18)7. 维护 (18)7.1 烤箱灯的更换 (18)7.2 拆卸和装配烤箱门（微烤一体机除外） (19)7.3 拆卸和装配烤箱门内玻璃 (21)7.4 拆卸和装配烤箱侧边支架 (22)7.5 拆卸后部背板 (22)8. 烤箱结构 (24)8.1 操作面板——触摸控制及屏显 (25)8.2 设置时钟 (26)9. 烧烤与烹饪菜单 (26)29.1 烹饪指南 (26)9.2 烤肉指南 (30)9.3 烧烤指南 (32)9.4 烘焙探针建议温度 (33)9.5 低温烹饪指南 (34)10. 烤箱功能 (35)10.1 烹饪功能 (35)10.2 特殊功能 (36)11. 烤箱的操作 (38)11.1 开启/关闭烤箱 (38)11.2 待机模式 (38)11.3 首次使用烤箱前的设置 (38)11.4 选择烹饪功能 (39)11.5 选择特殊功能 (40)11.6 烹饪过程中更改设置 (40)11.7 自动功能 (41)11.8 更改食材重量和温度 (42)11.9 设置时间 (43)11.10 快速加热（出厂已激活） (47)12. 菜单收藏 (47)12.1 访问收藏设定 (47)12.2 存储菜单至收藏夹 (48)12.3 删除收藏菜单 (48)13. 其他功能 (48)13.1 设置演示模式 (48)13.2 童锁 (48)13.3 恢复出厂设置 (49)13.4 自动确认 (49)13.5 ECO模式 (49)13.6 开机音设置 (50)13.7 单位设置 (50)14. 烘焙探针 (51)14.1 烹饪功能中使用烘焙探针 (52)14.2 自动功能中使用烘焙探针 (52)315. 部分型号的特殊设置、其他功能与设置 (53)15.1 高温热解功能 (53)15.2 故障原因 (54)41.图标的说明我们的产品都是通过最新最好的技术来进行生产的，但是仍会有一些使用风险存在。

PPC-4211W 用户手册说明书

针对本手册中相关产品的说明，研华公司保留随时变更的权利，恕不另行通知。

未经研华公司书面许可，本手册所有内容不得通过任何途径以任何形式复制、翻印、翻译或者传输。

本手册以提供正确、可靠的信息为出发点。

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研华对于不正确的使用、灾难、错误安装产生的问题有免责权利。

如果研华产品出现故障，在质保期内我们提供免费维修或更换服务。

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如果您认为您购买的产品出现了故障，请遵循以下步骤：1.收集您所遇到的问题信息（例如，CPU主频、使用的研华产品及其它软件、硬件等）。

请注意屏幕上出现的任何不正常信息显示。

2.打电话给您的供货商，描述故障问题。

请借助手册、产品和任何有帮助的信息。

3.如果您的产品被诊断发生故障，请从您的供货商那里获得RMA (ReturnMaterial Authorization) 序列号。

这可以让我们尽快地进行故障产品的回收。

4.请仔细地包装故障产品，并在包装中附上完整的售后服务卡片和购买日期证明（如销售发票）。

我们对无法提供购买日期证明的产品不提供质量保证服务。

5.把相关的RMA序列号写在外包装上，并将其运送给销售人员。

料号：200K421100第一版中国印刷2014年4月PPC-4211W用户手册ii符合性声明CE本设备已通过CE 测试，符合以屏蔽电缆进行外部接线的环境规格标准。

Blackfin CM-BF533 硬件用户手册说明书

Hardware User Manual CM-BF533 V2.0 (V1.3)ContactBluetechnix Mechatronische Systeme GmbHWaidhausenstr. 3/19A-1140 ViennaAUSTRIA/EUROPE*********************Document No.: 100-1203-2.0Version 6Date: 2007-04-05Table of Contents1Introduction (1)1.1Overview (1)1.2Benefits (2)1.3Applications (2)2Specification (3)2.1Functional Specification (3)2.2Boot Mode (3)2.3Memory Map (4)2.4Electrical Specification (4)2.4.1Supply Voltage (4)2.4.2Supply Voltage Ripple (4)2.4.3External Oscillator Frequency (4)2.4.4Real Time Clock Crystal (4)2.4.5Supply Current (4)2.5Environmental Specification (4)2.5.1Temperature (4)2.5.2Humidity (5)3CM-BF533 (Connector Version) (6)3.1Mechanical Outline (6)3.2Connector Footprint (7)3.3Top Mounted Connector (8)3.4Schematic Symbol (Signals of P1 and P2) (9)3.5Connectors Pin Assignment P1 – (1-60) (10)3.6Connector Pin Assignment P2 – (61-120) (11)3.7ITU656 Camera Connector P3 (1-22) (12)3.8Connector P4 (1-10) (12)4Test Points (13)4.1Footprint – Test Points (13)5Application Examples (14)5.1Sample Application (14)5.2Stand-alone Camera System (15)5.3Generic Signal Processing System (15)5.4Coprocessor Application (15)5.5Digital Video System (16)5.6Design Services (16)6Software Support (17)6.1BLACKSheep (17)6.2uClinux (17)7Known Bugs (18)8Product Changes (19)9Document Revision History (20)A List of Figures and Tables (21)Edition 2007-02© Bluetechnix Mechatronische Systeme GmbH 2007All Rights Reserved.The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics.Terms of delivery and rights of technical change reserved.We hereby disclaim any warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Bluetechnix makes and you receive no warranties or conditions, express, implied, statutory or in any communication with you. Bluetechnix specifically disclaims any implied warranty of merchantability or fitness for a particular purpose.Bluetechnix takes no liability for any damages and errors causing of the usage of this board. The user of this board is responsible by himself for the functionality of his application. He is allowed to use the board only if he has the qualification. More information is found in the General Terms and Conditions (AGB).InformationFor further information on technology, delivery terms and conditions and prices please contact Bluetechnix ().WarningsDue to technical requirements components may contain dangerous substances.BLACKFIN ProductsCore Modules:CM-BF533: Blackfin Processor Module powered by Analog Devices single coreADSP-BF533 processor; up to 600MHz, 32MB RAM, 2MB Flash,120 pin expansion connector and a size of 36.5x31.5mmCM-BF537E: Blackfin Processor Module powered by Analog Devices single coreADSP-BF537 processor; up to 600MHz, 32MB RAM, 4MB Flash,integrated TP10/100 Ethernet physical transceiver, 120 pin expansionconnector and a size of 36.5x31.5mmCM-BF537U: Blackfin Processor Module powered by Analog Devices single coreADSP-BF537 processor; up to 600MHz, 32MB RAM, 4MB Flash,integrated USB 2.0 Device, 120 pin expansion connector and a size of36.5x31.5mmTCM-BF537: Blackfin Processor Module powered by Analog Devices single coreADSP-BF537 processor; up to 500MHz, 32MB RAM, 8MB Flash,28x28mm, 120 pin expansion connector, Ball Grid Array or BorderPads for reflow soldering, industrial temperature range -40°C to+85°C.CM-BF561: Blackfin Processor Module powered by Analog Devices dual coreADSP-BF561 processor; up to 2x 600MHz, 64MB RAM, 8MBFlash, 120 pin expansion connector and a size of 36.5x31.5mmCM-BF527: From Q3 '07 a new Blackfin Processor Module powered by AnalogDevices single core ADSP-BF527 processor will be available; keyfeatures are USB OTG 2.0 and Ethernet. 2x120pin expansionconnectors are backwards compatible to other Core Modules.CM-BF548: From Q3 '07 a new Blackfin Processor Module powered by AnalogDevices single core ADSP-BF548 processor will be available; keyfeatures are 64MB DDR SD-RAM 2x100pin expansion connectors.Development Boards:EVAL-BF5xx: Low cost Blackfin processor Evaluation Board with one socket forany Bluetechnix Blackfin Core Module. Additional periphery isavailable, such as a SD-Card.DEV-BF5xxDA-Lite: Get ready to program and debug Bluetechnix Core Modules with thistiny development platform including a USB Based Debug Agent. TheDEV-BF5xxDA-Lite is a low cost starter development systemincluding VDSP++ Evaluation Software License.DEV-BF5xx-FPGA: Backfin Development Board with two sockets for any combination ofBlackfin Core Modules. Additional periphery is available, such asSD-Card, Ethernet, USB host, multi-port JTAG including a USBbased Debug Agent, connector for a LCD-TFT Display and connectorfor a digital camera system. A large on-board SPARTAN-3 FPGAand Soft IPs make this board the most flexible Blackfin developmentplatforms ever developed.Available Q2 2007EXT-Boards: The following Extender Boards are available: EXT-BF5xx-Audio,EXT-BF5xx-Video, EXT-BF5xx-Camera, EXT-BF5xx-Exp, *EXT-BF5xx-LVDS, *EXT-BF5xx-ETH-USB, *EXT-BF5xx-AD/DA.Additional boards based on customer request*Available Q2 2007Software Support:BLACKSheep: The BLACKSheep VDK is a multithreaded framework for theAnalog Devices Blackfin processor family that includes driversupport for a variety of hardware extensions. It is based on the real-time VDK kernel included within the VDSP++ developmentenvironment.LabVIEW: LabVIEW embedded support for the CM-BF537E, CM-BF537U andTCM-BF537 Core Modules based on the BLACKSheep VDK driverFramework.uClinux: All the Core Modules are supported by uClinux. The required bootloader and uClinux can be downloaded at .BLACKFIN Design ServiceBased on over three years Blackfin experience Bluetechnix offers development assistance as well as custom design services and software development.1 IntroductionThe CM-BF533 is a tiny, high performance and low power DSP/RISC core module incorporating Analog Devices Blackfin family of processors. The module allows easy integration into high demanding very space and power limited applications.1.1 OverviewThe Core Module CM-BF533 consists of the following components:Figure 1-1: Main Components of the CM-BF533 module▪Analog Devices Blackfin Processor BF533o ADSP-BF533SKBCZ600 (0°-70°C) Standard mounto ADSP-BF533SBBCZ500 (-40°-85°C) Option upon request▪32 MB SDRAMo SDRAM clock up to 133 MHzo MT48LC16M16A2BG-7 (16Mx16 at 3.3 V)▪2MB of Addressable Flasho ITLRC28F320J3C110 (2Mx16 at 3.3 V; 2MByte addressable only)o Additionally flash memory can be connected through the expansion board as parallel flash using asynchronous chip select lines or as a SPI flash.▪Low Voltage Reset Circuito Resets module if power supply goes below 2.93 V for at least 140 ms▪Dynamic Core Voltage Controlo Allows to adjust core voltage by setting software registers at the Blackfin Processoro Core voltage range: 0.8 – 1.32V▪Expansion Connector Ao Data Buso Address Buso Control Signalso Power Supply▪Expansion Connector Bo SPORT 0 and SPORT 1o JTAGo UARTo SPIo PPI (Parallel Port Interface)o GPIO’s1.2 Benefits▪The CM-BF533 is very compact and measures only 36.5x31.5mm▪Allows quick prototyping of product that comes very close to the final design ▪Reduces development costs, faster time to market▪Very cost effective for small and medium volumes1.3 Applications▪Generic high performance signal processor module▪Internet Connected Embedded System▪High performance web camera▪Robotics: Tiny processor module for mobile robots2 Specification2.1 Functional SpecificationFigure 2-1: Detailed Block DiagramFigure 2-1 shows a detailed block diagram of the CM-BF533 module. Beside the SDRAM control pins the CM-BF533 has all other pins of the Blackfin processor at its two main 60 pin connectors.Dynamic voltage control allows reducing power consumption to a minimum adjusting the core-voltage and the clock frequency dynamically in accordance to the required processing power.A low voltage reset circuit guarantees a power on reset and resets the system when the input voltage drops below 2.93V.2.2 Boot ModeDefault Boot Mode = 00 (BMODE1 = LOW, BMODE0 = LOW)BMODE0, BMODE1 has internal pull-down resistorConnect BMODE0 to Vcc and leave BMODE1 pin open for Boot Mode 01 (equals to 8 or 16 bit PROM/FLASH boot mode), this is the default boot mode of the Blacksheep software. See Blackfin Datasheets or Eval/DevBoard manuals for more details.2.3 Memory MapTable 2-1: Memory Map2.4 Electrical Specification2.4.1 Supply Voltage▪ 3.3 V DC +/-10%2.4.2 Supply Voltage Ripple▪100 mV peak to peak 0-20MHz2.4.3 External Oscillator Frequency▪25MHz2.4.4 Real Time Clock Crystal▪32.768kHz2.4.5 Supply Current▪Maximumsupplycurrent:**********▪Operating conditions:o Processor running at 600MHz, Core Voltage 1.2V, SDRAM 20% bandwidth utilization at 130MHz: 150mAo Processor running at 300MHz, Core Voltage 0.8V SDRAM 20% bandwidth utilization at 130MHz: 90mA2.5 Environmental Specification2.5.1 TemperatureDevelopment Version:▪Operating at full 600MHz: 0 to + 70° CIndustrial Version: (Only available upon request at a MOQ)2.5.2 HumidityOperating: 10% to 90% (non condensing)3 CM-BF533 (Connector Version)3.1 Mechanical OutlineTOP VIEWAll dimensions are given in millimeters!P336.517.57.059.2532.46.8526.7528.0531.522.450.60.35Ø0.652.551.7P1P27.759.0514.653452Figure 3-1: Mechanical outline and Bottom ConnectorsThe mechanical outline represents a top view of the connectors placed at the bottom of the core board.The module is shipped with two 60pin connectors.Figure 3-2: Side View with Connector mountedThe total minimum mounting height including receptacle at the motherboard is 6.1 mm.3.2 Connector FootprintIf the connector version (2x Hirose 0.6mm pitch) is used, the footprint for the baseboard may look as shown in Figure 3-3.For the baseboard the following connectors have to be used:Table 3-1: Baseboard connector typesThe connectors on the CM-BF533 are of the following type:Table 3-2: Module connector types36.526.7531.57.756.85Figure 3-3: Connector Footprint for Baseboard3.3 Top Mounted ConnectorThe optionally mounted connector P4 will not be supported in future versions.Figure 3-4: TOP VIEW3.4 Schematic Symbol (Signals of P1 and P2)SPORT0SPORT1PPIUARTSPIJTAGDataBusAddr.BusControlSignals Figure 3-5: Schematic Symbol of Module3.5 Connectors Pin Assignment P1 – (1-60)Table 3-3: Connector P1 pin assignmentAll Pin names of the connectors correspond to the names found in the Blackfin BF533 datasheet from Analog Devices.3.6 Connector Pin Assignment P2 – (61-120)Table 3-4: Connector P2 pin assignmentNon processor Pins:CLK_OUT: 25MHz buffered output clock of main oscillatorAll other pins are connected directly to the respective ADSP-BF533 processor pins.For details about the meaning of the signal names consult the Blackfin ADSP-BF533 datasheet.3.7 ITU656 Camera Connector P3 (1-22)The ITU656 connector has been tested only for the OmniVision cameras available in our camera kit Kit-CAM-OV. It is not recommended to use this connector!Table 3-5: Connector P3 pin assignment3.8 Connector P4 (1-10)The top optionally mounted connector P4 can be used as a stand-alone connector for a system requiring only power supply and one or two communication ports (UART and SPI)Table 3-6: Connector P4 pin assignment4 Test Points4.1 Footprint – Test Points9.859.251.25.057.4510.751.7524.0526.4529.7520.751233031322960596162909192119120Ø0.731.536.5Figure 4-1: Test Points of the Core Module5 Application Examples5.1 Sample ApplicationIn this minimum configuration the CM-BF533 is used as a high performance SPI-based co-processor module.Figure 5-1: Minimum Configuration with SPI and JTAG Connector5.2 Stand-alone Camera SystemThe CM-BF533 module can be used as a stand-alone module for a camera system requiring only power supply and the direct attachment of a compatible video camera. A camera kit including drivers can be purchased from Bluetechnix: KIT-CAM-OV (O.Nr 100-9901) The digital ITU656 camera directly connects to P3 while the power supply and any of two communication ports (SPI and UART) can be connected to the 10 pin P4 connector as well as over the large connectors P1 and P2 at the bottom.3.3 V Power, SPI, UARTFigure 5-2: Stand-alone Camera System5.3 Generic Signal Processing SystemFigure 5-3: Block Diagram – Analog Signal Processing Module5.4 Coprocessor ApplicationFigure 5-4: Block Diagram – Coprocessor Module5.5 Digital Video SystemFigure 5-5: Block Diagram: Digital Video System5.6 Design ServicesBluetechnix offers custom design services and software development.6 Software Support6.1 BLACKSheepThe Core Module is delivered with a pre-flashed basic version of the BLACKSheep VDK multithreaded framework. It contains a boot-loader for flashing the Core Module via the serial port.Please mind the software development documents.6.2 uClinuxThe Core Module is supported by the open source platform at . Since the Core Modules are pre-flashed with BLACKSheep you have to flash uBoot first. For flashing the uBoot you can use the BLACKSheep boot-loader.7 Known BugsTable 7-1: Known Bugs8 Product ChangesTable 8-1: Product Changes9 Document Revision HistoryTable 9-1: Revision HistoryA List of Figures and TablesFiguresFigure 1-1: Main Components of the CM-BF533 module (1)Figure 2-1: Detailed Block Diagram (3)Figure 3-1: Mechanical outline and Bottom Connectors (6)Figure 3-2: Side View with Connector mounted (6)Figure 3-3: Connector Footprint for Baseboard (7)Figure 3-4: TOP VIEW (8)Figure 3-5: Schematic Symbol of Module (9)Figure 4-1: Test Points of the Core Module (13)Figure 5-1: Minimum Configuration with SPI and JTAG Connector (14)Figure 5-2: Stand-alone Camera System (15)Figure 5-3: Block Diagram – Analog Signal Processing Module (15)Figure 5-4: Block Diagram – Coprocessor Module (15)Figure 5-5: Block Diagram: Digital Video System (16)TablesTable 2-1: Memory Map (4)Table 3-1: Baseboard connector types (7)Table 3-2: Module connector types (7)Table 3-3: Connector P1 pin assignment (10)Table 3-4: Connector P2 pin assignment (11)Table 3-5: Connector P3 pin assignment (12)Table 3-6: Connector P4 pin assignment (12)Table 7-1: Known Bugs (18)Table 8-1: Product Changes (19)Table 9-1: Revision History (20)。

Micromaster440 调试参数

Parameter (参数)Value (设定值)Description (描述)P10802最低频率P108250最高频率P112010斜坡上升时间-电动机从静止状态加速到最高频率所用的时间(如果设定的斜坡上升时间过短,就可能导致变频器跳闸--过电流)P112110斜坡下降时间-电动机从最高频率减速到静止停车所用的时间(如果设定的斜坡下降时间过短,就可能导致变频器跳闸--过电流/过电不用快速调试1结束快速调试,并按工厂设置使参数复位2结束快速调试3结束快速调试,只进行电动机数据的计算P00033P07331变频器运行准备就绪P00101P0700.01BOP 控制有效P0700.16COM 链路的通讯板(CB)设置P0733.01P0733.11P08102090.15(.F.)远程控制 (2090.F) / MCC 控制 0P0918XX 地址49CB.Address 通讯地址P1000.01电动电位计设定P1000.16通过COM 链路的CB 设定P2051.052P2051.121P2051.227P2051.353P2051.432P2051.535P0601.01PTC （正温度系数）热敏元件第一驱动数据组（DDS ）P0601.11PTC （正温度系数）热敏元件第二驱动数据组（DDS ）P0604XX 电动机温度保护的门限值0除报警外无应对措施1报警并降低最大电流Imax （引起输出频率降低）2报警和跳闸（F0011）P062520电动机运行的环境温度P0640150%电动机过载因子P3900结束快速调试P0610电动机过温应对措施↓↓进入数据计算Busy...↓主电源接触器吸合第一步完成,重新核对参数↓调设状态字 P2051↓温度保护项调设。

西门子变频器说明书下载

6SE6400-1PB00-0AA0 6SE6400-1DN00-0AA0 6SE6400-0EN00-0AA0
MICROMASTER 变频器
410
420
430
440
可以进行配置的组合
操作面板
BOP/OP
AOP
BOP-2
模块
PROFIBUS 通讯模块
4
Siemens DA51.2 • 2002
DeviceNet 通讯模块
0.12 kW 至 0.75 kW 100 V 至 120 V，单相交流 200 V 至 240 V，单相交流
控制
过程控制输入输出与自动化系统的接口附加特点
线性 V/f 控制特性多点设定的 v/f 控制特性 (可编程的 v/f 控制特性) FCC (磁通电流控制)
-
3 个数字输入 1 个模拟输入
快速电流限制 (FCL)，防止运行中不应有的跳闸
MICROMASTER 410
说明
快速的，可重复的数字输入响应时间
采用高分辨率的 10 位二进制模拟输入，实现输入的精确设定
具有一个跳转频率
用于 (中性点) 不接地的供电电源 (IT电源) 时具有可折
卸的“Y”形接线电容器
采用 USS 协议的 RS 485 串行通讯接口
0.12 kW 至 11 kW 200 V 至 240 V，单相交流 200 V 至 240 V，三相交流 380 V 至 480 V，三相交流
线性 V/f 控制特性多点设定的 v/f 控制特性 (可编程的 v/f 控制特性) FCC (磁通电流控制)
内置 PI 控制器
3 个数字输入 1 个模拟输入
线性 v/f 控制特性多点设定的 v/f 控制特性 (可编程的 v/f 控制特性) FCC (磁通电流控制) 矢量控制内置的 PID 控制器 (带参数自整定功能) 6 个数字输入 2 个模拟输入 1 个用于电动机过热保护的 PTC/KTY 输入 2 个模拟输出 3 个继电器输出是 SIMATIC S7-200，SIMATIC S7-300/400 (TIA) 或 SIMOTION 自动化系统的理想配套设备。

相机术语中英文对照表

59 color property 60 color temperature meter 61 preferences
62 standard white 63 false color 64 image recording quality 65 recording image quality 66 recording pixel count 67 image protection and erase 68 image recording format 69 recording media 70 cloudy 71 creative zone 72 processing 73 processing parameters 74 optical viewfinder 75 active AF point indicator 76 merge 77 frame
126 tab sheet 127 [Remove checkmark] button 128 autoflash system
129 noise reduction for long exposures 130 communication 131 TIFF format 132 TTL auto white balance 133 TTL 3 point AiAF (1 point measurement is possible) 134 apply 135 digital AF/AE SLR 136 digital signature 137 digital zoom 138 digital terminal 139 digital exposure compensation 140 digital exposure compensation amount
transmitting images to or from a CF card (while 141 connecting to a computer) 142 Design rule for Camera File system (sRGB143 cDoemsipglniarnutl)e for Camera File system, DPOF-compliant

533mcp 参数

533mcp 参数什么是533mcp？533mcp是一种参数，用于描述和控制电子设备的性能和功能。

533mcp代表着五个不同的参数，分别是：5G网络、3GB RAM、3GB存储容量、5000mAh电池容量和13MP相机。

5G网络5G网络是下一代移动通信技术，提供更快的速度、更低的延迟和更大的容量。

它将带来更好的网络体验，支持更多的设备连接和更快的数据传输。

533mcp中的5G网络意味着设备可以在5G网络下进行高速的互联网访问，观看高清视频、玩游戏和下载文件都将更加快速和稳定。

3GB RAMRAM（随机存取存储器）是电子设备中的一种内存，用于临时存储正在运行的程序和数据。

533mcp中的3GB RAM表示设备具有3GB的内存，可以同时运行多个应用程序和任务，提供流畅的用户体验。

较大的RAM容量还可以提高设备的多任务处理能力和性能。

3GB存储容量存储容量是指设备用于存储数据和文件的空间大小。

533mcp中的3GB存储容量意味着设备具有3GB的可用存储空间，可以存储大量的应用程序、照片、视频和文件。

用户可以轻松地保存和访问他们的个人和工作文件，而不必担心空间不足的问题。

5000mAh电池容量电池容量是指电池存储的电荷量，它决定了设备能够提供的使用时间和续航能力。

533mcp中的5000mAh电池容量表示设备具有5000毫安时的电池容量，可以提供较长的使用时间。

用户可以更长时间地使用设备，而不必频繁充电。

高容量的电池还可以支持设备在高负载情况下的稳定运行。

13MP相机相机是设备中的一个重要功能，用于拍摄照片和录制视频。

533mcp中的13MP相机表示设备具有1300万像素的摄像头。

较高的像素数意味着设备可以拍摄更清晰、更详细的照片和视频。

用户可以捕捉到更多的细节，并享受更好的拍摄体验。

总结533mcp参数包括5G网络、3GB RAM、3GB存储容量、5000mAh电池容量和13MP相机。

这些参数提供了一种全面、高性能的电子设备体验。

RICOH MP C3003 MP C3503 MP C4503 MP C5503 MP C60

Copieur Imprimante Télécopieur NumériseurMP C4503monochrome 45MP C3503monochrome 35MP C3003monochrome 30Puissance, précision et productivité — pour vousLa gamme d’appareils multifonctions (MFP) RICOH® MP C3003/MP C3503/MP C4503/ MP C5503/MP C6003 est conçue pour travailler comme vous le souhaitez. Elle combine une production couleur de qualité supérieure à des capacités génératrices de productivité pour que vous puissiez tirer parti d’encore plus d’information et de façon plus intelligente. Transformez votre MFP en portail d’information en vous connectant au nuage à partir de votre téléphone intelligent, de votre tablette ou d’un autre appareil sans fil et utilisez ces systèmes puissants pour imprimer, partager et découvrir la valeur de la commodité personnalisée. Offrant une polyvalenceévoluée et débordant de fonctions d’économie d’énergie dans un design compact, ce système est parfait pour les bureaux au rythme rapide ayant des charges de travail importantes. Choisissez-le comme système principal pour votre groupe de travail ou en tant que partie intégrante de la stratégie de services de gestion de documents (MDS) et stimulez votre productivité dans l’ensemble de votre organisation.• Haute performance et commodité dans un design compact et silencieux• Connectivité mobile pour un flux de travaux plus efficace et plus rapide• Commandes intuitives et connues pour une performance polyvalente et multifonction• Une solution unique pour l’impression, la copie, la numérisation et la télécopie (facultative) plus intelligente • Un rendement écoénergétique mesurable qui permet d’économiser de l’énergie, de réduire la consommation et de diminuer les coûts d’exploitationHarmoniser les flux de travaux pour améliorer la productivité Capacités évoluées pour un contrôle pratiqueUne production rapide et fiableCette gamme de MFP puissants et novateurs offre une productionmonochrome ou couleur de qualité supérieure à une vitesse allant jusqu’à60 ppm pour un débit incroyable. Alors que les systèmes Ricoh MP C3003et MP C3503 sont munis d’un dispositif d’alimentation automatique inversée(ARDF) de 100 feuilles, les appareils MP C4503, MP C5503 et MP C6003offrent un chargeur recto-verso à un seul passage (SPDF) standard de 220feuilles pour une numérisation rapide recto-verso de 180 ipm. Sélectionnezle finisseur* interne pour gagner de l’espace ou choisissez à partir d’unevaste gamme de finisseurs externes pour accélérer le flux des travaux.*Non offert sur le MP C6003Une fonctionnalité simpleRéalisez avec simplicité même les tâches les plus complexes. Lepanneau de contrôle inclinable couleur de 9 po du MFP vous permetd’accéder facilement à plusieurs caractéristiques. Retirez rapidementles erreurs de chargement en suivant les guides animés synchronisésou les voyants DEL** qui vous aident à identifier la source du problème.En plus, la fonction de retrait automatique complète permet aux bacsde retourner automatiquement en position fermée lorsque l’utilisateurpousse le bac pour le refermer.**Les voyants DEL ne sont pas offerts sur le MP C3003/MP C3503La performance partout et en touttempsLes systèmes MP C3003/MP C3503/MP C4503/MP C5503/MPC6003 de Ricoh peuvent imprimer à partir de plusieurs appareilsmobiles, incluant les téléphones intelligents, les tablettes ou lesordinateurs portables, sans utiliser de pilotes spécifiques auxappareils, et ce, pour une commodité sur le terrain incroyable. Pourles organisations qui souhaitent une impression mobile encore plussûre, le logiciel Ricoh HotSpot® MFP ou Ricoh HotSpot® EnterpriseServer offert en option peut être installé pour aider à améliorer laproductivité mobile sans compromettre la sécurité des données,des documents ou de l’utilisateur. De plus, les utilisateurs peuventimprimer des fichiers JPEG, TIFF et PDF en utilisant une clé USB ouune carte SD directement à l’appareil sans avoir besoin d’un accèsLAN ou d’applications natives.équipée pour tous les bureaux12534666877Appareil Ricoh MP C6003 illustré avec le finisseur facultatif SR3160, 1 bac (BN3110), une banque de papier à2 tiroirs (PB3160)123456786offertes dans un design compactAppareil Ricoh MP C3503 illustré avecle finisseur de livret SR3150 facultatif,bac à un tiroir (BN3110), 1 bac à grandecapacité tandem (PB3170) et un bac LCTsur le côté (RT3030)6Mémoire 2 GoRicoh Canada Inc., 100-5560 Explorer Drive, Mississauga, ON L4W 5M3, 1-888-742-6417Ricoh® et le logo Ricoh sont des marques de commerce enregistrées de Ricoh Company, Ltd. Toutes les autres marques de commerce sont la propriété de leur propriétaire respectif. Tous droits réservés. Le contenu de ce document, de même que l’apparence, les fonctions et les caractéristiques des produits de Ricoh peuvent changer de temps à autre sans préavis. Les produits illustrés comportent des options. Même après avoir pris toutes les précautions possibles pour assurer l’exactitude de l’information, Ricoh ne fait aucune déclaration ni ne garantit l’exactitude de l’information contenue dans le présent document et n’accepte aucune responsabilité à l’égard de toute erreur ou omission dans ledit texte. Les résultats réels peuvent varier selon l’utilisation faite des produits et des services, ainsi que les conditions et les facteurs pouvant affecter la performance. Les seules garanties relatives aux produits et services de Ricoh sont exposées dans les énoncés de garantie formelle s’y rattachant.www.ricoh.ca。

PowerPC 440中文资料

The PowerPC® 440 Core A high-performance, superscalar processor core for embedded applicationsIBM Microelectronics DivisionResearch Triangle Park, NC09/21/1999OverviewThe PowerPC 440 CPU core is the latest addition to IBM’s family of 32-bit RISC PowerPC embedded processor cores. The PPC440’s high-speed, superscalar design and Book E Enhanced PowerPC Architecture™ put it at the leading edge for high performance system-on-a-chip (SOC) designs. The PPC440 core marries the performance and features of standalone microprocessors with the flexibility, low power, and modularity of embedded CPU cores.Target ApplicationsThe PPC440 Core is primarily designed for applications in which maximum performance and extensive peripheral integration are the critical selection criteria.Target market segments for the PPC440 core include:•Consumer applications including digital cameras, video games, set-top boxes, and internet appliances •Office automation products such as laser printers, thin-client systems, and sub-notebooks •Storage and networking products such as RAID controllers, routers, ATM switches, cellular basestations, and network cardsFeatures•2-way superscalar design•Out-of-order issue, execution, and completion•Dynamic branch prediction•Single-cycle branch latency•Three execution pipelines•Single-cycle throughput on 32x32 multiply•24 DSP operations (16x16+32->32, MAC with single-cycle throughput)•Real-time non-invasive instruction traceTypical ApplicationA typical system on a chip design with the PPC440 Core uses the CoreConnect TM bus structure for system level communication. High bandwidth peripherals and the PPC440 core communicate with one another over the processor local bus (PLB). Less demanding peripherals share the on-chip peripheral bus (OPB) and communicate to the PLB through the OPB Bridge. The PLB and OPB provide common interfaces for peripherals and enable quick turnaround, custom solutions for high volume applications.F igure 1 shows an example PPC440 Core-based system on a chip, illustrating the two-level bus structure and modular core-based design.Figure 1. Example PPC440 Core + ASIC SpecificationsPerformance (Dhrystone 2.1)1000 MIPS @ 555MHz (est.), Nominal silicon, 1.8V, 55°C 720 MIPS @ 400MHz (est.), Slow silicon, 1.65V, 85°CFrequency0 – 400MHz , Slow silicon, 1.65V, 85°C555MHz nominalPower Dissipation 2.5mW / MHz @ 1.8V (est.), hard core with 32KI / 32KD cachesArchitecture32-bit PowerPC Book E compliant, application code compatible withall PowerPC processorsDie Size 4.0 mm2 for CPU only (est.)Caches0-64KB, 32-way to 128-way associativeTechnology0.18 µm CMOS copper technology0.12 µm L eff , 4 levels of metalPower Supply 1.8 VoltsTransistors 5.5M, hard core with 32KI / 32KD cachesOperating Range-40°C to 125°C, 1.6V to 1.9VData Bandwidth Up to 6.4 GB/sec via three 128-bit, 200MHz CoreConnect businterfacesTable 1- 440 CPU Core SpecificationsEmbedded Design SupportThe PPC440 Core, as a member of the PowerPC 400 Family, is supported by the IBM PowerPC Embedded Tools TM program, in which over 80 third party vendors have combined with IBM to provide a complete tools solution. Development tools for the PPC440 include C/C++ compilers, debuggers, bus functional models, hardware/software co-simulation environments, and real-time operating systems. As part of the tools program, IBM maintains a complete set of development tools by offering the High C/C++ Compiler, RISCWatch TM debugger with RISCTrace TM trace interface, VHDL and Verilog simulation models and a PPC440 Core Superstructure development kit.PPC440 CPU Core OrganizationPPC440 CPUThe PPC440 CPU operates on instructions in a dual issue, seven stage pipeline, capable of dispatching two instructions per clock to multiple execution units and to optional Auxiliary Processor Units (APUs). The PPC440 core is shown in Figure 2.Figure 2 - PPC440 Core Block DiagramThe pipeline contains the following stages, as shown in Figure 3:1.IFTH – Fetch instructions from instruction cache2.PDCD – Pre-decode; partial instruction decode3.DISS – Decode/Issue; final decode and issue to units4.RACC – Register Access; read from multi-ported General Purpose Register (GPR) file5.EXE1/AGEN – Execute stage 1; complete simple arithmetics, generate load/store address6.EXE2/CRD – Execute stage 2; multiplex in results from units in preparation for writing into GPRfile, Data Cache access7.WB – Writeback; write results into GPR file from integer operation or load operationFigure 3 - PPC440 CPU PipelineInstruction Fetch and Pre-decodeDuring the Instruction Fetch stage (IFTH), an entire cache line (eight words) is read into the instruction cache line read buffer. From there, the next two instructions in the pre-decode buffers PDCD0 and PDCD1 during the PDCD stage. The instruction cache is virtually indexed and tagged, and translation is performed in parallel with the cache access.Branch UnitThe PPC440 uses a Branch History Table (BHT) to maintain dynamic branch prediction of conditional branches. To perform dynamic branch prediction, a 2-bit counter in the BHT is used to decide whether prediction should agree or disagree with the normal PowerPC static branch prediction. The counter counts up if branch determination agrees, and down if it disagrees. Once the counter saturates, it can only count away from saturation. Therefore, four valid states exist: “Strongly agree”, “Agree”, “Disagree”, and “Strongly disagree”. By agreeing or disagreeing with static branch prediction, different branches can use the same counter in the BHT and have opposite static predictions, without the machine necessarily mispredicting a branch.The Branch Target Address Cache (BTAC) is used to predict branches and deliver their target addresses before the instruction cache can deliver the same data. It is accessed during IFTH, whereas normal branch prediction would not occur until PDCD, and therefore avoids a one cycle penalty. The BTAC is made up of an odd and even BTAC containing eight entries each. Only unconditional branches and bdnzinstructions are stored, which gives a significant performance boost while keeping the design straightforward.Decode and IssueThe four-entry decode queue accepts up to two instructions per clock submitted from the pre-decode buffers. Instructions always enter the lowest empty or emptying queue position, behind any instructions already in the queue. Therefore, the queue fills from the bottom up, instructions stay in order, and no bubbles exist in the queue. A significant portion of decode is performed in the lowest two positions (DISS0 and DISS1). Up to two instructions exit the queue based on the instructions’ decode and pipeline availability, and are issued to the RACC stage. DISS1 can issue out of order with respect to DISS0. Register AccessConceptually, the GPR file consists of thirty-two, 32-bit general purpose registers. It is implemented as two 6-port arrays, (one array for LRACC, one for IRACC) each with thirty-two, 32-bit registers containing three write ports and three read ports. On all GPR updating instructions, the appropriate GPR write ports will be written in order to keep the contents of the files the same. On GPR reads, however, the GPR read ports are dedicated to instructions that are dispatched to a RACC’s associated pipe(s). Execution PipelinesThe PPC440 contains three execution pipes: a load/store pipe (“L-pipe”), a simple integer pipe (“J-pipe”), and a complex integer pipe (“I-pipe”). The L-pipe and J-pipe instructions are dispatched from the LRACC; I-pipe instructions are dispatched from IRACC. The three pipes together perform all 32-bit PowerPC integer instructions in hardware compliant with the PowerPC Book E specification. Table 2 lists the rules for dispatching to each of the three execution pipes.L-pipe only Loads/stores1, cache instructions, mbar, msyncI-pipe or J-pipe2Add, addi, addis, and, andc, cntlzw, eqv, extsb, extsh, nand, neg, nor, or, orc, ori, oris, xori, xoris, rlwimi, rlwinm, rlwnm, slw, srw, subfI-pipe only Branches, multiplies, divides, move to/from DCR/SPR, indirect XER updates,indirect LR/CTR updates, indirect CR updates, CR-logicals, MAC instructions,mcrf, mcrxr, mtcrf, mfcr, compares, dlmzb, isync, rfi, rfci, sc, wrtee, wrteei,mtmsr, mfmsr, trapsTable 2 – Rules for Instruction IssueThe MAC unit is an auxiliary processor unit (APU) which adds 24 operations to the PPC440 instruction set. MAC instructions operate on either signed or unsigned 16 bit operands and accumulate the results in a 32-bit GPR. All MAC unit instructions have single cycle throughput. The MAC unit is contained within the I-pipe.1 The stwcx. instruction goes down both the L-pipe as well as the I-pipe, in order to update the CR.2 Instructions which update the CR or XER are not issued to the J-pipe.Instruction and Data CachesProcessor Local Bus (PLB) Memory AccessThe PPC440 has three independent 128-bit Processor Local Bus (PLB) master interfaces, one for instruction fetches, one for data reads, and a third for data writes. Memory accesses are performed through the PLB interfaces to/from the instruction cache (I-Cache) or data cache (D-Cache) units. Having three independent bus interfaces for the cache units provides maximum flexibility for designs to optimize system throughput. Memory accesses (loads/stores) which hit in the cache achieve single-cycle throughput.Cache ConfigurationThe PPC440 has separate instruction and data caches with 8 word (32 byte) cache lines. Instruction and data cache sizes are factory-configurable to any combination of 0KB, 8KB, 16KB, 32KB, or 64KB cache sizes. Configurable cache sizes provide designers with a parameter for optimizing the PPC440 to a desired price-performance for a particular application. The caches are highly associative, with associativity varying with cache size as shown in Table 3. High associativity enables advanced cache functions such as locking and transient memory regions (see “Cache Partitioning” below).Cache Size Ways8 KB3216KB6432KB6464KB128Table 3 – Number of Ways for Different PPC440 Cache SizesThe cache arrays are non-blocking. Non-blocking caches allow the PPC440 to overlap execution ofload/store instructions while instruction fetches take place over the PLB. The caches, therefore, continue supplying data and instructions without interruption to the pipeline. The PPC440 replaces cache lines according to a round-robin replacement policy.The initial PPC440A4 core offering will include a 32KB instruction cache and 32KB data cache. These caches are physically constructed using two, 16KB CAMRAM macros, each consisting of 8, 2KB sub-banks (or “sets”). This organization facilities low-power operation and fast hit/miss determination. Cache PartitioningThe PPC440 caches have the ability to be separated into “normal”, “transient”, and “locked” regions. Normal regions are what is traditionally thought of regarding cache replacement. Transient regions are used for data that is used temporarily and then not needed again, such as the data in a particular JPEG image. A separate transient region avoids castouts of more commonly accessed code in the normal region. The locked region is for code that is not to be cast out of the cache, and is the resulting region not included in the normal and transient regions. The regions are set via “victim” ceiling and floor pointers, as shown in Figure 4. Figure 4 shows two examples of cache partitioning, the left side shows separate transient and normal regions, and the right side shows part of the normal region overlapping with the transient region. The normal ceiling is defined as the top of the cache.Figure 4 – Two Examples of Cache PartitioningI-Cache Speculative Pre-fetchingThe I-Cache utilizes a programmable speculative pre-fetch mechanism to enhance performance. Software can enable up to three additional lines to be speculatively pre-fetched, using a burst protocol, upon any instruction cache miss. When this mode is enabled, the I-Cache controller will automatically inspect the I-Cache on a miss to see if any of up to the next three lines are also misses. If so, the hardware will present a burst request to the PLB immediately after the original line fill request. This speculative burst request takes advantage of the throughput capability of standard memory architectures such as SDRAM and brings in anticipated subsequent instructions after a miss. Furthermore, if the instruction stream branches away from the lines which are being speculatively filled, the burst request which is filling the speculative lines can be abandoned in the middle, and a new fill request at the branch target location immediately initiated. There is a programmable "threshold" to determine when to abandon a speculative line fill that may have been in progress at the time of a branch redirection. This threshold designates how many doublewords of the speculative cache line must be received to not abandon a current line fill. In this fashion, the speculative pre-fetch mechanism can be carefully tailored to provide optimum performance for specific applications and memory subsystems.D-Cache Line FillsThe D-Cache contains three line fill buffers and can queue up to four load misses to three separate cache lines. The PPC440 will then execute past these load misses, until the queue is full or the pipes are held waiting for a load value. The D-Cache controller places the target word on the bypass path as the fill buffer captures data words off the PLB. Additional requests of the cache line held in the fill buffer are also forwarded directly to the operand registers in the execute unit.D-Cache Non-cacheable Store GatheringThe D-Cache “gathers” up to 16 bytes for non-cacheable, write-through, and w/o allocate stores, and will burst the quadword to the PLB for fast writes to non-cacheable memory.D-Cache Write-Back and Write-Through ModesThe D-Cache supports write-back or write-through mode. In write-back mode, store hits are written to the cache and not to main memory. Main memory is later modified if and when the line is flushed from the cache. In write-through mode, the data cache controller writes main memory for store misses as well asstore hits; every store operation generates a PLB write request. (Although write-through requests to non-cacheable memory can be gathered as previously mentioned).D-Cache Store AllocationThe D-Cache can be programmed whether or not to allocate a line on a D-Cache store miss. Write-on-allocate is enabled by default. In this mode, a store miss to cacheable memory forces the data cache controller to allocate a line in the data cache and generate a line fill. In contrast, when “without allocate”is enabled, a store miss to cacheable memory will not allocate a line data cache and will simply write the data to memory.Big Endian and Little Endian SupportThe PPC440 supports big endian or little endian byte ordering for instructions and data stored in external memory. The PowerPC Book E architecture is endian neutral; each page in memory can be configured for big or little endian byte ordering via a storage attribute contained in the TLB entry for that region. Strapping signals on the PPC440 core initialize the beginning TLB entry’s endian attribute, so thePPC440 can boot from little or big endian memory.Memory Management Unit (MMU)The MMU supports multiple page sizes as well as a variety of storage protection attributes and access control options. Multiple page sizes improve TLB efficiency and minimize the number of TLB misses. The PPC440 gives programmers the flexibility to have any combination of the following eight possible page sizes in the translation look-aside buffer (TLB) simultaneously: 1KB, 4KB, 16KB, 64KB, 256KB,1MB, 16MB and 256MB. Having an extremely large page size allows users to define system memory with a minimal number of TLB entries, thereby simplifying TLB allocation and replacement. Small page sizes prevent the wasting of memory when allocating small areas of data.Each page of memory is accompanied by a set of storage attributes. These attributes include cacheability, write through/write back mode, big/little endian, guarded and four user-defined attributes. The user-defined attributes can be used to mark a memory page with an application-specific meaning. The guarded attribute controls speculative accesses. The big/little endian attribute marks a memory page as having big or little endian byte ordering. Write through/write back specifies whether memory is updated in addition to the cache during store operations.Two of the user-defined storage attributes can be programmed for special functions inside the core. One can be enabled to designate normal or transient cache regions. Another can be enabled to control whether or not store misses allocate a line in the D-Cache.Access control bits in the TLB entries enable system software to control read, write, and execute access for programs in both user and supervisor states.The MMU includes a 64-entry fully-associative unified TLB to reduce the overhead of address translation. Contention for the main TLB between data address and instruction address translation is minimized through the use of a four-entry instruction shadow TLB (ITLB) and an eight-entry data shadow TLB (DTLB). The ITLB and DTLB shadow the most recently used entries in the unified TLB. The MMU manages the replacement strategy of the ITLB and DTLB leaving the unified TLB to software control. Real-time operating systems are free to implement their own replacement algorithm for the unified TLB.Interrupt Handling LogicThe PPC440 services exceptions generated by error conditions, the internal timer facilities, debug events, and the external interrupt controller (EIC) interface. Altogether, there are sixteen different interrupt types supported.Interrupts are divided into two classes, critical and non-critical. Each class of interrupt has its own pair of save/restore registers for holding the program counter and machine state. Separate save/restore registers allow the PPC440 to quickly handle critical interrupts even within a non-critical interrupt handler. When an interrupt is taken, the PPC440 automatically writes the program counter and machine state to save/restore register SRR0 and SRR1 respectively for non-critical interrupts, or CSRR0 and CSRR1 respectively for critical interrupts. The machine status and program counter are automatically restored at the end of an exception handler when the return from interrupt (rfi) or return from critical interrupt (rfci) instruction is executed.TimersThe PPC440 contains a 64-bit time base and three timers: the Decrementer (DEC), the Fixed Interval Timer (FIT), and the WatchDog Timer (WDT). The time base counter increments synchronously with the CPU clock or an external clock source. The three timers are synchronous with the time base.The DEC is a 32-bit register that decrements at the time base increment rate. The user loads the DEC register with a value to create the desired delay. When the register reaches zero, the timer stops decrementing and generates a decrementer interrupt. Optionally, the DEC can be programmed to auto-reload the value last written to the DEC auto-reload register, after which the DEC continues to decrement.The FIT generates periodic interrupts based on one of four selectable bits in the time base. When the selected bit changes from 0 to 1, the PPC440 generates a FIT exception.The watchdog timer provides a periodic critical-class interrupt based on a selected bit in the time base. This interrupt can be used for system error recovery in the event of software or system lockups. Users may select one of four time periods for the interval and the type of reset generated if the watchdog timer expires twice without an intervening clear from software. If enabled, the watchdog timer generates a reset unless an exception handler updates the watchdog timer status bit before the timer has completed two of the selected timer intervals.Debug LogicAll architected resources on the PPC440 can be accessed through the debug logic. Upon a debug event, the PPC440 provides debug information to an external debug tool. Three different types of tools are supported depending on the debug mode: ROM Monitors, JTAG debuggers and instruction trace tools. Internal Debug ModeIn internal debug mode, a debug event enables exception-handling software at a dedicated interrupt vector to take over the PPC440 and communicate with a debug tool. Exception-handling software has read-write access to all registers and can set hardware or software breakpoints. ROM monitors typically use the internal debug mode.External Debug ModeIn external debug mode, the PPC440 enters stop state (i.e., stops instruction execution) when a debug event occurs. This mode offers a debug tool non-invasive read-write access to all registers in the PPC440 via the JTAG interface. Once the PPC440 is in stop state, the debug tool can start the PPC440, step an instruction, freeze the timers or set hardware or software break points. In addition to PPC440 control, the debug logic is capable of writing instructions into the instruction cache, eliminating the need for external memory during initial board bring up.Debug Wait ModeDebug wait mode offers the same functionality as external debug mode with one difference; in debug wait mode, the PPC440 will respond to interrupts and temporarily leave stop state to service them before returning to debug wait mode. In external debug mode, by contrast, interrupts are disabled while in stop state. Debug wait mode is particularly useful when debugging real-time control systems.Real-Time Trace Debug ModeIn real-time trace debug mode, instruction trace information is continuously broadcast to the trace port. When a debug event occurs, an external debug tool saves instruction trace information before and after the event. The number of traced instructions depends only on the memory buffer depth of the trace tool. Debug EventsDebug events signal the debug logic to either stop the PPC440, put the PPC440 in debug wait state, cause a debug exception, or save instruction trace information, depending on the debug mode. Table 4 on the following page lists the possible debug events and their description.Debug Event DescriptionBranch Taken A Branch Taken debug event occurs prior to the execution ofa taken branch instruction.Instruction Completion The Instruction Completion debug event occurs after thecompletion of any instruction.Return from Interrupt The Return From Interrupt debug event occurs after thecompletion of an rfi or rfci instruction.Interrupt The Interrupt debug event occurs after an interrupt is taken. Trap The Trap debug event occurs prior to the execution of a trapinstruction, where the trap condition is met.Instruction Address Compare (IAC)The IAC debug event occurs prior to the execution of aninstruction at an address that matches the contents of one offour IAC registers (IAC1, IAC2, IAC3, and IAC4).Alternatively, the registers can be combined to cause an IACdebug event prior to the execution of an instruction at anaddress contained in one of the following ranges as specifiedby the four IAC registers:IAC1 <= range < IAC2 (inclusive),IAC3 <= range < IAC4 (inclusive),range low < IAC1 < IAC2 <= range high (exclusive), orrange low < IAC3 < IAC4 <= range high (exclusive).Data Address Compare (DAC)The DAC debug event occurs prior to the execution of aninstruction that accesses a data address matching the contentsof one of the two DAC registers (DAC1 and DAC2).Alternatively, the registers can be combined to cause a DACdebug event occurs prior to the execution of an instructionthat accesses a data address within one of the followingranges specified by the two DAC registers:DAC1 <= range < DAC2 (inclusive), orrange low < DAC1 < DAC2 <= range high (exclusive). Data Value Compare (DVC)The Data Value Compare debug event occurs prior to theexecution of an instruction that accesses a data addressmatching one of the two DAC registers (or within a DACrange) and containing a particular data value as specified byone of the two DVC registers. The DVC debug event mayoccur when a selected data byte, half-word or word matchesthe corresponding element in DVC1 or DVC2. Unconditional Event An unconditional debug event is set by a debug tool throughthe JTAG port or by ASIC logic external to the PPC440.Table 4 - Debug EventsPower ManagementThe PPC440 core, in keeping with the IBM PowerPC 400 family tradition, utilizes aggressive power management techniques for minimizing power. The PPC440 utilizes three key techniques: redundant operand registers, half-cycle latch stabilization, and dynamic clock gating.Redundant Operand RegistersRedundant operand registers are used at various pipeline stages for feeding operands to each of the execution units. This saves power by preventing unused units from seeing the operand values being used by other units and improves performance by reducing loading and wire length in critical stages.Half-Cycle Latch StabilizationHalf-cycle stabilization latches minimize the propagation of glitches to downstream logic. This is easily employed since the PPC440 core contains a master/slave latch arrangement for scan-test purposes. Therefore, a master-only latch is simply needed in the logic path that is switching in the first half of a cycle. For example, if the select lines for a mux are being determined in the first half of a cycle, then by putting a master-only latch on these select lines before delivering them to the mux, the mux outputs are prevented from glitching while the select lines are being determined. Conversely, if the data lines are unstable in the first half of a cycle, a stabilization latch may be used on the data inputs, while leaving the select lines alone.Dynamic Clock GatingThe most important feature of the PPC440’s dynamic power management is the extensive use of clock gating. Given the PPC440’s master/slave latch organization, there are two possible gates that can be used. The relationship between them, and their relative affect on the clock splitter and hence power are shown in Figure 5.Figure 5 - PPC440 Clock GatingIn this figure, the early gate blocks the phase 1 clock and prevents the master latch from loading, while the late gate blocks the phase 2 clock and prevents the slave latch from loading. As illustrated in the simplified block diagram of the clock splitter, the early gate must arrive by mid-cycle -- which is when the system clock falls. If the gate is activated by this point, then the net effect is that internal to the clock splitter the fall on the system clock is never observed, and both the phase 1 and the phase 2 clock splitteroutputs remain stable, preventing any downstream master latches from loading, and hence their associated slave latches will not change either. This affords the maximum power savings, with the downstream logic dissipating no power other than leakage, and the clock splitter itself using almost zero power.In the event that the gate for a given latch cannot be determined by mid-cycle, the late gate can be used, which does not prevent the system clock fall and consequent phase 1 clock rise, but does prevent the corresponding next phase 2 clock rise. This does not save as much power, but the timing is much more relaxed and the power savings are still considerable.。

PA44-PZP;PA44-PP;中文规格书,Datasheet资料

Logical Systems CorporationPO Box 6184, Syracuse, NY 13217-6184 USA Tel (315) 478-0722, FAX (315) 479-6753, Email: info@ S Y T E M S S PA44-P(Z)P Data SheetDoc: 44PP.DOC Rev 08/06/99Page 1 of 1Supported Device/FootprintsThese adapters accepts 44 pin PLCC devices and plugs into 44pin PLCC production sockets. Test points are provided near the edges of the circuit board.Socket Plug Mfgr Device Package Device Package Many 44 pinPLCC 44 pinPLCCAdapter DimensionsPA44-PPPA44-PZPAdapter ConstructionThe adapter is made up of 2 sub-assemblies. They assemble via connectors making the adapter modular. This way the sub-assemblies can be replaced when they wear out.When disassembling the adapter take care not to bend the pins.When reassembling the adapter note the pin 1 indicators to align the parts correctly.The adapters described by this datasheet and their sub-assemblies are:Adapter Test Socket Board PA44-PP 44-30644-PP PA44-PZP 44-40044-PZP Test Sockets LSC #StyleMfgr/Pn44-306Auto-Eject Yamaichi IC120-0444-30644-400Lidded ZIF Yamaichi IC51-0444-400Test PointsThese adapters offer Test Points. The Test Points are rows of plate-thru-holes (PTH) along the 4 edges of the adapter.Grabbers may be used to hook onto the holes.Alternately, 0.050” pitch 11 pin strips can be soldered into the holes and connections made to the strip’s pins. A right angle strip should be considered for easier access to the pins.Adapter WiringThis adapter is wired 1 to 1. Pin 1 of the socket is connected to pin 1 of the plug. Pin 2 to pin 2 and so on around the adapter.PA44-P(Z)P Data Sheet44 pin PLCC socket/44 pin PLCC plug/分销商库存信息:LOGICAL-SYSTEMSPA44-PZP PA44-PP。

七彩虹 C.P4X400 主机板中文说明书

Colorful艺术品质服务主板型号 C.P4X400说明书版本 1.1七彩虹网站七彩虹信箱support@ 800免费服务热线800-830-5866Colorful版权本手册版权属于世和资讯公司所有，未经本公司书面许可，任何人不得对此说明书和其中所包含的任何资料进行复制、拷贝或翻译成其它语言。

声明本手册编辑时间有限，因为IT行业市场变化迅速，不保证本手册中没有错误，所以本手册仅提供用户参考使用，不提供任何形式的担保。

本公司保留对本文内容修订和改变的权力，对于所作修改本公司没有责任通知任何个人。

商标版权本手册中有使用到其他公司的注册商标，特声明如下：Microsoft 、MS-DOS和Windows是微软公司（Microsoft Corp.）的注册商标。

MMX、Pentium、Celeron是Intel公司的注册商标。

其他在本说明书中使用的产品名称是他们各自所属公司所拥有和被公认的。

世和资讯公司对本手册拥有最终解释权。

Colorful主机板简介 (1)主机板规格 (2)■处理器 (2)■芯片组 (2)■内存 (2)■AGP 介面 (2)■内建AC’ 97 Codec 控制器 (2)■BIOS (3)■超级I/O功能 (3)■扩展插槽 (3)■电源管理 (3)■主板结构 (3)C.P4X400主机板缩略图 (4)VIA P4X400 芯片组结构图 ... . (5)硬体设定 (6)■主板布局图 (6)■跳线设定 (7)■连接口介绍 (9)■内存条的安装说明 (14)■驱动程式安装说明 (15)ColorfulBIOS 设定 (16)■Award BIOS 设定主菜单 (16)■标准CMOS设定 (17)■高级BIOS设定 (18)■高级芯片设定 (21)■外部设备设定 (24)■电源管理设定 (28)■PNP/PCI即插即用 (32)■系统即时状态 (33)■频率/电压控制 (34)■载入安全预设值 (35)■载入优化预设值 (35)■密码设定 (36)■离开SETUP 并储存设定结果 (37)■离开SETUP但不储存设定结果 (37)开机系统自检常见错误讯息 (38)客户技术支持 (40)——激发Pentium的数字魅力体验科技前沿的动感脉博感谢您购买七彩虹C.P4X400主板。

RICOH MP C4504 MP C6004 多功能彩色复印机打印机传真扫描仪说明书

Copier Printer Facsimile ScannerMP C4504MP C600445& full-colour60&m f o u n ll o-c c h o r lo om ur emonochromeppm ppmImprove productivity in your own wayYou take your work personally. Why not use it to your advantage? Use what you know about your everyday tasksto customise digital workflows on the RICOH® MP C4504/MP C6004 Colour Multifunction Printer (MFP) with our Workstyle Innovation Technology. Choose from multiple user interfaces for intuitive fingertip control on an oversized 10.1"-wide Super VGA Smart Operation Panel. Create one-touch shortcuts to automate manual tasks. Place your own information-rich widgets on the control panel and check settings and critical details with a single glance. Produce more types of jobs in more formats — including brilliant colour prints on a wide range of paper stocks — with speed and convenience without compromising security or wasting resources. Add user authentication to protect information and to encourage more responsible printing. And take advantage of mobile technologies to remain productive from anywhere.•Print up to 60 colo u r prints/copies per minute•Use flick, pinch and swipe motions to navigate an interactive user interface•Customi s e your own automated workflows to reduce manual tasks•Use your personal mobile device to print and share information anywhere•Showcase your work in brilliant colo u rs with professional finishing•T ake advantage of eco-friendly features to lower operating costs and reduce overall environmental impactwithout sacrificing business productivityLeave your mark with brilliant colo u rsMake an unforgettable impression by producing compelling images and documents with densely rich colo u rs for more lifelike reproductions at up to 1200 dpi resolution. The RICOH MP C4504/MP C6004 recalibrates itself as it processes files, which means colo u rs never deteriorate and text and lines stay incredibly sharp page after page. Expand your reach by printing on a wider, thicker range of paper stocks — up to SRA3 sizes and 300 gsm. You can even create banners up to 1,260 mm long or create posters by printing one page across several sheets to then put them together, both features saving you on outsourcing costs. Want to save even further on outsourcing? Choose the new Fiery E-23C Colo u rController and produce spot colo u r professional output using the gamut of RGB, CMYK and PANTONE colo u rs.Make your mark from anywhereWith your smartphone or tablet in hand, productivity remains within your grasp. Download the RICOH Smart Device Connector app to connect to the MP C4504/MP C6004 without software, utilities, drivers or delays. Simply touch your mobile device to the MFP’s Near Field Communication (NFC) tag to print, scan and share documents, photos and more instantly. Send information to your phone just as easily. Scan originals at the device, deliver them to your smartphone and tablet and take them with you or save them to the cloud with Dropbox and Google Drive shortcuts within the app . Use your personal address book to bypass manual entry tasks and send emails to any recipient in a single action. Plus, you can use the dual optional network port to connect to two networks simultaneously.Expedite every task, every dayDecisions have to be made. You might as well ensure they’re the right ones by getting information where it needs to be — on time. A built-in motion sensor activates the Smart Operation Panel as you approach, so you can begin working the moment you arrive at the MFP. Print up to 60 pages per minute for incredibly fast turnarounds, even when producing full-colo u r brochures, presentations, spreadsheets and more. Add optional paper trays to extend paper capacity up to 4,700 sheets, and remove paper jams quickly via an animated guide to keep jobs moving. Scan full-colo u r originals and deliver them at breakneck speeds with a host of scan-to capabilities, including access to your LDAP directory for email delivery. Send and receive paperless faxes to ensure contracts, forms and other important documents arrive at the right destination at the right time.Do it all with speed and conveniencePerform more tasks with fewer hasslesA new way to work is within your reach Slide from one job to the next with easeSearching for ways to be more productive? Look right in front of you,it’s at your fingertips with our revolutionary Workstyle InnovationTechnology. Use the same motions you use on your smartphone or tablet— including swipe scrolling, drag-and-drop and pinch-and-flick gestures— to toggle between jobs and check settings quickly. Take advantageof the dynamic user interface layout on the oversized 10.1"-wide SuperVGA Smart Operation Panel to access information instantly. Becausethere are no hard keys, you simply tap icons to navigate from one taskto the next. The user interface even lets you print, scan, copy and faxusing convenient one-touch controls. Don’t worry, we didn’t forget aboutwhat’s worked in the past. You can opt to use a touchscreen versionof the legacy user interface found on previous Ricoh devices.Use intuition to work smarterDecisions are easier when you have the right information. WorkstyleInnovation Technology lets you access information at any time. Chooseto use the “smart apps” user interface so you can access details quicklyand intuitively with a single glance. Click on your choice of iconic appsto automate everyday print, copy, scan and fax workflows and reducetime-consuming manual entry that can derail even your best ideas.Check any setting — from the number of prints to scan-to destinationsto finishing options — with a tap of your finger. Need to make changesto settings or workflows? Touch the interactive Smart Operation Panelagain to make adjustments in only moments. Looking for more featuresand functions? Download additional apps from our Application Site andplace them as one-touch widgets on the Home Screen.Customi s e workflows tosimplify information flowYou have a lot of work to do. Who says you have to spend a lot oftime doing it? Simplify your workday and deploy workflowapplications that streamline business via Ricoh Workstyle InnovationTechnology and use what you know about everyday tasks to createunique, customised solutions powered by the Smart Operation Panel.Do you routinely print the same types of spreadsheets? Do you scanand share notes after the weekly meeting? Integrate multipleprocesses and simplify complex tasks, so you can simply press an iconand complete these tasks faster without repeating steps or recreatingthe work. You can use the interactive user interface as a one-touchpath for special tasks, too. Tap the ID Card Copy icon to scan two-sided identity documents, such as licences and insurance cards, onto asingle-sided document. For more complex workflows, add your choiceof plug-and-play workflow software to simplify your workday.Empower users to work quickly, collectivelyGrab and share information automaticallyMove information to the right people in the right format quickly.Access up to 3,000 frequently-used documents stored in theDocument Server. Use the built-in browser to capture files and imagesin the Cloud without servers, system integration and software updates.With optional Optical Character Recognition (OCR) software, you canplace keyword-searchable metadata on that information for easierretrieval. Ready to share with others? Scan originals at up to 180 ipmvia the 220-Sheet Single Pass Document Feeder and use scan-tocapabilities to send digital files to any recipient, anywhere. Or, useRicoh Device Software Manager to automate print driver installationand begin using the device in moments. You can also track everythingin real time with web-enabled tools.Hold yourself and others accountableYou’re responsible for getting company information to the rightpeople. So make certain the right people are sending it. With userauthentication, you can track activity for every user, set print quotas,restrict access to specific functions and more. Each user logs in to theMP C4504/MP C6004 by entering a passcode or billing code — orby passing an ID card over an optional NFC card reader at the device.With Locked Print, users can release jobs for printing only whenstanding at the MFP, which reduces unnecessary printing and helpsprotect confidential information. You can also place a watermark onspecific printed documents if unauthori s ed users try to recreate them.Take advantage of encryption protection and automatic overwrites toprevent access to information residing on the hard drive.Plan to saveThe MP C4504/MP C6004 is designed specifically to simplify workloadswhile reducing expenses. Because the MFP meets EPEAT® Gold criteria*and ENERGY STAR® certifications, you can reali s e incredibly low TypicalElectricity Consumption (TEC) rates — as low as 1.8 kWh/week. Useduplex printing as the default to reduce paper costs. Program the MFP topower down automatically when you know the office will be empty. Anduse the Eco-Friendly widget to send users hints and tips for conservingenergy. You can even track how much energy you’re saving. The systemis also equipped with an innovative motion sensor, which senses anapproaching user by detecting the differences in body temperature versusthe surrounding environment. The system will awake from Sleep Modeand turn on the operation panel within one second so it is ready to beginjob programming by the time the user arrives at the machine.*EPEAT Gold rating is applicable only in the USA.To view detailed features of our multifunctionproducts online go to .au/products123456Smart Operation Panel: Choose from multiple 6Document Server: Create up to 200 shared or Perform more jobs with fewer hassles478910121113Put it all together at the endBring your best ideas together by finishing them in style. With the External Hybrid Stapleless + Stapler Finisher, you can conserve resources by getting rid of staples entirely for document sets of 2 to 5 sheets (which are 4 to 10 pages in duplex printing). For document sets from 6 to 50 sheets , the finisher can automatically convert to staples. It is ideal for educational, manufacturing and healthcare environments.You can choose other finishing options, too. Each is specifically designed to simplify paper handling, stacking and stapling, so you can concentrate on other core tasks. Choose the one that meets your unique requirements and give your projects an affordable, impressive professional-grade look.Finisher Paper Capacity (A4)Hole-Punch Saddle StitchStapleless SR3130 Internal 500 Sheets Option N/A N/ASR3210 External 1,000 Sheets Option N/A Stapleless – Up to 5 Sheets Stapled – Up to 50 Sheets A4SR3220 External 1,000 Sheets Option Up to 15 Sheets N/A SR3240 External 2,000 Sheets Option Up to 20 SheetsN/A SR3230 External3,000 SheetsOptionN/AN/ASR3130 Internal Stapler Finisher*SR3210 External Hybrid Stapler + Stapleless FinisherSR3220 External Booklet FinisherSR3240 External Booklet FinisherSR3230 ExternalStapler FinisherGeneral SpecificationsConfiguration DesktopPrinting Process Output Speed (Copy/Print) Warm-Up Time Recovery from Sleep Mode First Copy Time (FC/B&W)Copy Resolution Quantity Indicator 4-Drum MethodMP C4504: 45-ppm B&W & FC (A4) MP C6004: 60-ppm B&W & FC (A4) 24 secondsApproximately 1.0 second (motion-sensor activated)MP C4504: 5.7/4.0 seconds MP C6004: 4.5/3.1 seconds 600 dpiUp to 999 copiesSingle Pass Document Original Capacity: 220 sheets Feeder (SPDF)Original Size: A5 - A3Paper Weights: Simplex: 40 – 128 g/m , Duplex: 52 – 128 g/mPaper Capacity Standard: 2 x 550 sheets + 100-Sheet Bypass Tray, Maximum: 4,700 sheets (w/Tandem LCT + Side LCT) Supported Paper Sizes1st Paper Tray: A42nd Paper Tray: A6 – SR A3, Envelopes Bypass: Up to SRA3, EnvelopesCustom Sizes: Width: 90 – 320 mm, Length: 148 – 1260 mm Supported Paper WeightsPaper TypesAuto DuplexOutput Capacity ZoomStandard Trays: 60 – 300 g/m Bypass Tray: 52 – 300 g/m Duplex Unit: 52 – 256 g/mPlain, Recycled, Special Paper 1 – 3, Letterhead, Cardstock, PreprintedPaper, Bond Paper, High-Gloss Coated Paper, Color Paper, Envelopes, Coated, Labels* & OHP*StandardStandard: 500 sheets Maximum: 3,625 sheets25% – 400% in 1% incrementsDimensions (WxDxH) WeightPower Requirements Power Consumption TEC Value**668 x 738 x 1205 mm (Includes SPDF and Two-Tray Paper Bank)103.4 kg (Machine + SPDF)220-240V 50/60Hz1,850W or less; Sleep Mode: .89W MP C4504: 1.8 kWh MP C6004: 2.7 kWh*Bypass Tray Only ** T ypical Electricity Consumption by ENERGY STAR Qualified Imaging Equipment Test ProcedurePrinter Specifications (Standard)CPUIntel Atom Processor Bay Trail 1.75 GHz Memory/HDD 2 GB RAM/320GB HDD Standard & 4GB RAM/320GB HDD Option Page Description Standard: PCL5c, PCL6, PDFLanguages Optional: Adobe PostScript 3, XPS, IPDS & PictBridgeFont SupportStandard: PCL: 45 Scalable fonts + International 13 fontsOptional: PostScript 3: 136 Roman fonts; IPDS: 108 Roman fonts Max. Print Resolution 1200 x 1200 dpiNetwork InterfacesStandard: 1000Base-T/100Base-TX/ 10Base-T Ethernet, USB2.0 Type A (3 Ports), SD Slot on Operation Panel Option: IEEE1284/ECP; IEEE802.11a/b/g/n; USB2.0 Type B Network Protocol TCP/IP (IPv4, IPv6)Support Network/OSWindows Vista/7/8/8.1/10/Server 2008/ Server 2008R2/ Server2012/ Server 2012R2Unix; Sun Solaris, HP-UX, SCO OpenServer , RedHat Linux, IBM AIX, CitrixPresentation Server 4.5, XenApp 5.0Mac OS X v.10.7 or later, SAP R/3, IBM iSeries AS/400-using OS/400 Host Print TransformUtilitiesDevice Manager NX, Web Image Monitor, @RemoteDocument Server Specifications (Standard)Max. Stored Documents 3,000Max. Pages/Document 2,000Max. Page Capacity 9,000Max. Number of Folders 200Scanner Specifications (Standard)Scanner ResolutionB&W and FC scanning at 100 – 600 dpi, Scanning Speed (B&W & Colo u r A4)Scan AreaCompression Method Up to 1200 dpi for TWAIN scanning200/300 dpi: 110 ipm Simplex/180 ipm Duplex 297 mm – 432 mm B&W TIFF: MH, MR, MMR, JBIG2Colo u r: JPEGSupported File Formats Single/Multi-Page TIFF , PDF , HighCompression PDF & PDF/A, Single-Page JPEGScan Modes Scan-to-Email (with LDAP support)Scan-to-Folder (SMB/FTP)Scan-to-URLScan-to-Media (USB/SD Card)Network TWAIN ScanningFacsimile Specifications (Optional)Type ITU-T (CCITT) G3Circuit PSTN, PBXResolution200 x 100 dpi, 200 x 200 dpi, 400 x 400 dpi (with optional SAF memory)Modem Speed 33.6K – 2,400 bps w/Auto Fallback Compression Method MH, MR, MMR, JBIG Transmission Speed G3: Approximately 2 seconds/page(JBIG)Scanning Speed Up to 81 spm Auto Dialing 2,000 Quick/Speed Dial numbers;100 Group Dial numbersMemory Capacity (SAF) Standard: 4 MB (approx. 320 pages),Optional: 64 MB (approx. 4,800 pages) with optional SAF memorySecurity Features (Standard)DataOverwriteSecurity System (DOSS), HDD Encryption, User Codes, SNMP v3 Support, Encryption, Locked Print, User Authentication, 802.1x Wired Authentication, Quota Setting/Account Limit, Digitally Signed PDF, and more*Not available for MP C6004Hardware Accessories Paper Handling Options Two-Tray Paper Bank (PB3160)Tray Capacity Paper Size Paper Weight 1,100 sheets (550 sheets x 2 trays) A5 – SR A352 – 300 g/m²Dimensions (WxDxH)587 x 685 x 247 mm One-Tray Paper Bank (PB3150)Tray Capacity Paper Size Paper Weight 550 sheets x 1 tray A5 – SR A352 – 300 g/m²Dimensions (WxDxH)587 x 685 x 120 mm Requires installation of Caster Table Type M3 Tandem Large Capacity Tray (PB3230)Tray Capacity Paper Size Paper Weight 2,000 sheets (1,000 sheets x 2) A452 – 300 g/m²Dimensions (WxDxH)587 x 685 x 247 mm Side Large Capacity Tray (RT3030)Tray Capacity Paper Size Paper Weight 1,500 sheets A452 – 300 g/m²Dimensions (WxDxH)340 x 545 x 290 mmRequires installation of Two-Tray Paper Bank (PB3160) or Tandem LCT (PB3230)Output Trays & Finisher OptionsInternal Shift-Sort Tray (SH3070)Tray Capacity250 sheets (A4 or smaller)125 sheets (B4 or larger)Paper Size A5 – SR A3Paper Weight52 – 300 g/m²Cannot be installed with any FinisherOne-Bin Tray (BN3110)Paper Size Paper Weight Tray Capacity A5 – SR A3 52 – 300 g/m 125 sheets500-Sheet Internal Finisher (SR3130)Paper Size Paper Weight A6 – SR A3 52 – 300 g/m²Stack Capacity Staple Paper Size Staple Paper Weight Staple CapacityStaple Positions Dimensions (WxDxH)500 sheets (A4 or smaller)250 sheets (B4 or larger)A4 – A352 – 105 g/m50 sheets (A4)30 sheets (B4 – A3, and/or Mixed Sizes) Top, Bottom, 2 Staples546 x 523 x 170 mm*Not available for MP C6004.2-/4-Hole Punch Unit (PU3040EU)(Optional; Installs inside SR3130 Internal Finisher)Punch Paper Sizes A4 – A3Punch Paper Weight52 – 169 g/m1,000-Sheet Hybrid Staple + Stapleless Finisher (SR3210) Paper Size Proof Tray: A6 – SRA3Shift Tray: A6 – SRA3Paper Weight Stack Capacity Proof Tray: 52 – 169 g/m²Shift Tray: 52 – 300 g/m²Proof Tray: 250 sheets (A4 or smaller); 50sheets (B4 or larger)Shift Tray: 1,000 sheets (A4 or smaller);500 sheets (B4 or larger)Stapleless CapacityStaple CapacityStaple Paper SizeStaple Paper WeightStaple PositionsDimensions (WxDxH)2 – 5 sheets/set50 sheets (A4 or smaller)30 sheets (B4 or larger)A4 – A352 – 105 g/mTop, Bottom, 2 Staples563 x 620 x 960 mm1,000-Sheet Booklet Finisher (SR3220)Paper Size Proof Tray: A6 – SRA3Paper WeightStack CapacityStaple CapacitySaddle StitchStaple Paper SizeStaple Paper WeightStaple PositionsDimensions (WxDxH)Shift Tray: A6 – SRA3Proof Tray: 52 – 169 g/mShift Tray: 52 – 300 g/m²P roof Tray: 250 sheets (A4 or smaller); 50sheets (B4 or larger)Shift Tray: 1,000 sheets (A4 or smaller);500 sheets (B4 or larger)Normal Staple: 50 sheets (A4 or smaller);30 sheets (B4 or larger)15 sheetsNormal Staple: A4 – A3Saddle Stitch: A4 – A352 – 105 g/mTop, Bottom, 2 Staples, Booklet563 x 620 x 960 mm2-/4-Hole Punch Unit(PU3050EU)(Optional; Installs inside SR3210 or SR3220 Finisher)Punch Paper SizesPunch Paper WeightA4 – A352 – 256 g/m²2,000-Sheet Booklet Finisher (SR3240)Paper Size Proof Tray: A6 – SRA3Paper WeightStack CapacityStaple CapacityStaple Paper SizeStaple Paper WeightStaple PositionsDimensions (WxDxH)Shift Tray: A6 – SRA3Proof Tray: 52 – 220 g/m²Shift Tray: 52 – 300 g/m²Proof Tray: 250 sheets (A4 or smaller)50 sheets (B4 or larger)Shift Tray: 2,000 sheets (A4)1,000 sheets (A4 - SRA3)Normal Staple: 50 sheets (A4 – A3 andMixed Sizes)Saddle Stitch: 20 sheets (80 g/m²)Normal Staple: A4 – A3Saddle Stitch: B5 – SR A3Normal: 52-105 g/m, Saddle: 64-105 g/m²T op, Bottom, 2 Staples, Top Slant, Booklet657 x 613 x 960 mm3,000-Sheet Finisher (SR3230)Paper Size Proof Tray: A6 – SRA3Shift Tray: A6 – SRA3Paper WeightStack CapacityStaple CapacityStaple Paper SizeStaple Paper WeightStaple PositionsDimensions (WxDxH)Proof Tray: 52 – 220 g/mShift Tray: 52 – 300 g/mProof Tray: 250 sheets (A4 or smaller)50 sheets (B4 or larger)Shift Tray: 3,000 sheets (A4)1,500 sheets (B5 - SRA3)50 sheets (A4 – A3, Mixed Sizes)B5 – A352 – 105 g/mTop, Bottom, 2 Staples, Top Slant657 x 613 x 960 m m2-/4-Hole Punch Unit (PU3060EU)(Optional; Installs inside SR3230 or SR3240 Finishers)Punch Paper SizesPunch Paper WeightB5 – A352 – 256 g/m²Colo u r Controller E-23CController Type Embedded TypeFiery Platform FS150CPU Intel Processor G850 2.9GHzHost Interface1000Base-T/100Base-TX/10Base-TMemory 2 GBInternal HDD500 GBOperating System LinuxNetwork Protocol TCP/IP (IPv4/IPv6), SMB, BonjourPrinter Description Standard: PostScript 3 & PCL6/5cLanguageMax Print ResolutionMax Scan ResolutionFontsUtilitiesColo u r ManagementToolsUp to 1200 dpi (2 bit)Up to 600 dpiPS3: 138 fonts/PCL: 81 AGFA fontsStandard: Command WorkStation 5, FieryScan, Printer Delete Utility, Fiery Web T ools,Fiery Bridge, Secure Erase and Fiery VUEOptional: Fiery Impose, Fiery Compose,Fiery Auto Trap, EFI Spot-On, Fiery HotFolders, Fiery Colo u r Profiler Suite v4.0,Fiery ES-2000 SpectrophotometerICC Profile, Colo u r Chart, CMYK Colo u rReference Pages, RGB Colo u r Tests,Trapping Support and ColorWise Pro ToolsAdditional AccessoriesBanner Paper Guide Tray Type M19, Caster Table Type M3, BridgeUnit BU3070, Cabinet, Camera Direct Print Card Type M19,Extended USB Board Type M19, Fax Connection Unit Type M20, FaxMemory Unit Type M19 64MB, File Format Converter Type M19, G3Interface Unit Type M20, IEEE 802.11a/g/n Interface Unit Type M19,IEEE 1284 Interface Board Type M19, Imageable Area Extension UnitType M19, Memory Unit Type M19 4GB, NFC Card Reader TypeM19, OCR Unit Type M13, Optional Counter Interface Unit TypeM12, Postscript3 Unit Type M19, Smart Card Reader Cover Unit TypeM19, USB Device Server Option Type M19, XPS Direct Print OptionType M19Either the Cabinet or one of the paper options must be installed.Requires configuration with Bridge Unit BU3070.Cannot be installed together.Requires installation of Two-Tray Paper Bank (PB3160) or Tandem Large CapacityTray (PB3230).Some options may not be available at the time of market release.Specifications are subject to change without notice.For maximum performance and yield, we recommend using genuineRicoh parts and supplies..auRicoh Australia Pty. Ltd. Suite G2, 2 Richardson Place, North Ryde, NSW, 2113. Phone: 13 RICOH (13 74264) Fax: (02) 9249 6244Web: .au Ricoh New Zealand Pty. 60 Stanley Street, Parnell, Auckland New Zealand. Phone: 0800 2 Ricoh (0800 2 74264) Fax: 09 915 1401Web: 。

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Part Number 440SPeRevision 1.23 - Sept 21, 2006 PowerPC 440SPe Embedded ProcessorPreliminary Data Sheet Features•PowerPC® 440 processor core operating up to 667 MHz with 32KB I- and D-caches (with parity checking)•On-chip 256KB SRAM configurable as L2 Cache or Ethernet Packet/Code store memory •Selectable Processor vs Bus clock ratios (Refer to the Clocking chapter in the PPC440SPeEmbedded Processor User’s Manual for details)•Support up to 16 GB (4 Chip Selects) of 64-bit/32-bit SDRAM with ECCDDR I 266-333-400DDR II 400-533-667•Three PCI-Express serial interfaces:one 8 lanes and two 4 lanes - 2.5Gb/s per lane Root and Endpoint support.Opaque bridge•One 64-bit DDR PCI-X interfaces up to 133 MHz (DDR 266) with support for conventional PCI •Optional: High throughput RAID 6 hardware acceleration, performs XOR and Galois Field P & Q parity computations, supports up to 255 drives •Optional:16 Programmable Galois Field polynomials including 14d and 11d•XOR Accelerator with DMA controller•I2O messaging with two DMA controllers•External Peripheral Bus (16-bit Data, 27-bit Address) for up to three devices; Bank0=16 MB, Bank1 and Bank2=128 MB each•One Ethernet 10/100/1000Mbps half- or full-duplex interface. Operational modes supported are MII and GMII.•Programmable Interrupt Controller supports interrupts from a variety of sources.•Programmable General Purpose Timers (GPT)•Three serial ports (16750 compatible UART)•Two IIC interfaces•General Purpose I/O (GPIO) interface available•JTAG interface for board level testing•Processor can boot from PCI memoryDescriptionDesigned specifically to address high-end embedded applications for storage, the PowerPC 440SPe (PPC440SPe) provides a high-performance, low power solution that interfaces to a wide range of peripherals by incorporating on-chip power management features and lower power dissipation. This chip contains a high-performance RISC processor core, a DDR1/DDR2 SDRAM controller, configurable 256KB SRAM to be used as L2 cache or software-controlled on-chip memory, three PCI-Express interfaces, one DDR PCI-X bus interface, a 1Gbps Ethernet interface, an I2O/DMA controller, control for external ROM and peripherals, optional RAID 6 acceleration, an XOR DMA unit, serial ports, IIC interfaces, and general purpose I/O.Technology: CMOS Cu-11, 0.13mm Package: 27mm, 675-ball, 1mm pitch, Flip Chip-Plastic Ball Grid Array (FC-PBGA)Power (estimated): Less than 14W @533MHz Supply voltages required: 3.3V, 2.5V, 1.8V, 1.5VPowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet ContentsOrdering and PVR Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Address Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 PowerPC 440 Processor Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9On-Chip SRAM/L2 Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DDR PCI-X Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DDR1/DDR2 SDRAM Memory Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 External Peripheral Bus Controller (EBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ethernet Controller Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13I2O/DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Optional RAID 5 and RAID 6 Acceleration Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 XOR/DMA2 Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Serial Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14IIC Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 General Purpose Timers (GPT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 General Purpose IO (GPIO) Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Universal Interrupt Controller (UIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1527mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Signal Lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Clock Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Spread Spectrum Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Input/Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 DDR SDRAM I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DDR SDRAM Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DDR SDRAM Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Serial Bootstrap ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet FiguresFigure 1. Order Part Number Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. PPC440SPe Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 3. 27mm, 675-Ball FC-PBGA Core Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 4. Clock Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Figure 5. Input Setup and Hold Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 6. Output Delay and Hold Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 7. DDR SDRAM Signal Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 8. DDR SDRAM Write Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Figure 9. DDR SDRAM Read Data Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 10. DDR SDRAM Memory Data and DQS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Figure 11. DDR SDRAM Read Cycle Timing—Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 TablesTable 1. System Memory Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Table 2. DCR Address Map (4KB of Device Configuration Registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. Signals Listed Alphabetically . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4. Signals Listed by Ball Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Table 5. Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 6. Signal Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 8. Package Thermal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 9. Recommended DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 10. Input Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 11. DC Power Supply Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 12. Clocking Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 13. Peripheral Interface Clock Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Table 14. I/O Specifications—All Speeds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Table 15. I/O Specifications—667MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 16. DDR SDRAM Output Driver Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 17. DDR SDRAM Read and Write I/O Timing—TSA and THA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 18. DDR SDRAM Clock to Write DQS Timing—T DS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 19. DDR SDRAM Write Data to DQS Timing—TSD and THD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 20. DDR SDRAM I/O Read Timing—T SD and T HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 21. Strapping Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77PowerPC 440SPe Embedded ProcessorRevision 1.23 - Sept 21, 2006Preliminary Data SheetOrdering and PVR InformationFor information about the availability of the following parts, contact your local sales office. The most current version of the 440SPe is Revision B. The part numbers for 440SPe Revision B are shown in the following figures.Each part number contains a revision code. This is the die mask revision number and is included in the part number for identification purposes only.The PVR (Processor Version Register) and the JTAG ID register are software accessible (read-only) and contain information that uniquely identifies the part. See the PPC440SPe Embedded Processor User’s Manual for details about accessing these registers.Note: Raid-enabled versions (Product Feature = R) require a RAID key license.Figure 1. Order Part Number KeyThe part numbers for 440SPe Revision A are shown in the following figure.Product Name Order Part Number (see Notes 1-5)Package Rev Level PVR Value JTAG ID PPC440SPe PPC440SPe-xpBfffC27mm, 675 FC-PBGAB0x534218910x14538049Notes:1.x = Product FeatureA = RAID6 not enabled (Rev LevelB only)R = RAID6 enabled (Rev Level B only)2.p = Module Package TypeG = leaded FC-PBGAN = lead free FC-PGBA (RoHS compliant)3. B = Chip Revision Level B (2.0)4.fff = Processor Frequency533 = 533MHz 667 = 667MHz5. C = Case Temperature Range of 0°C to +95°CProduct Name Order Part Number Processor Frequency Package Rev Level PVR Value JTAG ID PPC440SPe PPC440SPe-3GA533C 533MHz 27mm, 675 FC-PBGA A 0x534218900x14538049PPC440SPePPC440SPe-3GA667C667MHz27mm, 675 FC-PBGAA0x534218900x14538049PPC440SPe-RNB667CPackageProduct FeatureCase Temperature Range Revision LevelProcessor Speed AMCC Part NumberNote: The example part number above is a RAID6-enabled, lead-free package, at Chip Revision Level B, at PCI Express core revision level 1.1, capable of running at 667 MHz, and is shipped in tray packaging.PowerPC 440SPe Embedded ProcessorRevision 1.23 - Sept 21, 2006Preliminary Data SheetPPC440SPe Functional Block DiagramFigure 2. PPC440SPe Functional Block DiagramThe PPC440SPe is a System on a Chip (SOC) designed around the IBM CoreConnect Bus ™ Architecture.Implemented with the Crossbar option, the CoreConnect buses provide:•Two Master PLB bus 128-bit Data 64-bit Address PLB interfaces up to 166.66MHz, 2.6GB/s on both the Read and Write data path (10.6 GB/s total)•32-bit OPB interfaces up to 83.33MHz for a maximum throughput of 333MB/sProcessor Core DCR Bus32KB On-chip Peripheral Bus (OPB)GPIOIIC UART BridgeExternal Clock,Control,ResetPower MgmtJTAG Timers MMUOPB Interrupt ControllerUniversal I-Cache32KB D-CacheXOR/DMA PPC440PCI-Express x2x3MALEthernet DCRs GP Timers256 KBLow Latency (LL) SegmentHigh Bandwidth (HB) SegmentProcessor Local Bus (PLB)Trace ArbPLB I2O/DMA Memory PCI-E0PCI-E1PCI-E2MII,GMIIQueue DDR PCI-X4 lanes 8 lanes 4 lanesIRQ HandlerPCI-E Bus Controller(EBC)10/100/1000Controller (DMA0 and DMA1)AcceleratorUnit (DMA2)Registers64-bit64+81616 IRQsDDR 1 and 2 SDRAM CntlL2 Cache/SRAMMACPowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet Address MapsThe PPC440SPe incorporates two address maps. The first is a fixed processor system memory address map. This address map defines the possible contents of various processor accessible address regions. The second address map identifies the system Device Configuration Registers (DCRs). DCRs are accessed by software running on the PPC440SPe processor through the use of mtdcr and mfdcr instructions.Table 1. System Memory Address Map (Sheet 1 of 2)Function Sub Function Start Address End Address SizeLocal Memory (LL)1DDR SDRAM0000 0000 0000 00000000 0003 FFFF FFFF16GB SRAM0000 0004 0000 00000000 0004 0003 FFFF256KB Reserved0000 0004 0004 00000000 0004 000F FFFFInternal PLB Interfaces (LL)I2O Registers0000 0004 0010 00000000 0004 0010 00FF256B DMA 0 Registers0000 0004 0010 01000000 0004 0010 01FF256B DMA 1 Registers0000 0004 0010 02000000 0004 0010 02FF256B I20/DMA Buffers0000 0004 0010 03000000 0004 0010 0FFF3.25KB Reserved0000 0004 0010 10000000 0004 001F FFFFXOR/DMA20000 0004 0020 00000000 0004 0020 03FF1KB Reserved0000 0004 0020 04000000 0004 002F FFFFPCI Express Interrupt Handler0000 0004 0030 00000000 0004 0030 00FF256B Reserved0000 0004 0030 01000000 0004 DFFF FFFFInternal OPB Peripherals (LL)EBC Memory60000 0004 E000 00000000 0004 EFFF FFFF256MB Reserved0000 0004 F000 00000000 0004 F000 01FFUART00000 0004 F000 02000000 0004 F000 02078BReserved0000 0004 F000 02080000 0004 F000 02FFUART10000 0004 F000 03000000 0004 F000 03078BReserved0000 0004 F000 03080000 0004 F000 03FFIIC00000 0004 F000 04000000 0004 F000 041F32BReserved0000 0004 F000 04200000 0004 F000 04FFIIC10000 0004 F000 05000000 0004 F000 051F32BReserved0000 0004 F000 05200000 0004 F000 05FFUART20000 0004 F000 06000000 0004 F000 06078BReserved0000 0004 F000 06080000 0004 F000 06FF248BGPIO Controller Registers0000 0004 F000 07000000 0004 F000 077F128BReserved0000 0004 F000 07800000 0004 F000 07FFEthernet Controller Registers0000 0004 F000 08000000 0004 F000 08FF256BReserved0000 0004 F000 09000000 0004 F000 09FFPowerPC 440SPe Embedded ProcessorRevision 1.23 - Sept 21, 2006Preliminary Data SheetGeneral Purpose Timers 0000 0004 F000 0A000000 0004 F000 0B3F 320BReserved0000 0004 F000 0B400000 0004 FEFF FFFF Boot ROM 2, 3EBC Bank00000 0004 FF00 00000000 0004 FFFF FFFF 16MB Reserved0000 0005 0000 00000000 0007 FFFF FFFF Local Memory Alias (HB)Aliased DDR SDRAM 0000 0008 0000 00000000 000B FFFF FFFF 16GB PCI Space (HB)Reserved 0000 000C 0000 00000000 000C 07FF FFFF PCIX0 I/O 0000 000C 0800 00000000 000C 0800 FFFF 64KB Reserved0000 000C 0801 00000000 000C 0EBF FFFF PCIX0 Addressing configuration Regs 0000 000C 0EC0 00000000 000C 0EC0 00078B Reserved0000 000C 0EC0 00080000 000C 0EC7 FFFF PCIX0 Core Configuration Regs0000 000C 0EC8 00000000 000C 0EC8 0FFF 4KB Reserved0000 000C 0EC8 10000000 000C 0EC8 10FF PCIX0 Simple Message Passing 0000 000C 0EC8 11000000 000C 0EC8 11FF 256B Reserved0000 000C 0EC8 12000000 000C 0ECF FFFF PCIX0 Special Cycle 0000 000C 0ED0 00000000 000C 0EDF FFFF 1MB Reserved0000 000C 0EE0 00000000 000C 0FFF FFFF PCI Memory (PCI-Express & PCI-X)0000 000C 1000 00000000 000C FEFF FFFF 3.8GB PCI-X DDR boot ROM (PCI memory 0000 000C FF00 00000000 000C FFFF FFFF 16MB PCI Memory (PCI-Express & PCI-X)0000 000D 0000 00000000 000F FFFF FFFF 12GB Reserved 40000 0010 0000 00000FFF FFFF FFFF FFFF Reserved 51000 0000 0000 00001FFF FFFF FFFF FFFF PCI Core Space (HB)PCI Memory (PCI-Express & PCI-X)2000 0000 0000 0000FFFF FFFF FFFF FFFFNotes:1.DDR SDRAM and on-chip SRAM can be located anywhere in the Local Memory area of the memory map.2.The Boot ROM and Expansion ROM areas of the memory map are intended for use by ROM or Flash-type devices. While locating volatile DDR SDRAM and SRAM in this region is supported, use of these regions for this purpose is not recommended.3.When the optional boot from PCI-X memory is selected, the PCI-X Boot ROM address space begins at C FF00 0000 (16 MB).4.Never decoded.5.Unpredictable results on Read and Write operations.6.Accessed by means of EBC Peripheral Bank Configuration Registers.Table 1. System Memory Address Map (Sheet 2 of 2)FunctionSub FunctionStart Address End Address SizePowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data SheetTable 2. DCR Address Map (4KB of Device Configuration Registers)Function Start Address End Address Size Total DCR Address Space10003FF1KW (4KB)1By function:Reserved00000B12WClocking Power On Reset00C00D2WSystem DCRs 00E00F2WMemory Controller 0100112WExternal Bus Controller0120132WReserved01401F12WSRAM02002F16WL2 Controller03003F16WMemory Queue04005F32WI2O, DMA0 & DMA106007F32WPLB08008F16WPLB to OPB Bridge Out09009F16WReserved0A00AF16WReserved0B20BF14WInterrupt Controller 00C00CF16WInterrupt Controller 10D00DF16WInterrupt Controller 20E00EF16WInterrupt Controller 30F00FF16WPCI-Express 010011F32WPCI-Express 112013F32WPCI-Express 214015F32WPower Management1601678WReserved16817F24WEthernet MAL1801FF128WReserved2003FF512WNotes:1.DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a sin-gle 32-bit (word) register. One KW (1024W) equals 4KB (4096 bytes).PowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet PowerPC 440 Processor CoreThe PowerPC 440 processor core is designed for high-end applications such as RAID controllers, SAN, ISCSI, routers, switches, printers, set-top boxes, and so on. It is the first processor core to implement the Book E PowerPC embedded architecture and uses the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include:•Up to 800 MHz operation•PowerPC Book E architecture•32KB I-cache, 32KB D-cache–parity on data and tag address - Checking of parity with error injection•Three logical regions in D-cache: Locked, Transient, and Normal•D-cache full-line flush capability•41-bit virtual address, 36-bit (64GB) physical address•Superscalar, out-of-order execution•Seven-stage pipeline•Three execution pipelines•Dynamic branch prediction•Memory management unit–64-entry, full associative, unified TLB with parity–Separate instruction and data micro-TLBs–Storage attributes for write-through, cache-inhibited, guarded, and big or little endian•Debug facilities–Multiple instruction and data range breakpoints–Data value compare–Single step, branch, and trap events–Non-invasive real-time trace interface•24 DSP instructions–Single cycle multiply and multiply-accumulate–32 x 32 integer multiplyInternal BusesThe PowerPC 440SPe features three IBM standard on-chip buses: the Processor Local Bus (PLB), the On-Chip Peripheral Bus (OPB), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, the PCI Express and the DDR PCI-X bridges connect to the PLB. The OPB hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores.The PLB has a Crossbar arbiter that supports data transfer between the PLB master and two slave segments identified as the Low Latency (LL) and High Bandwidth (HB) segments. The LL segment allows PLB masters CPU and I2O, that are adversely affected by latency, to communicate with slave devices with minimal latency. The HB segment allows PLB masters DMA, XOR, PCI and PCI Express to exchange large blocks of data with SDRAM, PCI and PCI Express without interfering with the low latency PLB masters.Bus features include:•PLB–128-bit implementation of the PLB architecture–Separate and simultaneous read and write data paths–64-bit address–Simultaneous control, address, and data phases–Four levels of pipelining–Byte enable capability supporting unaligned transfers–32- and 64-byte burst transfersPowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet–166MHz, maximum 5.2GB/s (simultaneous read and write)–Processor vs Bus clock ratios of N:1 and N:2•OPB–Dynamic bus sizing: 32, 16, and 8-bit data path–32-bit address–83.33MHz, maximum 333MB/s•DCR–Register control bus–32-bit data path–10-bit addressOn-Chip SRAM/L2 CacheFeatures include:•Four banks of 64KB each for a total of 256KB•Configurable as either L2 cache or SRAM•Memory cycles supported:–Single beat read and write, 1 to 16 bytes–Quadword Read and Write burst for 12-bit master–Guarded memory accesses on 4KB boundaries•Sustainable 2.6GB/s peak bandwidth at 166MHz•Use as an L2 cache improves processor performance and reduces the PLB load–Cache coherency maintained by a hardware snoop mechanism on the Low Latency (LL) PLB or by software–Data Array and Tag Array parity–Unified data and instruction cache–Four-way set associative–36-bit addressing–Full LRU replacement algorithm–Write through, look aside•Use as Ethernet packet store allows Ethernet packets to be held for processing by the Ethernet corePCI ExpressFeatures include:•Three independent PCI Express interfaces–One 8 lanes–Two4lanes– 2.5 GB/sec full duplex per lane•Compliant with PCI Express base specification 1.0a•Each PCI Express port can be End Point or Root Complex. (Upstream & Downstream)–Applications compliant with MSI rules are limited to one End Point port per PPC440SPe•PCI-Express to PCI-Express opaque (Non-Transparent) bridge•Power Management•Supports one virtual channel (VC0) no Traffic Class (TC) filtering•Maximum Payload block size 512 Bytes•Supports up to 1024 byte maximum Read request size•Requests supported:–up to 4 posted outbound Write requests (memory and messages)–up to 4 posted inbound Write requests–up to 4 outbound Read requests outstanding on PCI Express–up to 4 inbound Read requests outstanding on PCI Express–Outbound I/O request as a PCI Express Root Port–Inbound I/O request as a PCI Express End PointPowerPC 440SPe Embedded Processor Revision 1.23 - Sept 21, 2006Preliminary Data Sheet•Buffering in each PCI Express Port for the following transaction types:–4K byte Replay buffer: up to 8 in flight transactions–2K bytes for Outbound posted Writes–8K bytes for Outbound Reads completion•2K prefetch request from first I2O/DMA PLB Master•1K prefetch request from 2nd I2O/DMA PLB Master•1K prefetch request from first PCIE 4x links•1K prefetch request from 2nd PCIE 4x links•256 byte from the PPC440–2K bytes for Inbound posted Writes–2K bytes for Inbound Reads completion•Parity checking on each buffer•POM Programmable Outbound Memory Regions: 3 Memory, 1 I/O, 1 Message, 1 config, 1 Internal Regs •PIM Programmable Inbound Memory Regions: 4 Memory, 1 I/O, 1 Expansion ROM•INTx Interrupts support (PCI legacy):–up to 4 INTx Termination for Root Ports. A/B/C/D interrupts are wired to the UIC–A/B/C/D INTx types Generation for Endpoints•MSI - Message Signaled Interrupts–MSI Generation for End Point–MSI Termination for Root Ports–MSI_X Termination for Root PortsDDR PCI-X InterfaceThe DDR PCI-X interface allows connection of PCI and PCI-X devices to the PowerPC processor and local memory. The PCI-X interface supports 64-bit PCI-X bus in DDR mode 2. It can be configured for either host or adapter mode. PCI 32/64-bit legacy mode, compatible with PCI Version 2.3, is also supported.Features include:•PCI-X2.0–Split transactions–Frequency to 266MHz–32- and 64-bit address/data bus–ECC supported for 266MHz Mode 2 only•PCI 2.3 backward compatibility–Frequency to 66MHz–32- and 64-bit bus•Can be the PCI Host Bus Bridge or an Adapter Device PCI interface•Optional PCI arbitration function with PCI and PCI-X mode 1, supporting up to four external devices, that can be disabled for use with an external arbiter•Support for PLB-based (external to PLB–PCI-X bridge) I2O•Support for Message Signaled Interrupts (MSI) on both in- and out-bound interrupts•Simple message passing capability•Asynchronous to the PLB•PCI Power Management Version 1.1•PCI arbitration function with PCI-X Mode 2 support (optional)•PCI register set addressable both from on-chip processor and PCI device sides•Ability to boot from PCI-X bus memory•Error tracking/status•Supports initiation of transfer to the following address spaces:–Single beat I/O reads and writes–Single beat and burst memory reads and writes–Single beat configuration reads and writes (Type 0 and Type 1)–Single beat special cycles。