智能安防 硬件部分 外文资料翻译

淮阴工学院毕业设计(论文)外文资料翻译系（院）：电子信息工程系专业：测控技术与仪器姓名：严素琴学号：1051203431外文出处：Springer-Link电子期刊Springer-Link(用外文写)附件： 1.外文资料翻译译文；2.外文原文。

附件1：外文资料翻译译文SJA1000 独立的CAN控制器应用指南1 介绍SJA1000是一个独立的CAN控制器，它在汽车和普通的工业应用上有先进的特征。

由于它和PCA82C200 在硬件和软件都兼容，因此它将会替代PCA82C200。

SJA1000有一系列先进的功能适合于多种应用，特别在系统优化、诊断和维护方面非常重要。

本文是要指导用户设计基于SJA1000 的完整的CAN节点。

同时本文还提供典型的应用电路图和编程的流程图。

2 概述SJA1000 独立的CAN控制器有2个不同的操作模式：BasicCAN模式(和PCA82C200）兼容PeliCAN模式BasicCAN模式是上电后默认的操作模式。

因此，用PCA82C200开发的已有硬件和软件可以直接在SJA1000上使用，而不用作任何修改。

PeliCAN模式是新的操作模式，它能够处理所有CAN2.0B 规范的帧类型。

而且它还提供一些增强功能使SJA1000能应用于更宽的领域。

2.1 CAN 节点结构通常，每个CAN 模块能够被分成不同的功能块。

SJA1000使用[3] [4] [5]最优化的CAN收发器连接到CAN 。

收发器控制从CAN控制器到总线物理层或相反的逻辑电平信号。

上面一层是一个CAN 控制器，它执行在CAN规范[8]里规定的完整的CAN协议。

它通常用于报文缓冲和验收滤波，而所有这些CAN功能，都由一个模块控制器控制它负责执行应用的功能。

例如，控制执行器、读传感器和处理人机接口（MMI）。

如图1所示，SJA1000独立的CAN控制器通常位于微型控制器和收发器之间，大多数情况下这个控制器是一个集成电路。

图1 CAN模块装置2.2 结构图下图是SJA1000 的结构图图2 SJA1000的结构图根据CAN规范，CAN核心模块控制CAN帧的发送和接收。

接口管理逻辑负责连接外部主控制器，该控制器可以是微型控制器或任何其他器件。

经过SJA1000复用的地址/数据总线访问寄存器和控制读/写选通信号都在这里处理。

另外，除了PCA82C200已有的BasicCAN功能，还加入了一个新的PeliCAN 功能。

因此，附加的寄存器和逻辑电路主要在这块里生效。

SJA1000的发送缓冲器能够存储一个完整的报文（扩展的或标准的）。

当主控制器初始化发送，接口管理逻辑会使CAN 核心模块从发送缓冲器读CAN 报文。

当收到一个报文时，CAN核心模块将串行位流转换成用于验收滤波器的并行数据。

通过这个可编程的滤波器SJA1000 能确定主控制器要接收哪些报文。

所有收到的报文由验收滤波器验收并存储在接收FIFO。

储存报文的多少由工作模式决定，而最多能存储32个报文。

因为数据超载可能性被大大降低，这使用户能更灵活地指定中断服务和中断优先级。

3 系统为了连接到主控制器，SJA1000提供一个复用的地址/数据总线和附加的读/写控制信号。

SJA1000可以作为主控制器外围存储器映射的I/O器件。

3.1 SJA1000 的应用SJA1000 的寄存器和管脚配置使它可以使用各种各样集成或分立的CAN收发器。

由于有不同的微控制器接口，应用可以使用不同的微控制器。

图3所示是一个包括80C51微型控制器和PCA82C251收发器的典型SJA1000应用。

CAN 控制器功能像是一个时钟源，复位信号由外部复位电路产生。

在这个例子里，SJA1000 的片选由微控制器的P2.7口控制。

否则，这个片选输入必须接到VSS。

它也可以通过地址译码器控制，例如，当地址/数据总线用于其他外围器件的时侯。

图3 典型的SJA1000应用3.2 电源SJA1000有三对电源引脚，用于CAN 控制器内部不同的数字和模拟模块。

VDD1/VSS1：内部逻辑（数字）VDD2/VSS2：输入比较器（模拟）VDD3/VSS3：输出驱动器（模拟）为了有更好的EME性能，电源应该分隔开来。

例如为了抑制比较器的噪声，VDD2 可以用一个RC滤波器来退耦。

3.3 复位为了使SJA1000正确复位，CAN控制器的XTAL1管脚必须连接一个稳定的振荡器时钟（见3.4）节。

引脚17的外部复位信号要同步并被内部延长到15个tXTAL。

这保证了SJA1000 所有寄存器能够正确复位（见[1] ）。

要注意的是上电后的振荡器的起振时间必须要考虑。

3.4 振荡器和时钟策略SJA1000能用片内振荡器或片外时钟源工作。

另外CLKOUT管脚可被使能，向主控制器输出时钟频率。

图4显示了SJA1000应用的四个不同的定时原理。

如果不需要CLKOUT信号，可以通过置位时钟分频寄存器（Clock Off=1）关断。

这将改善CAN 节点的EME性能。

CLKOUT信号的频率可以通过时钟分频寄存器改变：fCLKOUT = fXTAL / 时钟分频因子（1，2，4，6，8 ，10 ，12 ，14）。

上电或硬件复位后，时钟分频因子的默认值由所选的接口模式（引脚11）决定。

如果使用16MHz的晶振，Intel 模式下CLKOUT 的频率是8 MHz， Motorola 模式中复位后的时钟分频因子是12，这种情况CLKOUT会产生1.33MHz的频率。

图4 时钟策略3.4.1 睡眠和唤醒置位命令寄存器的进入睡眠位（BasicCAN ）模式或模式寄存器（PeliCAN模式）的睡眠模式位后，如果没有总线活动和中断等待，SJA1000就会进入睡眠模式。

振荡器在15个CAN位时间内保持运行状态。

此时,微型控制器用CLKOUT频率来计时，进入自己的低功耗模式。

如果出现三个唤醒条件之中的一个[1]，振荡器会再次启动并产生一个唤醒中断。

振荡器稳定后，CLKOUT频率被激活。

3.5 CPU接口SJA1000支持直接连接到两个著名的微型控制器系列：80C51和68xx。

通过SJA1000的MODE引脚可选择接口模式：Intel模式： MODE 高Motorola模式： MODE 低地址/数据总线和读/写控制信号在Intel模式和Motorola模式的连接如图5所示。

Philips基于80C51系列的8位微控制器和XA结构的16位微型控制器都使用Intel 模式。

为了和其他控制器的地址数据总线和控制信号匹配，必须要附加逻辑电路。

但是必须确保在上电期间不产生写脉冲。

另一个方法在这个时候使片选输入是高电平，禁能CAN 控制器。

图5 SJA1000的CPU时钟接口3.6 物理层接口为了和PCA82C200兼容,SJA1000包括一个模拟接收输入比较器电路。

如果收发器的功能由分立元件实现，就要用到这个集成的比较器。

图6 SJA1000的接收输入比较器如果使用外部集成收发器电路，而且没有在时钟分频寄存器里使能比较器旁路功能，RX1输出要被连接到2.5V 的参考电压（现有的收发器电路参考电压输出）。

图6显示了两种设置的相应电路：CBP=激活和CBP=非激活另外唤醒信号的通道被下拉对于使用集成的收发器电路的所有新应用我们建议激活（使用）SJA1000的比较器旁路功能（图7）。

如果这个功能被使能，施密特触发器的输入有效，内部的传播延迟tD2比接收比较器的延迟tD1要小得多。

它对最大的总线长度[6]有正面的影响。

另外，休眠模式的电流将显著降低。

图7 带有集成收发器电路的标准应用附件2：外文原文（复印件）SJA1000 Stand-alone CAN controller1. INTRODUCTIONThe SJA1000 is a stand-alone CAN Controller product with advanced features for use in automotive and general industrial applications. It is intended to replace the PCA82C200 because it is hardware and software compatible. Due to an enhanced set of functions this device is well suited for many applications especially when system optimization, diagnosis and maintenance are important.This report is intended to guide the user in designing complete CAN nodes based on the SJA1000. The report provides typical application circuit diagrams and flow charts for programming.2. OVERVIEWThe stand-alone CAN controller SJA1000 1 h as two different Modes of Operation: - BasicCAN Mode (PCA82C200 compatible)- PeliCAN ModeUpon Power-up the BasicCAN Mode is the default mode of operation. Consequently, existing hardware and software developed for the PCA82C200 can be used without any change. In addition to the functions known from the PCA82C200 [7], some extra features have been implemented in this mode which make the device more attractive. However, they do not influence the compatibility to the PCA82C200.The PeliCAN Mode is a new mode of operation which is able to handle all frame types according to CAN specification 2.0B [8]. Furthermore it provides a couple of enhanced features which makes the SJA1000 suitable for a wide range of applicatio ns.2.1 CAN Node ArchitectureGenerally each CAN module can be divided into different functional blocks. The connection to the CAN bus lines is usually built with a CAN Transceiver optimized for the applications [3], [4], [5]. The transceiver controls the logic level signals from the CAN controller into the physical levels on the bus and vice versa.The next upper level is a CAN Controller which implements the complete CAN protocol defined in the CAN Specification [8]. Often it also covers message buffering and acceptance filtering.All these CAN functions are controlled by a Module Controller which performs the functionality of the application. For example, it controls actuators, reads sensors and handles the man-machine interface (MMI).As shown in Figure 1 the SJA1000 stand-alone CAN controller is always located between a microcontroller and the transceiver, which is an integrated circuit in most cases.2.2 Block DiagramThe following figure shows the block diagram of the SJA1000.The CAN Core Block controls the transmission and reception of CAN frames according to the CAN specification.The Interface Management Logic block performs a link to the external host controller which can be a microcontroller or any other device. Every register access via theSJA1000 multiplexed address/data bus and controlling of the read/write strobes is handled in this unit. Additionally to the BasicCAN functions known from thePCA82C200, new PeliCAN features have been added. As a consequence of this, additional registers and logic have been implemented mainly in this block.The Transmit Buffer of the SJA1000 is able to store one complete message (Extended or Standard). Whenever a transmission is initiated by the host controller the Interface Management Logic forces the CAN Core Block to read the CAN message from the Transmit Buffer.When receiving a message, the CAN Core Block converts the serial bit stream into parallel data for the Acceptance Filter. With this programmable filter the SJA1000 decides which messages actually are received by the host controller.All received messages accepted by the acceptance filter are stored within a Receive FIFO. Depending on the mode of operation and the data length up to 32 messages can be stored. This enables the user to be more flexible when specifying interrupt services and interrupt priorities for the system because the probability of data overrun conditions is reduced extremely.3. SYSTEMFor connection to the host controller, the SJA1000 provides a multiplexed address/data bus and additional read/write control signals. The SJA1000 could be seen as a peripheral memory mapped I/O device for the host controller.3.1 SJA1000 ApplicationConfiguration Registers and pins of the SJA1000 allow to use all kinds of integrated or discrete CAN transceivers. Due to the flexible microcontroller interface applications with different microcontrollers are possible.In Figure 3 a typical SJA1000 application diagram including 80C51 microcontroller and PCA82C251 transceiver is shown. The CAN controller functions as a clock source and the reset signal is generated by an external reset circuitry. In this example the chip select of the SJA1000 is controlled by the microcontroller port function P2.7. Instead of this, the chip select input could be tied to VSS. Control via an address decoder is possible, e.g., when the address/data bus is used for other peripherals.3.2 Power SupplyThe SJA1000 has three pairs of voltage supply pins which are used for different digital and analog internal blocks of the CAN controller.VDD1 / VSS1: internal logic (digital)VDD2 / VSS2: input comparator (analog)VDD3 / VSS3: output driver (analog)The supply has been separated for better EME behaviour. For instance the VDD2 can be de-coupled via an RC3.3 ResetFor a proper reset of the SJA1000 a stable oscillator clock has to be provided at XTAL1 of the CAN controller, see also chapter 3.4. An external reset on pin 17 is synchronized and internally lengthened to 15 . This guarantees a correct reset of all SJA1000 registers (see [1]). Note that an oscillator start-up time has to be taken into account uponpower-up.3.4 Oscillator and Clocking StrategyThe SJA1000 can operate with the on-chip oscillator or with external clock sources. Additionally the CLK OUT pin can be enabled to output the clock frequency for the host controller. Figure 4 shows four different clocking principles for applications with the SJA1000. If the CLK OUT signal is not needed, it can be switched off with the Clock Divider register (Clock Off = 1). This will improve the EME performance of the CAN node.The frequency of the CLK OUT signal can be changed with the Clock Divider Register: f CLK OUT = f XTAL / Clock Divider factor (1,2,4,6,8,10,12,14).Upon power up or hardware reset the default value for the Clock Divider factor depends on the selected interface mode (pin 11). If a 16 MHz crystal is used in Intel mode, the frequency at CLK OUT is 8 MHz. In Motorola mode a Clock Divider factor of 12 is used upon reset which results in 1,33 MHz in this case.3.4.1 Sleep and Wake-upUpon setting the Go To Sleep bit in the Command Register (BasicCAN mode) or the Sleep Mode bit in the Mode Register (PeliCAN mode) the SJA1000 will enter Sleep Mode if there is no bus activity and no interrupt is pending. The oscillator keeps on running until 15 CAN bit times have been passed. This allows a microcontroller clocked with the CLK OUT frequency to enter its own low power consumption mode.If one of three possible wake-up conditions 1 o ccurs the oscillator is started again and a Wake-up interrupt is generated. As soon as the oscillator is stable the CLK OUT frequency is active.3.5 CPU InterfaceThe SJA1000 supports the direct connection to two famous microcontroller families:80C51 and 68xx. With the MODE pin of the SJA1000 the interface mode is selected. Intel Mode: MODE = highMotorola Mode: MODE = lowThe connection for the address/data bus and the read/write control signals in both Intel and Motorola mode is shown in Figure 5. For Philips 8-bit microcontrollers based on the 80C51 family and the 16-bit microcontrollers with XA architecture the Intel Mode is used.For other controllers additional glue logic is necessary for adaptation of the address/data bus and the control signals. However, it has to be made sure that no write pulses are generated during power-up. Another possibility is to disable the CAN controller with a high-level on the chip select input in this time.3.6 Physical Layer InterfaceFor compatibility purposes with the PCA82C200, the SJA1000 includes an analog receive input comparator circuit. This integrated comparator can be used if thetransceiver function is realized with discrete components.If an external integrated transceiver circuit is used and the comparator bypass function isnot enabled in the Clock Divider Register, the RX1 input has to be connected to a reference voltage of 2.5V (reference voltage output of existing transceiver circuits). Figure 6 shows the equivalent circuits for both configurations: CBP = active and CBP = inactive. Additionally the path for the wake-up signal is drawn. For all new applications where an integrated transceiver circuit is used, it is recommended to activate the comparator bypass function of the SJA1000 (Figure 7). If this function is enabled, a schmitt-trigger input is used and the internal propagation delay tD2 is much shorter as the delay tD1. of the receive comparator. This has a positive impact on the maximum bus length [6]. Additionally, it will reduce the supply current in sleep mode significantly.。