se555

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at .
8 VCC 7 DISCH 6 THRES 5 CONT
NC TRIG
NC OUT
NC
3 2 1 20 19
4
18
5
17
6
16
7
15
8
14
9 10 11 12 13
NC DISCH NC THRES NC
NC RESET
NC CONT
NC
NC – No internal connection
DESCRIPTION/ORDERING INFORMATION
(2) Package drawings, thermal data, and symbolization are available at /packaging.
RESET
Low High High High
Table 1. FUNCTION TABLE
TRIGGER VOLTAGE (1)

NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010
FUNCTIONAL BLOCK DIAGRAM
VCC
8
CONT
6 THRES
5 ÎÎÎÎ
RESET 4
ÎÎÎ R1
R
1ÎÎÎ
S
ÎÎÎ
3 OUT
11.2 V
11.2 V 11.2 V
10.6
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING
PDIP – P SOIC – D SOP – PS TSSOP – PW PDIP – P SOIC – D PDIP – P SOIC – D PDIP – P SOIC – D CDIP – JG LCCC – FK
NE555P NE555D NE555DR NE555PSR NE555PW NE555PWR SA555P SA555D SA555DR NA555P NA555D NA555DR SE555P SE555D SE555DR SE555JG SE555FK
NE555P NE555 N555 N555 SA555P SA555 NA555P NA555 SE555P SE555D SE555JG SE555FK
NA555, NE555, SA555, SE555
SLFS022H – SEPTEMBER 1973 – REVISED JUNE 2010

TA 0°C to 70°C –40°C to 85°C –40°C to 105°C –55°C to 125°C
VTHRES MAX VCC = 15 V
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
MINΒιβλιοθήκη MAX UNIT18 V
VCC
V
±225 mA
97
qJA
Package thermal impedance(3) (4)
P package PS package
85 °C/W
95
PW package
149
qJC
Package thermal impedance(5) (6)
FK package JG package
(TOP VIEW)
• Adjustable Duty Cycle • TTL-Compatible Output Can Sink or Source up
to 200 mA
SE555...FK PACKAGE (TOP VIEW)
NC GND NC CC V NC
GND 1 TRIG 2 OUT 3 RESET 4
The threshold and trigger levels normally are two-thirds and one-third, respectively, of VCC. These levels can be altered by use of the control-voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set, and the output goes high. If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is reset and the output is low. The reset (RESET) input can override all other inputs and can be used to initiate a new timing cycle. When RESET goes low, the flip-flop is reset, and the output goes low. When the output is low, a low-impedance path is provided between discharge (DISCH) and ground.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
• Timing From Microseconds to Hours • Astable or Monostable Operation
NA555...D OR P PACKAGE NE555...D, P, PS, OR PW PACKAGE
SA555...D OR P PACKAGE SE555...D, JG, OR P PACKAGE
(1) Voltage levels shown are nominal.
2
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Copyright © 1973–2010, Texas Instruments Incorporated
Product Folder Link(s): NA555 NE555 SA555 SE555
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage(2)
VI
Input voltage
IO
Output current
CONT, RESET, THRES, TRIG D package
Irrelevant <1/3 VCC >1/3 VCC >1/3 VCC
THRESHOLD VOLTAGE (1)
Irrelevant Irrelevant >2/3 VCC <2/3 VCC
OUTPUT
DISCHARGE SWITCH
Low
On
High
Off
Low
On
As previously established
Copyright © 1973–2010, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.
The output circuit is capable of sinking or sourcing current up to 200 mA. Operation is specified for supplies of 5 V to 15 V. With a 5-V supply, output levels are compatible with TTL inputs.
2 TRIG
ÎÎÎ
1 GND A. Pin numbers shown are for the D, JG, P, PS, and PW packages. B. RESET can override TRIG, which can override THRES.