MEMORY存储芯片MT29F32G08AFABAWPB中文规格书

General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (I/Ox) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection and monitor device status (R/B#).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). There is at least one NAND Flash die per chip enable
signal. For further details, see Device and Array Organization.
This device has an internal 4-bit ECC that can be enabled using the GET/SET features.
See Internal ECC and Spare Area Mapping for ECC for more information.
Notes: 1.See Device and Array Organization for detailed signal connections.
Table 28: DC Characteristics and Operating Conditions (1.8V)
Notes: 1.Typical and maximum values are for single-plane operation only. If device supports dual-
plane operation, values are 20mA (TYP) and 40mA (MAX).
2.Values are for single-die operations. Values could be higher for interleaved-die opera-
tions.
3.Measurement is taken with 1ms averaging intervals and begins after V CC reaches
V CC(MIN).
4.Test conditions for V OH and V OL.
5.DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full.
Electrical Specifications – AC Characteristics and Operating Conditions Table 29: AC Characteristics: Command, Data, and Address Input (3.3V)
Notes: 1.Operating mode timings meet ONFI timing mode 5 parameters.
2.Timing for t ADL begins in the address cycle, on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
Table 30: AC Characteristics: Command, Data, and Address Input (1.8V)
Notes: 1.Operating mode timings meet ONFI timing mode 4 parameters.
2.Timing for t ADL begins in the address cycle on the final rising edge of WE#, and ends
with the first rising edge of WE# for data input.
RDY
Figure 89: READ PAGE CACHE SEQUENTIAL
WE#
CE#
ALE
CLE
RE#
RDY
I/Ox WE#
CE#
ALE
CLE
RE#
RDY
I/Ox
Don’t Care。