Common Mode EMI Study and Reduction Technique

Common Mode EMI Study and Reduction Technique in Interleaved Multi-channel PFC
Pengju Kong1), 2), Shuo Wang1), Chuanyun Wang1) and Fred C. Lee1)
1)Center for Power Electronics Systems, Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA 2)Department of Electrical Engineering
Tsinghua University
Beijing 100084 CHINA
Abstract— Interleaved Multi-channel Power factor correction (PFC) converter is very popular nowadays with its ability to reduce the input and output current ripples. In this paper, common mode (CM) EMI noise emission model of multi-channel PFC is studied. Topolog y modification to implement balance technique is made to reduce its CM noise emission. To improve the hig h frequency balance, a novel topolog y with coupled-inductor structure is proposed. Desig n g uideline is provided to achieve balance in practice. This topolog y can g reatly reduce CM noise with only little chang es to the orig inal multi-channel PFC topolog y. Effects of phase shift and channel shedding on this solution are also studied. The proposed topolog y has effectively reduced CM noise under any phase shift and channel shedding condition. A two-channel PFC is built to verify the proposed balance technique. Experimental results show that CM noise is reduced up to 20dBuV between 150 kHz and 7 MHz.
I.I NTRODUCTION
Switching power converters have high electromagnetic
pollution due to their fast switching at relatively high voltage
and current. To limit their interference with other devices,
standards are mandatory to comply with for most of the
switching power converters. As a result, large EMI filter is
needed to reduce the converter’s EMI noise level below the standards in the whole specified frequency range, normally
from 150 kHz to 30 MHz. Such large EMI filter can take up
to 1/6 of the converter size and contribute to 1 percent power
loss. Today, to achieve high power density and high
efficiency, a lot of efforts have been made to reduce EMI
filter size by reducing the EMI noise emission in the PFC stage. Multi-channel PFC with interleaving feature is one promising technique to achieve this goal [1-4]. With proper interleaving strategy, both differential mode (DM) and CM noise emission can be reduced. [4]
This paper studies the CM EMI noise emission of multi-
channel PFC. Balance technique is introduced to further reduce the CM noise emission. Topology modification is made to implement balance in multi-channel PFC. Balance condition is derived based on the CM noise model. To improve high frequency noise reduction, a novel coupled-inductor structure is proposed. The guideline for achieving balance in practice is given. This proposed solution can
This work was supported primarily by the ERC Program of the National Science Foundation under Award Number EEC-9731677. greatly reduce the CM noise and it is independent of the
phase shift angle among phases, as well as the channel
number. Effect of channel shedding on this balance solution
is also studied. Balance can still effectively reduce the CM
noise when channels are shut down for higher efficiency at light load. A two-channel PFC prototype is built and
experimental results verify that the proposed solution can
achieve up to 20dBuV noise reduction in multi-channel PFC
converters.
II.CM NOISE IN MULTI-CHANNEL PFC
A two-channel PFC is used as an example for the CM noise study, as shown in Fig. 1. Parasitic capacitances that are important for CM noise are included. C d is drain-to-ground capacitance. C b is output-bus-to-ground capacitance. It is assumed that the two channels are identical including the parasitics. The CM noise model of this converter is shown in Fig. 2. The effect of line impedance stabilization networks (LISN) is modeled as two 50 Ohm resistors in parallel. A voltage source is used to model a switching MOSFET. [5] So in two-channel PFC there are two independent noise sources.
Fig. 1. Two-channel interleaved PFC converter
d
Fig. 2. CM noise model for two-channel PFC converter According to the superposition theory, effect of each noise source can be studied separately. Fig. 3(a) shows the CM noise model for noise source V1. In this case V2 is short-
circuit. High frequency voltage source V 1 will generate a CM current on the parasitic capacitance C d . This current i CM1 will return through the ground to the LISN and generate a noise voltage on LISN resistors. Effect of V 2 is shown in Fig. 3(b). CM noise current i cm2 is generated by V 2. The sum of two currents is the total CM noise current generated in the two-channel PFC converter.
)(21CM CM LISN CM i i R v += (1)
v CM1
v
(a) Effect of V 1 (b) Effect of V 2 Fig. 3. Effect of one noise source on the CM noise
When the two channels share the same control signal without any phase shift, they generate the same noise current so that the total current is twice of that in each channel. Interleaving the two channels can cancel some harmonics in the total CM noise current so that CM noise will be reduced. One common practice is to interleave the two channels with 180o phase shift. All the odd order harmonics in i cm1 and i cm2 are out of phase and cancel each other. So that in the total CM noise only the even order harmonics remain. Depending on the switching frequency and EMI specifications, other phase shift angle could be a better choice from the EMI filter size reduction point of view. For example, with 130 kHz switching frequency, also considering 150 kHz starting
frequency of EMI specifications, it is more important to cancel the second harmonic at 260 kHz. In this case 90o phase
shift is preferred. [4]
Cancellation of certain harmonics by this means requires accurate control of phase shift angle between channels.
General CM noise cancellation concepts, on the other hand,
can reduce CM noise in the whole low frequency range up to
10 MHz. Several CM noise cancellation techniques have
been proposed in [5-11]. In this paper, balance technique is applied to reduce the CM noise because of its simple implementation. III. CM NOISE REDUCTION WITH BALANCE TECHNIQUE A. Balance concept
In Fig. 3(a), V 1 and the inductors, capacitors forms a
bridge, which allows us to utilize the Wheatstone bridge theory to balance the bridge and minimize the CM noise. This concept is proposed in [5]. A Wheatstone bridge is shown in Figure 4. As long as the impedances on the four bridge legs satisfy the balance condition: 1234
Z Z Z Z = (1) the voltage between node M and N will be always zero
disregarding the source V.
This Balance concept can be applied to multi-channel PFC converter to reduce its CM noise emission. Balance should be achieved in both Fig. 3(a) and Fig. 3(b) so that effects of V 1 and V 2
B. Implementing balance concept in multi-channel PFC converter
Topology modification is made to implement balance in
two-channel PFC, as shown in Fig. 5. An inductor is added in the current return path. As a result, the CM noise model is changed as shown in Fig. 6(a). According to the superposition theory, effect of noise source V 1 on CM noise is modeled in Fig. 6(b). L L D 1D 2D 3D 4
V AC
C d C d
C b L b
Fig. 5. Two-channel PFC with balance technique V 1V 2
C b C d C d
L L
L b
V 1C b
C d C d
L L
L b
(a) CM noise model (b) Effect of V 1
Fig. 6. CM noise model of two-channel PFC with balance technique
In Fig. 6(b), L b and L are in parallel. So do C b and C d . To minimize the effect of V 1 on CM noise, balance condition should be achieved: Cb Cd Cd L Lb L
Z Z Z Z ////=
(3) Eq. 3 is also the balance condition for noise source V 2, since the model for the effect of V 2 is the same in topology as
that of V 1. As a result, achieving balance in two-channel PFC can reduce the CM noise in both channels, disregarding the phase shift angle between the two sources.
In frequency range below 2 MHz, the impedances of inductors are determined by the inductance and the impedances of parasitic capacitances are determined by the capacitance values. Balance can be achieved by designing L b value based on L and parasitic capacitance values. C. Coupled-inductor structure to achieve balance at high frequency
Although balance can be achieved by controlling L b at low frequency, it is not possible to control the parasitics for high frequency balance. Fig. 7 shows the equivalent model of boost inductor including its equivalent parallel capacitance (EPC) and equivalent parallel resistance (EPR). Beyond 2 MHz, EPC and EPR become dominant in impedance for boost inductors. Balance condition is no longer achieved. Although it is possible to achieve balance by compensating EPC and EPR with extra capacitors and resistors, the resulted large EPC will increase the high frequency DM noise. [12]
L
EPC
EPR
Fig. 7. Model of an inductor considering high frequency parastics
In single channel PFC, the added inductor is coupled with the boost inductor to solve the high frequency balance issue [5]. The coupling coefficient should be high to achieve better performance at high frequency. However, in multi-channel PFC converter where more than one boost inductors need to be coupled with the added inductor L b , it becomes complicated. A novel coupled-inductor structure is proposed in multi-channel PFC converters to achieve high frequency
balance. One winding is added in the boost inductor in each
channel. And these windings are inserted in series in the current return path, as shown in Fig. 8(a). Fig. 8(b) shows its CM noise model. Fig. 9(a) shows the effect of V 1. To study
its balance condition, an equivalent decoupled model is used
for this model, as shown in Fig. 9(b).
V
(a) Proposed multi-channel PFC topology with balance technique and
coupled-inductor structure
(b) CM noise model
Fig. 8 Proposed multi-channel PFC topology with balance technique and
coupled-inductor structure
d
(a) CM noise model with only the effect of V 1
(b) Equivalent decoupled model Fig. 9 CM noise model for one noise source and its equivalent decoupled model The ratio of Z a and Z b can be derived by matching the impedances of Fig. 9(a) and Fig. 9(b). Assume that coupling
coefficients between L and L a are unity, and the turns for windings L and L b are N1 and N2, the voltages and the currents across the windings have the relation as shown in
Eq. 4.
⎪
⎪
⎪⎭
⎪⎪⎪⎬⎫==+−==211111212
1
i i V V V N N V V N N V V n n m n n m m
(4)
The ratio of Z a and Z b can be derived from Eq. 4.
12
1//21+==N N i V i V Z Z n m b a (5)
Substitute (5) into (3), the balance condition for noise source V 1 is,
d b C C N N =21 (6) According to Eq. 4 and 6, with high coupling coefficient between L and L b , th
e balance condition is determined only by the turns ratio, effects o
f EPC and EPR are eliminated. The same procedure can be done to derive the balance condition for V 2. Since the inductor L and parasitic capacitance C d in all channels are the same, Eq. 6 is also the balance condition for noise source V 2. It is for both noise source and independent on the relation of V 1 and V 2. As lon
g as this balance condition is achieved, CM noise in the two-channel PFC can be minimized.
D. Achieving balance in N-channel PFC
The balance technique can be extended to multi-channel PFC with any channel number. Assume the channel number is N, there will be N noise sources in the model. Again superposition theory is used to analyze the effect of any one of the noise source. The CM noise model with one noise source is shown in Fig. 10(a). Following the same procedure, an equivalent decoupled model is introduced and shown in Fig. 10(b). Balance condition for this N-channel PFC model is
1−+=N C C Z Z d
b bN
aN
(7).
d
d
(b) CM noise model for N-channel PFC
d
(b) Equivalent decoupled model
Fig. 10 CM noise model for N-channel PFC and its equivalent decoupled
model
The ratio of Z aN and Z bN can be derived following the same
procedure.
⎪
⎪⎪⎪⎭⎪⎪⎪⎪
⎪
⎬
⎫==−=−==
∑−=211
1
2121...
2121i i V V N N V V N N V V N N V V n x x n m (8)
12
1//21−+==N N N i V i V Z Z m bN
aN (9)
The balance condition for N-channel PFC is derived by substitute (9) into (7). And it becomes the same as Eq. 6. The same conclusion can be derived for any other noise source. This balance condition can reduce the total CM noise of N-channel PFC converter and independent of the channel number.
E. Implementing balance in practice
In practice, Balance condition can be achieved in the multi-channel PFC converter by adjusting either turns ratio or parasitic capacitances according to Eq. 6. One method is to determine N2 according to the parasitic capacitances C b and C d . In PFC converters, C b is usually more than 10 times of C d . According to Eq. 6, N 2 is very small compared to N1. So in the implementation, a winding of 2 to 4 turns is needed to add on each boost inductor. Another method is to predetermine a proper turns ratio, and adjust C b or C d to achieve balance.
According to the analysis in [5], high turns ratio is preferred to achieve better balance. To achieve high turns ratio, N2 should be minimized to be 1 turn. In this case, to achieve balance, extra capacitor is added between output bus and ground to increase C b .
Another benefit of high turns ratio is that it avoids possible increase of the channel current ripple. In this coupled-inductor structure, the boost inductors in all channels are indirectly coupled. This coupling among channels will affect the channel current ripples of the converter. Such coupling effect is discussed and widely used in voltage regulation module (VRM) applications. [13] In the VRM application, take two-channel interleaved buck converter for example, the two inductors are reverse coupled, as shown in Fig. 11. The channel current ripple is reduced. However, in the proposed PFC application, the coupling polarity is the opposite and the channel current ripple will be increased. The stronger
coupling between two channels, the larger channel current ripple does the converter have, which is not desirable. To estimate the coupling effect, coupling coefficient between two channels in boost PFC converter can be derived by calculating the equivalent self-inductance L e in each channel and mutual inductance M e between the two channels, as given in Eq. 10 and 11. Assuming the coupling coefficient between L and L b is unity, the equivalent coupling coefficient between two channels can be calculated in Eq. 12.
b e L M L L 22++= (10)
b e L M M 22+= (11) 2
2222+++==n n n L M k e e e (12) where M is the mutual inductance between L and L b , n is the turns ratio of L and L b , n=N1/N2. It can be seen from Eq. 12 that lower turns ratio results in higher equivalent coupling coefficient between channels, so that channel current ripple will be larger. High turns ratio is preferred from this perspective to maintain relatively low
channel ripple. Fig. 12 shows the simulation results of the
current ripple comparison with different turns ratios. When turns ratio is 30, the channel current ripple is close to the non-couple inductors case. When the turns ratio is 10, channel
Fig. 11 Coupled inductors in multi-channel Buck converter
Fig. 12 Channel current ripple with different turns ratio n
In practice, with imperfect coupling, balance condition is not only determined by the turns ratio but also the coupling coefficient, in which case parasitic capacitance can be fine-tuned to achieve balance. Coupling coefficient between L and
L b should be higher than 0.7 for achieving balance up to 10 MHz.
F. Channel shedding and its effect on balance
One benefit of multi-channel PFC compared to single channel one is the possibility to shut down channels at different load condition for the purpose of improving light load efficiency. The proposed balance implementation can still reduce CM noise with any number of channel shedding. Take a three-channel PFC with one channel shut down for example. The MOSFET and diode remain off in the shut-down channel. They can be replaced by their junction capacitance, as shown in Fig. 13(a). The CM noise model is shown in Fig. 13(b). It is no longer a Wheatstone bridge so
that the equivalent decoupled model is not applicable for
analysis. The CM noise can be analyzed from the CM current cancellation point of view. Assume the coupling coefficient between L and L b
is unity, the voltages on them can be
calculated in Eq. 13. 2
1332211N N
V V V V V V m m m −=== (13) These voltages are fast switching voltages and introduce CM noise current through parasitic capacitances C d and C b :
⎪⎪⎪⎪⎭⎪⎪⎪
⎪⎬
⎫===++=dt dV C i dt dV C i dt
dV C i dt
V V V d C i m d
d m d
d m d
d b
b 3
32
211321)( (14). The total CM current is the sum of these currents, as shown
in Eq. 14.
dt
V V V d C dt V V V d C i i i i i i m m m d b d d d b CM )()(3213213
21++⋅
+++⋅=+++==∑ (15)
Substituting Eq. 13 into Eq. 15, condition for CM noise
current cancellation can be derived, which is exactly the same as Eq. 6. In conclusion, channel shedding does not change the ability of the balance approach in reducing CM noise. The same conclusion can be made in N-channel PFC converter with any number of shut-down channels.
V
b
d
d
diode
m3d3
(b) CM noise model
Fig. 13 3-channel PFC with one channel shut down and its CM model
III ． E XPERIMENTAL RESULT
A 1.2kW two-channel boost PFC converter is built to validate the proposed method. The input voltage is 110 Vac and the output is 400 Vdc. The switching frequency is 130 kHz in each channel. Boost inductance L in each channel is 330uH, implemented using toriodal core with 62 turns. Parasitic capacitances of the converter are measured. C d is 5.8pF and C b is 194pF. CM noises are measured and compared.
First, the original CM noise of two-channel 180o -phase-shift PFC converter is measured and shown in Fig. 14. The first order and third order harmonics, which is 130 kHz and 390 kHz respectively, are cancelled and significantly lower than the even order harmonics. Then balance is achieved by adding a 10uH inductor, as shown in Fig. 5, to verify the balance effect at low frequency and the high frequency issue. In Fig. 14, the measurement result shows that CM noise below 2 MHz is greatly reduced but high frequency noise remains and even increased around 4 MHz.
Then coupled-inductor structure is implemented to improve the high frequency noise reduction. A winding of 2 turns (N2 = 2) are added on each toriadal core to implement L b so that balance condition is satisfied. The measured CM noise is shown in Fig. 15. It is reduced as much as 20dBuV from 150 kHz up to 7 MHz. However, noise beyond 7 MHz is even worse than the original noise.
Another implementation of L b is to use 1 turn (N2 = 1) to get higher turns ratio and 176pF is added between the output bus of PFC and ground to achieve balance. Figure 16 shows the measured CM noise with different N2 (turns ratio). It can be seen that when N2 is 1, which means higher turns ratio, high frequency CM noise is lower.
In both cases, the parasitic capacitance ratio is not accurately equal to the turns ratio due to imperfect coupling coefficient. Fine-tune is done on C b value to achieve best noise reduction.
Figure 17 shows the CM noise with balance technique when the two channels have different phase shift angle. It is shown that phase shift does not affect the balance result. Fig. 18 shows the effect of channel shedding. When one channel is shut down, low frequency CM noise remains at the same level and the high frequency noise is even lower.
Frequency (Hz)
C M n o s i e (d B u V )
Fig. 14 Effect of balance on CM noise, without coupled-inductors
10
10
10
Frequency (Hz)
C M n o i s e (d B u V )
Fig. 15 Effect of balance on CM noise, with coupled-inductors
10
10
10
Frequency (Hz)
C M n o i s e (d B u V )
Fig. 16 Effect of N2 (turns ratio) on CM noise
10
10
Frequency (Hz)
C M n o i s e (d B u V )
Fig. 17. Effect of phase shift on balance
10
10
Frequency (Hz)
C M n o i s e (d B u V )
Fig. 18. CM noise when one phase is shut down
IV ． C ONCLUSION
In this paper, balance technique is introduced to reduce the CM noise in multi-channel PFC converter. The CM noise emission model of multi-channel PFC converter is derived. Balance technique is implemented in the converter and the balance condition is derived. To improve the high frequency CM noise, coupled-inductor structure is proposed to eliminate the effect of parasitics. This solution can greatly reduce CM noise and is independent of phase shift and channel number. This solution also works well when some of the channels are shut down for higher efficiency at light load. Experiments have been done to verify the proposed method. CM noise in multi-channel PFC with balance technique can be greatly reduced up to 20 MHz from 150 kHz to 7 MHz.
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