VHDL数字逻辑电路设计19例

VHDL 数字逻辑电路设计19例
第1章组合逻辑电路8例
1. 2-4译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ymq24 IS
PORT (EN,A,B:IN STD_LOGIC;
YN : OUT STD_LOGIC_vector(3 downto 0 ));
END ENTITY ymq24 ;
ARCHITECTURE rt1 OF ymq24 IS
SIGNAL T:STD_LOGIC_vector(1 downto 0 );
BEGIN
T<=A & B;
process(EN,T)
begin
IF EN='1' THEN YN<="1111";
ELSIF T="00" THEN YN<="1110";
ELSIF T="01" THEN YN<="1101";
ELSIF T="10" THEN YN<="1011";
ELSE YN<="0111";
END IF;
End process;
END ARCHITECTURE rt1;
2. 3-8译码器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ymq38 IS
PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;
YN : OUT STD_LOGIC_vector(7 downto 0 )); END ENTITY ymq38 ;
ARCHITECTURE rt1 OF ymq38 IS
SIGNAL T1,T2:STD_LOGIC_vector(2 downto 0 );
BEGIN
T1<=A & B & C;
T2<=G1 & G2N & G3N;
process(G1,G2N,G3N,T1,T2)
begin
IF T2/="100" THEN YN<="11111111";
ELSIF T1="000" THEN YN<="11111110";
ELSIF T1="001" THEN YN<="11111101";
ELSIF T1="010" THEN YN<="11111011";
ELSIF T1="011" THEN YN<="11110111";
ELSIF T1="100" THEN YN<="11101111";
ELSIF T1="101" THEN YN<="11011111";
ELSIF T1="110" THEN YN<="10111111";
ELSE YN<="01111111";
END IF;
End process;
END ARCHITECTURE rt1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xzq41 IS
PORT(gn: IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a0,a1: IN STD_LOGIC;
y: out STD_LOGIC);
END ENTITY xzq41;
ARCHITECTURE rt1 OF xzq41 IS
signal s: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN
S<= a1 & a0;
Process(S,D,gn)
begin
if gn='0' then
CASE (S) IS
WHEN "00"=> Y<=d(0);
WHEN "01"=> Y<=d(1);
WHEN "10"=> Y<=d(2);
WHEN "11"=> Y<=d(3);
WHEN OTHERS =>NULL;
END CASE;
else y<='0';
end if;
End process;
END ARCHITECTURE rt1;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xzq81 IS
PORT(gn: IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
a0,a1,a2: IN STD_LOGIC;
y: out STD_LOGIC);
END ENTITY xzq81;
ARCHITECTURE rt1 OF xzq81 IS
signal s: STD_LOGIC_VECTOR(2 DOWNTO 0); BEGIN
S<= a2 & a1 & a0;
Process(S,D,gn)
begin
if gn='0' then
CASE (S) IS
WHEN "000"=> Y<=d(0);
WHEN "001"=> Y<=d(1);
WHEN "010"=> Y<=d(2);
WHEN "011"=> Y<=d(3);
WHEN "100"=> Y<=d(4);
WHEN "101"=> Y<=d(5);
WHEN "110"=> Y<=d(6);
WHEN "111"=> Y<=d(7);
WHEN OTHERS =>NULL;
END CASE;
else y<='0';
end if;
End process;
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY l75 IS
PORT (A,B,C:IN STD_LOGIC;
d,g : OUT STD_LOGIC);
END ENTITY l75 ;
ARCHITECTURE rt1 OF l75 IS
COMPONENT ymq38
PORT (G1, G2N, G3N, A, B, C: IN STD_LOGIC;
YN : OUT STD_LOGIC_vector(7 downto 0 )); END COMPONENT ;
signal ynt : STD_LOGIC_vector(7 downto 0 );
BEGIN
U1 :ymq38 PORT MAP ('1','0','0',a,b,c,YNt(7 DOWNTO 0));
d<=not(ynt(1) and ynt(2) and ynt(4) and ynt(7));
g<=not(ynt(1) and ynt(2) and ynt(3) and ynt(7));
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY l76 IS
PORT (A,B,C,D:IN STD_LOGIC;
F : OUT STD_LOGIC);
END ENTITY l76 ;
ARCHITECTURE rt1 OF l76 IS
COMPONENT ymq38
PORT (G1,G2N,G3N,A,B,C:IN STD_LOGIC;
YN : OUT STD_LOGIC_vector(7 downto 0 ));
END COMPONENT ;
signal yn1t:STD_LOGIC_vector(7 downto 0 );
signal yn2t:STD_LOGIC_vector(7 downto 0 );
BEGIN
U1 :ymq38 PORT MAP ('1',A,'0',B,C,D,YN1t(7 DOWNTO 0));
U2 :ymq38 PORT MAP (A,'0','0',B,C,D,YN2t(7 DOWNTO 0));
F<=not( yn1t(2) and yn1t(4) and yn1t(6) and yn2t(0) and yn2t(2) and yn2t(4) and yn2t(6)); END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY l78 IS
PORT (A,B,C:IN STD_LOGIC;
f : OUT STD_LOGIC);
END ENTITY l78 ;
ARCHITECTURE rt1 OF l78 IS
COMPONENT xzq81
PORT(gn: IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
a0,a1,a2: IN STD_LOGIC;
y: out STD_LOGIC);
END COMPONENT ;
BEGIN
U1 :xzq81 PORT MAP ('0',"01101100",c,b,a,f);
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY l78 IS
PORT (A,B,C:IN STD_LOGIC;
f : OUT STD_LOGIC);
END ENTITY l78 ;
ARCHITECTURE rt1 OF l78 IS
COMPONENT xzq41
PORT(gn: IN STD_LOGIC;
d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
a0,a1: IN STD_LOGIC;
y: out STD_LOGIC);
END COMPONENT ;
signal t:STD_LOGIC;
signal dt:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
t<= not c;
dt<=t & c & '1' & '0';
U1 :xzq41 PORT MAP ('0',dt,b,a,f);
【作业】以下所有题目必须用VHDL代码实现。

每个题目建立各自的文件夹，文件夹名称用题目编号和题目。

例如：第一题文件夹名称是“v1-4-16译码器”。

V1.设计4-16译码器。

V2.设计16选1数据选择器。

V3.设逻辑函数:
F（A,B,C,D）=∑(0，2，3，7，8，9，10，13)
要求用下面4种方法实现该逻辑函数。

（1）4-16译码器（文件夹名称：V3-F-416译码器）
（2）4选1（文件夹名称：V3-F-4选1）
（3）8选1（文件夹名称：V3-F-8选1）
（4）16选1（文件夹名称：V3-F-16选1）
V4.设逻辑函数:
Y（A,B,C,D）=∑(0，1，5，7， 10，13,15)
要求用下面4种方法实现该逻辑函数。

（1）4-16译码器（文件夹名称：V4-Y-416译码器）
（2）4选1（文件夹名称：V4-Y-4选1）
（3）8选1（文件夹名称：V4-Y-8选1）
（4）16选1（文件夹名称：V4-Y-16选1）
V5用8选1和3-8译码器设计一个3位2进制等值比较器（参考图7.22）。

V6. 4-16译码器和适当的逻辑门实现一个一位十进制2421码的奇校验产生电路（习题7.5）。

V7.用4选1实现余3码到8421码的转换（习题77）。

第2章时序逻辑电路11例1. D触发器
（1）代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY CFQ IS
PORT(clk,rst,en: STD_LOGIC;
D: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END ENTITY CFQ;
ARCHITECTURE rt1 OF CFQ IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS(Q1,clk,rst)
BEGIN
if rst='1' then q1<='0';
elsIF(clk='1' AND clk'EVENT) THEN
if en='1' then Q1<=D; END IF;
END IF;
END PROCESS ;
Q<=Q1;
END ARCHITECTURE rt1;
（2）波形图
表1 D触发器功能
CLK RST EN Q 时间(单位NS)
上升沿 1 0 D 0~20
X 0 X 0 20~40
X 1 1 不变50~70
2. T触发器
（1）代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY tFF1 IS
PORT(RSTN,CLRN,clk: IN STD_LOGIC;
T: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END ENTITY TFF1;
ARCHITECTURE rt1 OF TFF1 IS
SIGNAL Q1:STD_LOGIC;
BEGIN
PROCESS(Q1,clk,RSTN,CLRN)
BEGIN
IF (RSTN='0' AND CLRN='1') THEN Q1<='1';
ELSIF (RSTN='1' AND CLRN='0') THEN Q1<='0';
ELSIF(clk='1' AND clk'EVENT) THEN---
IF T='0' THEN Q1<=Q1;
ELSE Q1<=NOT Q1;
END IF;
END IF;
END PROCESS ;
Q<=Q1;
END ARCHITECTURE rt1;
（2）波形图
（3）功能表
表2 T触发器功能
CLK RSTN CLRNN T Q 时间(单位NS) 上升沿 1 1 1 取反 5
上升沿 1 1 0 不变10~20
X 1 0 X 0 20~30
X 0 1 X 1 30~40
上升沿 1 1 1 取反45
上升沿 1 1 1 取反55
3. 4位2进制加法计数器
（1）代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNT4 IS
PORT(clk: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY CNT4;
ARCHITECTURE rt1 OF CNT4 IS
SIGNAL Q1:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF(clk='1' AND clk'EVENT) THEN
Q1<=Q1+1;
END IF;
END PROCESS ;
Q<=Q1;
END ARCHITECTURE rt1;
（2）波形图
4.表3是带控制端的二进制加法计数器功能表。

计数器的最大计数值是W，并且计数到W后输出进位‘1’。

仿真要求：计数初值设定为W-3，CLK周期是W，插入TIME BAR，把时间填入下表。

表3 二进制加法计数器控制端功能表
CLK RST EN LOAD Q 时间
上升沿0 0 1 载入初值 5
上升沿0 0 0 计数15~60
输出进位35
X 0 1 X 不变90~110
X 1 X X 0 60
下面波形图中的W值是136。

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CNTM IS
PORT(clk, rst, en, load : IN STD_LOGIC;
D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
QOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
Cout : OUT STD_LOGIC);
END ENTITY CNTM ;
ARCHITECTURE rt1 OF CNTM IS
BEGIN
PROCESS (clk, rst, en ,load)
Variable Q : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
If rst ='1' then Q:="00000000";
ElsIF (clk='1' AND clk' EVENT ) THEN
if en='0' then
if load ='1' then Q:=d ; else
if q<136 then q:=q+1;
else Q:="00000000";
end if;
END IF;
END IF;
END IF;
If q<136 then cout<='0'; else cout<='1'; END IF;
QOUT <= q;
END PROCESS ; END ARCHITECTURE rt1;
5. 加减计数器74193
（1）代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY JSQ193 IS
PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
QA,QB,Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
QCCN,QCBN: OUT STD_LOGIC);
END ENTITY JSQ193;
ARCHITECTURE rt1 OF JSQ193 IS
--例化T触发器
COMPONENT tFF1 IS
PORT(RSTN,CLRN,clk: IN STD_LOGIC;
T: IN STD_LOGIC;
Q: OUT STD_LOGIC);
END COMPONENT TFF1;
SIGNAL QTA,QTB:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL M,CLK:STD_LOGIC;
BEGIN
CLK<=CPU AND CPD;
--加法器
P1:PROCESS(CLR,LOADN,CPU,CPD,DA TA,QTA,QTB)
BEGIN
if CLR ='1' then QTA<="0000";
ELSIF LOADN='0' THEN QTA<=DATA;
ELSIF(CPU='1' AND CPU'EVENT) THEN
qTA<=qTA+1;
END IF;
QCCN<=CPU OR (NOT QTA(3)) OR (NOT QTA(2)) OR (NOT QTA(1)) OR( NOT QTA(0)) OR (NOT CPD); QA<=QTA;
END PROCESS ;
--减法器
P2:PROCESS(CLR,LOADN,CPU,CPD,DA TA,QTA,QTB)
BEGIN
ELSIF LOADN='0' THEN QTB<=DATA;
ELSIF(CPD='1' AND CPD'EVENT) THEN
qTB<=qTB-1;
END IF;
QCBN<=CPD OR QTB(3) OR QTB(2) OR QTB(1) OR QTB(0) OR(NOT CPU); QB<=QTB;
END PROCESS ;
U1:tFF1 PORT map (CPD,CPU,CLK,'0',M);
--选择器
P3:PROCESS(QTB,QTA,M)
BEGIN
IF M='1' THEN Q<=QTB;
ELSE Q<=QTA;END IF;
END PROCESS ;
END ARCHITECTURE rt1;
（2）波形图
表4 加减计数器功能
CLR LOADN CPU CPD Q 时间(单位NS)
0 0 X X 1011 0
0 1 上升沿 1 加法20~70
输出进位标志0 70
1 x x X 0 120
0 0 X X 0010 140
0 1 1 上升沿减法140~210
输出借位标志0 210
6. 例712
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY L712 IS
PORT(CP: IN STD_LOGIC;
F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY L712;
ARCHITECTURE rt1 OF L712 IS
--调用193
COMPONENT JSQ193
PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
QCCN,QCBN: OUT STD_LOGIC);
END COMPONENT JSQ193;
SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLRT,QCCNT,QCBNT:STD_LOGIC;
BEGIN
CLRT<=QT(3) AND QT(1);
U: JSQ193 PORT map(CLRT,'1',CP,'1',"0000",QT,QCCNT,QCBNT); F<=QT;
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY L713 IS
PORT(CP,LOADNX: IN STD_LOGIC;
F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY L713;
ARCHITECTURE rt1 OF L713 IS
--调用193
COMPONENT JSQ193 IS
PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
QCCN,QCBN: OUT STD_LOGIC);
END COMPONENT JSQ193;
SIGNAL QT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLRT,QCCNT,QCBNT,LOADNT:STD_LOGIC;
BEGIN
LOADNT<=LOADNX AND (QT(3) OR QT(2));
U: JSQ193 PORT map(CLRT,LOADNT,'1',CP,"1111",QT,QCCNT,QCBNT); F<=QT;
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY L714 IS
PORT(CP: IN STD_LOGIC;
FH,FL: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY L714;
ARCHITECTURE rt1 OF L714 IS
--调用193
COMPONENT JSQ193 IS
PORT(CLR,LOADN,CPU,CPD: IN STD_LOGIC;
DATA: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
QCCN,QCBN: OUT STD_LOGIC);
END COMPONENT JSQ193;
SIGNAL QTH,QTL:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL CLRT,QCCNTH,QCBNTH,QCCNTL,QCBNTL:STD_LOGIC;
BEGIN
CLRT<=QTH(3) AND QTH(0) AND QTL(1) AND QTL(0);
U1: JSQ193 PORT map(CLRT,'1',CP,'1',"0000",QTL,QCCNTL,QCBNTL);
U2: JSQ193 PORT map(CLRT,'1',QCCNTL,'1',"0000",QTH,QCCNTH,QCBNTH); FH<=QTH;FL<=QTL;
END ARCHITECTURE rt1;
9. 移位寄存器194
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY shft194 IS
PORT( d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CP,clrn,DL,DR: IN STD_LOGIC;
S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q: buffer STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY shft194;
ARCHITECTURE rt1 OF shft194 IS
BEGIN
PROCESS(CP,CLRN,DL,DR,S,D)
BEGIN
if clrn ='0' then q<="0000";
ELSIF(CP='1' AND CP'EVENT) THEN
case S is
when "01"=>q<=DR & q(3 downto 1);
when "10"=>q<=q(2 downto 0) & DL;
when "11"=>q<=d;
when others =>null;
end case;
end if;
END PROCESS ;
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY L716 IS
PORT(CP: IN STD_LOGIC;
F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY L716;
ARCHITECTURE rt1 OF L716 IS
--调用193
COMPONENT SHFT194 IS
PORT( d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CP,clrn,DL,DR: IN STD_LOGIC;
S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q: buffer STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT SHFT194;
SIGNAL FT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DLT:STD_LOGIC;
BEGIN
DLT<=NOT FT(3) ;
U1: SHFT194 PORT map("0000",CP,'1',DLT,'1',"10",FT);
F<=FT;
END ARCHITECTURE rt1;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY L717 IS
PORT(CP: IN STD_LOGIC;
S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
F: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END ENTITY L717;
ARCHITECTURE rt1 OF L717 IS
--调用193
COMPONENT SHFT194 IS
PORT( d: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
CP,clrn,DL,DR: IN STD_LOGIC;
S: IN STD_LOGIC_VECTOR(1 DOWNTO 0);
q: buffer STD_LOGIC_VECTOR(3 DOWNTO 0)); END COMPONENT SHFT194;
SIGNAL FT:STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL DRT:STD_LOGIC;
BEGIN
DRT<=((NOT FT(3)) OR FT(2) ) XOR FT(1);
U1: SHFT194 PORT map("1000",CP,'1','1',DRT,S,FT);
F<=FT;
END ARCHITECTURE rt1;
【作业】编写代码: V8. 习题79。

V9. 习题710。