FPGA可编程逻辑器件芯片XC95108-10PQ100I中文规格书
FPGA可编程逻辑器件芯片XXC95144-10PQ100I中文规格书
Chapter1 Configuration OverviewConfiguration Modes and PinsVirtex®-5 devices are configured by loading application-specific configuration data—thebitstream—into internal memory. Because Xilinx FPGA configuration memory is volatile,it must be configured each time it is powered-up. The bitstream is loaded into the devicethrough special configuration pins. These configuration pins serve as the interface for anumber of different configuration modes:∙Master-serial configuration mode∙Slave-serial configuration mode∙Master SelectMAP (parallel) configuration mode (x8 and x16 only)∙Slave SelectMAP (parallel) configuration mode (x8, x16, and x32)∙JTAG/Boundary-Scan configuration mode∙Master Serial Peripheral Interface (SPI) Flash configuration mode∙Master Byte Peripheral Interface Up (BPI-Up) Flash configuration mode(x8 and x16 only)∙Master Byte Peripheral Interface Down (BPI-Down) Flash configuration mode(x8 and x16 only)The configuration modes are explained in detail in Chapter2, “Configuration Interfaces.”The specific configuration mode is selected by setting the appropriate level on thededicated Mode input pins M[2:0]. The M2, M1, and M0 mode pins should be set at aconstant DC voltage level, either through pull-up or pull-down resistors, or tied directly toground or V CC_CONFIG. The mode pins should not be toggled during and afterconfiguration. See Table2-1, page37 for the mode pin setting options.The terms Master and Slave refer to the direction of the configuration clock (CCLK):∙In Master configuration modes, the Virtex-5 device drives CCLK from an internaloscillator. To get the desired frequency, BitGen -g ConfigRate is used. The“BitGen” section of the Development System Reference Guide provides moreinformation. After configuration, the CCLK is turned off unless the persist optionis selected or SEU detection is used. The CCLK pin is 3-stated with a weak pull-up.∙In Slave configuration modes, CCLK is an input.The JTAG/Boundary-Scan configuration interface is always available, regardless of theMode pin settings. The JTAG/Boundary-Scan configuration mode disables all otherconfiguration modes to prevent conflicts between configuration interfaces.Certain pins are dedicated to configuration (Table1-1), while others are dual-purpose(Table1-2). Dual-purpose pins serve both as configuration pins and as user I/O afterconfiguration. Dedicated configuration pins retain their function after configuration.Configuration SequenceConfiguration SequenceWhile each of the configuration interfaces is different, the basic steps for configuring a Virtex-5 device are the same for all modes. Figure 1-2 shows the Virtex-5 configuration process. The following subsections describe each step in detail, where the current step is highlighted in gray at the beginning of each subsection.The Virtex-5 device is initialized and the configuration mode is determined by sampling the mode pins in three setup steps.Setup (Steps 1-3)The setup process is similar for all configuration modes (see Figure 1-3).The setup steps are critical for proper device configuration. The steps include Device Power-Up, Clear Configuration Memory, and Sample Mode Pins.Table 1-7:Sync Word Bit Swap ExampleSync Word[31:24](1)[23:16][15:8][7:0]Bitstream Format 0xAA 0x990x550x66Bit Swapped0x550x990xAA0x66Notes:1.[31:24] changes from 0xAA to 0x55 after bit swapping.Table 1-8:Sync Word Data Sequence Example for x8, x16, and x32 ModesCCLK Cycle 1234D[7:0] pins for x8 0x550x990xAA0x66D[15:0] pins for x160x55990xAA66D[31:0] pins for x320x5599AA66Figure 1-2:Virtex-5 Device Configuration ProcessUG191_c1_01_050406StepsBoundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1TAP ControllerFigure3-2 diagrams a 16-state finite state machine. The four TAP pins control how data isscanned into the various registers. The state of the TMS pin at the rising edge of TCKdetermines the sequence of state transitions. There are two main sequences, one forshifting data into the data register and the other for shifting an instruction into theinstruction register.A transition between the states only occurs on the rising edge of TCK, and each state has adifferent name. The two vertical columns with seven states each represent the InstructionPath and the Datapath. The data registers operate in the states whose names end with"DR," and the instruction register operates in the states whose names end in "IR." The statesare otherwise identical.The operation of each state is described below.Test-Logic-Reset:All test logic is disabled in this controller state, enabling the normal operation of the IC.The TAP controller state machine is designed so that regardless of the initial state of thecontroller, the Test-Logic-Reset state can be entered by holding TMS High and pulsingTCK five times. Consequently, the Test Reset (TRST) pin is optional.Run-Test-Idle:In this controller state, the test logic in the IC is active only if certain instructions arepresent. For example, if an instruction activates the self test, then it is executed when thecontroller enters this state. The test logic in the IC is idle otherwise.Select-DR-Scan:This controller state controls whether to enter the Datapath or the Select-IR-Scan state.Select-IR-Scan:This controller state controls whether or not to enter the Instruction Path. The controllercan return to the Test-Logic-Reset state otherwise.Capture-IR:In this controller state, the shift register bank in the Instruction Register parallel loads apattern of fixed values on the rising edge of TCK. The last two significant bits must alwaysbe 01.Shift-IR:In this controller state, the instruction register gets connected between TDI and TDO, andthe captured pattern gets shifted on each rising edge of TCK. The instruction available onthe TDI pin is also shifted in to the instruction register.Exit1-IR:This controller state controls whether to enter the Pause-IR state or Update-IR state.Pause-IR:This state allows the shifting of the instruction register to be temporarily halted.Exit2-DR:This controller state controls whether to enter either the Shift-IR state or Update-IR state.Update-IR:In this controller state, the instruction in the instruction register is latched to the latch bankof the Instruction Register on every falling edge of TCK. This instruction becomes thecurrent instruction after it is latched.。
FPGA可编程逻辑器件芯片XC95144XL-7TQ100I中文规格书
Configuration PacketsIf it is a known-vendor command, the SPI read command needs to be loaded to GENERAL2.In case of SPI, the general register contains an 8-bit command plus a 24-bit address. See Table 5-42.BPI has a 26-bit address (there are 6 don’t care bits). See Table 5-43.MODE RegisterThe MODE register contains the mode setting (two bits for bus width, three bits for mode, and eight bits for vsel), which can be used for the reboot. The default is the original pin setting.This register is cleared in the same way as General registers, that is they can only be cleared by bus_reset0 but NOT by reboot_rst (bus_reset = bus_reset || reboot_rst ). See Table 5-44.Table 5-42:SPI General Register Examplegen2[15:0]gen1[15:0]rd_cmd[7:0], addr[23:16]addr[15:0]Table 5-43:BPI General Register Examplegen2[15:0]gen1[15:0]xxxxxx, address[25:16]addr[15:0]Table 5-44:MODE Registers DescriptionName Bits DescriptionDefault RESERVED 15Reserved.0RESERVED 14Reserved.0NEW_MODE130: Physical mode, ignore bit[10:0] (default).1: Bitstream mode, use bit[10:0], required for MultiBoot and Fallback.0BUSWIDTH 12:11The buswidth setting to reboot.SPI:00: by 101: by 210: by 400 (SPI by1)BOOTMODE 10:8Mode setting required for MultiBoot and Fallback. Enabled by NEW_MODE.bit [10]: Reserved bit [9]: BOOTMODE <1>bit [8]: BOOTMODE <0>001BOOTVSEL 7:0The vsel setting to reboot.Read only.Chapter 5:Configuration DetailsiMPACT Access to Device IdentifierThe iMPACT software in ISE 10.1 (and later) tools can also read the device DNA value.readDna -p <position> is the batch command that reads the device DNA from theFPGA.Bitstream CompressionBy default, FPGA bitstreams are uncompressed. However, Spartan-6 FPGAs support basicbitstream compression. The compression is fairly simple, yet effective for someapplications. The ISE bitstream generator software examines the FPGA bitstream for anyduplicate configuration data frames. These duplicates occur often in these situations:•FPGA designs with unused block RAM or hardware multipliers.•FPGA designs with low logic utilization, such as when most of the FPGA array isempty.The ISE software can then generate a compressed FPGA bitstream. As the FPGAconfigures, the internal configuration controller copies the redundant data frame tomultiple locations. Compression is not supported for encrypted bitstreams.The amount of compression is non-deterministic. Changes to the source FPGA design cancause the size of the compressed bitstream to grow. Sparse, mostly empty FPGA designshave the greatest overall compression factor. Similarly, FPGA designs with an emptycolumn of block RAM have a high compression factor.The overall benefits of a compressed bitstream are:•Smaller memory footprint.•Faster programming time for nonvolatile memory.•Faster configuration time.Compression is enabled using the BitGen option -g compress.Parallel Platform Flash PROMs offer their own compression mechanisms. For more details,see the “XCFxxP Decompression and Clock Options” chapter in UG161, Platform FlashPROM User Guide.Chapter 2:Configuration Interface BasicsChapter 3:Boundary-Scan and JTAG ConfigurationChapter 5:Configuration DetailsConfiguration Watchdog Timer RegisterThe configuration watchdog timer (CWDT) register stores the value of the number of clock cycles that the FPGA will wait before the watchdog time-out (in which SYNCWORD is not received). The default is 64k clock cycles. The minimum value is 16h'0201.HC_OPT_REG RegisterThe HC_OPT_REG register can only be reset to default by por_b.GENERAL Registers 1, 2, 3, 4, and 5GENERAL1 and GENERAL2 registers are used to store loadable multiple configuration addresses for SPI and BPI.GENERAL3 and GENERAL4 registers have a similar function as GENERAL1 andGENERAL2, except that GENERAL3 and GENERAL4 store the golden bitstream address instead of the MultiBoot address.The GENERAL5 register is a 16-bit register that allows users to store and access any extra information desired for the fail-safe scheme. These register contents are untouched during a soft reboot.These registers are set by the bitstream. BitGen can be instructed not to write to these registers using the -g next_config_register_write:Disable command. This allows the ability to store user data in the FPGA between re-configuration attempts.If the second configuration needs a previously unknown SPI vendor command, the new vendor command has already been loaded in GENERAL2 from the bitstream by this point.Table 5-39:CWDT RegisterBits Value [15:0]16h'ffffTable 5-40:HC_OPT_REG DescriptionName Bits DescriptionDefault INIT_SKIP 60: Do not skip initialization.1: Skip initialization.0RESERVED5:0Reserved.011111Table 5-41:General RegistersName Bits DescriptionGENERAL1[15:0]The lower half of the multiple boot address.GENERAL2[15:0]15:8 – SPI opcode.7:0 – Higher half of the boot address.GENERAL3[15:0]The lower half of the golden bitstream address.GENERAL4[15:0]15:8 – SPI opcode.7:0 – Higher half of the golden boot address.GENERAL5[15:0]The user-defined scratchpad register.。
XC95108-10PQG100I中文资料
• Slew rate control on individual outputs • User programmable ground pin capability • Extended pattern security features for design
XC9500 concurrently • Available in 84-pin PLCC, 100-pin PQFP, 100-pin
TQFP, and 160-pin PQFP packages
Description
The XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
V
VIN
Input voltage relative to GND
–0.5 to VCC + 0.5
V
VTS TSTG
TJ
Voltage applied to 3-state output Storage temperature (ambient) Junction temperature
FPGA可编程逻辑器件芯片XC95288XL-10FG256I4124中文规格书
The VC707 board uses power regulators and PMBus compliant digital PWM system controllersfrom Texas Instruments to supply the core and auxiliary voltages listed in Table1-29.Table 1-29:Onboard Power System DevicesDevice Type ReferenceDesignatorDescriptionPower RailNet NamePower RailVoltageSchematicPageCore voltage controller and regulatorsUCD9248PFC(1)U42PMBus Controller (Addr=52)46PTD08A020WU25Adjustable switching regulator20A, 0.6V to 3.6VVCCINT_FPGA 1.00V47PTD08D210W(V OUT A)U20Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCCAUX 1.80V48PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC3V3 3.30V48PTD08A010WU12Adjustable switching regulator10A, 0.6V to 3.6VVCC_ADJ0-3.30V49Auxiliary voltage controller and regulatorsUCD9248PFC(2)U43PMBus Controller(Addr=53)50PTD08D210W(V OUT A)U21Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC2V5_FPGA 2.50V51PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VVCC1V5_FPGA 1.50V51PTD08D210W(V OUT A)U22Adjustable switching regulatordual 10A, 0.6Vto 3.6VMGTA VCC 1.00V52PTD08D210W (V OUT B)Adjustable switching regulatordual 10A, 0.6Vto 3.6VMGTA VTT 1.20V52UCD9248PFC(3)U64PMBus Controller(Addr=54)53PTD08D210W(V OUT A)U62Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCAUX_IO 2.00V54PTD08D210W(V OUT B)Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCBRAM 1.00V54PTD08D210W(V OUT A)U63Dual 10A 0.6V - 3.6V Adj. Switching Regulator MGTVCCAUX 1.80V55PTD08D021W(V OUT B)Dual 10A 0.6V - 3.6V Adj. Switching Regulator VCCBRAM 1.00V55 Linear regulatorsLMZ12002U71Fixed Linear Regulator 2A VCC5V0 5.00V46 TL1962ADC U62Fixed Linear Regulator, 1.5A VCC1V8 1.80V46 ADP123U17Fixed Linear Regulator, 300mA VCC_SPI 2.80V46 ADP123U18Fixed Linear Regulator, 300mA XADC_VCC 1.80V31Table 1-30 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 52 (U42).Table 1-31 defines the voltage and current values for each power rail controlled by the UCD9248 PMBus controller at address 53 (U43).Table 1-30:Power Rail Specifications for UCD9248 PMBus Controller at Address 52Shutdown Threshold (1)Rail Number Rail Name Schematic Rail NameN o m i n a l V O U T (V )P G O n T h r e s h o l d (V )P G O f f T h r e s h o l d (V )O n D e l a y (m s )R i s e T i m e (m s )O f f D e l a y (m s )F a l l T i m e (m s )V O U T O v e r F a u l t (V )I O U T O v e r F a u l t (A )T e m p O v e r F a u l t (°C )1Rail #1VCCINT_FPGA 10.90.8505101 1.1520902Rail #2VCCAUX 1.8 1.62 1.530551 2.0710.41903Rail #3VCC3V3 3.3 2.97 2.8050541 3.79510.41904Rail #4V ADJ1.81.621.535312.0710.4190Notes:1.The values defined in these columns are the voltage, current, and temperature thresholds that cause the regulator to shut down if the value is exceeded.Table 1-31:Power Rail Specifications for UCD9248 PMBus Controller at Address 53Shutdown Threshold (1)Rail Number Rail Name Schematic Rail NameN o m i n a l V O U T (V )P G O n T h r e s h o l d (V )P G O f f T h r e s h o l d (V )O n D e l a y (m s )R i s e T i m e (m s )O f f D e l a y (m s )F a l l T i m e (m s )V O U T O v e r F a u l t (V )I O U T O v e r F a u l t (A )T e m p O v e r F a u l t (°C )1Rail #1VCC2V5_FPGA 2.5 2.25 2.1250511 2.87510.41902Rail #2VCC1V5 1.5 1.35 1.2750501 1.72510.41903Rail #3MGTA VCC 10.90.850571 1.4510.41904Rail #4MGTA VTT1.21.081.025811.3810.4190Notes:1.The values defined in these columns are the voltage, current, and temperature thresholds that causes the regulator to shut down if the value is exceeded.Feature DescriptionsFor external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA's dedicated VP/VN channel, and to the V AUXP[0]/V AUXN[0],V AUXP[8]/V AUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-35 shows the XADC header connections.Table 1-33 describes the XADC header J19 pin functions.Figure 1-35:XADC Header (J19)Table 1-33:XADC Header J19 PinoutNet Name J19 Pin Number DescriptionVN, VP 1, 2Dedicated analog input channel for the XADC.XADC_V AUX0P, N 3, 6Auxiliary analog input channel 0. Also supports use as I/O inputs when anti-alias capacitor is not present.XADC_V AUX8N, P7, 8Auxiliary analog input channel 8. Also supports use as I/O inputs when anti-alias capacitor is not present.DXP, DXN 9, 12Access to thermal diode.XADC_AGND 4, 5, 10Analog ground reference.XADC_VREF 11 1.25V reference from the board.XADC_VCC5V013Filtered 5V supply from board.XADC_VCC_HEADER14Analog 1.8V supply for XADC.V ADJ 15VCCO supply for bank which is the source of DIO pins.GND16Digital Ground (board) ReferenceXADC_GPIO_3, 2, 1, 019, 20, 17, 18Digital I/O. These pins should come from the same bank. These I/Os should not be shared with other functions because they are required to support 3-state operation.Chapter 1:VC707 Evaluation Board FeaturesAppendix B:VITA 57.1 FMC Connector Pinouts。
FPGA可编程逻辑器件芯片XC95144-10PQ160I中文规格书
Module 1:Introduction and Ordering Information DS099 (v3.1) June 27, 2013•Introduction•Features•Architectural Overview•Array Sizes and Resources•User I/O Chart•Ordering InformationModule 2: Functional DescriptionDS099 (v3.1) June 27, 2013•Input/Output Blocks (IOBs)•IOB Overview•SelectIO™ Interface I/O Standards •Configurable Logic Blocks (CLBs)•Block RAM•Dedicated Multipliers•Digital Clock Manager (DCM)•Clock Network•ConfigurationModule 3:DC and Switching CharacteristicsDS099 (v3.1) June 27, 2013•DC Electrical Characteristics•Absolute Maximum Ratings•Supply Voltage Specifications•Recommended Operating Conditions•DC Characteristics•Switching Characteristics•I/O Timing•Internal Logic Timing•DCM Timing•Configuration and JT AG Timing Module 4: Pinout DescriptionsDS099 (v3.1) June 27, 2013•Pin Descriptions•Pin Behavior During Configuration•Package Overview•Pinout T ables•FootprintsSpartan-3 FPGA FamilyData SheetDS099 June 27, 2013Product SpecificationTable 35:Recommended Operating Conditions for User I/Os Using Single-Ended StandardsSignal Standard (IOSTANDARD)V CCO V REF V IL V IH Min (V)Nom (V)Max (V)Min (V)Nom (V)Max (V)Max (V)Min (V)GTL(3)–––0.740.80.86V REF – 0.05V REF + 0.05 GTL_DCI– 1.2–0.740.80.86V REF – 0.05V REF + 0.05 GTLP(3)–––0.881 1.12V REF – 0.1V REF + 0.1 GTLP_DCI– 1.5–0.881 1.12V REF – 0.1V REF + 0.1 HSLVDCI_15 1.4 1.5 1.6–0.75–V REF – 0.1V REF + 0.1 HSLVDCI_18 1.7 1.8 1.9–0.9–V REF – 0.1V REF + 0.1 HSLVDCI_25 2.3 2.5 2.7– 1.25–V REF – 0.1V REF + 0.1 HSLVDCI_33 3.0 3.3 3.465– 1.65–V REF – 0.1V REF + 0.1 HSTL_I, HSTL_I_DCI 1.4 1.5 1.60.680.750.9V REF – 0.1V REF + 0.1 HSTL_III,HSTL_III_DCI 1.4 1.5 1.6–0.9–V REF – 0.1V REF + 0.1HSTL_I_18,HSTL_I_DCI_18 1.7 1.8 1.90.80.9 1.1V REF – 0.1V REF + 0.1 HSTL_II_18,HSTL_II_DCI_18 1.7 1.8 1.9–0.9–V REF – 0.1V REF + 0.1HSTL_III_18,HSTL_III_DCI_18 1.7 1.8 1.9– 1.1–V REF – 0.1V REF + 0.1 LVCMOS12 1.14 1.2 1.3–––0.37V CCO0.58V CCO LVCMOS15,LVDCI_15,LVDCI_DV2_151.4 1.5 1.6–––0.30V CCO0.70V CCOLVCMOS18,LVDCI_18,LVDCI_DV2_181.7 1.8 1.9–––0.30V CCO0.70V CCOLVCMOS25(4,5),LVDCI_25,LVDCI_DV2_25(4)2.3 2.5 2.7–––0.7 1.7LVCMOS33,LVDCI_33,LVDCI_DV2_33(4)3.0 3.3 3.465–––0.8 2.0 LVTTL 3.0 3.3 3.465–––0.8 2.0PCI33_3(7) 3.0 3.3 3.465–––0.30V CCO0.50V CCO SSTL18_I,SSTL18_I_DCI 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL18_II 1.7 1.8 1.90.8330.9000.969V REF – 0.125V REF + 0.125 SSTL2_I,SSTL2_I_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 SSTL2_II,SSTL2_II_DCI 2.3 2.5 2.7 1.15 1.25 1.35V REF – 0.15V REF + 0.15 Notes:1.Descriptions of the symbols used in this table are as follows:V CCO – the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputsV REF – the reference voltage for setting the input switching thresholdV IL – the input voltage that indicates a Low logic levelV IH – the input voltage that indicates a High logic level2.For device operation, the maximum signal voltage (V IH max) may be as high as V IN max. See Table28.3.Because the GTL and GTLP standards employ open-drain output buffers, V CCO lines do not supply current to the I/O circuit, rather this current isprovided using an external pull-up resistor connected from the I/O pin to a termination voltage (V TT). Nevertheless, the voltage applied to the associated V CCO lines must always be at or above V TT and I/O pad voltages.4.There is approximately 100mV of hysteresis on inputs using LVCMOS25 or LVCMOS33 standards.5.All dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS standard and draw power from theV CCAUX rail (2.5V). The dual-purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and INIT_B) use the LVCMOS standard before the user mode. For these pins, apply 2.5V to the V CCO Bank 4 and V CCO Bank 5 rails at power-on and throughout configuration. For information concerning the use of 3.3V signals, see 3.3V-T olerant Configuration Interface, page47.6.The Global Clock Inputs (GCLK0-GCLK7) are dual-purpose pins to which any signal standard can be assigned.7.For more information, see XAPP457.Table 36:DC Characteristics of User I/Os Using Single-Ended StandardsSignal Standard (IOSTANDARD) and Current Drive Attribute (mA)Test Conditions Logic Level Characteristics I OL(mA)I OH(mA)V OLMax (V)V OHMin (V)GTL32–0.4–GTL_DCI Note 3Note 3GTLP36–0.6–GTLP_DCI Note 3Note 3HSLVDCI_15Note 3Note 30.4V CCO – 0.4 HSLVDCI_18HSLVDCI_25HSLVDCI_33HSTL_I8–80.4V CCO – 0.4 HSTL_I_DCI Note 3Note 3HSTL_III24–80.4V CCO – 0.4 HSTL_III_DCI Note 3Note 3HSTL_I_188–80.4V CCO – 0.4 HSTL_I_DCI_18Note 3Note 3HSTL_II_1816–160.4V CCO – 0.4 HSTL_II_DCI_18Note 3Note 3HSTL_III_1824–80.4V CCO – 0.4 HSTL_III_DCI_18Note 3Note 3LVCMOS12(4)22–20.4V CCO – 0.4 44–466–6LVCMOS15(4)22–20.4V CCO – 0.4 44–466–688–81212–12LVDCI_15,LVDCI_DV2_15Note 3Note 3LVCMOS18(4)22–20.4V CCO – 0.4 44–466–688–81212–121616–16LVDCI_18,LVDCI_DV2_18Note 3Note 3LVCMOS25(4,5)22–20.4V CCO – 0.4 44–466–688–81212–121616–162424–24LVDCI_25,LVDCI_DV2_25Note 3Note 3。
FPGA可编程逻辑器件芯片XC9572-15PQ100I中文规格书
Serial Configuration InterfaceNotes relevant to Figure 2-4:1.The DONE pin is by default an open-drain output requiring an external pull-upresistor. For all devices except the first, the active driver on DONE must be disabled.For the first device in the chain, the active driver on DONE can be enabled. See “Guidelines and Design Considerations for Serial Daisy Chains.”2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.3.The BitGen startup clock setting must be set for CCLK for serial configuration.4.The PROM in this diagram represents one or more Xilinx PROMs. Multiple Xilinx PROMs can be cascaded to increase the overall configuration storage capacity.5.The BIT file must be reformatted into a PROM file before it can be stored on the Xilinx PROM. Refer to the “Generating PROM Files” section.6.On some Xilinx PROMs, the reset polarity is programmable. RESET should be configured as active Low when using this setup.7.The CCLK net requires Thevenin parallel termination. See “Board Layout for Configuration Clock (CCLK),” page 73.8.Serial daisy chains are specific to the Platform Flash XCFS and XCFP PROM only.The first device in a serial daisy chain is the last to be configured. CRC checks only include the data for the current device, not for any others in the chain. (See “Cyclic Redundancy Check (Step 7)” in Chapter 1.)After the last device in the chain finishes configuration and passes its CRC check, it enters the Startup sequence. At the Release DONE pin phase in the Startup sequence, the device places its DONE pin in a High-Z state while the next to the last device in the chain isconfigured. After all devices release their DONE pins, the common DONE signal is either pulled High externally or driven High by the first device in the chain. On the next rising CCLK edge, all devices move out of the Release DONE pin phase and complete their startup sequences.It is important that all DONE pins in a Slave serial daisy chain be connected. Only the first device in the serial daisy chain should have the DONE active pull-up driver enabled. Enabling the DONE driver on downstream devices causes contention on the DONE signal.Figure 2-4:Master/Slave Serial Mode Daisy Chain Configuration09PlChapter 2:Configuration InterfacesMixed Serial Daisy ChainsVirtex-5 devices can be daisy-chained with the Virtex, Spartan™-II, Virtex-E, Spartan-IIE,Virtex-II, Virtex-II Pro, Spartan-3, and Virtex-4 families. There are three important designconsiderations when designing a mixed serial daisy chain:∙Many older FPGA devices cannot accept as fast a CCLK frequency as a Virtex-5 devicecan generate. Select a configuration CCLK speed supported by all devices in thechain.∙Virtex-5 devices should always be at the beginning of the serial daisy chain, witholder family devices located at the end of the chain.∙All Virtex device families have similar BitGen options. The guidelines provided forVirtex-5 BitGen options should be applied to all Virtex devices in a serial daisy chain.∙The number of configuration bits that a device can pass through its DOUT pin islimited. This limit varies for different families (Table2-3). The sum of the bitstreamlengths for all downstream devices must not exceed the number in Table2-3 for eachfamily.Table 2-3:Maximum Number of Configuration Bits, Various Device FamiliesArchitecture Maximum DOUT BitsVirtex-5, Virtex-4, Virtex-II Pro, and Virtex-II Devices32 x (227 – 1) = 4,294,967,264Spartan-3 Devices32 x (227 – 1) = 4,294,967,264Virtex, Virtex-E, Spartan-II, and Spartan-IIE Devices32 x (220 – 1) = 33,554,216 Guidelines and Design Considerations for Serial Daisy ChainsThere are a number of important considerations for serial daisy chains:Startup Sequencing (GTS)GTS should be released before DONE or during the same cycle as DONE to ensure theVirtex-5 device is operational when all DONE pins have been released.Active DONE DriverAll devices except the first should disable the driver on the DONE pin (refer to the BitGensection of the Development System Reference Guide for software settings). The first device ina chain is programmed last:∙DriveDone is disabled (all devices except the first)∙DriveDone is enabled (first device)Alternatively, the driver can be disabled for all DONE pins and an external pull-up resistorcan be added to pull the signal High after all devices have released it.Connect All DONE PinsIt is important to connect the DONE pins for all devices in a serial daisy chain. Failing toconnect the DONE pins can cause configuration to fail. For debugging purposes, it is oftenhelpful to have a way of disconnecting individual DONE pins from the common DONEsignal, so that devices can be individually configured through the serial or JTAG interface.Serial Configuration InterfaceDONE Pin Rise TimeAfter all DONE pins are released, the DONE pin should rise from logic 0 to logic 1 in oneCCLK cycle. External pull-up resistors are required. If additional time is required for theDONE signal to rise, the BitGen donepipe option can be set for all devices in the serialdaisy chain. (Refer to the BitGen section of the Development System Reference Guide forsoftware settings.)Ganged Serial ConfigurationMore than one device can be configured simultaneously from the same bitstream using aganged serial configuration setup (Figure2-5). In this arrangement, the serial configurationpins are tied together such that each device sees the same signal transitions. One device istypically set for Master serial mode (to drive CCLK) while the others are set for Slave serialmode. For ganged serial configuration, all devices must be identical. Configuration can bedriven from a configuration PROM or from an external configuration controller.u g191_c2_31_090808Figure 2-5:Ganged Serial ConfigurationNotes relevant to Figure2-5:1.For ganged serial configuration, the optional DONE driver must be disabled for alldevices if one device is set for Master mode because each device might not start up onexactly the same CCLK cycle. An external pull-up resistor is required in this case.2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor isrequired.3.The BitGen startup clock setting must be set for CCLK for serial configuration.Board Layout for Configuration Clock (CCLK)Chapter 2:Configuration Interfaces。
FPGA可编程逻辑器件芯片XC95144XL-10TQG144I中文规格书
Feature DescriptionsVITA 57.1 FMC1 HPC Connector (Partially Populated)[Figure1-2, callout 30]The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector.This section discusses the FMC1 HPC J35 connector.Note:The FMC1 HPC J35 connector is a keyed connector oriented so that a plug-on card facesaway from the VC707 board.The VITA 57.1 FMC standard calls for two connector densities: a high pin count (HPC) and a lowpin count (LPC) implementation. A 400 pin 10x40 position connector form factor is used for bothversions. The HPC version is fully populated with all 400 pins present. The LPC version is partiallypopulated with 160 pins.The 10x40 rows of an FMC HPC connector provides pins for up to:•160 single-ended or 80 differential user-defined signals•10 GTX transceivers• 2 GTX clocks• 4 differential clocks•159 ground and 15 power connectionsThe VC707 board FMC1 HPC connector J35 implements a subset of the maximum signal and clockconnectivity capabilities:•80 differential user-defined pairs•34 LA pairs (LA00-LA33)•24 HA pairs (HA00-HA23)•22 HB pairs (HB00-HB21)•8 GTX transceivers• 2 GTX clocks• 2 differential clocksThe FMC1 HPC signals are distributed across GTX Quads 118 and 119. Each Quad has the VCCOvoltage connected to V ADJ.Note:The VC707 board VADJ voltage for the FMC1 HPC (J35) connector is determined by theFMC VADJ power sequencing logic described in FMC_VADJ Voltage Control.VITA 57.1 FMC2 HPC Connector (Partially Populated)[Figure1-2, callout 31]The VC707 board implements two instances of the FMC HPC VITA 57.1 specification connector.This section discusses the FMC2 HPC J37 connector.Note:The FMC2 HPC J37 connector is a keyed connector oriented so that a plug-on card facesaway from the VC707 board.The FMC standard calls for two connector densities: a High Pin Count (HPC) and a Low Pin Count(LPC) implementation. A 400pin 10x40 position connector form factor is used for both versions.The HPC version is fully populated with all 400 pins present. The LPC version is partially populatedwith 160 pins.Chapter 1:VC707 Evaluation Board FeaturesXADC Analog-to-Digital Converter7series FPGAs provide an analog front end XADC block. The XADC block includes a dual 12-bit,1MSPS analog-to-digital convertor (ADC) and on-chip sensors. See 7Series FPGAs XADC Dual12-Bit 1MSPS Analog-to-Digital Converter User Guide (UG480) [Ref11] for details on thecapabilities of the analog front end. Figure1-34 shows the XADC block diagram.Figure 1-34:XADC Block DiagramThe VC707 board supports both the internal FPGA sensor measurements and the externalmeasurement capabilities of the XADC. Internal measurements of the die temperature, VCCINT,VCCAUX, and VCCBRAM are available. The VC707 board VCCINT and VCCBRAM areprovided by a common 1.0 V supply.Jumper J42 can be used to select either an external differential voltage reference (VREF) or on-chipvoltage reference for the analog-to-digital converter.Feature DescriptionsFor external measurements an XADC header (J19) is provided. This header can be used to provide analog inputs to the FPGA's dedicated VP/VN channel, and to the V AUXP[0]/V AUXN[0],V AUXP[8]/V AUXN[8] auxiliary analog input channels. Simultaneous sampling of Channel 0 and Channel 8 is supported.A user-provided analog signal multiplexer card can be used to sample additional external analog inputs using the 4 GPIO pins available on the XADC header as multiplexer address lines. Figure 1-35 shows the XADC header connections.Table 1-33 describes the XADC header J19 pin functions.Figure 1-35:XADC Header (J19)Table 1-33:XADC Header J19 PinoutNet Name J19 Pin Number DescriptionVN, VP 1, 2Dedicated analog input channel for the XADC.XADC_V AUX0P, N 3, 6Auxiliary analog input channel 0. Also supports use as I/O inputs when anti-alias capacitor is not present.XADC_V AUX8N, P7, 8Auxiliary analog input channel 8. Also supports use as I/O inputs when anti-alias capacitor is not present.DXP, DXN 9, 12Access to thermal diode.XADC_AGND 4, 5, 10Analog ground reference.XADC_VREF 11 1.25V reference from the board.XADC_VCC5V013Filtered 5V supply from board.XADC_VCC_HEADER14Analog 1.8V supply for XADC.V ADJ 15VCCO supply for bank which is the source of DIO pins.GND16Digital Ground (board) ReferenceXADC_GPIO_3, 2, 1, 019, 20, 17, 18Digital I/O. These pins should come from the same bank. These I/Os should not be shared with other functions because they are required to support 3-state operation.Appendix A:Default Switch and Jumper SettingsAppendix B:VITA 57.1 FMC Connector Pinouts。
FPGA可编程逻辑器件芯片XC95144XL-7TQG100I中文规格书
Chapter 5:Configuration DetailsConfiguration Options Register (COR1 and COR2)The Configuration Options Register is used to set certain configuration options for thedevice. The name of each bit position in COR1 and COR2 is given in Table5-36.Table 5-36:Configuration Options (COR1 and COR2) DescriptionsRegister Field Bit Index Description BitGen DefaultCOR1DRIVE_AWAKE150: Does not drive the awake pin (open drain).1: Actively drives the awake pin.RESERVED14:5Reserved.0110111000CRC_BYPASS4Does not check against the updated CRC value.0DONE_PIPE30: No pipeline stage for DONEIN.1: Add pipeline stage to DONEIN.DRIVE_DONE20: DONE pin is open drain.1: DONE pin is actively driven High.SSCLKSRC1:0Startup sequence clock.00: CCLK.01: UserClk.1x: TCK.00COR2RESET_ON_ERROR15Option to fallback when a crc_error occurs.0: Disable reset on error.1: Enable reset on error.0 RESERVED14:12Reserved000DONE_CYCLE11:9Startup phase in which DONE pin is released.(001,010,011,100,101,110)100LCK_CYCLE8:6Stall in this startup phase until DCM or PLL lock isasserted. (001,010,011,100,101,110,111<Nowait>)111 (No wait)GTS_CYCLE5:3Startup phase in which I/Os switch from 3-state to userdesign.(000<Keep>, 001,010,011,100,101,110,111<Done>)101GWE_CYCLE2:0Startup phase in which the global write enable is asserted.(000<Keep>, 001,010,011,100,101,110,111<Done>)110Spartan-6 FPGA Unique Device Identifier (Device DNA)Spartan-6 FPGA Unique Device Identifier (Device DNA)Spartan-6 FPGAs contain an embedded, unique device identifier (device DNA). Theidentifier is nonvolatile, permanently programmed into the FPGA, and is unchangeable,making it tamper resistant.The FPGA application accesses the identifier value using the Device DNA Access Port(DNA_PORT) design primitive, shown in Figure5-13.Figure 5-13:Spartan-6 FPGA DNA_PORT Design PrimitiveIdentifier ValueAs shown in Figure5-14, the device DNA value is 57 bits long. The two most-significantbits are always 1 and 0. The remaining 55 bits are unique to a specific Spartan-6 FPGA.OperationFigure5-14 shows the general functionality of the DNA_PORT design primitive. An FPGAapplication must first instantiate the DNA_PORT primitive, shown in Figure5-13, within adesign.Figure 5-14:DNA_PORT OperationTo read the device DNA, the FPGA application must first transfer the identifier value intothe DNA_PORT output shift register. The READ input must be asserted during a risingedge of CLK, as shown in Table5-51. This action parallel loads the output shift registerwith all 57 bits of the identifier. Because bit 56 of the identifier is always 1, the DOUToutput is also 1. The READ operation overrides a SHIFT operation.To continue reading the identifier values, SHIFT must be asserted, followed by a risingedge of CLK, as shown in Table5-51. This action causes the output shift register to shift itscontents toward the DOUT output. The value on the DIN input is shifted into the shiftregister.Chapter 5:Configuration DetailsA Low-to-High transition on SHIFT should be avoided when CLK is High because this causes a spurious initial clock edge. Ideally, SHIFT should only be asserted when CLK is Low or on a falling edge of CLK.If both READ and SHIFT are Low, the output shift register holds its value and DOUT remains unchanged.Identifier Memory SpecificationsThe unique FPGA identifier value is retained for a minimum of ten years of continuous usage under worst-case recommended operating conditions. The identifier can be read, using the READ operation defined in Table 5-51, a minimum of 30 million cycles, which roughly correlates to one read operation every 11 seconds for the operating lifetime of the Spartan-6FPGA.Extending Identifier LengthAs shown in Figure 5-15, most applications that use the DNA_PORT primitive tie the DIN data input to a static value.Table 5-51:DNA_PORT Operations Operation DIN READ SHIFT CLK Shift Register DOUTHOLD X 00X Hold previous value Hold previous value READ X 1X ↑Parallel load with 57-bit IDBit 56 of identifier, which is always 1SHIFTDIN1↑Shift DIN into bit 0, shift contents of ShiftRegister toward DOUTBit 56 of Shift RegisterNotes:X = Don’t care↑= Rising clock edgeFigure 5-15:Shift in ConstantChapter 6:Readback and Configuration VerificationChapter 7:Reconfiguration and MultiBoot。
FPGA可编程逻辑器件芯片XC95108-10TQG100C中文规格书
Features•7.5 ns pin-to-pin logic delays on all pins •f CNT to 125 MHz•108 macrocells with 2,400 usable gates •Up to 108 user I/O pins•5V in-system programmable-Endurance of 10,000 program/erase cycles-Program/erase over full commercial voltage andtemperature range•Enhanced pin-locking architecture •Flexible 36V18 Function Block-90 product terms drive any or all of 18 macrocellswithin Function Block-Global and product term clocks, output enables,set and reset signals•Extensive IEEE Std 1149.1 boundary-scan (JTAG)support•Programmable power reduction mode in each macrocell•Slew rate control on individual outputs •User programmable ground pin capability •Extended pattern security features for design protection•High-drive 24 mA outputs • 3.3V or 5V I/O capability•Advanced CMOS 5V FastFLASH™ technology •Supports parallel programming of more than one XC9500 concurrently•Available in 84-pin PLCC, 100-pin PQFP , 100-pin TQFP , and 160-pin PQFP packagesDescriptionThe XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architec-ture overview.Power ManagementPower dissipation can be reduced in the XC95108 by con-figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.Operating current for each design can be approximated for specific operating conditions using the following equation:I CC (mA) = MC HP (1.7) + MC LP (0.9) + MC (0.006 mA/MHz) f Where:MC HP = Macrocells in high-performance mode MC LP = Macrocells in low-power mode MC = T otal number of macrocells used f = Clock frequency (MHz)Figure 1 shows a typical calculation for the XC95108device.DS066 (v5.0) May 17, 2013Product SpecificationFigure 1: Typical I CC vs. Frequency for XC95108找FPGA ，上赛灵思半导体（深圳）有限公司Absolute Maximum RatingsQuality and Reliability CharacteristicsSymbol DescriptionValue Units V CC Supply voltage relative to GND –0.5 to 7.0V V IN Input voltage relative to GND –0.5 to V CC + 0.5V V TS Voltage applied to 3-state output –0.5 to V CC + 0.5VT STG Storage temperature (ambient)–65 to +150o CT JJunction temperature+150o CNotes:1.Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.Symbol ParameterMin Max Units T DR Data Retention20-Y ears N PEProgram/Erase Cycles (Endurance)10,000-CyclesXC95108-15PCG84C 15 ns PCG8484-pin Plastic Lead Chip Carrier (PLCC); Pb-FreeC XC95108-15PQ100C 15 ns PQ100100-pin Plastic Quad Flat Pack (PQFP)C XC95108-15PQG100C 15 ns PQG100100-pin Plastic Quad Flat Pack (PQFP); Pb-FreeC XC95108-15TQ100C 15 ns TQ100100-pin Thin Quad Flat Pack (TQFP)C XC95108-15TQG100C 15 ns TQG100100-pin Thin Quad Flat Pack (TQFP); Pb-FreeC XC95108-15PQ160C 15 ns PQ160160-pin Plastic Quad Flat Pack (PQFP)C XC95108-15PQG160C 15 ns PQG160160-pin Plastic Quad Flat Pack (PQFP); Pb-FreeC XC95108-15PC84I 15 ns PC8484-pin Plastic Lead Chip Carrier (PLCC)I XC95108-15PCG84I 15 ns PCG8484-pin Plastic Lead Chip Carrier (PLCC); Pb-FreeI XC95108-15PQ100I 15 ns PQ100100-pin Plastic Quad Flat Pack (PQFP)I XC95108-15PQG100I 15 ns PQG100100-pin Plastic Quad Flat Pack (PQFP); Pb-FreeI XC95108-15TQ100I 15 ns TQ100100-pin Thin Quad Flat Pack (TQFP)I XC95108-15TQG100I 15 ns TQG100100-pin Thin Quad Flat Pack (TQFP); Pb-FreeI XC95108-15PQ160I 15 ns PQ160160-pin Plastic Quad Flat Pack (PQFP)I XC95108-15PQG160I 15 ns PQG160160-pin Plastic Quad Flat Pack (PQFP); Pb-FreeI XC95108-20PC84C 20 ns PC8484-pin Plastic Lead Chip Carrier (PLCC)C XC95108-20PCG84C 20 ns PCG8484-pin Plastic Lead Chip Carrier (PLCC); Pb-FreeC XC95108-20PQ100C 20 ns PQ100100-pin Plastic Quad Flat Pack (PQFP)C XC95108-20PQG100C 20 ns PQG100100-pin Plastic Quad Flat Pack (PQFP); Pb-FreeC XC95108-20TQ100C 20 ns TQ100100-pin Thin Quad Flat Pack (TQFP)C XC95108-20TQG100C 20 ns TQG100100-pin Thin Quad Flat Pack (TQFP); Pb-FreeC XC95108-20PQ160C 20 ns PQ160160-pin Plastic Quad Flat Pack (PQFP)C XC95108-20PQG160C 20 ns PQG160160-pin Plastic Quad Flat Pack (PQFP); Pb-FreeC XC95108-20PC84I 20 ns PC8484-pin Plastic Lead Chip Carrier (PLCC)I XC95108-20PCG84I 20 ns PCG8484-pin Plastic Lead Chip Carrier (PLCC); Pb-FreeI XC95108-20PQ100I 20 ns PQ100100-pin Plastic Quad Flat Pack (PQFP)I XC95108-20PQG100I 20 ns PQG100100-pin Plastic Quad Flat Pack (PQFP); Pb-FreeI XC95108-20TQ100I 20 ns TQ100100-pin Thin Quad Flat Pack (TQFP)I XC95108-20TQG100I 20 ns TQG100100-pin Thin Quad Flat Pack (TQFP); Pb-FreeI XC95108-20PQ160I 20 ns PQ160160-pin Plastic Quad Flat Pack (PQFP)I XC95108-20PQG160I 20 nsPQG160160-pinPlastic Quad Flat Pack (PQFP); Pb-FreeINotes:1. C = Commercial: T A = 0° to +70°C; I = Industrial: T A = –40° to +85°CDevice Ordering and Part Marking Number Speed (pin-to-pin delay)Pkg. Symbol No. of Pins Package TypeOperating Range (1)XC95108 In-System Programmable CPLDWarranty DisclaimerTHESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT . THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULL Y AT THE RISK OF CUSTOMER SUBJECT TO APPLICABLE LAWS AND REGULATIONS.。
FPGA可编程逻辑器件芯片XC95108-10PQG100I中文规格书
Table 1-3 lists alphabetically the signal names, clock domains, directions, and descriptions for the GTX_DUAL ports, and provides links to their detailed descriptions.MGTRREF_R In (Pad)TXT only: Reference resistor input for the X1 column. Analog Design Guidelines (page 254)MGTRREF_L In (Pad)TXT only: Reference resistor input for the X0 column. Analog Design Guidelines (page 254)MGTRXN0MGTRXP0MGTRXN1MGTRXP1In (Pad)Differential complements forming adifferential receiver input pair foreach transceiver.RX Termination andEqualization (page 162)MGTTXN0MGTTXP0MGTTXN1MGTTXP1Out (Pad)Differential complements forming a differential transmitter output pair for each transceiver.RX Termination and Equalization (page 162)Table 1-2:GTX_DUAL Analog Pin Summary (Cont’d)PinDir DescriptionSection (Page)Table 1-3:GTX_DUAL Port Summary PortDir Domain DescriptionSection (Page)CLKINInAsyncReference clock input to the shared PMA PLL.Shared PMA PLL (page 87), Clocking (page 98),Power Control (page 110)DADDR[6:0]In DCLK DRP address bus.Dynamic Reconfiguration Port (page 117)DCLK In N/A DRP interface clock.Dynamic Reconfiguration Port (page 117)DENIn DCLK Enables DRP read or write operations.Dynamic Reconfiguration Port (page 117)DFECLKDLYADJ0[5:0]DFECLKDLYADJ1[5:0]In RXUSRCLK2DFE clock delay adjust control for each transceiver.Decision Feedback Equalization (page 167)DFECLKDLYADJMONITOR0[5:0]DFECLKDLYADJMONITOR1[5:0]Out RXUSRCLK2DFE clock delay adjust monitor for each transceiver.Decision Feedback Equalization (page 167)DFEEYEDACMONITOR0[4:0]DFEEYEDACMONITOR1[4:0]Out RXUSRCLK2Vertical Eye Scan for each transceiver (voltage domain).Decision Feedback Equalization (page 167)DFESENSCAL0[2:0]DFESENSCAL1[2:0]OutRXUSRCLK2DFE calibration status.Decision Feedback Equalization (page 167)DFETAP10[4:0]DFETAP11[4:0]In RXUSRCLK2DFE tap 1 weight value control for each transceiver (5-bit resolution).Decision Feedback Equalization (page 167)DFETAP1MONITOR0[4:0]DFETAP1MONITOR1[4:0]Out RXUSRCLK2DFE tap 1 weight value monitorfor each transceiver (5-bitresolution).Decision FeedbackEqualization (page 167)TERMINATION_CTRL[4:0]5-bitBinaryControls internal terminationcalibration circuit.Analog Design Guidelines(page254)TERMINATION_IMP_0 TERMINATION_IMP_1IntegerSet to 50. Implies 50Ω terminatedinputs and outputs with a differentialimpedance of 100Ω.RX Termination andEqualization (page163),Analog Design Guidelines(page255)TERMINATION_OVRD Boolean Selects whether the external 59Ω(2)precision resistor connected to theMGTRREF pin or an override value isused, as defined byTERMINATION_CTRL.Analog Design Guidelines(page255)TRANS_TIME_FROM_P2_0 TRANS_TIME_FROM_P2_112-bitHexTransition time from the P2 power-down state in internal 25MHz clockcycles. The exact time depends on theCLKIN rate and the setting ofCLK25_DIVIDER.Power Control (page111)TRANS_TIME_NON_P2_0 TRANS_TIME_NON_P2_18-bit HexTransition time to or from any power-down state except P2 in internal25MHz clock cycles. The exact timedepends on the CLKIN rate and thesetting of CLK25_DIVIDER.Power Control (page111)TRANS_TIME_TO_P2_0 TRANS_TIME_TO_P2_110-bitHexTransition time to the P2 power-downstate in internal 25MHz clock cycles.The exact time depends on the CLKINrate and the setting ofCLK25_DIVIDER.Power Control (page111)TX_BUFFER_USE_0 TX_BUFFER_USE_1BooleanIndicates whether or not the TX bufferis used.TX Buffering, PhaseAlignment, and TX SkewReduction (page144)TX_DETECT_RX_CFG_0 TX_DETECT_RX_CFG_114-bitHexConfiguration for the transmitterdetect remote receiver circuit.TXGEARBOX_USE_0TXGEARBOX_USE_1Boolean Enables TX Gearbox.TX Gearbox (page135)TX_IDLE_DELAY_0 TX_IDLE_DELAY_13-bitBinarySets the idle delay.TXRX_INVERT0 TXRX_INVERT13-bitBinaryControls inverters that optimize theclock paths within the GTX transceiver.When bypassing the TX buffer, set to111.Otherwise, set to 011.TX Buffering, PhaseAlignment, and TX SkewReduction (page144)Table 1-5:GTX_DUAL Attribute Summary (Cont’d)Attribute Type Description Section (Page)Chapter 3:Simulationphased out after ISE 11.1 software. The FAST setting is highly recommended for newcustomer designs.This attribute can be used independently of the SIM_GTXRESET_SPEEDUP attribute.SIM_PLL_PERDIV2The GTX_DUAL tile contains an analog PLL to generate the transmit and receive clocksout of a reference clock. Because HDL simulators do not fully model the analog PLL, theGTX_DUAL Smartmodel includes an equivalent behavioral model to simulate the PLLoutput. The SIM_PLL_PERDIV2 attribute is used by the behavioral model to generate thePLL output as accurately as possible. It must be set to one-half the period of the sharedPMA PLL. See “Examples,” page 58 for how to calculate SIM_PLL_PERDIV2 for a givenrate.SIM_RECEIVER_DETECT_PASSThe GTX_DUAL includes a TXDETECTRX feature that allows the transmitter to detectwhether its serial ports are currently connected to a receiver by measuring rise time on theTXP/TXN differential pin pair (see “Receive Detect Support for PCI Express Operation,”page 153).The GTX_DUAL SmartModel includes an attribute for simulating TXDETECTRX calledSIM_RECEIVER_DETECT_PASS. This attribute allows TXDETECTRX to be simulated foreach GTX transceiver without modelling the measurement of rise time on the TXP/TXNdifferential pin pair.By default, SIM_RECEIVER_DETECT_PASS is set to TRUE. When TRUE, the attributemodels a connected receiver, and TXDETECTRX operations indicate a receiver isconnected. To model a disconnected receiver, SIM_RECEIVER_DETECT_PASS for thetransceiver is set to FALSE.Power-Up and ResetLink Idle ResetTo simulate correctly, the Link Idle Reset circuit, described in“Link Idle Reset Support,”page 105, must be implemented and connected to each GTX_DUAL instance. This circuit isincluded automatically when the Wizard is used to configure the GTX_DUAL instance.T oggling GSRThe GSR signal is a global routing of nets in the design that provide a means of setting orresetting applicable components in the device during configuration.The simulation behavior of this signal is modeled using the glbl module in Verilog and theROC/ROCBUF components in VHDL.Providing Clocks in SimulationIn simulation, the clocks inside the PMA are generated using the SIM_PLL_PERDIV2parameter (in picoseconds). Any other clocks driven into the user clock must have thesame level of precision, or TX buffer errors (and RX buffer errors in systems without clockcorrection) can result. When generating USRCLK, USRCLK2, or reference clock signals inthe test bench, the clock periods must be related to SIM_PLL_PERDIV2 and also be a roundPackage Placement Information。
XC95144-10PQG100C中文资料
Min
Max
2.4
-
2.4
-
-
0.5
-
0.4
-
±10
-
±
-
10
160 (Typical)
Units V V V V μA
XC9500 concurrently • Available in 100-pin PQFP, 100-pin TQFP, and 160-pin
PQFP packages
Description
The XC95144 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of eight 36V18 Function Blocks, providing 3,200 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview.
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used
f = Clock frequency (MHz)
Figure 1 shows a typical calculation for the XC95144 device.
FPGA可编程逻辑器件芯片XC95108-10TQ100I中文规格书
Capture-DR:In this controller state, the data is parallel-loaded into the data registers selected by the current instruction on the rising edge of TCK.Shift-Dr, Exit1-DR, Pause-DR, Exit2-DR, and Update-DR:These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, and Update-IR states in the Instruction path.Virtex-5 devices support the mandatory IEEE 1149.1 commands, as well as several Xilinx vendor-specific commands. The EXTEST, INTEST, SAMPLE/PRELOAD, BYPASS,IDCODE, USERCODE, and HIGHZ instructions are all included. The TAP also supports internal user-defined registers (USER1, USER2, USER3, and USER4) and configuration/readback of the device.The Virtex-5 Boundary-Scan operations are independent of mode selection. TheBoundary-Scan mode in Virtex-5 devices overrides other mode selections. For this reason, Boundary-Scan instructions using the Boundary-Scan register (SAMPLE/PRELOAD, INTEST, and EXTEST) must not be performed during configuration. All instructions except the user-defined instructions are available before a Virtex-5 device is configured. After configuration, all instructions are available.JSTART and JSHUTDOWN are instructions specific to the Virtex-5 architecture andconfiguration flow. In Virtex-5 devices, the TAP controller is not reset by the PROGRAM_B pin and can only be reset by bringing the controller to the TLR state. The TAP controller is reset on power up.For details on the standard Boundary-Scan instructions EXTEST, INTEST, and BYPASS, refer to the IEEE Standard.Figure 3-2:Boundary-Scan TAP Controller1UG191_c3_02_050406NOTE: The value shown adjacent to each state transition in this figure represents the signal present at TMS at the time of a rising edge at TCK.Multiple Device ConfigurationIt is possible to configure multiple Virtex-5 devices in a chain. (See Figure3-7.) The devices in the JTAG chain are configured one at a time. The multiple device configuration steps can be applied to any size chain.Refer to the state diagram in Figure3-2 for the following TAP controller steps:1.On power-up, place a logic 1 on the TMS and clock the TCK five times. This ensuresstarting in the TLR (Test-Logic-Reset) state.2.Load the CFG_IN instruction into the target device (and BYPASS in all other devices).Go through the RTI state (RUN-TEST/IDLE).3.Load in the configuration bitstream per step7 through step11 in Table3-4.4.Repeat step2 and step3 for each device.5.Reset all TAPs by clocking five 1s on TMS.6.Load the JSTART command into all devices.7.Go to the RTI state and clock TCK 12 times.All devices are active at this point.JT AG He a derDevice 0Device 1Device 2UG191_c3_01_020609Figure 3-7:Boundary-Scan Chain of DevicesIf JTAG is the only configuration mode, then PROGRAM_B, INIT_B, and DONE can each be tied High to separate resistors as shown in the Master serial or Master/Slave Serial Mode Daisy Chain Configuration (see Figure2-3 and Figure2-4).Boundary-Scan for Virtex-5 Devices Using IEEE Standard 1149.1Reconfiguring through Boundary-ScanThe ability of Virtex-5 devices to perform partial reconfiguration is the reason that the configuration memory is not cleared when reconfiguring the device. When reconfiguring a chain of devices, refer to step3 in Table3-4. There are two methods to reconfigure Virtex-5 devices without possible internal contention. The first method is to pulse thePROGRAM_B pin, resetting the internal configuration memory. The alternate method is to perform a shutdown sequence, placing the device in a safe state. The following shutdown sequence includes using internal registers. (For details on internal registers, refer toChapter7, “Readback and Configuration Verification.”)1.Load the CFG_IN instruction.2.In the SHIFT-DR state, load the synchronization word followed by the Reset CRCRegister (RCRC) command.1111 1111 1111 1111 1111 1111 1111 1111∅ Dummy word1010 1010 1001 1001 0101 0101 0110 0110∅ Synchronization word0011 0000 0000 0000 1000 0000 0000 0001∅ Header: Write to CMD register0000 0000 0000 0000 0000 0000 0000 0111∅ RCRC command0010 0000 0000 0000 0000 0000 0000 0000∅ NO-OP0000 0000 0000 0000 0000 0000 0000 0000∅ flush pipe3.Load JSHUTDOWN.4.Go to the RTI state and clock TCK at least 12 times to clock the shutdown sequence.5.Proceed to the SHIFT-IR state and load the CFG_IN instruction again.6.Go to the SHIFT-DR state and load the configuration bits. Make sure the configurationbits contain the AGHIGH command, asserting the global signal GHIGH_B. Thisprevents contention while writing configuration data.0011 0000 0000 0000 1000 0000 0000 0001∅ Header: Write to CMD0000 0000 0000 0000 0000 0000 0000 1000∅ AGHIGH command assertsGHIGH_B0000 0000 0000 0000 0000 0000 0000 0000∅ flush pipe7.When all configuration bits have been loaded, reset the TAP by clocking five 1s onTMS.8.Go to the SHIFT-IR state and load the JSTART instruction.9.Go to the RTI state and clock TCK at least 12 times to clock the startup sequence.10.Go to the TLR state to complete the reconfiguration process.Chapter 3:Boundary-Scan and JTAG ConfigurationChapter 5:Dynamic Reconfiguration Port (DRP)。
FPGA可编程逻辑器件芯片XC95216-10PQG160I中文规格书
Table 1: Summary of Spartan-3 FPGA Attributes
Device
XC3S50(2) XC3S200 (2) XC3S400 (2) XC3S1000 (2)
System Gates
CLB Array
Equivalent (One CLB = Four Slices)
Logic Cells(1) Rows Columns
Total CLBs
50K
1,728
16
12
192
200K
4,320
24
20
480
400K
8,064
32
28
896
1M
17,280
48
40
1,920
XC3S1500
1.5M
29,952
64
52
3,328
XC3S2000
2M
46,080
80
64
5,120
Distributed RAM Bits (K=1024)
Block RAM Bits (K=1024)
Dedicated Multipliers
DCMs
Max. User I/O
Maximum Differential
I/O Pairs
12K
72K
4
30K
216K
12
56K
288K
16
120K
432K
• Logic resources • Abundant logic cells with shift register capability • Wide, fast multiplexers • Fast look-ahead carry logic • Dedicated 18 x 18 multipliers • JTAG logic compatible with IEEE 1149.1/1532
FPGA可编程逻辑器件芯片XC9536-10PCG44I中文规格书
Configuration Sequence Startup (Step8)Figure 5-11:Startup Sequence (Step 8)After the configuration frames are loaded, the bitstream asserts the DESYNC command, and then the START command instructs the device to enter the startup sequence. Thestartup sequence is controlled by an eight-phase (phases 0–7) sequential state machine that is clocked by the JTAG clock or any user clock defined by the BitGen -g StartupCLK option. The startup sequencer performs the tasks outlined in Table5-15.Table 5-15:User-Selectable Cycle of Startup EventsPhase Event1–6Wait for DCMs and PLLs to lock (optional)1–6Assert Global Write Enable (GWE), allowing RAMs and flip-flops to change state1–6Negate Global 3-State (GTS), activating I/O1–6Release DONE pin7Assert End Of Startup (EOS)The specific order of startup events (except for EOS assertion) is user-programmablethrough BitGen options (refer to UG628, Command Line Tools User Guide). Table5-15 shows the general sequence of events, although the specific phase for each of these startup events is user-programmable (EOS is always asserted in the last phase). Refer to Chapter2,Configuration Interface Basics, for important startup option guidelines. By default, startup events occur as shown in Table5-16.Table 5-16:Default BitGen Sequence of Startup EventsPhase Event4Release DONE pin5Negate GTS, activating I/O6Assert GWE, allowing RAMs and flip-flops to change state7Assert EOSThe startup sequence can be forced to wait for the DCMs and PLLs to lock with theappropriate BitGen options. These options are typically set to prevent DONE and GWE from being asserted (preventing device operation) before the DCMs and PLLs have locked.Startup can wait for DCMs and PLLs by assigning the LCK_CYCLE option to a startup phase. If this is not done, startup does not wait for any DCMs or PLLs. When theLCK_CYCLE is set to a startup phase, the FPGA waits for all DCMs and PLLs to lock prior to moving to the next phase of startup. To only wait for specific DCMs to lock, assign the STARTUP_WAIT attribute to those instances. There is no corresponding attribute for PLLs.When waiting for DCM and PLL lock, the GTS startup setting must be enabled on a phase before LCK_CYCLE. Failing to do so results in the FPGA waiting for the clock componentsChapter 5:Configuration Detailsindefinitely and never completing startup. For additional information on using theLCK_CYCLE feature in master configuration modes, see Required Data Spacing between MultiBoot Images, page 138.The DONE signal is released by the startup sequencer on the cycle indicated by the user, but the startup sequencer does not proceed until the DONE pin actually sees a logic High. The DONE pin is an open-drain bidirectional signal with an internal pull-up by default. By releasing the DONE pin, the device simply stops driving a logic Low and the pin is weakly pulled High. Table 5-17 shows signals relating to the startup sequencer. Figure 5-12 shows the waveforms relating to the startup sequencer.In a Slave configuration mode, additional clocks are needed after DONE goes High to complete the startup events. In Master configuration mode, the FPGA provides these clocks. The number of clocks necessary varies depending on the settings selected for the startup events. A general rule is to apply eight clocks (with DIN all 1’s) after DONE has gone High. More clocks are necessary if the startup is configured to wait for the DCM and PLLs to lock (LCK_CYCLE).When using the external master clock (USERCCLK) pin, I/O standard becomes enabled at the EOS phase. As I/O standard changes from the default pre-configuration value to the user specified value, a glitch might appear. It is recommended to use clock enables or a reset to prevent glitches from affecting the design.Table 5-17:Signals Relating to the Startup SequencerSignal NameTypeAccess (1)DescriptionDONEBidirectional (2)DONE pin or Spartan-6 FPGA Status RegisterIndicates configuration is complete. Can be held Low externally to synchronize startup with other FPGAs. GWE StatusSpartan-6 FPGA Status RegisterGlobal Write Enable (GWE). When deasserted, GWE disables the CLB and the IOB flip-flops as well as other synchronous elements on the FPGA.GTSGlobal 3-State (GTS). When asserted, GTS disables all the I/O driversexcept for the configuration pins.DCM_LOCKDCM_LOCK indicates when all DCMs and PLLs have locked. This signal is asserted by default. It is active if the STARTUP_WAIT option is used on a DCM and the LCK_CYCLE option is used when the bitstream is generated.Notes:rmation on the Spartan-6 FPGA status register is available in Table 5-35, page 105. Information on accessing the device status register via JTAG is available in Table 6-5, page 124. Information on accessing the device status register via SelectMAP is available in Table 6-1, page 119.2.Open-drain output with internal pull-up by default; the optional driver is enabled using the BitGen DriveDone option.3.GWE is asserted synchronously to the configuration clock (CCLK) and has a significant skew across the part. Therefore, sequential elements might not be released synchronously to the system clock and timing violations can occur during startup. It is recommended to reset the design after startup and/or apply some other synchronization technique.Required Data Spacing between MultiBoot ImagesChapter 7:Reconfiguration and MultiBootChapter 9:Advanced Configuration InterfacesMultiple Device SelectMAP ConfigurationMultiple Spartan-6 devices in Slave SelectMAP mode can be connected on a common SelectMAP bus (Figure 9-3). In a SelectMAP bus, the D, CCLK, RDWR_B, BUSY,PROGRAM_B, DONE, and INIT_B pins share a common connection between all of the devices. To allow each device to be accessed individually, the CSI_B (Chip Select) inputs must not be tied together. External control of the CSI_B signal is required and is usually provided by a microprocessor or CPLD.If Readback is going to be performed on the device after configuration, the RDWR_B and BUSY signals must be handled appropriately. (For details, refer to Chapter 6, Readback and Configuration Verification .)Otherwise, RDWR_B can be tied Low and BUSY can be ignored. The BUSY signal never needs to be monitored when configuring Spartan-6 devices. Refer to Bitstream Loading (Steps 4-7), page 85 and to Chapter 6, Readback and Configuration Verification .Notes relevant to Figure 9-3:1.The DONE pin is by default an open-drain output requiring an external pull-up resistor. In this arrangement, the active DONE driver must be disabled.2.The INIT_B pin is a bidirectional, open-drain pin. An external pull-up resistor is required.3.The BitGen startup clock setting must be set for CCLK for SelectMAP configuration.4.The BUSY signals can be left unconnected if readback is not needed.5.An external controller such as a microprocessor or CPLD is needed to control configuration.Figure 9-3:Multiple Slave Device Configuration on an 8-Bit SelectMAP Bus。
FPGA可编程逻辑器件芯片XC95216-20PQ160I中文规格书
Table 30:Power Voltage Ramp Time RequirementsSymbol Description Device Package Min Max Units T CCO V CCO ramp time for all eight banks All All No limit(4)–N/A T CCINT V CCINT ramp time, only if V CCINT is last inthree-rail power-on sequenceAll All No limit No limit(5)N/ANotes:1.If a limit exists, this specification is based on characterization.2.The ramp time is measured from 10% to 90% of the full nominal voltage swing for all I/O standards.3.For information on power-on current needs, see Power-On Behavior, page544.For mask revisions earlier than revision E (see Mask and Fab Revisions, page58), T CCO min is limited to 2.0ms for the XC3S200 andXC3S400 devices in QFP packages, and limited to 0.6ms for the XC3S200, XC3S400, XC3S1500, and XC3S4000 devices in the FT and FG packages.5.For earlier device versions with the FQ fabrication/process code (see Mask and Fab Revisions, page58), T CCINT max is limited to 500µs. Table 31:Power Voltage Levels Necessary for Preserving RAM ContentsSymbol Description Min Units V DRINT V CCINT level required to retain RAM data 1.0V V DRAUX V CCAUX level required to retain RAM data 2.0V Notes:1.RAM contents include data stored in CMOS configuration latches.2.The level of the V CCO supply has no effect on data retention.3.If a brown-out condition occurs where V CCAUX or V CCINT drops below the retention voltage, then V CCAUX or V CCINT must drop below theminimum power-on reset voltage indicated in Table29 in order to clear out the device configuration content.Table 32:General Recommended Operating ConditionsSymbol Description Min Nom Max Units T J Junction temperature Commercial02585°CIndustrial–4025100°C V CCINT Internal supply voltage 1.140 1.200 1.260V V CCO(1)Output driver supply voltage 1.140– 3.465V V CCAUX Auxiliary supply voltage 2.375 2.500 2.625V ΔV CCAUX(2)Voltage variance on VCCAUX when using a DCM––10mV/msV IN(3)Voltage applied to all User I/O pins and Dual-Purpose pins relative to GND(4)(6)V CCO = 3.3V, IO–0.3– 3.75V V CCO = 3.3V, IO_Lxxy(7)–0.3– 3.75V V CCO≤ 2.5V, IO–0.3–V CCO+0.3(4)V V CCO≤ 2.5V, IO_Lxxy(7)–0.3–V CCO+0.3(4)VVoltage applied to all Dedicated pins relative to GND(5)–0.3–V CCAUX+0.3(5)VNotes:1.The V CCO range given here spans the lowest and highest operating voltages of all supported I/O standards. The recommended V CCO rangespecific to each of the single-ended I/O standards is given in Table35, and that specific to the differential standards is given in T able37.2.Only during DCM operation is it recommended that the rate of change of V CCAUX not exceed 10mV/ms.3.Input voltages outside the recommended range are permissible provided that the I IK input diode clamp diode rating is met. Refer to Table28.4.Each of the User I/O and Dual-Purpose pins is associated with one of the V CCO rails. Meeting the V IN limit ensures that the internal diodejunctions that exist between these pins and their associated V CCO and GND rails do not turn on. The absolute maximum rating is provided in Table28.5.All Dedicated pins (PROG_B, DONE, TCK, TDI, TDO, and TMS) draw power from the V CCAUX rail (2.5V). Meeting the V IN max limit ensuresthat the internal diode junctions that exist between each of these pins and the V CCAUX and GND rails do not turn on.6.See XAPP459, Eliminating I/O Coupling Effects when Interfacing Large-Swing Single-Ended Signals to User I/O Pins on Spartan-3Generation FPGAs.7.For single-ended signals that are placed on a differential-capable I/O, V IN of –0.2V to –0.3V is supported but can cause increased leakagebetween the two pins. See the Parasitic Leakage section in UG331, Spartan-3 Generation FPGA User Guide.Simultaneously Switching Output GuidelinesThis section provides guidelines for the maximum allowable number of Simultaneous Switching Outputs (SSOs). These guidelines describe the maximum number of user I/O pins, of a given output signal standard, that should simultaneously switch in the same direction, while maintaining a safe level of switching noise. Meeting these guidelines for the stated test conditions ensures that the FPGA operates free from the adverse effects of ground and power bounce.Ground or power bounce occurs when a large number of outputs simultaneously switch in the same direction. The output drive transistors all conduct current to a common voltage rail. Low-to-High transitions conduct to the V CCO rail; High-to-Low transitions conduct to the GND rail. The resulting cumulative current transient induces a voltage difference across the inductance that exists between the die pad and the power supply or ground return. The inductance is associated with bonding wires, the package lead frame, and any other signal routing inside the package. Other variables contribute to SSO noise levels, including stray inductance on the PCB as well as capacitive loading at receivers. Any SSO-induced voltage consequently affects internal switching noise margins and ultimately signal quality.Table49 and Table50 provide the essential SSO guidelines. For each device/package combination, T able49 provides the number of equivalent V CCO/GND pairs. The equivalent number of pairs is based on characterization and will possibly not match the physical number of pairs. For each output signal standard and drive strength, Table50 recommends the maximum number of SSOs, switching in the same direction, allowed per V CCO/GND pair within an I/O bank. The T able50 guidelines are categorized by package style. Multiply the appropriate numbers from T able49 and Table50 to calculate the maximum number of SSOs allowed within an I/O bank. Exceeding these SSO guidelines may result in increased power or ground bounce, degraded signal integrity, or increased system jitter.SSO MAX/IO Bank = Table49 x Table50The recommended maximum SSO values assume that the FPGA is soldered on the printed circuit board and that the board uses sound design practices. The SSO values do not apply for FPGAs mounted in sockets, due to the lead inductance introduced by the socket.The number of SSOs allowed for quad-flat packages (VQ, TQ, PQ) is lower than for ball grid array packages (FG) due to the larger lead inductance of the quad-flat packages. Ball grid array packages are recommended for applications with a large number of simultaneously switching outputs.Table 49:Equivalent V CCO/GND Pairs per BankDevice VQ100CP132(1)(2)TQ144(1)PQ208FT256FG320FG456FG676FG900FG1156(2) XC3S501 1.5 1.52––––––XC3S2001– 1.523–––––XC3S400–– 1.52335–––XC3S1000––––3355––XC3S1500–––––356––XC3S2000––––––569–XC3S4000–––––––61012XC3S5000–––––––61012 Notes:Table 50:Recommended Number of Simultaneously Switching Outputs per V CCO/GND PairSignal Standard (IOSTANDARD)PackageVQ100TQ144PQ208CP132FT256, FG320, FG456,FG676, FG900, FG1156Single-Ended StandardsGTL000114 GTL_DCI000114 GTLP000119 GTLP_DCI000119 HSLVDCI_15666614 HSLVDCI_18777710 HSLVDCI_25777711 HSLVDCI_331010101010 HSTL_I1111111117 HSTL_I_DCI1111111117 HSTL_III77777 HSTL_III_DCI77777 HSTL_I_181313131317 HSTL_I_DCI_181313131317 HSTL_II_1899999 HSTL_II_DCI_1899999 HSTL_III_1888888 HSTL_III_DCI_1888888 LVCMOS12Slow217171717554131313133261010101018Fast2121212123141111111113699999 LVCMOS15Slow2161212195548779316777918866661512555510Fast210101013254677716677771386666111266667。
FPGA可编程逻辑器件芯片XC95108-10PQ100I中文规格书
Chapter 1:Configuration OverviewCreating an Encrypted BitstreamBitGen, provided with the Xilinx ISE software, can generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the user specifies a 256-bit key as aninput to BitGen. BitGen in turn generates an encrypted bitstream file (BIT) and anencryption key file (NKY).For specific BitGen commands and syntax, refer to the Development System Reference Guide.Loading the Encryption KeyThe encryption key can only be loaded onto a Virtex-5 device through the JTAG interface.The iMPACT tool, provided with the Xilinx ISE software, can accept the NKY file as aninput and program the device with the key through JTAG, using a supported Xilinxprogramming cable.To program the key, the device enters a special key-access mode using theISC_PROGRAM_KEY instruction. In this mode, all FPGA memory, including theencryption key and configuration memory, is cleared. After the key is programmed andthe key-access mode is exited, the key cannot be read out of the device by any means, andit cannot be reprogrammed without clearing the entire device. The key-access mode istransparent to most users.Loading Encrypted BitstreamsOnce the device has been programmed with the correct encryption key, the device can beconfigured with an encrypted bitstream. After configuration with an encrypted bitstream,it is not possible to read the configuration memory through JTAG or SelectMAP readback,regardless of the BitGen security setting.While the device holds an encryption key, a non-encrypted bitstream can be used toconfigure the device; in this case the key is ignored. After configuring with a non-encrypted bitstream, readback is possible (if allowed by the BitGen security setting). Theencryption key still cannot be read out of the device, preventing the use of Trojan Horsebitstreams to defeat the Virtex-5 encryption scheme.The method of configuration is not affected by encryption. The configuration bitstream canbe delivered in any mode (Serial, JTAG, or any x8 parallel modes) from any configurationsolution (PROM, System ACE™ controller, etc.). The x16 and x32 bus widths are notsupported for encrypted bitstreams. Configuration timing and signaling are alsounaffected by encryption.The encrypted bitstream must configure the entire device because partial reconfigurationthrough any configuration interface is not permitted for encrypted bitstreams. Afterconfiguration, the device cannot be reconfigured without toggling the PROGRAM_B pin,cycling power, or issuing the JPROGRAM instruction. Fallback reconfiguration andIPROG reconfiguration (see “Fallback MultiBoot,” page153) are disabled after encryptionis turned on. Readback is available through the ICAP primitive (see “Bitstream Encryptionand Internal Configuration Access Port (ICAP)”). None of these events resets the key ifV BATT or V CCAUX is maintained.A mismatch between the key in the encrypted bitstream and the key stored in the devicecauses configuration to fail with the INIT_B pin going Low and the DONE pin remainingLow.Bitstream EncryptionBitstream Encryption and Internal Configuration Access Port (ICAP) The Internal Configuration Access Port (ICAP) primitive provides the user logic withaccess to the Virtex-5 configuration interface. The ICAP interface is similar to theSelectMAP interface, although the restrictions on readback for the SelectMAP interface donot apply to the ICAP interface after configuration. Users can perform readback throughthe ICAP interface even if bitstream encryption is used. Unless the designer wires the ICAPinterface to user I/O, this interface does not offer attackers a method for defeating theVirtex-5 AES encryption scheme.Users concerned about the security of their design should not:∙Wire the ICAP interface to user I/O-or-∙Instantiate the ICAP primitive.Like the other configuration interfaces, the ICAP interface does not provide access to thekey register.V BATTThe encryption key memory cells are volatile and must receive continuous power to retaintheir contents. During normal operation, these memory cells are powered by the auxiliaryvoltage input (V CCAUX), although a separate V BATT power input is provided for retainingthe key when V CCAUX is removed. Because V BATT draws very little current (on the order ofnanoamperes), a small watch battery is suitable for this supply. (To estimate the battery life,refer to V BATT DC Characteristics in DS202, Virtex-5 Data Sheet: DC and SwitchingCharacteristics and the battery specifications.) At less than a 100nA load, the endurance ofthe battery should be limited only by its shelf life.V BATT does not draw any current and can be removed while V CCAUX is applied. V BATTcannot be used for any purpose other than retaining the encryption keys when V CCAUX isremoved.Chapter 1:Configuration OverviewSelectMAP Configuration Interface PROM files for ganged serial configuration are identical to the PROM files used toconfigure single devices. There are no special PROM file considerations.SelectMAP Configuration InterfaceThe SelectMAP configuration interface (Figure2-6) provides an 8-bit, 16-bit, or 32-bitbidirectional data bus interface to the Virtex-5 configuration logic that can be used for bothconfiguration and readback. (For details, refer to Chapter7, “Readback and ConfigurationVerification.”) The bus width of SelectMAP is automatically detected (see “Bus Width AutoDetection”).CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. Oneor more Virtex-5 devices can be configured through the SelectMAP bus.There are four methods of configuring an FPGA in SelectMAP mode:∙Single device Master SelectMAP∙Single device Slave SelectMAP∙Multiple device SelectMAP bus∙Multiple device ganged SelectMAPTable2-4 describes the SelectMAP configuration interface.Figure 2-6:Virtex-5 Device SelectMAP Configuration InterfaceTable 2-4:Virtex-5 Device SelectMAP Configuration Interface PinsPin Name Type Dedicatedor Dual-PurposeDescriptionM[2:0]Input Dedicated Mode pins - determine configuration modeCCLK Input andOutputDedicatedConfiguration clock source for all configurationmodes except JTAGD[31:0]Three-StateBidirectionalDual-PurposeConfiguration and readback data bus, clockedon the rising edge of CCLK. See “Parallel BusBit Order” and Table1-2.BU S YDONECCLKPROGRAM_BINIT_BD[31:0]M[2:0]C S_BRDWR_BC S O_BUG191_c2_10_072407Board Layout for Configuration Clock (CCLK)。
FPGA可编程逻辑器件芯片XC95288XL-10TQ144I中文规格书
Chapter 6:Readback and Configuration VerificationThe MSB of all configuration packets sent through the CFG_IN register must be sentfirst. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.4.Shift the CFG_OUT instruction into the JTAG Instruction Register through the Shift-IRstate. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted whilemoving the TAP controller out of the SHIFT-IR state.5.Shift 32 bits out of the Status register through the Shift-DR state.6.Reset the TAP controller.Table 6-5:Status Register Readback Command Sequence (JTAG)Step Description Set and Hold# ofClocks(TCK) TDI TMS1Clock five 1s on TMS to bring the device to the TLR state.X15 Move into the RTI state.X01 Move into the Select-IR state.X12 Move into the Shift-IR state.X022Shift the first five bits of the CFG_IN instruction, LSBfirst.00101(CFG_IN)05Shift the MSB of the CFG_IN instruction while exitingSHIFT-IR.011 Move into the SELECT-DR state.X12 Move into the SHIFT-DR state.X023Shift configuration packets into the CFG_IN dataregister, MSB first.a: 0xAA99a: 0x5566b: 0x2901c: 0x2000c: 0x2000d: 0x2000d: 0x20000111Shift the LSB of the last configuration packet whileexiting SHIFT-DR.011 Move into the SELECT-IR state.X13 Move into the SHIFT-IR state.X024Shift the first five bits of the CFG_OUT instruction, LSBfirst.00100(CFG_OUT)05Shift the MSB of the CFG_OUT instruction while exitingShift-IR.011 Move into the SELECT-DR state.X12 Move into the SHIFT-DR state.X02Readback Command SequencesThe packets shifted in to the JTAG CFG_IN register are identical to the packets shifted in through the SelectMAP interface when reading the STAT register through SelectMAP.Configuration Memory Read Procedure (IEEE Std 1149.1 JTAG)The process for reading configuration memory from the FDRO register through the JTAG interface is similar to the process for reading from other registers. However, additional steps are needed to accommodate frame logic. Configuration data coming from the FDRO register pass through the frame buffer, therefore the first frame of readback data is dummy data and should be discarded (refer to the FDRI and FDRO register description). The IEEE Std 1149.1 JTAG readback flow is recommended for most users.1.Reset the TAP controller.2.Shift the CFG_IN instruction into the JTAG Instruction Register. The LSB of theCFG_IN instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state.3.Shift packet write commands into the CFG_IN register through the Shift-DR state:a.Write a dummy word to the device.b.Write the synchronization word to the device.c.Write 1 word to CMD register header.d.Specify the length of the data frame to be read back.e.Write the starting frame address to the FAR registers.4.Shift the JSHUTDOWN instruction into the JTAG Instruction Register.5.Move into the RTI state; remain there for 24 TCK cycles to complete the Shutdown sequence. The DONE pin goes Low during the Shutdown sequence.6.Shift the CFG_IN instruction into the JTAG Instruction Register.7.Move to the Shift-DR state and shift packet write commands into the CFG_IN register:a.Write a dummy word to the device.b.Write the synchronization word to the device.c.Write 1 word to CMD register header.d.Specify the length of the data frame to be read back.e.Write the starting frame address to the FAR registers.f.Write the RCFG command to the device.g.Write the read FDRO register Type-1 packet header to the device.5Shift the contents of the STAT register out of the CFG_OUT data register.0x SSSS015Shift the last bit of the STAT register out of the CFG_OUT data register while exiting SHIFT-DR.S 11Move into the Select-IR state.X 13Move into the Shift-IR State.X 026Reset the TAP Controller.X15Table 6-5:Status Register Readback Command Sequence (JTAG) (Cont’d)StepDescriptionSet and Hold# of Clocks (TCK)TDI TMSh.Write two dummy words to the device to flush the packet buffer.The MSB of all configuration packets sent through the CFG_IN register must be sent first. The LSB is shifted while moving the TAP controller out of the SHIFT-DR state.8.Shift the CFG_OUT instruction into the JTAG Instruction Register through theShift-DR state. The LSB of the CFG_OUT instruction is shifted first; the MSB is shifted while moving the TAP controller out of the SHIFT-IR state.9.Shift frame data from the FDRO register through the Shift-DR state.10.Reset the TAP controller.Table 6-6:Shutdown Readback Command Sequence (JTAG)Step Description Set and Hold# of Clocks(TCK) TDI TMS1Clock five 1s on TMS to bring the device to the TLRstate.X15 Move into the RTI state.X01 Move into the Select-IR state.X12 Move into the Shift-IR state.X022Shift the first five bits of the CFG_IN instruction,LSB first.0010105Shift the MSB of the CFG_IN instruction whileexiting Shift-IR.011 Move into the SELECT-DR state.X12 Move into the SHIFT-DR state.X023Shift configuration packets into the CFG_IN dataregister, MSB first.a: 0xFFFFb: 0xAA99b: 0x5566c: 0x30A1d: 0x0007e: 0x2000f: 0x20000111Shift the LSB of the last configuration packet whileexiting SHIFT-DR.011 Move into the SELECT-IR state.X13 Move into the SHIFT-IR state.X024Shift the first five bits of the JSHUTDOWNinstruction, LSB first.0110105Shift the MSB of the JSHUTDOWN instructionwhile exiting SHIFT-IR.0115Move into the RTI state; remain there for 24TCKcycles.X024 Move into the Select-IR state.X12 Move into the Shift-IR state.X02Required Data Spacing between MultiBoot Images。
FPGA可编程逻辑器件芯片XC9572XL-10TQ100I中文规格书
TX Buffering, Phase Alignment, and TX Skew Reductionor TXRESET (see “FPGA TX Interface,” page 120). Assertion of GTXRESET triggers a sequence that resets the entire GTX_DUAL tile.Using the TX Phase-Alignment Circuit to Minimize TX SkewTo use the phase-alignment circuit to force the XCLK phase of multiple lanes to match the common TXUSRCLK phase, follow these steps.Initial conditions when TX_BUFFER_USE is TRUE:♦Set TX_BUFFER_USE_0 and TX_BUFFER_USE_1 to TRUE.♦Set TXRX_INVERT0 and TXRX_INVERT1 to 011.♦Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXOUT.♦Set PMA_TX_CFG0 and PMA_TX_CFG1 to 20'h80082.1.Set TX_XCLK_SEL0 and TX_XCLK_SEL1 to TXUSR .2.Wait for all clocks to stabilize, then drive TXENPMAPHASEALIGN High.Keep TXENPMAPHASEALIGN High unless the phase-alignment procedure must be repeated. Driving TXENPMAPHASEALIGN Low causes phase alignment to be lost.3.Wait 32 TXUSRCLK2 clock cycles, and then drive TXPMASETPHASE High.4.Wait the number of required TXUSRCLK2 clock cycles as specified in Table 6-11, and then drive TXPMASETPHASE Low. The phase of the PMACLK is now aligned with TXUSRCLK.5.Set TX_XCLK_SEL0 and TX_XCLK_SEL1 back to TXOUT.6.Assert and deassert TXRESET synchronously to TXUSRCLK. In this use mode,TXRESET must be deasserted simultaneously to all GTX Transceivers on which the deskew operation is being performed.The phase-alignment procedure must be redone if any of the following conditions occur:•GTXRESET is asserted•PLLPOWERDOWN is deasserted •The clocking source changedFigure 6-20 shows the TX phase-alignment procedure. TXENPMAPHASEALIGN(0/1) and TXPMASETPHASE(0/1) are independent for each GTX transceiver. Thisimplementation is different from the GTP_DUAL tile where TXENPHASEALIGN and TXPMASETPHASE are shared tile pins. The procedure is always applied to each GTX transceiver’s TXENPMAPHASEALIGN(0/1) signal on the tile. TXOUTCLK cannot be the source for TXUSRCLK when the TX phase-alignment circuit is used. See “FPGA TX Interface,” page 120 for details.Table 6-11:Number of Required TXUSRCLK2 Clock CyclesPLL_DIVSEL_OUT_0PLL_DIVSEL_OUT_1TXUSRCLK2 Wait Cycles18,192216,384432,767Chapter 6:GTX Transmitter (TX)TX PRBS GeneratorOverviewPseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link.The GTX PRBS block can generate several industry-standard PRBS patterns. Table 6-13 lists the available PRBS patterns and their typical uses.Ports and AttributesTable 6-14 defines the TX PRBS generator ports.There are no attributes in this section.DescriptionEach GTX transceiver includes a built-in PRBS generator. This feature can be used inconjunction with other test features, such as loopback and the built-in PRBS checker, to run tests on a given channel.To use the PRBS generator, the PRBS test mode is selected using the TXENPRBSTST port. Table 6-14 lists the available settings.Table 6-13:Pseudo-Random Bit Sequences Name Polynomial Length of Sequence (bits)Consecutive ZerosTypical UsePRBS-71+X 6+X 7 (inverted)27–17Used to test channels with 8B/10B.PRBS-231+X 18+X 23 (inverted)223–123ITU-T Recommendation O.150, Section 5.6. One of therecommended test patterns in the SONET specification.PRBS-311+X 28+X 31 (inverted)231–131ITU-T Recommendation O.150, Section 5.8. A recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE 802.3ae-2002.Table 6-14:TX PRBS Generator PortsPortDirectionClock DomainDescriptionTXENPRBSTST0[1:0]TXENPRBSTST1[1:0]InTXUSRCLK2Transmitter test pattern generation control. A pseudo-random bit sequence (PRBS) is generated by enabling the test pattern generation circuit.00: Test pattern generation off (standard operation mode)01: Enable 27–1 PRBS generation 10: Enable 223–1 PRBS generation 11: Enable 231–1 PRBS generationBecause PRBS patterns are deterministic, the receiver can check the received data against a sequence of its own PRBS generator.TX Out-of-Band/Beacon SignalingChapter 6:GTX Transmitter (TX)Parallel In to Serial OutParallel In to Serial OutOverviewThe Parallel In to Serial Out (PISO) block is the heart of the GTX TX datapath. It serializes parallel data from the PCS using a high-speed clock from the shared PMA PLL.The PISO block serializes 16 or 20 bits per parallel clock cycle, depending on the internal data width for the tile (INTDATAWIDTH). The clock rate is determined by the shared PMA PLL rate, divided by a local TX divider.Ports and AttributesTable 6-15 defines the TX PISO ports.Table 6-16 defines the TX PISO attributes.DescriptionEquation 6-5 shows how to calculate the TX line rate when operating without oversampling (OVERSAMPLE_MODE = FALSE).Equation 6-5When oversampling is activated, use Equation 6-6 to calculate the line rate.Equation 6-6See “Oversampling,” page 185 for more information about oversampling.Table 6-15:TX PISO PortsPortDirectionClock DomainDescriptionINTDATAWIDTH In AsyncSpecifies the width of the internal datapath for the entire GTX_DUAL tile. This shared port is also described in “Shared PMA PLL,” page 86.0: Internal datapath is 16 bits wide 1: Internal datapath is 20 bits wideTable 6-16:TX PISO AttributesAttributeTypeDescriptionOVERSAMPLE_MODEBooleanThis shared attribute activates the built-in 5x digital oversampling circuits in both GTX transceivers. Oversampling must be enabled when running the GTX transceivers at line rates between 150Mb/s and 750Mb/s.TRUE: Built-in 5x digital oversampling enabled for both GTX transceivers on the tileFALSE: Digital oversampling disabledSee “Oversampling,” page 185 for more details about 5x digital oversampling.PLL_TXDIVSEL_OUT_0 PLL_TXDIVSEL_OUT_1IntegerSets the divider for the TX line rate for the individual GTX transceiver. The divider can be set to 1, 2, or 4.Tx Line Rate PLL Clock Rate 2×PLL_TXDIVSEL_OUT----------------------------------------------------------=Tx Line Rate PLL Clock Rate 2×PLL_TXDIVSEL_OUT 5×---------------------------------------------------------------------=。
FPGA可编程逻辑器件芯片EP1C3T100I7中文规格书
TWI Registers•Receive FIFO status (RCVSTAT[1:0])The RCVSTAT field is read only. It indicates the number of valid databytes in the receive FIFO buffer. The status is updated with eachFIFO buffer read using the peripheral data bus or write access bythe receive shift register. Simultaneous accesses are allowed.[b#11] The FIFO is full and contains two bytes of data. Either asingle or double byte peripheral read of the FIFO is allowed.[b#10] Reserved[b#01] The FIFO contains one byte of data. A single byte periph-eral read of the FIFO is allowed.[b#00] The FIFO is empty.•Transmit FIFO status (XMTSTAT[1:0])The XMTSTAT field is read only. It indicates the number of valid databytes in the FIFO buffer. The status is updated with each FIFObuffer write using the peripheral data bus or read access by thetransmit shift register. Simultaneous accesses are allowed.[b#11] The FIFO is full and contains two bytes of data.[b#10] Reserved[b#01] The FIFO contains one byte of data. A single byte periph-eral write of the FIFO is allowed.[b#00] The FIFO is empty. Either a single or double byte periph-eral write of the FIFO is allowed.ADSP-BF54x Blackfin Processor Hardware ReferenceTWI RegistersADSP-BF54x Blackfin Processor Hardware ReferenceTWI FIFO Receive Data Single Byte (TWIx_RCV_DATA8) RegisterThe TWIx_RCV_DATA8 register holds an 8-bit data value read from the FIFO buffer. Receive data is read from the corresponding receive buffer in a first-in first-out order. Although peripheral bus reads are 16 bits, a read access to TWIx_RCV_DATA8 accesses only one transmit data byte from the FIFO buffer. With each access, the receive status (RCVSTAT ) field in the TWIx_FIFO_STAT register is updated. If an access is performed while the FIFO buffer is empty, the data is unknown and the FIFO buffer status remains indicating it is empty.Figure 23-27. TWI FIFO Receive Data Single Byte Register 15141312111098765432100000000000000000TWI FIFO Receive Data Single Byte Register (TWIx_RCV_DATA 8)All bits are RO.RCVDATA 8[7:0] (ReceiveFIFO 8-Bit Data)Reset = 0x0000TWI0_RCV_DATA 8 0xFFC00788TWI1_RCV_DATA 8 0xFFC02288。
FPGA可编程逻辑器件芯片EPC8QI100N中文规格书
PowerPlay Early Power Estimator InputsTable17–6.I/O Section Information(Part 2 of 2)Other Input InformationThere are three other buttons below the input parameters section: Set Toggle %, Reset,and Import Quartus File, as shown in Figure17–12.Figure17–12.The Three ButtonsSet Toggle %Sets the toggle rate for the Logic Module and I/O Module.Power Estimation Summary Power Estimation SummaryThe main worksheet of the PowerPlay Early Power Estimator spreadsheetsummarizes the power and current estimates for the design. It displays the totalpower, thermal analysis, and power supply current information. The accuracy of the information depends on the information entered. The power consumed can also vary greatly depending on the toggle rates entered. The following sections provide a description of the results of the PowerPlay Early Power Estimator spreadsheet.PowerThis section shows the power dissipated in the MAX II device. The total thermal power is shown in mWatts and is a sum of the thermal power of all the resources being used in the device. The total thermal power includes the typical power from standby and dynamic power. Figure 17–13 shows the Power section.Table 17–7 describes the thermal power parameters in the PowerPlay Early Power Estimator spreadsheet.Figure 17–13.Power SectionTable 17–7.Power InformationChapter 17:Understanding and Evaluating Power in MAX II DevicesPower Estimation Summary Thermal AnalysisIn the Thermal Analysis part, the PowerPlay Early Power Estimator spreadsheet considers the device’s ambient temperature and the airflow to determine the junction temperature (T J ) of the device in °C. The device can be considered a heat source and the junction temperature is the temperature at the device. The thermal resistance of the path is referred to as the junction-to-ambient thermal resistance (θJA ). Figure 17–14 shows the thermal model for the PowerPlay Early Power Estimator spreadsheet.The PowerPlay Early Power Estimator spreadsheet determines the junction-to-ambient thermal resistance (θJA ) based on the device, package, and airflow selected in the main input parameters.The PowerPlay Early Power Estimator spreadsheet calculates the total power based on the device properties which provide θJA and the ambient and junction temperature using the following equation:Figure 17–15 shows the Thermal Analysis section and Table 17–8 describes the thermal analysis parameters in the PowerPlay Early Power Estimator spreadsheet.Figure 17–14.Thermal Model for the PowerPlay Early Power Estimator Equation 17–1.Figure 17–15.Thermal Analysis SectionT J T A θJA P T J T A –θJA ----------------=。
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Chapter 1:Configuration OverviewCreating an Encrypted BitstreamBitGen, provided with the Xilinx ISE software, can generate encrypted as well as non-encrypted bitstreams. For AES bitstream encryption, the user specifies a 256-bit key as aninput to BitGen. BitGen in turn generates an encrypted bitstream file (BIT) and anencryption key file (NKY).For specific BitGen commands and syntax, refer to the Development System Reference Guide.Loading the Encryption KeyThe encryption key can only be loaded onto a Virtex-5 device through the JTAG interface.The iMPACT tool, provided with the Xilinx ISE software, can accept the NKY file as aninput and program the device with the key through JTAG, using a supported Xilinxprogramming cable.To program the key, the device enters a special key-access mode using theISC_PROGRAM_KEY instruction. In this mode, all FPGA memory, including theencryption key and configuration memory, is cleared. After the key is programmed andthe key-access mode is exited, the key cannot be read out of the device by any means, andit cannot be reprogrammed without clearing the entire device. The key-access mode istransparent to most users.Loading Encrypted BitstreamsOnce the device has been programmed with the correct encryption key, the device can beconfigured with an encrypted bitstream. After configuration with an encrypted bitstream,it is not possible to read the configuration memory through JTAG or SelectMAP readback,regardless of the BitGen security setting.While the device holds an encryption key, a non-encrypted bitstream can be used toconfigure the device; in this case the key is ignored. After configuring with a non-encrypted bitstream, readback is possible (if allowed by the BitGen security setting). Theencryption key still cannot be read out of the device, preventing the use of Trojan Horsebitstreams to defeat the Virtex-5 encryption scheme.The method of configuration is not affected by encryption. The configuration bitstream canbe delivered in any mode (Serial, JTAG, or any x8 parallel modes) from any configurationsolution (PROM, System ACE™ controller, etc.). The x16 and x32 bus widths are notsupported for encrypted bitstreams. Configuration timing and signaling are alsounaffected by encryption.The encrypted bitstream must configure the entire device because partial reconfigurationthrough any configuration interface is not permitted for encrypted bitstreams. Afterconfiguration, the device cannot be reconfigured without toggling the PROGRAM_B pin,cycling power, or issuing the JPROGRAM instruction. Fallback reconfiguration andIPROG reconfiguration (see “Fallback MultiBoot,” page153) are disabled after encryptionis turned on. Readback is available through the ICAP primitive (see “Bitstream Encryptionand Internal Configuration Access Port (ICAP)”). None of these events resets the key ifV BATT or V CCAUX is maintained.A mismatch between the key in the encrypted bitstream and the key stored in the devicecauses configuration to fail with the INIT_B pin going Low and the DONE pin remainingLow.Bitstream EncryptionBitstream Encryption and Internal Configuration Access Port (ICAP) The Internal Configuration Access Port (ICAP) primitive provides the user logic withaccess to the Virtex-5 configuration interface. The ICAP interface is similar to theSelectMAP interface, although the restrictions on readback for the SelectMAP interface donot apply to the ICAP interface after configuration. Users can perform readback throughthe ICAP interface even if bitstream encryption is used. Unless the designer wires the ICAPinterface to user I/O, this interface does not offer attackers a method for defeating theVirtex-5 AES encryption scheme.Users concerned about the security of their design should not:∙Wire the ICAP interface to user I/O-or-∙Instantiate the ICAP primitive.Like the other configuration interfaces, the ICAP interface does not provide access to thekey register.V BATTThe encryption key memory cells are volatile and must receive continuous power to retaintheir contents. During normal operation, these memory cells are powered by the auxiliaryvoltage input (V CCAUX), although a separate V BATT power input is provided for retainingthe key when V CCAUX is removed. Because V BATT draws very little current (on the order ofnanoamperes), a small watch battery is suitable for this supply. (To estimate the battery life,refer to V BATT DC Characteristics in DS202, Virtex-5 Data Sheet: DC and SwitchingCharacteristics and the battery specifications.) At less than a 100nA load, the endurance ofthe battery should be limited only by its shelf life.V BATT does not draw any current and can be removed while V CCAUX is applied. V BATTcannot be used for any purpose other than retaining the encryption keys when V CCAUX isremoved.Chapter 1:Configuration OverviewSelectMAP Configuration Interface PROM files for ganged serial configuration are identical to the PROM files used toconfigure single devices. There are no special PROM file considerations.SelectMAP Configuration InterfaceThe SelectMAP configuration interface (Figure2-6) provides an 8-bit, 16-bit, or 32-bitbidirectional data bus interface to the Virtex-5 configuration logic that can be used for bothconfiguration and readback. (For details, refer to Chapter7, “Readback and ConfigurationVerification.”) The bus width of SelectMAP is automatically detected (see “Bus Width AutoDetection”).CCLK is an output in Master SelectMAP mode; in Slave SelectMAP, CCLK is an input. Oneor more Virtex-5 devices can be configured through the SelectMAP bus.There are four methods of configuring an FPGA in SelectMAP mode:∙Single device Master SelectMAP∙Single device Slave SelectMAP∙Multiple device SelectMAP bus∙Multiple device ganged SelectMAPTable2-4 describes the SelectMAP configuration interface.Figure 2-6:Virtex-5 Device SelectMAP Configuration InterfaceTable 2-4:Virtex-5 Device SelectMAP Configuration Interface PinsPin Name Type Dedicatedor Dual-PurposeDescriptionM[2:0]Input Dedicated Mode pins - determine configuration modeCCLK Input andOutputDedicatedConfiguration clock source for all configurationmodes except JTAGD[31:0]Three-StateBidirectionalDual-PurposeConfiguration and readback data bus, clockedon the rising edge of CCLK. See “Parallel BusBit Order” and Table1-2.BU S YDONECCLKPROGRAM_BINIT_BD[31:0]M[2:0]C S_BRDWR_BC S O_BUG191_c2_10_072407Board Layout for Configuration Clock (CCLK)。