三星Exynos 4 Quad (Exynos 4412) RISC微处理器用户手册

Samsung Exynos 4 Quad
(Exynos 4412)
RISC Microprocessor
Revision 1.00
October 2012 U s e r's M a n u a l
2012 Samsung Electronics Co., Ltd. All rights reserved.
Important Notice
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Customers are responsible for their own products and applications. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by the customer's technical experts.
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Copyright 2012 Samsung Electronics Co., Ltd.
Samsung Electronics Co., Ltd.
San #24 Nongseo-Dong, Giheung-Gu
Yongin-City, Gyeonggi-Do, Korea 446-711 Contact Us: bach1004@
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Trademarks
All brand names, trademarks and registered trademarks belong to their respective owners.
∙Exynos, Exynos4412, FlexOneNAND, and OneNAND are trademarks of Samsung Electronics.
∙ARM, Jazelle, TrustZone, and Thumb are registered trademarks of ARM Limited.
∙Cortex, ETM, ETB, Coresight, ISA, and Neon are trademarks of ARM Limited.
∙Java is a trademark of Sun Microsystems, Inc.
∙SD is a registered trademark of Toshiba Corporation.
∙MMC and eMMC are trademarks of MultiMediaCard Association.
∙JTAG is a registered trademark of JTAG Technologies, Inc.
∙Synopsys is a registered trademark of Synopsys, Inc.
∙I2S is a trademark of Phillips Electronics.
∙I2C is a trademark of Phillips Semiconductor Corp.
∙MIPI and Slimbus are registered trademarks of the Mobile Industry Processor Interface (MIPI) Alliance. All other trademarks used in this publication are the property of their respective owners.
Chip Handling Guide
Precaution against Electrostatic Discharge
When using semiconductor devices, ensure that the environment is protected against static electricity:
1. Wear antistatic clothes and use earth band.
2. All objects that are in direct contact with devices must be made up of materials that do not produce static
electricity.
3. Ensure that the equipment and work table are earthed.
4. Use ionizer to remove electron charge.
Contamination
Do not use semiconductor products in an environment exposed to dust or dirt adhesion.
Temperature/Humidity
Semiconductor devices are sensitive to:
∙Environment
∙Temperature
∙Humidity
High temperature or humidity deteriorates the characteristics of semiconductor devices. Therefore, do not store or use semiconductor devices in such conditions.
Mechanical Shock
Do not to apply excessive mechanical shock or force on semiconductor devices.
Chemical
Do not expose semiconductor devices to chemicals because exposure to chemicals leads to reactions that deteriorate the characteristics of the devices.
Light Protection
In non- Epoxy Molding Compound (EMC) package, do not expose semiconductor IC to bright light. Exposure to bright light causes malfunctioning of the devices. However, a few special products that utilize light or with security functions are exempted from this guide.
Radioactive, Cosmic and X-ray
Radioactive substances, cosmic ray, or X-ray may influence semiconductor devices. These substances or rays may cause a soft error during a device operation. Therefore, ensure to shield the semiconductor devices under environment that may be exposed to radioactive substances, cosmic ray, or X-ray.
EMS (Electromagnetic Susceptibility)
Strong electromagnetic wave or magnetic field may affect the characteristic of semiconductor devices during the operation under insufficient PCB circuit design for Electromagnetic Susceptibility (EMS).
Revision History
Revision Descriptions for Revision 1.00
Table of Contents
1 PRODUCT OVERVIEW ................................................................................. 1-1
1.1 Introduction .............................................................................................................................................. 1-1
1.2 Features ................................................................................................................................................... 1-2
1.2.1 Multi-Core Processing Unit ............................................................................................................... 1-4
1.2.2 Memory Subsystem .......................................................................................................................... 1-5
1.2.3 Multimedia ........................................................................................................................................ 1-6
1.2.4 Audio Subsystem .............................................................................................................................. 1-8
1.2.5 Image Signal Processing Subsystem ............................................................................................... 1-8
1.2.6 Connectivity ...................................................................................................................................... 1-9
1.2.7 System Peripheral .......................................................................................................................... 1-11
1.3 Conventions ........................................................................................................................................... 1-13
1.3.1 Register RW Conventions .............................................................................................................. 1-13
1.3.2 Register Value Conventions ........................................................................................................... 1-13
2 MEMORY MAP .............................................................................................. 2-1
2.1 Overview .................................................................................................................................................. 2-1
2.2 SFR Base Address .................................................................................................................................. 2-2
3 CHIP ID .......................................................................................................... 3-1
3.1 Overview .................................................................................................................................................. 3-1
3.2 Register Description ................................................................................................................................. 3-2
3.2.1 Register Map Summary .................................................................................................................... 3-2
4 GENERAL PURPOSE INPUT/OUTPUT (GPIO) CONTROL ......................... 4-1
4.1 Overview .................................................................................................................................................. 4-1
4.2 Features ................................................................................................................................................... 4-3
4.2.1 Input/Output Description ................................................................................................................... 4-3
4.3 Register Description ................................................................................................................................. 4-5
4.3.1 Registers Summary .......................................................................................................................... 4-5
4.3.2 Part 1 .............................................................................................................................................. 4-20
4.3.3 Part 2 ............................................................................................................................................ 4-124
4.3.4 Part 3 ............................................................................................................................................ 4-289
4.3.5 Part 4 ............................................................................................................................................ 4-298
5 CLOCK MANAGEMENT UNIT ...................................................................... 5-1
5.1 Overview .................................................................................................................................................. 5-1
5.2 Clock Domains ......................................................................................................................................... 5-1
5.3 Clock Declaration ..................................................................................................................................... 5-3
5.3.1 Clocks from Clock Pads ................................................................................................................... 5-3
5.3.2 Clocks from CMU .............................................................................................................................. 5-4
5.4 Clock Relationship ................................................................................................................................... 5-5
5.4.1 Recommended PLL PMS Value for APLL and MPLL ...................................................................... 5-7
5.4.2 Recommended PLL PMS Value for EPLL ........................................................................................ 5-8
5.4.3 Recommended PLL PMS Value for VPLL ........................................................................................ 5-9
5.5 Clock Generation ................................................................................................................................... 5-10
5.6 Clock Configuration Procedure .............................................................................................................. 5-15
5.6.1 Clock Gating ................................................................................................................................... 5-16
5.6.2 Clock Diving .................................................................................................................................... 5-16
5.7 Special Clock Description ...................................................................................................................... 5-17
5.7.1 Special Clock Table ........................................................................................................................ 5-17
5.8 CLKOUT ................................................................................................................................................. 5-20
5.9 I/O Description ....................................................................................................................................... 5-23
5.10 Register Description ............................................................................................................................. 5-24
5.10.1 Register Map Summary ................................................................................................................ 5-26
6 INTERRUPT CONTROLLER ......................................................................... 6-1
6.1 Overview .................................................................................................................................................. 6-1
6.2 Features ................................................................................................................................................... 6-2
6.2.1 Security Extensions Support ............................................................................................................ 6-2
6.2.2 Implementation-Specific Configurable Features .............................................................................. 6-3
6.3 Interrupt Source ....................................................................................................................................... 6-4
6.3.1 Interrupt Sources Connection ........................................................................................................... 6-4
6.3.2 GIC Interrupt Table ........................................................................................................................... 6-5
6.4 Functional Overview .............................................................................................................................. 6-13
6.5 Register Description ............................................................................................................................... 6-14
6.5.1 Register Map Summary .................................................................................................................. 6-14
7 INTERRUPT COMBINER .............................................................................. 7-1
7.1 Overview .................................................................................................................................................. 7-1
7.2 Features ................................................................................................................................................... 7-1
7.3 Functional Description ............................................................................................................................. 7-2
7.3.1 Block Diagram .................................................................................................................................. 7-2
7.4 Interrupt Sources...................................................................................................................................... 7-3
7.4.1 Interrupt Combiner ............................................................................................................................ 7-3
7.5 Functional Description ............................................................................................................................. 7-8
7.6 Register Description ................................................................................................................................. 7-9
7.6.1 Register Map Summary .................................................................................................................... 7-9
7.6.2 Interrupt Combiner .......................................................................................................................... 7-10
8 DIRECT MEMORY ACCESS CONTROLLER (DMAC) ................................. 8-1
8.1 Overview .................................................................................................................................................. 8-1
8.2 Features ................................................................................................................................................... 8-2
8.3 Register Description ................................................................................................................................. 8-5
8.3.1 Register Map Summary .................................................................................................................... 8-5
8.4 Instruction ............................................................................................................................................... 8-14
9 SROM CONTROLLER ................................................................................... 9-1
9.1 Overview .................................................................................................................................................. 9-1
9.2 Features ................................................................................................................................................... 9-1
9.3 Block Diagram .......................................................................................................................................... 9-1
9.4 Functional Description ............................................................................................................................. 9-2
9.4.1 nWAIT Pin Operation ........................................................................................................................ 9-2
9.4.2 Programmable Access Cycle ........................................................................................................... 9-3
9.5 I/O Description ......................................................................................................................................... 9-4
9.6 Register Description ................................................................................................................................. 9-5
9.6.1 Register Map Summary .................................................................................................................... 9-5
10 NAND FLASH CONTROLLER .................................................................. 10-1
10.1 Overview .............................................................................................................................................. 10-1
10.2 Features ............................................................................................................................................... 10-1
10.3 Functional Description ......................................................................................................................... 10-2
10.3.1 Block Diagram .............................................................................................................................. 10-2
10.3.2 NAND Flash Memory Timing ........................................................................................................ 10-3
10.4 Software Mode ..................................................................................................................................... 10-4
10.4.1 Data Register Configuration ......................................................................................................... 10-4
10.4.2 1/4/8/12/16-bit ECC ...................................................................................................................... 10-5
10.4.3 2048 Byte 1-bit ECC Parity Code Assignment Table ................................................................... 10-6
10.4.4 32 Byte 1-bit ECC Parity Code Assignment Table ....................................................................... 10-6
10.4.5 1-bit ECC Module Features .......................................................................................................... 10-6
10.4.6 1-bit ECC Programming Guide ..................................................................................................... 10-7
10.4.7 4-bit ECC Programming Guide (ENCODING) .............................................................................. 10-8
10.4.8 4-bit ECC Programming Guide (DECODING) .............................................................................. 10-9
10.4.9 8/12/16-bit ECC Programming Guide (ENCODING) .................................................................. 10-10
10.4.10 8/12/16-bit ECC Programming Guide (DECODING) ................................................................ 10-11
10.4.11 ECC Parity Conversion Code Guide for 8/12/16-bit ECC ........................................................ 10-12
10.4.12 Lock Scheme for Data Protection ............................................................................................. 10-13
10.5 Programming Constraints .................................................................................................................. 10-14
10.6 I/O Description ................................................................................................................................... 10-14
10.7 Register Description ........................................................................................................................... 10-15
10.7.1 Register Map Summary .............................................................................................................. 10-15
10.7.2 NAND Flash Interface and 1/4-bit ECC Registers ...................................................................... 10-17
10.7.3 ECC Registers for 8, 12 and 16-bit ECC .................................................................................... 10-29
11 PULSE WIDTH MODULATION TIMER ..................................................... 11-1
11.1 Overview .............................................................................................................................................. 11-1
11.2 Features ............................................................................................................................................... 11-4
11.3 PWM Operation.................................................................................................................................... 11-5
11.3.1 Prescaler and Divider ................................................................................................................... 11-5
11.3.2 Basic Timer Operation .................................................................................................................. 11-6
11.3.3 Auto-Reload and Double Buffering ............................................................................................... 11-8
11.3.4 Timer Operation Example ............................................................................................................. 11-9
11.3.5 Initialize Timer (Setting Manual-Up Data and Inverter) .............................................................. 11-10
11.3.6 PWM ........................................................................................................................................... 11-10
11.3.7 During Current ISR. (Interrupt Service Routine) Output Level Control ...................................... 11-11
11.3.8 Dead Zone Generator ................................................................................................................. 11-12
11.4 I/O Description ................................................................................................................................... 11-13
11.5 Register Description ........................................................................................................................... 11-14
11.5.1 Register Map Summary .............................................................................................................. 11-14
12 WATCHDOG TIMER .................................................................................. 12-1
12.1 Overview .............................................................................................................................................. 12-1
12.2 Features ............................................................................................................................................... 12-1
12.3 Functional Description ......................................................................................................................... 12-2
12.3.1 WDT Operation ............................................................................................................................. 12-2
12.3.2 WTDAT and WTCNT .................................................................................................................... 12-3
12.3.3 WDT Start ..................................................................................................................................... 12-3
12.3.4 Consideration of Debugging Environment .................................................................................... 12-3
12.4 Register Description ............................................................................................................................. 12-4
12.4.1 Register Map Summary ................................................................................................................ 12-4
13 UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER ......... 13-1
13.1 Overview .............................................................................................................................................. 13-1
13.2 Features ............................................................................................................................................... 13-0
13.3 UART Description ................................................................................................................................ 13-1
13.3.1 Data Transmission ........................................................................................................................ 13-2
13.3.2 Data Reception ............................................................................................................................. 13-2
13.3.3 AFC ............................................................................................................................................... 13-3
13.3.4 Example of Non AFC (Controlling nRTS and nCTS by Software) ............................................... 13-4
13.3.5 Trigger Level of Tx/Rx FIFO and DMA Burst Size in DMA Mode ................................................ 13-4
13.3.6 RS-232C Interface ........................................................................................................................ 13-4
13.3.7 Interrupt/DMA Request Generation .............................................................................................. 13-5
13.3.8 UART Error Status FIFO .............................................................................................................. 13-7
13.4 UART Input Clock Description ........................................................................................................... 13-10
13.5 I/O Description ................................................................................................................................... 13-11
13.6 Register Description ........................................................................................................................... 13-12
13.6.1 Register Map Summary .............................................................................................................. 13-12
14 INTER-INTEGRATED CIRCUIT ................................................................. 14-1
14.1 Overview .............................................................................................................................................. 14-1
14.2 Features ............................................................................................................................................... 14-2
14.3 Functional Description ......................................................................................................................... 14-2
14.3.1 Block Diagram .............................................................................................................................. 14-2
14.4 I2C-Bus Interface Operation ................................................................................................................ 14-3
14.4.1 Start and Stop Conditions ............................................................................................................. 14-4
14.4.2 Data Transfer Format ................................................................................................................... 14-5
14.4.3 ACK Signal Transmission ............................................................................................................. 14-6
14.4.4 Read-Write Operation ................................................................................................................... 14-7
14.4.5 Bus Arbitration Procedures ........................................................................................................... 14-7
14.4.6 Abort Conditions ........................................................................................................................... 14-7
14.4.7 Configuring I2C-Bus ..................................................................................................................... 14-7
14.4.8 Flowcharts of Operations in Each Mode ...................................................................................... 14-8
14.5 I/O Description ................................................................................................................................... 14-12
14.6 Register Description ........................................................................................................................... 14-13
14.6.1 Register Map Summary .............................................................................................................. 14-13
15 SERIAL PERIPHERAL INTERFACE ......................................................... 15-1
15.1 Overview .............................................................................................................................................. 15-1
15.2 Features ............................................................................................................................................... 15-1
15.2.1 Operation of SPI ........................................................................................................................... 15-2
15.3 SPI Input Clock Description ................................................................................................................. 15-5
15.4 IO Description ...................................................................................................................................... 15-6
15.5 Register Description ............................................................................................................................. 15-7
15.5.1 Register Map Summary ................................................................................................................ 15-7
16 DISPLAY CONTROLLER .......................................................................... 16-1
16.1 Overview .............................................................................................................................................. 16-1
16.2 Features ............................................................................................................................................... 16-2
16.3 Functional Description ......................................................................................................................... 16-4
16.3.1 Brief Description ........................................................................................................................... 16-4。