K4S560832D中文资料

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K4H560838D-TCB0

- Changed operating condition. from Vil/Vih(ac) VIL/VIH(dc) Vref +/- 0.35V Vref +/- 0.18V to Vref +/- 0.31V Vref +/- 0.15V
- Added Overshoot/Undershoot spec . Vih(max) = 4.2V, the overshoot voltage duration is ≤ 3ns at VDD. . Vil(min) =- 1.5V, the overshoot voltage duration is ≤ 3ns at VSS. - Changed AC parameters as follows. from tDQSQ tDV tQH tHP - Added DC spec values. +/- 0.5(PC266), +/- 0.6(PC200) +/- 0.35tCK to +0.5(PC266), +0.6(PC200) tHPmin - 0.75ns(PC266) tHPmin - 1.0ns(PC200) tCLmin or tCHmin New Definition Removed New Definition Comments
Version 0.71 (April, 2000) - Corrected a typo for tRAS at 133Mhz/CL2.5 from 48ns t0 45ns. - Corrected a typo in "General Information" table from 64Mx4 to 8Mx16. Version 0.72(May,2000) - Changed DC spec item & test condition Version 0.73(June,2000) - Added updated DC spec values - Deleted tDAL in AC parameter Version 1.0(November,2000) - Eliminate "preliminary"

K4H560838F-UCCC中文资料

256Mb F-die DDR400 SDRAM Specification66 TSOP-II with Pb-Free(RoHS compliant)Revision 1.1Rev. 1.1 August. 2003256Mb F-die Revision HistoryRevison 1.0 (June. 2003)1. First releaseRevison 1.1 (August. 2003)1. Added x8 org (K4H560838F)Rev. 1.1 August. 2003Rev. 1.1 August. 2003• 200MHz Clock, 400Mbps data rate.• VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V• Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe(DQS)• Four banks operation• Differential clock inputs(CK and CK)• DLL aligns DQ and DQS transition with CK transition • MRS cycle with address key programs-. Read latency 3 (clock) for DDR400 , 2.5 (clock) for DDR333 -. Burst length (2, 4, 8)-. Burst type (sequential & interleave)• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)• Data I/O transactions on both edges of data strobe • Edge aligned data output, center aligned data input • LDM,UDM for write masking only (x16)• Auto & Self refresh• 7.8us refresh interval(8K/64ms refresh) • Maximum burst refresh cycle : 8• 66pin TSOP II Pb-Free package • RoHS compliantOrdering InformationPart .Max Freq.Interface Package K4H560838F-UCCC 32M x 8 CC(DDR400@CL=3)SSTL266pin TSOP IIK4H560838F-UCC4 C4(DDR400@CL=3)K4H561638F-UCCC 16M x 16CC(DDR400@CL=3)SSTL266pin TSOP IIK4H561638F-UCC4C4(DDR400@CL=3)Key Features*CL : CAS LatencyOperating Frequencies- CC(DDR400@CL=3)- C4(DDR400@CL=3)Speed @CL3200MHz 200MHz CL-tRCD-tRP 3 - 3 - 33 -4 - 4Rev. 1.1 August. 2003Pin DescriptionDM is internally loaded to match DQ and DQS identically.256Mb Package PinoutRow & Column address configurationV DD 166Pin TSOP II (400mil x 875mil)DQ 02V DDQ 3NC 4DQ 15V SSQ 6NC 7DQ 28V DDQ 9NC 10DQ 311V SSQ 12BA 020CS 19RAS 18CAS 17WE 16NC 15V DDQ 14NC 13V DD 27A 326A 225A 124A 023AP/A 1022BA 121V SS 54DQ 753V SSQ 52NC 51DQ 650V DDQ 49NC 48DQ 547V SSQ 46NC 45DQ 444V DDQ 43A 113536CKE 37CK 38DM 39V REF 40V SSQ 41NC 42V SS55A 456A 557A 658A 759A 860A 934(0.65mm Pin Pitch)333231302928616263646566NC NC NC NC NC V DDNC DQS NC V SS CK NC A 12 16Mb x 16V SS DQ 15V SSQ DQ 14DQ 13V DDQ DQ 12DQ 11V SSQ DQ 10DQ 9V DDQ A 11CKE CK UDM V REF V SSQ DQ 8V SSA 4A 5A 6A 7A 8A 9NC UDQS NC V SS CK NC A 12V DD DQ 0V DDQ DQ 1DQ 2V SSQ DQ 3DQ 4V DDQ DQ 5DQ 6V SSQ BA 0CS RAS CAS WE LDM V DDQ DQ 7V DD A 3A 2A 1A 0AP/A 10BA 1NC LDQS NC NC NC V DDBank Address BA0~BA1Auto PrechargeA10OrganizationRow Address Column Address32Mx8A0~A12A0-A916Mx16A0~A12A0-A832Mb x 8Package Physical Demension66pin TSOPII / Package dimensionRev. 1.1 August. 2003CK, CKADDCK, CK CKE CS RAS CAS WE Data StrobeBlock Diagram (8Mb x 8 / 4Mb x 16 I/O x 4 Banks)L(U)DMRev. 1.1 August. 2003SYMBOL TYPE DESCRIPTIONCK, CK Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam-pled on the positive edge of CK and negative edge of CK. Output (read) data is referenced to both edges of CK. Internal clock signals are derived from CK/CK.CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for all functions except for disabling outputs, which is achieved asynchronously. Input buffers, excluding CK, CK and CKE are disabled dur-ing power-down and self refresh modes, providing low standby power. CKE will recognize an LVCMOS LOW level prior to VREF being stable on power-up.CS Input Chip Select : CS enables(registered LOW) and disables(registered HIGH) the command decoder. All commands are masked when CS is registered HIGH. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code.RAS, CAS, WE Input Command Inputs : RAS, CAS and WE (along with CS) define the command being entered.LDM,(UDM)Input Input Data Mask : DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0~D7 ; UDM corresponds to the data on DQ8~DQ15. DM may be driven high, low, or floating during READs.BA0, BA1Input Bank Addres Inputs : BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRE-CHARGE command is being applied.A [0 : 12]Input Address Inputs : Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the mem-ory array in the respective bank. A10 is sampled during a PRECHARGE command to deter-mine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS).A12 & A13 are used on device densities of 256Mb and greater, and A13 is used only on 1Gb decices.DQ I/O Data Input/Output : Data busLDQS,(U)DQS I/O Data Strobe : Output with read data, input with write data. Edge-aligned with read data, cen-tered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0~D7 ; UDQS corresponds to the data on DQ8~DQ15NC-No Connect : No internal electrical connection is present.VDDQ Supply DQ Power Supply : +2.6V ± 0.1V.VSSQ Supply DQ Ground.VDD Supply Power Supply : +2.6V ± 0.1V (device specific).VSS Supply Ground.VREF Input SSTL_2 reference voltage.Input/Output Function DescriptionRev. 1.1 August. 2003Command Truth Table (V=Valid, X=Don′t Care, H=Logic High, L=Logic Low)COMMAND CKEn-1CKEn CS RAS CAS WE BA0,1A10/AP A0 ~ A9,A11, A12NoteRegister Extended MRS H X L L L L OP CODE1, 2 Register Mode Register Set H X L L L L OP CODE1, 2Refresh Auto RefreshHHL L L H X3SelfRefreshEntry L3Exit L HL H H HX3H X X X3Bank Active & Row Addr.H X L L H H V Row AddressRead & Column Address Auto Precharge DisableH X L H L H VLColumnAddress4 Auto Precharge Enable H4Write & Column Address Auto Precharge DisableH X L H L L VLColumnAddress4 Auto Precharge Enable H4, 6Burst Stop H X L H H L X7Precharge Bank SelectionH X L L H LV LXAll Banks X H5Active Power Down Entry H LH X X XXL V V VExit L H X X X XPrecharge Power Down Mode Entry H LH X X XXL H H HExit L HH X X XL V V VDM(UDM/LDM for x16 only)H X X8No operation (NOP) : Not defined H X H X X XX9 L H H H91. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS)2. EMRS/MRS can be issued only at all banks precharge state.A new command can be issued 2 clock cycles after EMRS or MRS.3. Auto refresh functions are same as the CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto".Auto/self refresh can be issued only at all banks precharge state.4. BA0 ~ BA1 : Bank select addresses.If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected.If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected.6. During burst write with auto precharge, new read/write command can not be issued.Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.7. Burst stop command is valid at every burst length.8. DM(x4/8) sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0).UDM/LDM(x16 only) sampled at the rising and falling edges of the UDQS/LDQS and Data-in are masked at the both edges (Write UDM/LDM latency is 0).9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.Note :Rev. 1.1 August. 20038M x 8bit x 4 Banks / 4M x 16Bit x 4 Banks Double Data Rate SDRAMGeneral DescriptionThe K4H560838F / K4H561638F is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 / 4x 4,194,304 words by 8 / 16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequen-cies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.Absolute Maximum RatingsParameter Symbol Value Unit Voltage on any pin relative to V SS V IN, V OUT-0.5 ~ 3.6V Voltage on V DD & V DDQ supply relative to V SS V DD, V DDQ-1.0 ~ 3.6V Storage temperature T STG-55 ~ +150°CPower dissipation P D 1.5WShort circuit current I OS50mANote : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommend operation condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.DC Operating Conditions Recommended operating conditions(Voltage referenced to V SS=0V, T A=0 to 70°C) Parameter Symbol Min Max Unit Note Supply voltage(for device with a nominal V DD of 2.5V)V DD 2.5 2.75I/O Supply voltage V DDQ 2.5 2.7V5I/O Reference voltage V REF0.49*VDDQ0.51*VDDQ V1I/O Termination voltage(system)V TT V REF-0.04V REF+0.04V2 Input logic high voltage V IH(DC)V REF+0.15V DDQ+0.3VInput logic low voltage V IL(DC)-0.3V REF-0.15VInput Voltage Level, CK and CK inputs V IN(DC)-0.3V DDQ+0.3VInput Differential Voltage, CK and CK inputs V ID(DC)0.36V DDQ+0.6V3V-I Matching: Pullup to Pulldown Current Ratio VI(Ratio)0.71 1.4-4 Input leakage current I I-22uAOutput leakage current I OZ-55uAOutput High Current(Normal strengh driver) ;V OUT = V TT + 0.84V I OH-16.8mAOutput High Current(Normal strengh driver) ;V OUT = V TT - 0.84V I OL16.8mAOutput High Current(Half strengh driver) ;V OUT = V TT + 0.45V I OH-9mAOutput High Current(Half strengh driver) ;V OUT = V TT - 0.45V I OL9mANote :1.VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same.Peak-to peak noise on VREF may not exceed +/-2% of the dc value.2. V TT is not applied directly to the device. V TT is a system supply for signal termination resistors, is expected to be set equal toV REF, and must track variations in the DC level of V REF3. V ID is the magnitude of the difference between the input level on CK and the input level on CK.4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entiretemperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of themaximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0.5. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20MHz. Any noise above 20MHz at the DRAMgenerated from any source other than the DRAM itself may not exceed the DC voltage range of 2.6V +/-100mV.Rev. 1.1 August. 2003DDR SDRAM Spec Items & Test ConditionsConditions Symbol Operating current - One bank Active-Precharge;tRC=tRCmin; tCK=5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle;address and control inputs changing once every two clock cycles; CS = high between valid commands.IDD0Operating current - One bank operation ; One bank open, BL=4, Reads- Refer to the following page for detailed test condition; CS = high between valid commands.IDD1 Percharge power-down standby current; All banks idle; power - down mode; CKE = <VIL(max); tCK=5ns forDDR400; Vin = Vref for DQ,DQS and DM.IDD2P Precharge Floating standby current; CS# > =VIH(min);All banks idle; CKE > = VIH(min); tCK=5ns for DDR400;Address and other control inputs changing once per clock cycle; Vin = Vref for DQ,DQS and DMIDD2F Precharge Quiet standby current; CS# > = VIH(min); All banks idle;CKE > = VIH(min); tCK=5ns for DDR400; Address and other control inputs stable at >= VIH(min) or =<VIL(max);Vin = Vref for DQ ,DQS and DMIDD2QActive power - down standby current ; one bank active; power-down mode; CKE=< VIL (max); tCK=5nsDDR400; Vin = Vref for DQ,DQS and DMIDD3PActive standby current; CS# >= VIH(min); CKE>=VIH(min);one bank active; active - precharge; tRC=tRASmax; tCK=5ns for DDR400; DQ, DQS and DM inputs changing twiceper clock cycle; address and other control inputs changing once per clock cycleIDD3NOperating current - burst read; Burst length = 2; reads; continguous burst; One bank active; address and controlinputs changing once per clock cycle; CL=3 at 5ns for DDR400;50% of data changing on every transfer; lout = 0 mAIDD4ROperating current - burst write; Burst length = 2; writes; continuous burst;One bank active address and control inputs changing once per clock cycle; CL=3 at tCK=5ns for DDR400; DQ, DMand DQS inputs changing twice per clock cycle, 50% of input data changing at every transferIDD4W Auto refresh current; tRC = tRFC(min) - 14*tCK for DDR400 at tCK=5ns; IDD5Self refresh current; CKE =< 0.2V; External clock on; tCK = 5ns for DDR400.IDD6 Input/Output Capacitance(V DD=2.6, V DDQ=2.6V, T A= 25°C, f=1MHz) Parameter Symbol Min Max Delta Unit NoteInput capacitance(A0 ~ A12, BA0 ~ BA1, CKE, CS, RAS,CAS, WE)CIN1230.5pF4Input capacitance( CK, CK)CIN2230.25pF4Data & DQS input/output capacitance COUT450.5pF1,2,3,4Input capacitance(DM for 8, UDM/LDM for x16)CIN345pF1,2,3,41.These values are guaranteed by design and are tested on a sample basis only.2. Although DM is an input -only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins.This is required to match signal propagation times of DQ, DQS, and DM in the system.3. Unused pins are tied to ground.4. This parameteer is sampled. VDDQ = +2.6V +0.1V, VDD = +2.6V +0.1V, f=100MHz, tA=25°C, Vout(dc) =VDDQ/2, Vout(peak to peak) = 0.2V. DM inputs are grouped with I/O pins - reflecting the fact that they are matched in loading (to facilitate trace matching at the board level).Note :Rev. 1.1 August. 2003DDR SDRAM I DD spec table (V DD=2.7V, T = 10°C)Symbol32Mx8Unit Notes - CC(DDR400@CL=3)- C4(DDR400@CL=3)IDD0105100mAIDD1130130mAIDD2P44mAIDD2F3030mAIDD2Q2525mAIDD3P5555mAIDD3N7575mAIDD4R185185mAIDD4W220220mAIDD5200200mAIDD6Normal33mA Low power 1.5 1.5mA Optional IDD7A350350mASymbol16Mx16Unit Notes - CC(DDR400@CL=3)- C4(DDR400@CL=3)IDD0110105mAIDD1150145mAIDD2P44mAIDD2F3030mAIDD2Q2525mAIDD3P5555mAIDD3N7575mAIDD4R220220mAIDD4W250250mAIDD5200200mAIDD6Normal33mALow power 1.5 1.5mA Optional IDD7A380380mARev. 1.1 August. 2003< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >IDD1 : Operating current: One bank operation1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs change logic state once per Deselect cycle.Iout = 0mA2. Timing patterns- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCKSetup : A0 N N R0 N N N N P0 N NRead : A0 N N R0 N N N N P0 N N - repeat the same timing with random address changing*50% of data changing at every transferIDD7A : Operating current: Four bank operation1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on Deselet edge are not changing.Iout = 1mA2. Timing patterns- CC/C4(200Mhz,CL=3) : tCK=5ns, CL=3, BL=4, tRCD=3*tCK(CC) 4*tCK(C4), tRC=11*tCK(CC) 12*tCK(C4), tRAS=8*tCKSetup : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N NRead : A0 N A1 RA0 A2 RA1 A3 RA2 N RA3 N N - repeat the same timing with random address changing*50% of data changing at every transferLegend : A = Activate, R=Read, W=Write, P=Precharge, N=NOPRev. 1.1 August. 2003Rev. 1.1 August. 2003AC Operating ConditionsParameter/ConditionSymbol Min Max-10Unit NoteInput High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC)VREF + 0.31V Input Low (Logic 0) Voltage, DQ, DQS and DM signals.VIL(AC)VREF - 0.31V Input Differential Voltage, CK and CK inputs VID(AC)0.7VDDQ+0.6V 1Input Crossing Point Voltage, CK and CK inputsVIX(AC)0.5*VDDQ-0.20.5*VDDQ+0.2V2AC Overshoot/Undershoot specification for Address and Control PinsParameterSpecification DDR400Maximum peak amplitude allowed for overshoot 1.5V Maximum peak amplitude allowed for undershoot1.5V The area between the overshoot signal and VDD must be less than or equal to 4.5V-ns The area between the undershoot signal and GND must be less than or equal to4.5V-ns543210-1-2-3-4-50.50.68751.01.52.02.53.03.5 4.04.55.05.5 6.06.31256.57.0VDDOvershootMaximum Amplitude = 1.5VArea = 4.5V-nsMaximum Amplitude = 1.5V undershootGNDV o l t s (V )Tims(ns) AC overshoot/Undershoot DefinitionNotes :1. VID is the magnitude of the difference between the input level on CK and the input level on /CK.2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.Rev. 1.1 August. 2003Overshoot/Undershoot specification for Data, Strobe, and Mask PinsParameterSpecification DDR400Maximum peak amplitude allowed for overshoot 1.2V Maximum peak amplitude allowed for undershoot1.2V The area between the overshoot signal and VDD must be less than or equal to2.5V-ns The area between the undershoot signal and GND must be less than or equal to2.5V-ns543210-1-2-3-4-500.51.01.421.52.02.53.03.54.04.55.05.55.686.06.57.0VDDQOvershootMaximum Amplitude = 1.2VArea = 2.5V-nsMaximum Amplitude = 1.2VundershootGNDV o l t s (V )Tims(ns)DQ/DM/DQS AC overshoot/Undershoot DefinitionAC Timing Parameters and SpecificationsParameter Symbol - CC(DDR400@CL=3)- C4(DDR400@CL=3)Unit Note Min Max Min MaxRow cycle time tRC5560ns Refresh row cycle time tRFC7070ns Row active time tRAS4070K4070K ns RAS to CAS delay tRCD1518ns Row precharge time tRP1518ns Row active to Row active delay tRRD1010ns Write recovery time tWR1515ns Internal write to read command delay tWTR22tCKClock cycle time CL=3.0tCK510510ns16 CL=2.5612612nsClock high level width tCH0.450.550.450.55tCKClock low level width tCL0.450.550.450.55tCKDQS-out access time from CK/CK tDQSCK-0.55+0.55-0.55+0.55nsOutput data access time from CK/CK tAC-0.65+0.65-0.65+0.65nsData strobe edge to ouput data edge tDQSQ-0.4-0.4ns13 Read Preamble tRPRE0.9 1.10.9 1.1tCKRead Postamble tRPST0.40.60.40.6tCKCK to valid DQS-in tDQSS0.72 1.280.72 1.28tCKWrite preamble setup time tWPRES00ps5 Write preamble tWPRE0.250.25tCKWrite postamble tWPST0.40.60.40.6tCK4 DQS falling edge to CK rising-setup time tDSS0.20.2tCKDQS falling edge from CK rising-hold time tDSH0.20.2tCKDQS-in high level width tDQSH0.35 0.35 tCKDQS-in low level width tDQSL0.35 0.35 tCKAddress and Control Input setup time tIS0.60.6ns h,7~10 Address and Control Input hold time tIH0.60.6ns h,7~10 Data-out high impedence time from CK/CK tHZ- tAC max- tAC max ns3 Data-out low impedence time from CK/CK tLZ tAC min tAC max tAC min tAC max ns3 Mode register set cycle time tMRD22tCKDQ & DM setup time to DQS, slew rate 0.5V/ns tDS0.40.4ns i, j DQ & DM hold time to DQS, slew rate 0.5V/ns tDH0.40.4ns i, j DQ & DM input pulse width tDIPW 1.75 1.75ns9 Control & Address input pulse width for each input tIPW 2.2 2.2ns9 Refresh interval time tREFI7.87.8us6Output DQS valid window tQHtHP-tQHS-tHP-tQHS-ns12Clock half period tHPmintCH/tCL-mintCH/tCL-ns11, 12Rev. 1.1 August. 2003Rev. 1.1 August. 2003Component Notes1.V ID is the magnitude of the difference between the input level on CK and the input level on CK.2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the dc level of the same.3. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).4. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly.5. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.6. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.7. For command/address input slew rate ≥ 0.5 V/ns8. For CK & CK slew rate ≥ 0.5 V/ns9. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation.10. Slew Rate is measured between VOH(ac) and VOL(ac).11. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of theperiod, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces.12. tQH = tHP - tQHS, where:tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p- channel to n-channel variation of the output drivers.13. tDQSQConsists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.14. tDAL = (tWR/tCK) + (tRP/tCK)For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR400(CC) at CL=3 and tCK=5ns tDAL = (15 ns / 5 ns) + (15 ns/ 5ns) = {(3) + (3)}CLK tDAL = 6 clocks15. In all circumstances, tXSNR can be satisfied using tXSNR=tRFCmin+1*tCK16. The only time that the clock frequency is allowed to change is during self-refresh mode.ParameterSymbol - CC(DDR400@CL=3)- C4(DDR400@CL=3)Unit Note MinMax MinMax Data hold skew factortQHS 0.50.5ns 12Auto Precharge write recovery + precharge time tDAL ----ns 14Exit self refresh to non-READ command tXSNR 7575ns 15Exit self refresh to READ commandtXSRD200-200-tCKRev. 1.1 August. 2003Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew RateTable 5 : Output Slew Rate Characteristice (X8 Devices only)Table 6 : Output Slew Rate Characteristice (X16 Devices only)Table 7 : Output Slew Rate Matching Ratio CharacteristicsDelta Slew Rate tDS tDH Units Notes +/- 0.0 V/ns 00ps i +/- 0.25 V/ns +50+50ps i +/- 0.5 V/ns+100+100psiSlew Rate CharacteristicTypical Range(V/ns)Minimum (V/ns)Maximum (V/ns)Notes Pullup Slew Rate 1.2 ~ 2.5 1.0 4.5a,c,d,f,g Pulldown slew1.2 ~2.51.04.5b,c,d,f,gSlew Rate CharacteristicTypical Range(V/ns)Minimum (V/ns)Maximum (V/ns)Notes Pullup Slew Rate 1.2 ~ 2.50.7 5.0a,c,d,f,g Pulldown slew1.2 ~2.50.75.0b,c,d,f,gAC CHARACTERISTICSDDR400PARAMETERMINMAX Notes Output Slew Rate Matching Ratio (Pullup to Pulldown)--e,kSystem Characteristics for DDR SDRAMThe following specification parameters are required in systems using DDR400 devices to ensure proper system perfor-mance. these characteristics are for system simulation purposes and are guaranteed by design.Table 1 : Input Slew Rate for DQ, DQS, and DMTable 2 : Input Setup & Hold Time Derating for Slew RateTable 3 : Input/Output Setup & Hold Time Derating for Slew RateAC CHARACTERISTICSDDR400PARAMETERSYMBOL MIN MAX Units Notes DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC)DCSLEW0.54.0V/nsa, kInput Slew RatetIS tIH Units Notes 0.5 V/ns 00ps h 0.4 V/ns +500ps h 0.3 V/ns+100pshInput Slew RatetDS tDH Units Notes 0.5 V/ns 00ps j 0.4 V/ns +75+75ps j 0.3 V/ns+150+150psjSystem Notes :a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.Test pointOutput50ΩVSSQFigure 1 : Pullup slew rate test loadb. Pulldown slew rate is measured under the test conditions shown in Figure 2.VDDQ50ΩOutputTest pointFigure 2 : Pulldown slew rate test loadc. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV)Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV)Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching.Example : For typical slew rate, DQ0 is switchingFor minmum slew rate, all DQ bits are switching from either high to low, or low to high.For Maximum slew rate, only one DQ is switching from either high to low, or low to high.The remaining DQ bits remain the same as for previous state.d. Evaluation conditionsTypical : 25 °C (T Ambient), VDDQ = 2.6V, typical processMinimum : 70 °C (T Ambient), VDDQ = 2.5V, slow - slow processMaximum : 0 °C (T Ambient), VDDQ = 2.7V, fast - fast processe. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation.f. Verified under typical conditions for qualification purposes.g. TSOPII package divices only.h. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/nsas shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) orVIH(DC) to VIL(DC), similarly for rising transitions.i. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions.The delta rise/fall rate is calculated as:{1/(Slew Rate1)} - {1/(Slew Rate2)}For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps.Rev. 1.1 August. 2003。

2SK1358中文资料

MIN.
– – 900 1.5 – 2.0 – – – – – – –
TYP.
– – – – 1.1 4.0 1300 100 180 25 40 20 100
MAX.
±100 300 0 50 80 40 200
UNIT
nA µA V V Ω S pF
2sk1358 toshibatoshiba corporation 1/6 discrete semiconductors 2sk1358 field effect transistor silicon channelmos type -mosii.5) high speed, high current dc-dc converter, relay drive motordrive applications features lowdrain-source highforward transfer admittance 4.0s(typ.) lowleakage current electrostaticsensitive device. please handle care.absolute maximum ratings (ta characteristicsymbol rating unit drain-source voltage dss900 drain-gatevoltage dgr900 gate-sourcevoltage draincurrent dc dp27 drain power dissipation (tc channeltemperature ch150 storagetemperature range stg-55 thermalcharacteristics characteristic symbol max. unit thermal resistance, channel th(ch-c)0.833 thermalresistance, channel th(ch-a)50 mmindustrial applications 2/6 toshiba corporation 2sk1358 source-drain diode ratings characteristics(ta electricalcharacteristics (ta characteristicsymbol test condition min. typ. max. unit gate leakage current 100na drain cut-off current drain-sourcebreakdown voltage (br)dss 0v900 gatethreshold voltage

K9S5608V0C资料

tCH tCSTO tWHR tCHZ
RE
tDS
tDH tIR
tRSTO tRHZ
Status Output
I/O0~7
70h
tCLS
CLE
tCLS tCLH tCS
CE
tWP
WE
tCH tCEA tWHR tCHZ
RE
tDH tDS
I/O0~7 70h
tIR
tREA tRHZ
Status Output
≈
1
元器件交易网
K9S5608V0C/B K9S2808V0C/B
Revision History
Revision No
0.4
K9S6408V0C/B
SmartMediaTM
History
1. Unified access timing parameter definition for multiple operating modes - Changed AC characteristics (Before) Parameter ALE to RE Delay (ID read) ALE to RE Delay (Read cycle) RE Low to Status Output CE Low to Status Output RE access time(Read ID) - AC characteristics (After) . Deleted tRSTO, tCSTO and tREADID / Added tCLR, tCEA Parameter ALE to RE Delay (ID read) ALE to RE Delay (Read cycle) CLE to RE Delay CE Access Time Symbol tAR1 tAR2 tCLR tCEA Min 50 50 10 45 Max ns Unit Symbol tAR1 tAR2 tRSTO tCSTO tREADID Min 100 100 Max 35 45 35detailed features and specifications including FAQ, please refer to Samsung Flash web site. /Products/Semiconductor/Flash/TechnicalInfo/datasheets.htm The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office.

K4S280832O 三星 SDRAM 规格书

K4S280832OSAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE.Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind.This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or other-wise.Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.For updates or additional information about Samsung products, contact your nearest Samsung office.All brand names, trademarks and registered trademarks belong to their respective owners.ⓒ2010 Samsung Electronics Co., Ltd. All rights reserved.K4S281632O128Mb O-die SDRAM54TSOP(II) with Lead-Free & Halogen-Free (RoHS compliant)datasheetRev. 1.0 K4S280832OK4S281632O datasheet SDRAM Revision HistoryRevision No.History Draft Date Remark Editor1.0- First Spec. Release May. 2010-S.H.KimTable Of Contents128Mb O-die SDRAM1. KEY FEATURES (4)2. GENERAL DESCRIPTION (4)3. ORDERING INFORMATION (4)4. PACKAGE PHYSICAL DIMENSION (5)5. FUNCTIONAL BLOCK DIAGRAM (6)6. PIN CONFIGURATION (TOP VIEW) (7)7. INPUT/OUTPUT FUNCTION DESCRIPTION (7)8. ABSOLUTE MAXIMUM RATINGS (8)9. DC OPERATING CONDITIONS (8)10. CAPACITANCE (8)11. DC CHARACTERISTICS (x8) (9)12. DC CHARACTERISTICS (x16) (10)13. AC OPERATING TEST CONDITIONS (11)14. OPERATING AC PARAMETER (12)15. AC CHARACTERISTICS (13)16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICS (13)17. IBIS SPECIFICATION (14)18. SIMPLIFIED TRUTH TABLE (18)1. KEY FEATURES• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation• MRS cycle with address key programs-. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation • DQM (x8) & L(U)DQM (x16) for masking • Auto & self refresh• 64ms refresh period (4K Cycle)• 54pin TSOP II Lead-Free and Halogen-Free package • RoHS compliant2. GENERAL DESCRIPTIONThe K4S280832O / K4S281632O is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG ′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.3. ORDERING INFORMATION[ Table 1 ] Row & Column address configurationPart ainization Max Freq.InterfacePackageK4S280832O-LC/L7516Mb x 8 133MHz (CL=3)LVTTL54pin TSOP(II)Lead-Free & Halogen-FreeK4S280832O-LC/L6016Mb x 8 166MHz (CL=3)K4S281632O-LC/L758Mb x 16133MHz (CL=3)K4S281632O-LC/L608Mb x 16166MHz (CL=3)OrganizationRow Address Column Address16Mx8A0~A11A0-A98Mx16A0~A11A0-A84. PACKAGE PHYSICAL DIMENSIONFigure 1. 54Pin TSOP(II) Package Dimension5. FUNCTIONAL BLOCK DIAGRAMBank SelectData Input Register4M x 8 / 2M x 164M x 8 / 2M x 16Sense AMPOutput BufferI/O ControlColumn DecoderLatency & Burst Length Programming RegisterAddress RegisterRow BufferRefresh CounterRow DecoderCol. BufferLRASLCBRLCKELRASLCBRLWELDQMCLK CKE CS RAS CAS WE L(U)DQMLWE LDQMDQiCLK ADDLCAS LWCBR 4M x 8 / 2M x 164M x 8 / 2M x 16Timing Register* Samsung Electronics reserves the right to change products or specification without notice.6. PIN CONFIGURATION (TOP VIEW)7. INPUT/OUTPUT FUNCTION DESCRIPTIONPin Name Description CLK System clock Active on the positive going edge to sample all inputs.CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMCKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.A0 ~ A11Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA11,Column address : (x8 : CA0 ~ CA9), (x16 : CA0 ~ CA8)BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access.WE Write enable Enables write operation and row precharge. Latches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active.DQ0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins. (x8 : DQ0 ~ 7), (x16 : DQ0 ~ 15)V DD/V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ/V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFU No connection/reserved for future useThis pin is recommended to be left No Connection on the device.54Pin TSOP(400mil x 875mil)(0.8 mm Pin pitch)123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928V DDDQ0V DDQN.CDQ1V SSQN.CDQ2V DDQN.CDQ3V SSQN.CV DDN.CWECASRASCSBA0BA1A10/APA0A1A2A3V DDV SSDQ7V SSQN.CDQ6V DDQN.CDQ5V SSQN.CDQ4V DDQN.CV SSN.C/RFUDQMCLKCKEN.CA11A9A8A7A6A5A4V SSV DDDQ0V DDQDQ1DQ2V SSQDQ3DQ4V DDQDQ5DQ6V SSQDQ7V DDLDQMWECASRASCSBA0BA1A10/APA0A1A2A3V DDV SSDQ15V SSQDQ14DQ13V DDQDQ12DQ11V SSQDQ10DQ9V DDQDQ8V SSN.C/RFUUDQMCLKCKEN.CA11A9A8A7A6A5A4V SSx16x8x16x88. ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to V SS V IN, V OUT-1.0 ~ 4.6V Voltage on V DD supply relative to V SS V DD, V DDQ-1.0 ~ 4.6V Storage temperature T STG-55 ~ +150°C Power dissipation P D1WShort circuit current I OS50mA NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.9. DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)Parameter Symbol Min Typ Max Unit NOTE Supply voltage V DD, V DDQ 3.0 3.3 3.6VInput logic high voltage V IH 2.0 3.0V DD+0.3V1 Input logic low voltage V IL-0.300.8V2 Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL--0.4V I OL = 2mA Input leakage current I LI-10-10uA3 NOTE :1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN≤ V DDQ.Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.10. CAPACITANCE(VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)Pin Symbol Min Max Unit Clock CCLK 2.5 3.5pF RAS, CAS, WE, CS, CKE, DQM CIN 2.5 3.8pF Address CADD 2.5 3.8pF (x8 : DQ0 ~ DQ7), (x16 : DQ0 ~ DQ15) COUT 4.0 6.0pF(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)NOTE :1. Measured with outputs open.2. Refresh period is 64ms.3. K4S280832O-LC4. K4S280832O-LL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).ParameterSymbolTest ConditionVersion UnitNOTE6075Operating current (One bank active)ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA4040mA 1Precharge standby current in power-down modeICC2PCKE ≤ V IL (max), tCC = 10ns22mAICC2PS CKE & CLK ≤ V IL (max), tCC = ∞22Precharge standby current in non power-down modeICC2NCKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns1515mAICC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞Input signals are stable 1010Active standby current in power-down modeICC3PCKE ≤ V IL (max), tCC = 10ns55mA ICC3PS CKE & CLK ≤ V IL (max), tCC = ∞55Active standby current in non power-down mode (One bank active)ICC3N CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 2525mA ICC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞Input signals are stable 2020mAOperating current (Burst mode)ICC4IO = 0 mA Page burst4Banks Activated tCCD = 2CLKs 6060mA 1Refresh current ICC5tRC ≥ tRC(min)100100mA 2Self refresh currentICC6CKE ≤ 0.2VC 22mA 3L0.80.8mA4(Recommended operating condition unless otherwise noted, TA = 0 to 70°C)NOTE :1. Measured with outputs open.2. Refresh period is 64ms.3. K4S281632O-LC4. K4S281632O-LL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).ParameterSymbolTest ConditionVersion UnitNOTE6075Operating current (One bank active)ICC1 Burst length = 1 tRC ≥ tRC(min) IO = 0 mA4040mA 1Precharge standby current in power-down modeICC2PCKE ≤ V IL (max), tCC = 10ns22mAICC2PS CKE & CLK ≤ V IL (max), tCC = ∞22Precharge standby current in non power-down modeICC2NCKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns1515mAICC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞Input signals are stable 1010Active standby current in power-down modeICC3PCKE ≤ V IL (max), tCC = 10ns55mA ICC3PS CKE & CLK ≤ V IL (max), tCC = ∞55Active standby current in non power-down mode (One bank active)ICC3N CKE ≥ V IH (min), CS ≥ V IH (min), tCC = 10ns Input signals are changed one time during 20ns 2525mA ICC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), tCC = ∞Input signals are stable 2020mAOperating current (Burst mode)ICC4IO = 0 mA Page burst4Banks Activated tCCD = 2CLKs 6060mA 1Refresh current ICC5tRC ≥ tRC(min)100100mA 2Self refresh currentICC6CKE ≤ 0.2VC 22mA 3L0.80.8mA4Figure 3. AC output load circuitFigure 2. DC output load circuit13. AC OPERATING TEST CONDITIONS(V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit Input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Figure 33.3V1200Ω870ΩOutput50pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput50pFZ0 = 50Ω14. OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)NOTE : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .6. t RC = t RFC , t RDL = t WRParameterSymbol VersionUnit 6075Row active to row active delay tRRD(min)1215ns RAS to CAS delay tRCD(min)1820ns Row precharge time tRP(min)1820ns Row active time tRAS(min)4245ns tRAS(max)100us Row cycle timetRC(min)6065ns Last data in to row precharge tRDL(min)2CLK Last data in to Active delaytDAL(min) 2 CLK + tRP-Last data in to new col. address delay tCDL(min)1CLK Last data in to burst stoptBDL(min)1CLK Col. address to col. address delay tCCD(min)1CLK Number of valid output dataCAS latency=32eaCAS latency=2-115. AC CHARACTERISTICS(AC operating conditions unless otherwise noted)NOTE : 1. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.4. tSS applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.tSH applies for address setup tiem, clock enable setup time, commend setup tiem and data setup time.16. DQ BUFFER OUTPUT DRIVE CHARACTERISTICSNOTE : 1. Rise time specification based on 0pF + 50 Ω to VSS, use these values to design to.2. Fall time specification based on 0pF + 50 Ω to VDD, use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to VSS.ParameterSymbol6075Min Max Min Max CLK cycle time CAS latency=3tCC 610007.51000CAS latency=2-10CLK to valid output delay CAS latency=3tSAC 5 5.4CAS latency=2-6Output data hold timeCAS latency=3tOH 2.53CAS latency=2-3CLK high pulse width tCH 2.5 2.5CLK low pulse width tCL 2.5 2.5Input setup time tSS 1.5 1.5Input hold time tSH 10.8CLK to output in Low-Z tSLZ11CLK to output in Hi-ZCAS latency=3tSHZ5 5.4CAS latency=2-6ParameterSymbol ConditionMin TypMax Unit NOTE Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.9 5.0Volts/ns1,217. IBIS SPECIFICATION [ Table 2 ] IOH Characteristics (Pull-up)Voltage 200MHz166MHz133MHzMin200MHz166MHz133MHzMax(V)I (mA)I (mA) 3.45 -2.4 3.3 -27.3 3.0 0.0 -74.1 2.6-21.1-129.2 2.4-34.1-153.3 2.0-58.7-197.0 1.8-67.3-226.2 1.65-73.0-248.0 1.5-77.9-269.7 1.4-80.8-284.3 1.0-88.6-344.5 0.0-93.0-502.40 -100 -200 -300 -400 -500 -600030.51 1.52 2.5 3.5VoltagemAI OH Min (200MHz/166MHz/133MHz)I OH Max (200MHz/166MHz/133MHz)Figure 4. 200MHz/166MHz/133MHz Pull-upFigure 5. 200MHz/166MHz/133MHz Pull-down[ Table 3 ] IOL Characteristics (Pull-down)Voltage 200MHz 166MHz 133MHz Min 200MHz 166MHz 133MHz Max (V)I (mA)I (mA)0.0 0.0 0.00.427.5 70.2 0.6541.8107.5 0.8551.6133.81.058.0151.21.470.7187.71.572.9194.4 1.6575.4202.51.877.0208.6 1.9577.6212.03.080.3219.6 3.4581.4222.6250200150100500030.511.522.53.5Voltagem AI OL Min (200MHz/166MHz/133MHz)I OL Max (200MHz/166MHz/133MHz)Figure 6. Minimum V DD clamp current (Referenced to V DD )V DD (V)I (mA)0.0 0.00.2 0.00.4 0.00.6 0.00.7 0.00.8 0.00.9 0.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31201510500312Voltagem AI (mA)Figure 7. Minimum V SS clamp currentV SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.00.0m AI (mA)0-10-20-30-40-30-2-1-50-60Voltage18. SIMPLIFIED TRUTH TABLE(V=Valid, X=Don ′t care, H=Logic high, L=Logic low)NOTE :1. OP Code : Operand codeA0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA0 ~ BA1 : Bank select addresses.If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at tRP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)CommandCKEn-1CKEn CS RAS CAS WE DQM BA 0,1A10/AP A0 ~ A9, A11,NOTE Register Mode register set HX L L L L X OP code1,2RefreshAuto refreshH H L L L H X X 3Self refreshEntryL 3ExitL H L H H H X X3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable H X L H L H X V L Column address 4Auto precharge enable H 4,5Write &column address Auto precharge disable H X L H L L X V L Column address4Auto precharge enableH 4,5Burst stop HX L H H L X X6PrechargeBank selection H X L L H L X V L XAll banksXH Clock suspend or active power downEntry H L H X X X X XL V V V Exit L H X X X X X Precharge power down modeEntryH L H X X X XXL H H H ExitL HH X X X X LV VVDQMH X V X 7No operation commandHXH X X X XXLHHH。

K4S560832E-TC75中文资料

CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)256Mb E-die SDRAM SpecificationRevision 1.5May 2004* Samsung Electronics reserves the right to change products or specification without notice.CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)Revision HistoryRevision 1.0 (May. 2003)- First release.Revision 1.1 (June. 2003)- Correct TypoRevision 1.2 (June. 2003)- Added 166MHz speed bin in x16Revision 1.3 (September. 2003)- Corrected typo in ordering information.Revision 1.4 (February, 2004) - Corrected typo.Revision 1.5 (May, 2004)Added Note 5. sentense of tRDL parameterCMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)Part No.Orgainization Max Freq.InterfacePackageK4S560432E-TC(L)7564M x 4 133MHz (CL=3)LVTTL54pin TSOP(II)K4S560832E-TC(L)7532M x 8 133MHz (CL=3)K4S561632E-TC(L)60/7516M x 16166MHz (CL=3)The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 4 bits / 4 x 8,388,608 words by 8bits / 4 x 4,194,304 words by 16bits, fabricated with SAMSUNG's high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.• JEDEC standard 3.3V power supply • LVTTL compatible with multiplexed address • Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh• 64ms refresh period (8K Cycle)GENERAL DESCRIPTIONFEATURES16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAMOrdering InformationRow & Column address configurationOrganizationRow Address Column Address 64Mx4A0~A12A0-A9, A1132Mx8A0~A12A0-A916Mx16A0~A12A0-A8CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)54Pin TSOP(II) Package DimensionPackage Physical DimensionCMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)FUNCTIONAL BLOCK DIAGRAMLWE LDQMDQi* Samsung Electronics reserves the right to change products or specification without notice.CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)PIN CONFIGURATION (Top view)V DD N.C V DDQ N.C DQ0V SSQ N.C N.C V DDQ N.C DQ1V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/APA0A1A2A3V DD123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928V SS N.C V SSQ N.C DQ3V DDQ N.C N.C V SSQ N.C DQ2V DDQ N.C V SSN.C/RFU DQM CLK CKE A12A11A9A8A7A6A5A4V SS54Pin TSOP(400mil x 875mil)(0.8 mm Pin pitch)PIN FUNCTION DESCRIPTIONPin NameInput FunctionCLK System clock Active on the positive going edge to sample all inputs.CS Chip select Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMCKEClock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.A 0 ~ A 12AddressRow/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 12,Column address : (x4 : CA 0 ~ CA 9,CA 11), (x8 : CA 0 ~ CA 9), (x16 : CA 0 ~ CA 8)BA 0 ~ BA 1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enableEnables write operation and row tches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ 0 ~ N Data input/output Data inputs/outputs are multiplexed on the same pins.(x4 : DQ 0 ~ 3), (x8 : DQ 0 ~ 7), (x16 : DQ 0 ~ 15)V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFUNo connection/reserved for future useThis pin is recommended to be left No Connection on the device.V DD DQ0V DDQ N.C DQ1V SSQ N.C DQ2V DDQ N.C DQ3V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ7V SSQ N.C DQ6V DDQ N.C DQ5V SSQ N.C DQ4V DDQ N.C V SSN.C/RFU DQM CLK CKE A12A11A9A8A7A6A5A4V SSV DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7V DD LDQM WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SSN.C/RFU UDQM CLK CKE A12A11A9A8A7A6A5A4V SSx16x8x4x16x8x4CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C) Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA31. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)PinSymbol Min Max Unit ClockC CLK 2.5 3.5pF RAS, CAS, WE, CS, CKE, DQM C IN 2.5 3.8pF AddressC ADD2.53.8pF (x4 : DQ 0 ~ DQ 3), (x8 : DQ 0 ~ DQ 7), (x16 : DQ 0 ~ DQ 15) C OUT4.06.0pFCMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)ParameterSymbolTest ConditionVersion Unit Note75Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA80mA 1Precharge standby current in power-down mode I CC2P CKE ≤ V IL (max), t CC = 10ns 2mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞2Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns20mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 10Active standby current in power-down mode I CC3PCKE ≤ V IL (max), t CC = 10ns6mA I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞6Active standby current in non power-down mode (One bank active)I CC3N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 25mA I CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25mAOperating current (Burst mode)I CC4 I O = 0 mA Page burst4banks Activated.t CCD = 2CLKs 100mA 1Refresh current I CC5t RC ≥ t RC (min)180mA 2Self refresh currentI CC6CKE ≤ 0.2VC 3mA 3L1.5mA41. Measured with outputs open.2. Refresh period is 64ms.3. K4S5604(08)32E-TC4. K4S5604(08)32E-TL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).Notes :DC CHARACTERISTICS (x4, x8)CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)ParameterSymbolTest ConditionVersion Unit Note6075Operating current (One bank active)I CC1Burst length = 1t RC ≥ t RC (min)I O = 0 mA14090mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 2mA I CC2PS CKE & CLK ≤ V IL (max), t CC = ∞2Precharge standby current in non power-down mode I CC2N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 20mAI CC2NS CKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 10Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 6mA I CC3PS CKE & CLK ≤ V IL (max), t CC = ∞6Active standby current in non power-down mode (One bank active)I CC3N CKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns 25mA I CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25mAOperating current (Burst mode)I CC4I O = 0 mA Page burst4banks Activated.t CCD = 2CLKs 170130mA 1Refresh current I CC5t RC ≥ t RC (min)200180mA 2Self refresh currentI CC6CKE ≤ 0.2VC 3mA 3 L1.5mA41. Measured with outputs open.2. Refresh period is 64ms.3. K4S561632E-TC4. K4S561632E-TL5. Unless otherwise noticed, input swing level is CMOS(V IH /V IL =V DDQ /V SSQ ).Notes :DC CHARACTERISTICS (x16)CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit AC input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Fig. 23.3V1200Ω870ΩOutput50pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput50pFZ0 = 50Ω(Fig. 2) AC output load circuit(Fig. 1) DC output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbol VersionUnit Note 6075Row active to row active delay t RRD (min)1215ns 1RAS to CAS delay t RCD (min)1820ns 1Row precharge time t RP (min)1820ns 1Row active time t RAS (min)4245ns 1t RAS (max)100us Row cycle timet RC (min)6065ns 1Last data in to row precharge t RDL (min)2CLK 2,5Last data in to Active delayt DAL (min) 2 CLK + tRP-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stopt BDL (min)1CLK 2Col. address to col. address delay t CCD (min)1CLK 3Number of valid output dataCAS latency=32ea4CAS latency=2-11. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .Notes :CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)DQ BUFFER OUTPUT DRIVE CHARACTERISTICSParameterSymbol ConditionMin TypMax Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.9 5.0Volts/ns1,21. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to.2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to V SS .Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol 6075Unit Note Min Max Min Max CLK cycle time CAS latency=3t CC 610007.51000ns 1CAS latency=2-10CLK to valid output delay CAS latency=3t SAC 5 5.4ns 1,2CAS latency=2-6Output data hold timeCAS latency=3t OH 2.53ns 2CAS latency=2-3CLK high pulse width t CH 2.5 2.5ns 3CLK low pulse width t CL 2.5 2.5ns 3Input setup time t SS 1.5 1.5ns 3Input hold time t SH 10.8ns 3CLK to output in Low-Z t SLZ 11ns2CLK to output in Hi-ZCAS latency=3t SHZ5 5.4nsCAS latency=2-61. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Notes :CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)0-100-200-300-400-500-600030.511.522.53.5Voltagem A100MHz/133MHz Pull-upI OH Min (100MHz/133MHz)I OH Max (66 and 100MHz/133MHz)250200150100500030.511.522.53.5Voltagem A100MHz/133MHz Pull-downI OL Min (100MHz/133MHz)I OL Max (100MHz/133MHz)I OH Characteristics (Pull-up)Voltage 100MHz 133MHz Min 100MHz 133MHz Max (V)I (mA)I (mA) 3.45 -2.43.3 -27.33.0 0.0 -74.12.6-21.1-129.22.4-34.1-153.32.0-58.7-197.01.8-67.3-226.2 1.65-73.0-248.01.5-77.9-269.71.4-80.8-284.31.0-88.6-344.50.0-93.0-502.4IBIS SPECIFICATIONI OL Characteristics (Pull-down)Voltage 100MHz 133MHz Min 100MHz 133MHz Max (V)I (mA)I (mA)0.0 0.0 0.00.427.5 70.2 0.6541.8107.5 0.8551.6133.81.058.0151.21.470.7187.71.572.9194.4 1.6575.4202.51.877.0208.6 1.9577.6212.03.080.3219.6 3.4581.4222.6CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)V DD Clamp @ CLK, CKE, CS, DQM & DQV DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31V SS Clamp @ CLK, CKE, CS, DQM & DQV SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.00.0201510500312Voltagem AI (mA)Voltagem AI (mA)Minimum V DD clamp current(Referenced to V DD )Minimum V SS clamp current0-10-20-30-40-30-2-1-50-60CMOS SDRAMRev. 1.5 May 2004SDRAM 256Mb E-die (x4, x8, x16)SIMPLIFIED TRUTH TABLE (V=Valid, X=Don't care, H=Logic high, L=Logic low)CommandCKEn-1CKEnCSRASCASWEDQMBA 0,1A 10/APA 0 ~ A 9 A 11, A 12NoteRegisterMode register set H X L L L L X OP code1,2RefreshAuto refreshH H L L L H X X 3Self refreshEntry L 3ExitL H L H H H X X3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable H X L H L H X V L Column address 4Auto precharge enable H 4,5Write &column address Auto precharge disable H X L H L L X VL Column address4Auto precharge enableH 4,5Burst stop HX L H H L X X 6Precharge Bank selection H X L L H L X V L XAll banksX H Clock suspend or active power downEntry H L H X X X X XL V V V Exit L H X X X X X Precharge power down modeEntryH L H X X X XXL H H H ExitL HH X X X X L V V V DQMH X V X 7No operation commandHXH X X X XXLHHHNotes :1. OP Code : Operand codeA 0 ~ A 12 & BA 0 ~ BA 1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)。

SDRAM存储器k4s641632详细参数及说明

SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM 64Mb H-die SDRAM SpecificationRevision 1.4November 2003* Samsung Electronics reserves the right to change products or specification without notice.Rev. 1.4 November 2003SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Revision HistoryRevision 0.0 (May, 2003)• Target spec releaseRevision 0.1 (July, 2003)• Preliminary spec releaseRevision 0.2 (August, 2003)• Modified IBIS characteristic.Revision 1.0 (September, 2003)• FinalizedRevision 1.1 (September, 2003)• Corrected IBIS Specification.Revision 1.2 (October, 2003)• Deleted speed 7C at x4/x8.Revision 1.3 (October, 2003)• Deleted AC parameter notes 5.Revision 1.4 (November, 2003)• Modified Pin Function description.Rev. 1.4 November 2003SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003Part No.Orgainization Max Freq.InterfacePackageK4S640432H-TC(L)7516Mb x 4 133MHz(CL=3)LVTTL54pin TSOP(II)K4S640832H-TC(L)758Mb x 8133MHz(CL=3) K4S641632H-TC(L)604Mb x 16166MHz(CL=3) K4S641632H-TC(L)70143MHz(CL=3) K4S641632H-TC(L)75133MHz(CL=3)The K4S640432H / K4S640832H / K4S641632H is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits, / 4 x 2,097,152 words by 8 bits, / 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG ′s high perfor-mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.• JEDEC standard 3.3V power supply• LVTTL compatible with multiplexed address • Four banks operation• MRS cycle with address key programs -. CAS latency (2 & 3)-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)• All inputs are sampled at the positive going edge of the system clock• Burst read single-bit write operation• DQM (x4,x8) & L(U)DQM (x16) for masking • Auto & self refresh• 64ms refresh period (4K cycle)GENERAL DESCRIPTIONFEATURESOrdering Information4M x 4Bit x 4 / 2M x 8Bit x 4 / 1M x 16Bit x 4 Banks Synchronous DRAMSDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAM Package Physical Dimension54Pin TSOP(II) Package DimensionRev. 1.4 November 2003SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003LWE LDQMDQiSamsung Electronics reserves the right to change products or specification without notice.*SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928PIN CONFIGURATION (Top view)54Pin TSOP (II)(400mil x 875mil)(0.8 mm Pin pitch)PIN FUNCTION DESCRIPTIONPin NameInput FunctionCLK System clock Active on the positive going edge to sample all inputs.CSChip selectDisables or enables device operation by masking or enabling all inputs except CLK, CKE and DQMCKE Clock enableMasks system clock to freeze operation from the next clock cycle.CKE should be enabled at least one cycle prior to new command.Disable input buffers for power down in standby.A 0 ~ A 11AddressRow/column addresses are multiplexed on the same pins.Row address : RA 0 ~ RA 11,Column address : (x4 : CA 0 ~ CA 9, x8 : CA 0 ~ CA 8 , x16 : CA 0 ~ CA 7)BA 0 ~ BA 1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enableEnables write operation and row tches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ 0 ~ X15Data input/output Data inputs/outputs are multiplexed on the same pins.V DD /V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ /V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noise immunity.N.C/RFUNo connection/reserved for future useThis pin is recommended to be left No Connection on the device.x16x8x4x16x8x4V DD DQ0V DDQ DQ1DQ2V SSQ DQ3DQ4V DDQ DQ5DQ6V SSQ DQ7V DD LDQM WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ15V SSQ DQ14DQ13V DDQ DQ12DQ11V SSQ DQ10DQ9V DDQ DQ8V SSN.C/RFU UDQM CLK CKE N.C A11A9A8A7A6A5A4V SSV DD N.C V DDQ N.C DQ0V SSQ N.C N.C V DDQ N.C DQ1V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/APA0A1A2A3V DDV SS N.C V SSQ N.C DQ3V DDQ N.C N.C V SSQ N.C DQ2V DDQ N.C V SSN.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SSV DD DQ0V DDQ N.C DQ1V SSQ N.C DQ2V DDQ N.C DQ3V SSQ N.C V DD N.C WE CAS RAS CS BA0BA1A10/AP A0A1A2A3V DD V SS DQ7V SSQ N.C DQ6V DDQ N.C DQ5V SSQ N.C DQ4V DDQ N.C V SSN.C/RFU DQM CLK CKE N.C A11A9A8A7A6A5A4V SSSDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to V SS V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to V SS V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA31. V IH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.Notes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)PinSymbol Min Max Unit Note ClockC CLK 2.5 4.0pF 1RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0pF 2Address C ADD 2.5 5.0pF 2DQ 0 ~ DQ 3C OUT4.06.5pF31. -75 only specify a maximum value of 3.5pF2. -75 only specify a maximum value of3.8pF 3. -75 only specify a maximum value of 6.0pFNotes :SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 20031. Measured with outputs open.2. Refresh period is 64ms.3. K4S6404(08)32H-TC**4. K4S6404(08)32H-TL**5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)Notes :(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x4, x8)ParameterSymbolTest ConditionVersion Unit Note75Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA75mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 1mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞1Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns15mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mAI CC3PS CKE & CLK ≤ V IL (max), t CC = ∞3Active standby current in non power-down mode (One bank active)I CC3NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns30mAI CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25Operating current (Burst mode)I CC4 I O = 0 mA Page burst4Banks Activated t CCD = 2CLKs 115mA 1Refresh current I CC5t RC ≥ t RC (min)135mA 2Self refresh currentI CC6CKE ≤ 0.2VC 1mA 3L400uA4DC CHARACTERISTICSSDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 20031. Measured with outputs open.2. Refresh period is 64ms.3. K4S641632H-TC**4. K4S641632H-TL**5. Unless otherwise noted, input swing IeveI is CMOS(V IH /V IL =V DDQ /V SSQ)Notes :DC CHARACTERISTICS(Recommended operating condition unless otherwise noted, T A = 0 to 70°C for x16 only)ParameterSymbolTest ConditionVersionUnit Note607075Operating current (One bank active)I CC1 Burst length = 1 t RC ≥ t RC (min) I O = 0 mA140115110mA 1Precharge standby current in power-down modeI CC2P CKE ≤ V IL (max), t CC = 10ns 1mAI CC2PS CKE & CLK ≤ V IL (max), t CC = ∞1Precharge standby current in non power-down mode I CC2NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns15mAI CC2NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 6Active standby current in power-down mode I CC3P CKE ≤ V IL (max), t CC = 10ns 3mAI CC3PS CKE & CLK ≤ V IL (max), t CC = ∞3Active standby current in non power-down mode (One bank active)I CC3NCKE ≥ V IH (min), CS ≥ V IH (min), t CC = 10nsInput signals are changed one time during 20ns30mAI CC3NSCKE ≥ V IH (min), CLK ≤ V IL (max), t CC = ∞Input signals are stable 25Operating current (Burst mode)I CC4 I O = 0 mA Page burst4Banks Activated t CCD = 2CLKs 160140135mA 1Refresh current I CC5t RC ≥ t RC (min)160140135mA 2Self refresh currentI CC6CKE ≤ 0.2VC 1mA 3L400uA4SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit AC input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Fig. 23.3V1200Ω870ΩOutput30pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput30pFZ0 = 50Ω(Fig. 2) AC output load circuit(Fig. 1) DC output load circuit Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbol VersionUnit Note 607075Row active to row active delay t RRD (min)121415ns 1RAS to CAS delay t RCD (min)182020ns 1Row precharge time t RP (min)182020ns 1Row active time t RAS (min)424945ns 1t RAS (max)100us Row cycle timet RC (min)606865ns 1Last data in to row precharge t RDL (min)2CLK 2Last data in to Active delayt DAL (min) 2 CLK + tRP-Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stopt BDL (min)1CLK 2Col. address to col. address delay t CCD (min)1CLK 3Number of valid output dataCAS latency = 32ea4CAS latency = 21SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 20031. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns.If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Notes :DQ BUFFER OUTPUT DRIVE CHARACTERISTICSParameterSymbol Condition Min TypMax Unit Notes Output rise time trh Measure in linear region : 1.2V ~ 1.8V 1.37 4.37Volts/ns 3 Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3 Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.9 5.0Volts/ns1,21. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to.2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to V SS .Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol607075Unit NoteMin Max Min Max Min Max CLK cycle time CAS latency=3t CC 61000710007.51000ns 1CAS latency=2--10CLK to valid output delay CAS latency=3t SAC 56 5.4ns 1,2CAS latency=2--6Output data hold timeCAS latency=3t OH 2.533ns 2CAS latency=2--3CLK high pulse width t CH 2.53 2.5ns 3CLK low pulse width t CL 2.53 2.5ns 3Input setup time t SS 1.52 1.5ns 3Input hold time t SH 110.8ns 3CLK to output in Low-Z t SLZ111ns2CLK to output in Hi-ZCAS latency=3t SHZ56 5.4nsCAS latency=2--6SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003I OH Characteristics (Pull-up)Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.45- -1.683.30- -19.113.00-0.35 -51.872.70-3.75-90.442.50-6.65-107.311.95-13.75-137.91.80-17.75-158.341.65-20.55-173.61.50-23.55-188.791.40-26.2-199.011.00-36.25-241.150.20-46.5-351.68IBIS SPECIFICATIONI OL Characteristics (Pull-down)Voltage 133MHz Min 133MHz Max (V)I (mA)I (mA)3.4543.92155.823.30--3.0043.36153.721.9541.20148.401.8040.56146.021.6539.60141.751.5038.40136.081.4037.28131.391.0030.08105.840.8526.6493.660.6521.5275.250.4014.1649.140-100-200-300-400-500-600030.511.522.53.5Voltagem A250200150100500030.511.522.53.5Voltagem A133MHz Pull-up133MHz Pull-downI OH Min (133MHz)I OH Max (133MHz)I OL Min (133MHz)I OL Max (133MHz)SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003V DD Clamp @ CLK, CKE, CS, DQM & DQV DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31V SS Clamp @ CLK, CKE, CS, DQM & DQV SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.0 0.00.0201510500312Voltagem AI (mA)Voltagem AI (mA)Minimum V DD clamp current(Referenced to V DD )Minimum V SS clamp current0-10-20-30-40-30-2-1-50-60SDRAM 64Mb H-die (x4, x8, x16)CMOS SDRAMRev. 1.4 November 2003SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low)CommandCKEn-1CKEnCSRASCASWEDQMBA 0,1A 10/APA 11,A 9 ~ A 0NoteRegisterMode register set H X L L L L X OP code1,2RefreshAuto refreshH H L L L H X X 3Self refreshEntry L 3ExitL H L H H H X X3H X X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable H X L H L H X V L Column address (A 0 ~ A 9)4Auto precharge enable H 4,5Write &column address Auto precharge disable H X L H L L X VL Column address (A 0 ~ A 9)4Auto precharge enableH 4,5Burst stop HX L H H L X X 6Precharge Bank selection H X L L H L X V L XAll banksX H Clock suspend or active power downEntry H L H X X X X XL V V V Exit L H X X X X X Precharge power down modeEntryH L H X X X XXL H H H ExitL HH X X X X L V V V DQMH X V X 7No operation commandHXH X X X XXLHHH1. OP Code : Operand codeA 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)Notes :。

CD4538中文资料

C in Farads) s ±1.0% pulse-width variation from part to part (typ.) s Wide pulse-width range: 1 µs to ∞ s Separate latched reset inputs s Symmetrical output sink and source capability s Low standby current: 5 nA (typ.) @ 5 VDC s Pin compatible to CD4528BC
Inputs
Outputs
Clear
A
B
Q
Q
L
X
X
L
H
X
H
X
L
H
X H H
X L ↑
L
L
H
↓
H
H = HIGH Level L = LOW Level ↑ = Transition from LOW-to-HIGH
↓ = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant
© 1999 Fairchild Semiconductor Corporation DS006000.prf

元器件交易网
Block am
CD4538BC
RX and CX are External Components VDD = Pin 16 VSS = Pin 8
Ordering Code:
Order Number Package Number
Package Description

TAS5602DCA中文资料

FEATURESAPPLICATIONSDESCRIPTIONInputs2TAS5602 ......................................................................................................................................................................................................SLAS593–JUNE 200820W STEREO DIGITAL AMPLIFIER POWER STAGE•Integrated Self-Protection Circuits Including Overvoltage,Undervoltage,Overtemperature,•Supports Multiple Output Configurations and Short Circuit With Error Reporting–2×20-W into a 8-ΩBTL Load at 18V –4×10-W into a 4-ΩSE Load at 18V –2×10W (SE)+1×20W (BTL)at 18V •Flat-Panel,Rear-Projection,and CRT TV •Thermally Enhanced Package •Consumer Audio Applications–DCA (56-pin HTTSOP)•Wide Voltage Range:10V–26V–No Separate Supply Required for Gate The TAS5602is a 20-W (per channel)efficient,stereo digital amplifier power stage for driving 4Drivesingle-ended speakers,2bridge-tied speakers,or •Efficient Class-D Operation Eliminates Need combination of single and bridge-tied loads.The for Heat SinksTAS5602can drive a speaker with an impedance as •Closed Loop Power Stage Architecture low as 4Ω.The high efficiency of the TAS5602eliminates the need for an external heat sink.–Improved PSRR Reduces Power Supply Performance RequirementsA simple interface to a digital audio PWM processor –High Damping Factor Provides for Tighter,is shown below.The TAS5602is fully protected More Accurate Sound With Improved Bass against faults with short-circuit protection and thermal protection as well as overvoltage and undervoltage Responseprotection.Faults are reported back to the processor –Constant Output Power Over Variation in to prevent devices from being damaged during Supply Voltage overload conditions.•Differential InputsSIMPLIFIED APPLICATION CIRCUITPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPad is a trademark of Texas Instruments.System Two,Audio Precision are trademarks of Audio Precision,Inc.PRODUCTION DATA information is current as of publication date.Copyright ©2008,Texas Instruments IncorporatedProducts conform to specifications per the terms of the Texas Instruments standard warranty.Production processing does not necessarily include testing of all parameters.OUTA PGNDB OUTB PVCCB PVCCB BSBVCLAMP_AB BSA NC AVCC AGND BYPASS BSDVCLAMP_CD BSC PVCCC OUTC OUTC PGNDC OUTD OUTDOUTA PGNDB PGNDB OUTB PVCCC PGNDC PGNDC TAS5602SLAS593–JUNE These devices have limited built-in ESD protection.The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.DCA PACKAGE (TOP VIEW)TERMINAL FUNCTIONSTERMINALI/ODESCRIPTION 40BSD I/O Bootstrap I/O for channel D high-side FET–Internally generated voltage supply for channel C and D bootstrap.Not to be used as a supply or 39VCLAMP_CDconnected to any component other than the decoupling capacitor.38BSC I/O Bootstrap I/O for channel C high-side FET 43AVCC –Analog power supply 42AGND Analog ground8DVDD I Digital supply (3V–4.2V).Supply for PWM input signal conditioning,FAULT and RST I/O buffers 9DGND I Ground reference input for PWM and digital inputs10PWM_AP I Positive audio signal PWM input for channel A (Must be the compliment of PWM_AN)12PWM_BP I Positive audio signal PWM input for channel B (Must be the compliment of PWM_BN)14PWM_CP I Positive audio signal PWM input for channel C (Must be the compliment of PWM_CN)16PWM_DPI Positive audio signal PWM input for channel D (Must be the compliment of PWM_DN)2Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TAS5602TAS5602 ......................................................................................................................................................................................................SLAS593–JUNE2008TERMINAL FUNCTIONS(continued)TERMINAL I/O DESCRIPTIONForces the output to high impedance e this terminal to quickly(<1ms)disable the outputswitching in cases like power fail.If HIZ is tied to RESET,the volume ramps up slowly at start-up, 17HIZ–but the output switching is stopped quickly at power down.HIZ=High,normal operation.HIZ=Low,the outputs held in high impedance state.No switching at output.Enable/Disable e this terminal for pop-free start/stop.18RESET I RESET=High,normal operationRESET=Low,held in reset modeShort circuit faultFAULT=High,normal operation19FAULT O FAULT=Low,short circuit at output detected.FAULT will latch if short circuit detected and will bereset if the RESET pin is pulled low or the VCC power supplies are turned off.Thermal fault willnot be reported by the FAULT pin.20SE/BTL I Single-ended or Bridge-tied output select terminal.If any output is configured as a single-endedload,this pin should be connected to DVDD.For2-channel,BTL operation,connect to GND.Thermal warning output flag.THERM_WARN=HIGH,normal operation.21THERM_WARN OTHERM_WARN=LOW,die temperature has reached125deg.C.Automatically resets whentemperature falls back to normal range.TTL compatible push-pull output.41BYPASS O VCC/8reference for analog cells47BSB I/O Bootstrap I/O for channel B high-side FET–Internally generated voltage supply for channel A and B bootstrap.Not to be used as a supply or 46VCLAMP_ABconnected to any component other than the decoupling capacitor.45BSA I/O Bootstrap I/O for channel A high-side FET4–6PVCCA–Positive power supply for channel A output55,56OUTA O Channel A＝H-bridge output1–3PGNDA–Power ground reference for channel A output48,49PVCCB–Positive power supply for channel B output52–54PGNDB–Power ground reference for channel B output50,51OUTB O Channel B＝H-bridge output34,35OUTC O Channel C＝H-bridge output31–33PGNDC–Power ground reference for channel C output36,37PVCCC–Positive power supply for channel C output26–28PGNDD–Power ground reference for channel D output29,30OUTD O Channel D＝H-bridge output23–25PVCCD–Positive power supply for channel D output7,11,13,15,NC–No internal connection.22,44–Thermal Pad Connect to PGNDxCopyright©2008,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TAS5602ABSOLUTE MAXIMUM RATINGSDISSIPATION RATINGSRECOMMENDED OPERATING CONDITIONSTAS5602SLAS593–JUNE over operating free-air temperature range (unless otherwise noted)(1)VALUEUNIT DV DD –0.3to 5V Supply Voltage AV CC ,PV CC–0.3to 30V Input VoltageRESET,SE/BTL,PWM_xP,PWM_xN–0.3to DV DD +0.3V Operating free-air temperature,T A –40to 85°C Operating junction temperature range,T J –40to 150°C Storage temperature range,T stg –65to 150°C(1)Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.These are stress ratings only,and functional operations of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.PACKAGE (1)T A ≤25°C DERATING FACTORT A =70°C T A =85°C DCA (56pin HTSSOP) 5.5W44mW/°C3.52W2.86W(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI website at .over operating free-air temperature range (unless otherwise noted)MINNOMMAX UNITPVCCx,AVCC (minimum series inductance of 5uH 1026for full output short circuit protection)Supply voltage,V CC VPVCCx,AVCC (output is fully protected from shorts 1020with no inductance between short and terminal)Digital reference voltage DVDD3 3.3 4.2V High-level input voltage,V IH PWM_xx,RESET,SE/BTL,HIZ 2V Low-level input voltage,V IL PWM_xx,RESET,SE/BTL,HIZ 0.8V High-level output voltage,V OH FAULT,THERM_WARN,I OH =10µA DVDD–0.4VV Low-level output voltage,V OL FAULT,THERM_WARN,I OL =–10µA DGND+0.4VV PWM input frequency,f PWM PWM_xx200400kHz Operating free-air temperature,T A –4085°C R L (BTL) 6.08R L (SE)Load ImpedanceOutput filter:L=22µH,C =680nF3.24ΩR L (PBTL) 3.2Lo(BTL)10Output-filter Minimum output inductance under short-circuit Lo (SE)10µHInductanceconditionLo (PBTL)104Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TAS5602DC ELECTRICAL CHARACTERISTICS DC ELECTRICAL CHARACTERISTICS TAS5602......................................................................................................................................................................................................SLAS593–JUNE2008T A=25°C,V CC=24V,R L=8Ω(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage(measured with respect|V OS|50%duty cycle PWM at PWM_xx inputs2680mV to V CC/2for SE and output-to-output for BTL)V BYPASS V CC/8reference for analog section No load V CC/8VPWM_xx,RESET,SE/BTL,HIZ,V I=DVDD,DVDD=5I IH High-level input current5µAVI IL Low-level input current PWM_xx,RESET,SE/BTL,HIZ,V I=0,DVDD=5V5µAI DVDD DVDD supply current RESET=2.0V,DVDD=3.3V,No load2050µAI CC Quiescent supply current RESET=2.0V No load,PV CC=18V193560mAI CC(RESET)Quiescent supply current in reset mode RESET=0.8V,No load,PV CC=18V64216µAHigh side240VCC=24V,Io=500mA,T J=25°C,R DS(on)Drain-source on-state resistance Low side240mΩincludes metallization resistanceTotal480Turn-on time(SE mode),voltage on BYPASS pinC(BYPASS)=1µF,RESET=2V,SE/BTL=2V500 reaches final value of PVCC/8t ON ms Turn-on time(BTL mode),voltage on BYPASS pinC(BYPASS)=1µF,RESET=2V,SE/BTL=0.8V30 reaches final value of PVCC/8Turn-off time(SE mode),voltage on BYPASS pinC(BYPASS)=1µF,RESET=0.8V,SE/BTL=2V500 reaches final value of PVCC/8t OFF ms Turn-off time(BTL mode),voltage on BYPASS pinC(BYPASS)=1µF,RESET=0.8V,SE/BTL=0.8V1 reaches final value of PVCC/8t on/off Turn-on and turn-off time when HIZ goes low<1msT A=25°C,V CC=12V,R L=8Ω(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Class-D output offset voltage(measured with|V OS|respect to V CC/2for SE and output-to-output50%duty cycle PWM at PWM_xx inputs2680mV for BTL)V BYPASS V CC/8reference for analog section No load V CC/8VI DVDD DVDD supply current RESET=2.0V,DVDD=3.3V,No load2050µAI CC Quiescent supply current RESET=2.0V,No load142851mAI CC(RESET)Quiescent supply current in reset mode RESET=0.8V,No load64216µAHigh side240VCC=12V,Io=500mA,T J=25°C,R DS(on)Drain-source on-state resistance Low side240mΩincludes metallization resistanceTotal480Turn-on time(SE mode),voltage on BYPASSC(BYPASS)=1µF,RESET=2V,SE/BTL=2V500 pin reaches final value of PVCC/8t ON ms Turn-on time(BTL mode),voltage on BYPASSC(BYPASS)=1µF,RESET=2V,SE/BTL=0.8V30 pin reaches final value of PVCC/8t OFF Turn-off time(SE mode),voltage on BYPASSC(BYPASS)=1µF,RESET=0.8V,SE/BTL=2V500 pin reaches final value of PVCC/8ms Turn-off time(BTL mode),voltage on BYPASSC(BYPASS)=1µF,RESET=0.8V,SE/BTL=0.8V1 pin reaches final value of PVCC/8t on/off Turn-on and turn-off time when HIZ goes low<1msCopyright©2008,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):TAS5602AC ELECTRICAL CHARACTERISTICSAC ELECTRICAL CHARACTERISTICSTAS5602SLAS593–JUNE T A =25°C,V CC =24V,R L =8Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAX UNIT K SVRSupply Ripple Rejection200mV PP ripple at 20Hz–20kHz,BTL 50%–60dBduty cycle PWM at inputsBTL –R L =8Ω,THD+N =7%,f =1kHz,20V CC =18VP OContinuous output powerWSE –R L =4Ω,THD+N =10%,f =1kHz,19V CC =24VTotal Harmonic Distortion +Noise (SE)V CC =24V,f =1kHz,P O =10W 0.08%THD+NV CC =18V,R L =8Ω,f =1kHz,Total Harmonic Distortion +Noise (BTL)0.04%Po =10W (half-power)125µV 20Hz to 22kHz,A-weighted filter,BD V nOutput Integrated Noise modulation –78dBv CrosstalkPo =1W,f =1kHz–70dB Max.Output at THD+N <1%,f =1kHz,SNRSignal-to-noise ratio99dB A-weighted,V CC =18VThermal trip point (output shutdown,150°C unlatched fault)Thermal warning trip (THERM_WARN =Low)125°C Thermal hysteresis20°C T A =25°C,V CC =12V,R L =8Ω(unless otherwise noted)PARAMETERTEST CONDITIONSMINTYP MAXUNIT K SVR Supply Ripple Rejection200mV PP ripple at 20Hz–20kHz,BTL 50%–60dB duty cycle PWM at inputsBTL –R L =8Ω,THD+N =10%,f =1kHz,9.5P OContinuous output powerWSE –R L =4Ω,THD+N =10%,f =1kHz, 4.50.04Total Harmonic Distortion +Noise (SE)V CC =12V,f =1kHz,P O =2W (half-power)%THD+NV CC =12V,R L =8Ω,f =1kHz,0.07Total Harmonic Distortion +Noise (BTL)%P O =5W (half-power)125µV 20Hz to 22kHz,A-weighted filter,BD V nOutput Integrated Noise modulation –78dBv CrosstalkP O =1W,f =1kHz–70dB Max.Output at THD+N <1%,f =1kHz,SNRSignal-to-noise ratio96dB A-weightedThermal trip point (output shutdown,unlatched 150°C fault)Thermal warning trip (THERM_WARN =Low)125°C Thermal hysteresis20°C6Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TAS5602APPLICATION CIRCUITSTo PWM Modulator8W8WTAS5602 ......................................................................................................................................................................................................SLAS593–JUNE 2008Figure 1.Bridge Tied Load (BTL)Application SchematicCopyright ©2008,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TAS5602To PWM ModulatorWWTAS5602SLAS593–JUNE Figure 2.Single Ended (SE)Application Schematic8Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TAS5602TYPICAL CHARACTERISTICSf − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0010.011020k0.1G0011f − Frequency − Hz201001k10kT H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0010.011020k0.1G0021f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0010.011020k0.1G0031P O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G004TAS5602 ......................................................................................................................................................................................................SLAS593–JUNE 2008THD+N Vs.Frequency (BTL)THD+N Vs.Frequency (BTL)Figure 3.Figure 4.THD+N Vs.Frequency (BTL)THD+N Vs.Output Power (BTL)Figure 5.Figure 6.Copyright ©2008,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TAS5602P O − Output Power − W 0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G005P O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G006P O− Output Power − W 010203040506070809010005101520253035404550E f f i c i e n c y − %G008P O −T otal Output Power −W10203040I C C −S u p p l y C u r r e n t −AG009TAS5602SLAS593–JUNE TYPICAL CHARACTERISTICS (continued)Figure 7.Figure 8.Efficiency Vs.Output Power (BTL)Supply Current Vs.Total Output Power (BTL)Figure 9.Figure 10.10Submit Documentation FeedbackCopyright ©2008,Texas Instruments IncorporatedProduct Folder Link(s):TAS5602−120−100−80−60−40−20f − Frequency − HzC r o s s t a l k − d BG014201001k10k 20kV CC −Supply V oltage −V0510152025303540455010121416182022242628P O−O u t p u t P o w e r −WG010−120−100−80−60−40−200f − Frequency − HzC r o s s t a l k − d BG015201001k10k 20kf − Frequency − HzP S R R − P o w e r S u p p l y R e j e c t i o nR a t i o − d BG021201001k10k 20k−120−100−80−60−40−20Output Power Vs.Supply Voltage (BTL)Crosstalk Vs.Frequency (BTL)Figure 11.Figure 12.Crosstalk Vs.Frequency (BTL)PSRR Vs.Frequency (BTL)Figure 13.Figure 14.f − Frequency − HzP S R R − P o w e r S u p p l y R e j e c t i o n R a t i o − d BG022201001k10k 20k−120−100−80−60−40−20f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0010.011020k0.1G017110203040506070809010005101520253035404550P O − Output Power (Per Channel) − WE f f i c i e n c y − %G020P O − Output Power − W0.010.111040G018PSRR Vs.Frequency (BTL)THD+N Vs.Frequency (SE)Figure 16.Efficiency Vs.Output Power (SE)Figure 17.Figure 18.f − Frequency − HzP S R R − P o w e r S u p p l y R e j e c t i o n R a t i o − d BG025201001k10k 20k−120−100−80−60−40−20PSRR Vs.Frequency (SE)Figure 19.APPLICATION INFORMATIONCLOSED-LOOP POWER STAGE CHARACTERISTICSThe TAS5602is PWM input power stage with a closed loop architecture.A2nd order feedback loop varies the PWM output duty cycle with changes in the supply voltage.This ensures that the output voltage(and output power)remain the same over transitions in the power supply.Open-loop power stages have an output duty cycle that is equal to the input duty cycle.Since the duty cycle does NOT change to compensate for changes in the supply voltage,the output voltage(and power)change with supply voltage changes.This is undesirable effect that closed-loop architecture of the TAS5602solves.The single-ended(SE)gain of the TAS5602is fixed,and specified below:TAS5602Gain=0.13/Modulation Level(Vrms/%)Modulation level=fraction of full-scale modulation of the PWM signal at the input of the power stage.TAS5602(SE)Voltage Level(in Vrms)=0.13x Modulation LevelThe bridge-tied(BTL)gain of the TAS5602is equal to2x the SE gain:TAS5602(BTL)Voltage Level(in Vrms)=0.26x Modulation LevelFor a digital modulator like the TAS5706,the default maximum modulation limit is97.7%.For a full scale input, the PWM output switches between2.3%and97.7%.This equates to a modulation level of95.4%for a full scale input(0dBFS).For example,calculate the output voltage in RMS volts given a–20dBFS signal to a digital modulator with a maximum modulation limit of97.7%in a BTL output configuration:TAS5602Output Voltage=0.1(–20dB)x0.26(Gain)x95.4(Modulation Level)=2.48VrmsIt is also important to maintain a switching signal at the PWM inputs of the TAS5602while the terminal is held HIGH(>1.9V).If a switching signal is not maintained on the inputs under the previous condition,a loud “pop”can occur in the speaker.The TAS5602is not compatible with modulators that hard mute the outputs (output go to LOW-LOW state).For MUTE case,the modulator needs to hold outputs switching at50%duty cycle.For power-up,ensure that the PWM inputs are switching before RESET is transitioned HIGH(>1.9V).For shutdown and power-down,the PWM inputs should remain switching for the“turn-off”time specified in the DC Electrical Characteristics table.For SE mode,this is approximately500ms.For BTL mode,the time is much faster,at30ms.This ensures the best“pop”performance in the system.POWER SUPPLIESTo allow simplified system design,the TAS5602requires only a single supply(PVCC)for the power blocks and a 3.3V(DVDD)supply for PWM input blocks.In addition,the high-side gate drive is provided by built-in bootstrap circuits requiring only an external capacitor for each half-bridge.In order for the bootstrap circuit to function properly,it is necessary to connect a small ceramic capacitor from each bootstrap pin(BS_)to the corresponding output pin(OUT_).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode.When the power-stage output is high,the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate drive.DEVICE PROTECTION SYSTEMThe TAS5602contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits,overload, overtemperature,and undervoltage.TAS5602 Fault timing chartFigure20.Device Protection Flow ChartProtection Mechanisms in the TAS5602Single-Ended Output Capacitor,C OOutput Filter and Frequency Response•SCP (short-circuit protection,OCP)protects against shorts across the load,to GND,and to PVCC.•OTP turns off the device if T die (typical)>150°C.•UVP turns off the device if PVCC (typical)<8.4V •OVP turns off the device if PVCC (typical)>27.5VIn single-ended (SE)applications,the dc blocking capacitor forms a high-pass filter with the speaker impedance.The frequency response rolls of with decreasing frequency at a rate of 20dB/decade.The cutoff frequency is determined by:f c =＝πC O Z LTable 1shows some common component values and the associated cutoff frequencies:Table mon Filter ResponsesC SE –DC Blocking Capacitor (µF)Speaker Impedance (Ω)f c =60Hz (–3dB)f c =40Hz (–3dB)f c =20Hz (–3dB)46801000220083304701000For the best frequency response,a flat-passband output filter (second-order Butterworth)may be used.The output filter components consist of the series inductor and capacitor to ground at the output pins.There are several possible configurations,depending on the speaker impedance and whether the output configuration is single-ended (SE)or bridge-tied load (BTL).Table 2lists the recommended values for the filter components.It is important to use a high-quality capacitor in A rating of at least X7R is required.Table 2.Recommended Filter Output ComponentsOutput Configuration Speaker Impedance (Ω)Filter Inductor (µH)Filter Capacitor (nF)422680Single Ended (SE)8473904101500Bridge Tied Load (BTL)822680Figure 21.BTL Filter Configuration Figure 22.SE Filter ConfigurationCommon Mode ResonanceThe BTL filter shown above is an excellent,low-cost way to attenuate the high frequency energy from the Class D output stage while passing the audio signal cleanly to the speakers.However,at the resonant frequency of the LC combination,ringing can occur as a common mode output from the amplifier.This ringing can result in resonant frequency energy appearing on the speaker leads and can also cause the power dissipation in the filter L and C to increase.To keep the common mode ringing to a reasonable level,some series resistance should be designed into the circuit.Testing and simulations have shown that75mΩof series resistance in the path which includes the filter L and C is enough to control the common mode ringing.The series resistance of the filter coil and the ESR of the cap can be used to form the resistance.The copper traces in series with the filter capacitor are another good place to add some series resistance to the circuit.Another way to improve the common mode ringing is to add an RC network to ground on each output.Testing has shown that a series network consisting of100Ωand47nF is enough to damp the ringing for most speaker systems.Power-Supply Decoupling,C SThe TAS5602is a high-performance CMOS audio amplifier that requires adequate power-supply decoupling to ensure that the output total harmonic distortion(THD)is as low as possible.Power-supply decoupling also prevents oscillations for long lead lengths between the amplifier and the speaker.The optimum decoupling is achieved by using two capacitors of different types that target different types of noise on the power-supply leads. For higher-frequency transients,spikes,or digital hash on the line,a good low equivalent-series-resistance(ESR) ceramic capacitor,typically0.1µF to1µF,placed as close as possible to the device V CC lead works best.For filtering lower frequency noise signals,a larger aluminum electrolytic capacitor of220µF or greater placed near the audio power amplifier is recommended.The220-µF capacitor also serves as local storage capacitor for supplying current during large signal transients on the amplifier outputs.The PVCC terminals provide the power to the output transistors,so a220-µF or larger capacitor should be placed on each PVCC terminal.A10-µF capacitor on the AVCC terminal is adequate.These capacitors must be properly derated for voltage and ripple-current rating to ensure reliability.BSN and BSP CapacitorsThe half H-bridge output stages use only NMOS transistors.Therefore,they require bootstrap capacitors for the high side of each output to turn on correctly.A220-nF ceramic capacitor,rated for at least25V,must be connected from each output to its corresponding bootstrap input.The bootstrap capacitors connected between the BSx pins and their corresponding outputs function as a floating power supply for the high-side N-channel power MOSFET gate-drive circuitry.During each high-side switching cycle,the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs turned on.VCLAMP CapacitorTo ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded,one internal regulator clamps the gate voltage.One1-µF capacitor must be connected from each VCLAMP(terminal) to ground and must be rated for at least16V.The voltages at the VCLAMP terminal vary with V CC and may not be used for powering any other circuitry.VBYP Capacitor SelectionThe scaled supply reference(BYPASS)nominally provides an AVCC/8internal bias for the preamplifier stages. The external capacitor for this reference(C BYP)is a critical component and serves several important functions. During start-up or recovery from shutdown mode,C BYP determines the rate at which the amplifier starts.The start up time is proportional to0.5s per microfarad in single-ended mode(SE/BTL=DVDD).Thus,the recommended 1-µF capacitor results in a start-up time of approximately500ms(SE/BTL=DVDD).The second function is to reduce noise produced by the power supply caused by coupling with the output drive signal.This noise could result in degraded power-supply rejection and THD+N.The circuit is designed for a C BYP value of1µF for best pop performance.The input capacitors should have the same value.A ceramic or tantalum low-ESR capacitor is recommended.SE/BTL CONTROL PINIf the SE/BTL CONTROL pin is pulled low(tied to ground),the start-up time is typically20msec which is optimized for the bridge tied load(BTL)output configuration.If the pin is pulled high,the start-up time is controlled by the V BYP Capacitor as described in the previous section.For a value of C BYP=1µF,the start-up time is typically500msec.This gives a smooth,pop-free startup for single-ended(SE)output stages.PINThe pin can be used to immediately take the Class D output H Bridges to a Hi-Z state in the case of an unexpected power down situation.This allows the user to control the amplifier turn-off quickly if e a power supply which drops relatively quickly to pull the HIZ pin low before the PVCC reaches the UVLO voltage of 8.4V(typ.)to avoid popping at power down.RESET OPERATIONThe TAS5602employs a RESET mode of operation designed to reduce supply current(I CC)to the absolute minimum level during periods of nonuse for power conservation.The input terminal should be held high (see specification table for trip point)during normal operation when the amplifier is in use.Pulling RESET low causes the outputs to ramp to GND and the amplifier to enter a low-current state.Never leave unconnected,because amplifier operation would be unpredictable.For the best power-up pop performance,place the amplifier in the RESET mode prior to applying the power-supply voltage.USING LOW-ESR CAPACITORSLow-ESR capacitors are recommended throughout this application section.A real(as opposed to ideal)capacitor can be modeled simply as a resistor in series with an ideal capacitor.The voltage drop across this resistor minimizes the beneficial effects of the capacitor in the circuit.The lower the equivalent value of this resistance, the more the real capacitor behaves like an ideal capacitor.SHORT-CIRCUIT PROTECTIONThe TAS5602has short-circuit protection circuitry on the outputs that prevents damage to the device during output-to-output shorts and output-to-GND shorts after the filter and output capacitor(at the speaker terminal.) Directly at the device terminals,the protection circuitry prevents damage to device during output-to-output, output-to-ground,and output-to-supply.When a short circuit is detected on the outputs,the part immediately disables the output drive.Normal operation is restored once the fault is cleared by cycling the RESET pin.The FAULT will transition low when a short is detected.The FAULT pin will be cleared on the rising edge of after is cycled low to high.THERMAL PROTECTIONThermal protection on the TAS5602prevents damage to the device when the internal die temperature exceeds 150°C.There is a±15°C tolerance on this trip point from device to device.Once the die temperature exceeds the thermal set point,the device enters into the shutdown state and the outputs are disabled.This is not a latched fault.The thermal fault is cleared once the temperature of the die is reduced by20°C.The device begins normal operation at this point with no external system interaction.Thermal protection fault is NOT reported on the FAULT terminal.A terminal can be used to monitor when the internal device temperature reaches125°C.The terminal will transition low at this point and transition back high after the device cools approximately20°C.It is not necessary to cycle to clear this warning flag.。

MAX4382ESD中文资料

MAX4382ESD中⽂资料General DescriptionThe MAX4380–MAX4384 family of op amps are unity-gain-stable devices that combine high-speed perfor-mance, Rail-to-Rail ?outputs, and high-impedance disable mode. These devices operate from a +4.5V to +11V single supply or from ±2.25V to ±5.5V dual sup-plies. The common-mode input voltage range extends beyond the negative power-supply rail (ground in sin-gle-supply applications).The MAX4380–MAX4384 require only 5.5mA of quies-cent supply current per op amp while achieving a 210MHz -3dB bandwidth, 55MHz 0.1dB gain flatness and a 485V/µs slew rate. These devices are an excel-lent solution in low-power/low-voltage systems that require wide bandwidth, such as video, communica-tions, and instrumentation.The MAX4380 single with disable is available in an ultra-small 6-pin SC70 package.ApplicationsSet-Top BoxesSurveillance Video Systems Battery-Powered InstrumentsAnalog-to-Digital Converter Interface CCD Imaging SystemsVideo Routing and Switching Systems Digital Cameras Video-on-Demand Video Line DriverFeatureso Low Cost and High Speed:210MHz -3dB Bandwidth 55MHz 0.1dB Gain Flatness 485V/µs Slew Rateo Disable Mode Places Outputs in High-Impedance State o Single +4.5V to +11V Operation o Rail-to-Rail Outputso Input Common-Mode Range Extends Beyond V EE o Low Differential Gain/Phase: 0.02%/0.08°o Low Distortion at 5MHz -65dBc SFDR-63dB Total Harmonic Distortiono Ultra-Small 6-Pin SC70, 6-Pin SOT23, 10-Pin µMAX,14-Pin TSSOP, and 20-Pin TSSOP PackagesMAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and DisableTypical Operating Circuit19-2012; Rev 2; 4/03________________________________________________________________Maxim Integrated Products 1For pricing, delivery, and ordering information,please contact Maxim/Dallas Direct!at 1-888-629-4642, or visit Maxim’s website at /doc/bc7974621.html.Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and DisableABSOLUTE MAXIMUM RATINGSSupply Voltage (V CC to V EE )................................................+12V IN_-, IN_+, OUT_, DISABLE_...........(V EE - 0.3V) to (V CC + 0.3V)Output Short-Circuit to V CC or V EE ...........................................1s Continuous Power Dissipation (T A = +70°C)6-Pin SC70 (derate 3.1mW/°C above +70°C).............245mW 6-Pin SOT23 (derate 7.1mW/°C above +70°C)...........571mW 10-Pin µMAX (derate 5.6mW/°C above +70°C)..........444mW 14-Pin TSSOP (derate 9.1mW/°C above +70°C).........727mW 14-Pin SO (derate 8.3mW/°C above +70°C)...............667mW 16-Pin QSOP (derate 8.3mW/°C above +70°C)..........667mW 16-Pin Narrow SO (derate 8.7mW/°C above +70°C)..696mW 20-Pin TSSOP (derate 10.9mW/°C above +70°C).......879mW Operating Temperature Range...........................-40°C to +85°C Junction Temperature......................................................+150°C Storage Temperature Range.............................-65°C to +150°C Lead Temperature (soldering,10s).................................+300°CStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or at any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.DC ELECTRICAL CHARACTERISTICS –Single Supply(V CC = +5V, V EE = 0, V CM = V CC /2, V OUT = V CC /2, R L = ∞to V CC /2, DISABLE_= V CC(MAX4380/MAX4381/MAX4382/MAX4384),MAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable_______________________________________________________________________________________3DC ELECTRICAL CHARACTERISTICS –Single Supply(V CC = +5V, V EE = 0, V CM = V CC /2, V OUT = V CC /2, R L = ∞to V CC /2, DISABLE_= V CC(MAX4380/MAX4381/MAX4382/MAX4384), T A = T MIN to T MAX , unless otherwise noted. Typical values are at T A =+25°C.) (Note 1)M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and DisableAC ELECTRICAL CHARACTERISTICS –Single Supply(V CC = +5V, V EE = 0, V CM = +1.5V, R L = 100?to V CC /2, DISABLE_= V CC (MAX4380/MAX4381/MAX4382/MAX4384), V = V /2, A = +1V/V, T = +25°C, unless otherwise noted.)DC ELECTRICAL CHARACTERISTICS –Dual Supply (continued)(V CC = +5V, V EE = -5V, V CM = 0, V OUT = 0, R L = ∞to 0, DISABLE_= V CC (MAX4380/MAX4381/MAX4382/MAX4384), MAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable_______________________________________________________________________________________5AC ELECTRICAL CHARACTERISTICS –Single Supply (continued)Note 1:All devices are 100% production tested at T A = +25°C. Specifications over temperature limits are guaranteed by design.Note 2: PSRR for single +5V supply tested with V EE = 0, V CC = +4.5V to +5.5V; PSRR for dual ±5V supply tested with V EE = -4.5Vto -5.5V, V CC = +4.5V to +5.5V.4-6100k10M 100M1M1GSMALL-SIGNAL GAIN vs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-5-4-3-2-101234-6100k 10M 100M 1M 1G LARGE-SIGNAL GAIN vs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-5-4-3-2-101230.4-0.6100k 10M 100M 1M 1GSMALL-SIGNAL GAIN FLATNESSvs. FREQUENCYFREQUENCY (Hz)G A I N (d B )-0.5-0.4-0.3-0.2-0.100.10.20.3Typical Operating Characteristics(V CC = +5V, V EE = 0, V CM = +1.5V, A VCL = +1V/V, R L = 100?to V CC /2, T A = +25°C, unless otherwise noted.)M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable6_______________________________________________________________________________________Typical Operating Characteristics (continued)(V CC = +5V, V EE = 0, V CM = +1.5V, A VCL = +1, R L = 100?to V CC /2, T A = +25°C, unless otherwise noted.)100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40 FREQUENCY (Hz)D I S T O R T I O N (d B c )-10-100100k100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40 FREQUENCY (Hz)D I S T O R T I O N (d B c )-100-70-80-90-60-50-40-30-20-100 040020060080010001200 DISTORTION vs. RESISTIVE LOAD R LOAD (?)D I S T O R T I O N (d B c )-100-70-80-90-60-50-40-30-20-1000.51.01.52.0DISTORTION vs. VOLTAGE SWING VOLTAGE SWING (Vp-p)D I S T O R T I O N (d B c )DIFFERENTIAL GAIN AND PHASE -0.01000.0050.0150.025IRED I F F P H A SE (d e g r e e s )D I F F G A I N (%)M A X 4380-84 t o c 11IRE-0.0050.0200.010-0.040.020.040.080.1200.100.06-0.020 -100100k 10M 100M 1M 1G COMMON-MODE REJECTION vs. FREQUENCYM A X 4380-84 t o c 12 FREQUENCY (Hz)C M R (d B )-90-80-70-60-50-40-30-20-100.3-0.7 100k1M10M 100M1GLARGE-SIGNALGAIN FLATNESS vs. FREQUENCY -0.5FREQUENCY (Hz)G A I N (d B )-0.3-0.10.10-0.2-0.4-0.60.2100k10M 1M100M1GOUTPUT IMPEDANCE vs. FREQUENCYM A X 4380-84 t o c 05FREQUENCY (Hz)I M P E D A N C E (?)1000.010.1110-10-100100k100M10M1MDISTORTION vs. FREQUENCY-70-90-30-500-60-80-20-40FREQUENCY (Hz)D I S T O R T I O N (d B c )MAX4380–MAX4384Ultra-Small, Low-Cost, 200MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable_______________________________________________________________________________________7 Typical Operating Characteristics (continued)(V CC = +5V, V EE = 0, V CM = +1.5V, A VCL = +1, R L = 100?to V CC /2, T A = +25°C, unless otherwise noted.) INPUT 50mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/div A VCL = +1V/VINPUT 25mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/div R F = 500?A VCL = +2V/VINPUT 10mV/divOUTPUT 50mV/divSMALL-SIGNAL PULSE RESPONSE20ns/divR F = 500?A VCL = +5V/VINPUT 1V/divOUTPUT 1V/divLARGE-SIGNAL PULSE RESPONSE20ns/div A VCL = +1V/VINPUT 500mV/divOUTPUT 1V/divLARGE-SIGNAL PULSE RESPONSE20ns/div R F = 500?A VCL = +2V/V20ns/divINPUT 200mV/divOUTPUT 1V/divLARGE-SIGNAL PULSE RESPONSER F = 500?A VCL = +5V/V0-10-20-30-40-50-60-70-80100k10M 100M1M1G POWER-SUPPLY REJECTIONvs. FREQUENCYM A X 4380-84 t o c 13FREQUENCY (Hz)P S R (d B )0.20.10.30.60.70.50.40.80 10015020025050300350400450500OUTPUT VOLTAGE SWING vs. RESISTIVE LOADR LOAD (?)O U T P U T V O L T A G E S W I N G (V )00.40.20.61.21.41.00.81.6 10015020025050300350400450500OUTPUT VOLTAGE SWING vs. RESISTIVE LOAD R LOAD (?)O U T P U T V O L T A G E S W I N G (V )M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable Typical Operating Characteristics (continued)(V CC = +5V, V EE = 0, V CM = +1.5V, A VCL = +1, R L = 100?to V CC /2, T A = +25°C, unless otherwise noted.)0501001502002503000200100300400500600700800SMALL-SIGNAL BANDWIDTH vs. LOAD RESISTANCEM A X 4380-84 t o c 24R LOAD (?)B A N D W I D T H (M H z )8001001k 10k OPEN-LOOP GAIN vs. RESISTIVE LOAD2010R LOAD (?)O P E N -L O O P G A I N (d B )4030506070CROSSTALK vs. FREQUENCYM A X 4380-84 t o c 26FREQUENCY (Hz)C R O S S T A L K (d B )-140-80-100-120-60-40-2002040600.1M 1M 10M 100M1G110k100101k100k1M10MVOLTAGE NOISE vs. FREQUENCYFREQUENCY (Hz)110100V O L T A G E N O I S E (n V /H z )C U R R E N T N O IS E (p A /H z )110k100101k100k1M10MCURRENT NOISE vs. FREQUENCYFREQUENCY (Hz)11010091110131********20010030040050250150350450500ISOLATION RESISTANCE vs. CAPACITIVE LOADM A X 4380-84 t o c 23C LOAD (pF)R I S O (?)8_______________________________________________________________________________________ SHUTDOWN RESPONSE200ns/div5V1.5V V OUTMAX4380-84 toc27DISABLE-5-2-3-4-1012345-50-25255075100INPUT OFFSET VOLTAGE vs. TEMPERATURETEMPERATURE (°C)I N P U T O F F S E T V O L T A G E (m V )042861012-50025-255075100INPUT BIAS CURRENT vs. TEMPERATURETEMPERATURE (°C)I N P U T B I A S C U R R E N T (m A )MAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable************-50-25255075100SUPPLY CURRENT vs. TEMPERATURETEMPERATURE (°C)S U P P L Y C U R R E N T (m A )Typical Operating Characteristics (continued)(V CC = +5V, V EE = 0, V CM = +1.5V, A VCL = +1, R L = 100?to V CC /2, T A = +25°C, unless otherwise noted.)M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable10______________________________________________________________________________________The MAX4380–MAX4384 are single-supply, rail-to-rail,voltage-feedback amplifiers that employ current-feed-back techniques to achieve 485V/µs slew rates and 210MHz bandwidths. Excellent harmonic distortion and differential gain/phase performance make these ampli-fiers an ideal choice for a wide variety of video and RF signal-processing applications. Applications InformationThe output voltage swings to within 50mV of each sup-ply rail. Local feedback around the output stage ensures low open-loop output impedance to reduce gain sensitivity to load variations. The input stage per-mits common-mode voltages beyond the negative sup-ply and to within 2.25V of the positive supply rail.Unity-Gain ConfigurationThe MAX4380–MAX4384 are internally compensated for unity gain. When configured for unity gain, a 24?resistor (R F ) in series with the feedback path optimizes AC performance. This resistor improves AC response by reducing the Q of the parallel LC circuit formed by the parasitic feedback capacitance and inductance.Video Line DriverThe MAX4380–MAX4384 are low-power, voltage-feed-back amplifiers featuring bandwidths up to 210MHz,0.1dB gain flatness to 55MHz. They are designed to minimize differential-gain error and differential-phase error to 0.02% and 0.08 degrees respectively. TheyMAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable______________________________________________________________________________________11have a 16ns settling time to 0.1%, 485V/µs slew rates,and output-current-drive capability of up to 75mA making them ideal for driving video loads.Inverting and Noninverting ConfigurationsSelect the gain-setting feedback (R F ) and input (R G )resistor values to fit your application. Large resistor val-ues increase voltage noise and interact with the ampli-fier ’s input and PC board capacitance. This can generate undesirable poles and zeros and decrease bandwidth or cause oscillations. For example, a nonin-verting gain-of-two configuration (R F = R G ) using 1k ?resistors, combined with 1pF of amplifier input capaci-tance and 1pF of PC board capacitance, causes a pole at 159MHz. Since this pole is within the amplifier bandwidth, it jeopardizes stability. Reducing the 1k ?resistors to 100?extends the pole frequency to 1.59GHz, but could limit output swing by adding 200?in parallel with the amplifier ’s load resistor (Figures 1a and 1b).Layout and Power-Supply BypassingThese amplifiers operate from a single +4.5V to +11V power supply or from dual ±2.25V to ±5.5V supplies. Forsingle-supply operation, bypass V CC to ground with a 0.1µF capacitor as close to the pin as possible. If operat-ing with dual supplies, bypass each supply with a 0.1µF capacitor.Maxim recommends using microstrip and stripline techniques to obtain full bandwidth. To ensure that the PC board does not degrade the amplifier ’s perfor-mance, design it for a frequency greater than 1GHz.Pay careful attention to inputs and outputs to avoid large parasitic capacitance. Whether or not you use a constant-impedance board, observe the following design guidelines:Don ’t use wire-wrap boards; they are too inductive.Don ’t use IC sockets; they increase parasitic capaci-tance and inductance.Use surface-mount instead of through-hole compo-nents for better high-frequency performance.Use a PC board with at least two layers; it should be as free from voids as possible.Keep signal lines as short and as straight as possi-ble. Do not make 90°turns; round all corners.Rail-to-Rail Outputs, Ground-Sensing InputsFor +5V single-supply operation, the input common-mode range extends from (V EE - 200mV) to (V CC - 2.25V) with excellent common-mode rejection.Beyond this range, the amplifier output is a nonlinear function of the input, but does not undergo phase reversal or latchup.For ±5V dual-supply operation, the common-mode range is from V EE to (V CC - 2.25V)For +5V single-supply operation the output swings to within 50mV of either power-supply rail with a 2k ?load. The input ground sensing and the rail-to-rail out-put substantially increase the dynamic range. With a symmetric input in a single +5V application, the input can swing 2.95Vp-p and the output can swing 4.9Vp-p with minimal distortion.Low-Power Disable ModeThe disable feature (DISABLE_) allows the amplifier to be placed in a low-power, high-output-impedance state. When the disable pin (DISABLE_) is active, the amplifier ’s output impedance is 35k ?. This high resis-tance and the low 2pF output capacitance make the MAX4380–MAX4382 and the MAX4384 ideal in RF/video multiplexer or switch applications. For larger arrays, pay careful attention to capacitive loading.Refer to the Output Capac itive Loading and Stability section.Figure 1b. Inverting Gain ConfigurationFigure 1a. Noninverting Gain ConfigurationM A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable12______________________________________________________________________________________Output Capacitive Loading and StabilityThe MAX4380–MAX4384 are optimized for AC perfor-mance. They are not designed to drive highly reactive loads, which decrease phase margin and may produce excessive ringing and oscillation. Figure 2 shows a cir-cuit that eliminates this problem. Figure 3 is a graph of the Optimal Isolation Resistor (R S ) vs. Capacitive Load.Figure 4 shows how a capacitive load causes exces-sive peaking of the amplifier ’s frequency response if the capacitor is not isolated from the amplifier by a resistor. A small isolation resistor (usually 10?to 15?)placed before the reactive load prevents ringing and oscillation. At higher capacitive loads, AC performance is controlled by the interaction of the load capacitance and the isolation resistor. Figure 5 shows the effect of a 15?isolation resistor on closed-loop response.Chip InformationMAX4380 TRANSISTOR COUNT: 66MAX4381 TRANSISTOR COUNT: 132MAX4382 TRANSISTOR COUNT:196MAX4383 TRANSISTOR COUNT: 264MAX4384 TRANSISTOR COUNT: 264Figure 4. Small-Signal Gain vs. Frequency with Load Capacitance and No Isolation ResistorFigure 5. Small-Signal Gain vs. Frequency with Load Capacitance and 27?Isolation ResistorFigure 2. Driving a Capacitive Load Through an Isolation ResistorFigure 3. Isolation Resistance vs. Capacitive LoadMAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable______________________________________________________________________________________13Pin Configurations (continued)M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable14______________________________________________________________________________________ Package Information(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /doc/bc7974621.html/packages .)MAX4380–MAX4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and Disable______________________________________________________________________________________15Package Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /doc/bc7974621.html/packages .)Maxim c annot assume responsibility for use of any c irc uitry other than c irc uitry entirely embodied in a Maxim produc t. No c irc uit patent lic enses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.16Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-1737-76002003 Maxim Integrated ProductsPrinted USAis a registered trademark of Maxim Integrated Products.M A X 4380–M A X 4384Ultra-Small, Low-Cost, 210MHz, Single-Supply Op Amps with Rail-to-Rail Outputs and DisablePackage Information (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to /doc/bc7974621.html/packages .)。

AFND5608U1-CKAK规格书 (K9F5608)

256Mbit (32Mx8Bit)NAND FLASH256Mb NAND FLASHAFND5608U1 (/CE Don’t Don t Care mode)PreliminaryConfidential1256Mbit (32Mx8Bit)NAND FLASHRevision No. Rev.00 Initial DraftHistoryDraft Date June. 2012Remark PreliminaryPreliminaryConfidential2256Mbit (32Mx8Bit)NAND FLASHFEATURES SUMMARY• Power Supply-3.3V Device(AFND5608U1) 2.7V ~ 3.6V• Copy-Back PROGRAM Operation-Fast Page copy without external buffering• Organization-Memory Cell Array : (32M + 1024K) x 8bits -Data Register : (512 + 16) x 8bits• Command Register Operation y features • Security-OTP area, 16Kbytes(32 pages)• Automatic Program and Erase-Page Program : (512 + 16)Bytes -Block Erase : (16K +512)Bytes• Hardware Data Protection-Program / Erase locked during Power transitions• Page Read Operation-Page g Size : (512 + 16)Bytes y -Random Access : 12us(Max.) -Serial Page Access : 30ns(Min.)• Data Integrity-Endurance : 100K Program / Erase Cycles (With 1bit/528byte ECC) -Data Retention : 10 years• Fast Write Cycle Time-Program time : 200us(Typ.) -Block Erase time : 2ms(Typ.)• Package-AFND5608U1 : Pb-Free Package 48-pin TSOP(12 x 20 / 0.5 mm pitch) 48-Ball FBGA: 9.0 x 9.0 x 1.0mmPreliminaryConfidential3256Mbit (32Mx8Bit)NAND FLASHProduct InformationPart number AFND5608U1-CKAK AFND5608U1-CKCK Voltage 2.7~3.6V Bus Width x8 Package 12x20mm TSOP 9x9mm FBGAPreliminaryConfidential4256Mbit (32Mx8Bit)NAND FLASHGENERAL DESCRIPTIONThe AFND5608U1 is 256Mbit with spare 8Mbit capacity. The device is offered in 3.3V power supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. A program operation can be performed in typical 200us on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can be read out at 30ns cycle time per byte. byte The I/O pins serve as the ports for address and data input/output as well as command input. Command, data and address are synchronously introduced using /CE, /WE, ALE and CLE input pin. The output pin R/B(open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the AFND5608U1’s extended reliability of 100K program / erase cycles by providing ECC(Error Correction Code) with real time mapping-out algorithm. The chip could be offered with the /CE don’t care function. This function allows the direct download of the code form the NAND flash memory device by a microcontroller, since the /CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management : when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. Also, this device includes extra features like OTP area. The AFND5608U1 is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.PreliminaryConfidential5256Mbit (32Mx8Bit)NAND FLASHOrdering InformationAF ND XXATO Solution S l i Co. LtdXX X X X - X XX XPage Read Mode K : /CE don’t care Package Typeyp Product type ND : NAND FlashKA : 48pin-TSOP 12x20mm KC : 48ball-FBGA 9x9mm Temperature C : 0℃~70℃Generation NAND Flash Density 56 : 256Mbit Blank : 1st A : 2nd B : 3rd Classification 1 : SLC S/BNAND Flash I/O 8 : x8Operation Voltage U : 2.7~3.6VPreliminaryConfidential6256Mbit (32Mx8Bit)NAND FLASHPIN CONFIGURATION (TSOP1)PACKAGE DIMENSIONS48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)PreliminaryConfidential7256Mbit (32Mx8Bit)NAND FLASHPIN CONFIGURATION (48ball-FBGA )1 A23456WP#ALEVSSCE#WE#R/BBNCRE#CLENCNCNCCNCNCNCNCNCNCDNCNCNCNCNCNCENCNCNCNCNCNCFNCIO0NCNCNCVCCGNCIO1NCVCCIO5IO7HVSSIO2IO3IO4IO6VSSPreliminaryConfidential8256Mbit (32Mx8Bit)NAND FLASHPACKAGE OUTLINE DRAWING (48ball-FBGA 9x9mm)DescriptionFBGA 48BALLDimension9.0mm x 9.0mm x 0.90mm (Max. 1.0mm T)1. ALL DIMENSIONS are in Millimeters. 2. POST REFLOW SOLDER BALL DIAMETER. (Pre Reflow diameter : Ø0 Ø0.40 40±0.02) 0 02)PreliminaryConfidential9256Mbit (32Mx8Bit)NAND FLASHPIN DESCRIPTIONPin Name I/O0 ~ I/O7 Pin Function DATA INPUTS/OUTPUTS The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE The CLE input controls the activating path for commands sent to the command register. register When active high, commands are latched into the command register through the I/O ports on the rising edge of the /WE signal. ADDRESS LATCH ENABLE The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of /WE with ALE high CHIP ENABLE The /CE input is the device selection control. When the device is in the Busy state, /CE high is ignored, and the device does not return to standby mode in program or erase operation. Regarding /CE control during read operation, refer to ‘Page Read’ section of device operation. READ ENABLE The /RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of /RE which also increments the internal column address counter by one. WRITE ENABLE The /WE input p controls writes to the I/O p port. Commands, address and data are latched on the rising edge of the /WE pulse. WRITE PROTECT The /WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when the /WP pin is active low. READY/BUSY OUTPUT The R/B output indicates the status of the device operation. When low, it indicates that a program, erase of random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled. POWER Vcc is the power supply for device. GROUND NO CONNECTION Lead is not internally connected.CLEALE/CE/RE/WE/WPR/BVcc Vss N.CN t :C Note Connect t all ll V Vcc and dV Vss pins i of f each hd device i t to common power supply l outputs t t Do not leave Vcc or Vss disconnected.PreliminaryConfidential10256Mbit (32Mx8Bit)NAND FLASHFigure 1. AFND5608U1 FUNCTIONAL BLOCK DIAGRAMFigure 2. AFND5608U1 ARRAY ORGANIZATIONPreliminaryConfidential11NOTE : Column Address : Starting Address of the Register.00h Command(Read) : Defines the starting address of the 1st half of the register.01h Command(Read) : Defines the starting address of the 2nd half of the register.* A8 is set to “Low” or “High” by the 00h or 01h Command.* The device ignores any additional input of address cycles than required.256Mbit (32Mx8Bit)NAND FLASHPRODUCT INTRODUCTIONThe AFND5608U1 is a 264Mbits(276,824,064 bits) memory organized as 65,536 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The program and read operations are executed on a page basis while the erase operation is executed on a block operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 2,048 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the AFND5608U1.The AFND5608U1 has addresses multiplexed into 8 I/O’s. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O’s by bringing /WE to low while /CE is low. Data is latched on the rising edge of /WE. Command Latch Enable(CLE) and Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 32M byte physical space requires 24 addresses, thereby requiring three cycles for byte-level addressing : 1 cycle of column address, 2 cycles of row address, in that order. Page Read and Page Program need the same three address cycles following the required command input. In Block Erase operation, however only the 2 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the AFND5608U1.Table 1. Command SetsFunction1’st Cycle 2’nd CycleAcceptable CommandDuring BusyRead 100h/01h(1)-Read 250h -Read ID 90h -Reset FFh -oNOTE : Caution : Any undefined command inputs are prohibited except for above command set of Table 1.Page Program 80h 10h Copy Back Program 00h 8Ah Block Erase 60h D0h Read Status70h-o PreliminaryConfidential12256Mbit (32Mx8Bit)NAND FLASH ABSOLUTE MAXIMUM RATINGSParameter Symbol Rating UnitVoltage on any pin relative to Vss Vcc-0.6 to + 4.6V VIN-0.6 to + 4.6VI/O-0.6 to +4.6Temperature Under Bias TBIAS-50 to + 125˚CStorage Temperature TSTG-65 to + 150˚Cg pNOTE :1.Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to –2.0V for periods<20ns.Maximum DC voltage on input/output pins is VCC+0.3V which, during transition, may overshoot toVCC+0.2V for periods < 20ns.2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operationshould be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure top p absolute maximum rating conditions for extended periods may affect reliability.RECOMMENDED OPERATING CONDITIONS(Voltage reference to GND, AFND5608U1-CX : T A= 0 to 70℃, AFND5608U1-IX : T A= -40 to 85℃)Parameter Symbol3.3VUnit Min Typ MaxSupply Voltage Vcc 2.7 3.3 3.6V Vss000VPreliminary Confidential13256Mbit (32Mx8Bit)NAND FLASHDC AND OPERATING CHARACTERISTICSParameterSymbol Test Conditions 3.3VUnitMin Typ Max OperatingCurrentSequential Read ICC1tRC=30ns, /CE=VIL,Iout=0mA-1020mAProgram ICC2-1020EraseICC3-1020Standby Current(TTL)ISB1/CE-VIH, /WP=0V/Vcc--1Standby Current(CMOS)ISB2/CE=Vcc-0.2, /WP=0V/Vcc -1050uAInput Leakage Current ILI VIN=0 to Vcc(max)--±10Output Leakage Current ILO Vout=0 to Vcc(max)--±10Input High Volgate VIH -0.8*VCC-Vcc +03+0.3VInput Low Voltage, All inputs VIL --0.3-0.2*VCCOutput High Voltage Level VOH AFND5608U1: IOH = -400uA 2.4--Output Low Voltage Level VOL AFND5608U1: IOL = 2.1mA --0.4Output Low Current(R/B)IOLVOL=0.4V 810-mAp (/)(R/B)VALID BLOCKParameter Symbol Min Typ Max Unit Valid Block NumberNVB2,008-2,048BlocksNote :1.The device may include invalid blocks when first shipped. Additional invalid blocks may developwhile being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erasecycles with 1bit/528Byte ECC.3. Minimum 1,004 valid blocks are guaranteed for each contiguous 128Mb memory space.PreliminaryConfidential14256Mbit (32Mx8Bit)NAND FLASHAC TEST CONDITION(AFND5608U1CX:T=0to70℃AFND5608U1IX:T=40to85℃)ParameterValue AFND5608U1(3.3V)Input Pulse Levels0.4V to 2.4VInput Rise and Fall Times5nsInput and Output Timing Levels 1.5V(AFND5608U1-CX : T A= 0 to 70℃, AFND5608U1-IX : T A= -40 to 85℃)Output Load 1 TTL GATE and CL=100pF CAPACITANCE (Temp=25℃, Vcc=3.3V, f=1.0Mhz)Item Symbol Test Condition Min Typ Max Input/Output Capacitance CI/O VIL=0V-10pF Input Capacitance CIN VIN=0V-10pFMODE SELECTIONCLE ALE/CE/WE/RE/WP ModeH L L↑edge H XRead Mode Command InputL H L↑edge H X Address Input(3 clocks) NOTE: Capacitance is periodically sampled and not 100% tested.H L L↑edge H HWrite Mode Command InputL H L↑edge H H Address Input(3 clocks) L L L↑edge H H Data InputL L L H↓edge X Data OutputX X X X H X During Read(Busy)During Program(Busy) X X X X X H During Program(Busy)X X X X X H During Erase(Busy)X X X X X L Write ProtectX X H X X0V/Vcc(1)StandbyNote : 1. /WP should be biased to CMOS high or CMOS low for standby.Preliminary Confidential15256Mbit (32Mx8Bit)NAND FLASH Program / Erase CharacteristicsParameter Symbol Min Typ Max Unit Program Time tPROG-200500usNumber of Partial Program Cycles in the same page Main ArrayNop--2Cycle Spare Array--3CycleBlock Erase Time tVERS-23msAC TIMING CAHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUTParameter Symbol Min Max UnitCLE setup Time tCLS0 -nsCLE Hold Time tCLH10-ns/CE setup Time tCS0 -ns/CE Hold Time tCH10-ns//WE Pulse Width tWP(1)15-nsALE setup Time tALS0 -nsALE Hold Time tALH10-nsData setup Time tDS10-nsData Hold Time tDH5-nsW it C l Ti30Write Cycle Time tWC30 -ns/WE High Hold Time tWH10-ns Address to Data Loading Time tADL100-ns Note : 1. If tCS is set less than 10ns, tWP must be minimum 25ns, otherwise, tWP may be minimum 15ns.Preliminary Confidential16256Mbit (32Mx8Bit)NAND FLASHAC CAHARACTERISTICS FOR OPERATIONParameterSymbol Min Max Unit Data Transfer from Cell to RegistertR -12us ALE to /RE Delay tAR 10-ns CLE to /RE Delay tCLR 10-ns Ready to /RE Low tRR 20-ns RE Pulse Width tRP/ tRPB 15-ns WE High to Busy tWB -100ns Read Cycle Time tRC 30-ns /RE Access Time tREA/tREAB -18ns /CE Access Time tCEA -23ns /RE High to Output Hi-Z tRHZ -30ns /CE High to Output Hi-Z tCHZ -20ns /CE High to ALE or CLE Don’t Care tCSD 10-ns /RE or /CE High to Output holdtOH 15-ns /RE High Hold Time tREH 10-ns Output Hi-Z to /RE Low tIR 0-ns /WE High to /RE Low tWHR 50-ns ParameterSymbol Min Max Unit Last /RE High to Busy(at sequential read)tRB -100ns /CE High to Ready(in case of interception by /CE at read)tCRY -50+tr(R/B)ns /CE High Hold Time(at the last serial read)(2)/g /Device resetting time(Read/Program/Erase)tRST-5/10/500(1)us/CE High Hold Time(at the last serial read)(2)tCEH100-nsNote : 1. If reset command(FFh) is written at Ready state, the device goes into Busy for maximum 5us.2. The time to Ready depends on the value of the pull-up resistor tied R/B pin.PreliminaryConfidential17256Mbit (32Mx8Bit)NAND FLASHNAND FLASH TECHNICAL NOTESInitial Invalid Block(s)Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability isnot guaranteed by ATO. The information regarding the initial invalid block(s) is so called as the initial invalid block information.Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics. An initial invalid block(s) does not affect the performance of valid block(s)because it is isolated from the bit line and the common source line by a select transistor The block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the initial invalid block(s) address mapping. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/528Byte ECC.Identifying Initial Invalid Block(s)All device locations are erased(FFh) except locations where the initial invalid block(s) information is written prior to shipping. The initial invalid block(s) status is defined by the 6th byte in the spare area. ATO makes f sure that either the 1st or 2nd page of every initial invalid block has non-FFh data at the column address of 517. Since the initial invalid block Information is also erasable in most cases, it is impossible to recover the information once it has been erased.Therefore, the system must be able to recognize the initial invalid block(s) based on the initial invalid block information and create the initial invalid block table via the following suggested flow chart(Figure3). Any intentional erasure of the Initial invalid block information is prohibited.PreliminaryConfidentialFigure 3. Flow chart to create initial invalid block table18Error in write or read operationWithin its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the block failure rate. The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase orConfidential256Mbit (32Mx8Bit)NAND FLASH Erase Flow Chart Read Flow ChartBlock Replacement* Step1. When an error happens in the nth page of the Block ‘A’ during erase or program operation.* Step2. Copy the nth page data of the Block ‘A’ in the buffer memory to the nth page of another free block (Block ‘B) * Step3. Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ‘B’* Step4. Do not further erase Block ‘A’ by creating an ‘invalid Block’ table or other appropriate scheme.ConfidentialPointer Operation of AFND5608U1ATO NAND Flash has three address pointer commands as a substitute for the two most significant column address. ‘00h’ Command sets the pointer to ‘A’ area(0~255byte), ‘01h’ command sets the pointer to ‘B’Figure 4. Block Diagram of Pointer Operation (1) Command input sequence for programming ‘A’ area(2) Command input sequence for programming ‘B’ area(3) Command input sequence for programming ‘C’ areaPreliminary Confidential256Mbit (32Mx8Bit)NAND FLASHSystem Interface Using /CE don’t-careFor an easier system interface, /CE may be inactive during the data-loading or sequential data-reading as shown below. The internal 528bytes page registers are utilized as separate buffers for thisoperation and the system design gets more flexible. In addition, for voice or audio applications whichuse slow cycle time on the order of u-seconds, de-activating /CE during the data-loading and reading would provide significant savings in power consumption.Figure 5. Program Operation with /CE don’t careFigure 6. Read Operation with /CE don’t-carePreliminary Confidential22256Mbit (32Mx8Bit)NAND FLASH * Command Latch Cycle* Address Latch CyclePreliminary Confidential23256Mbit (32Mx8Bit)NAND FLASH * Input Data Latch Cycle* Sequential Out Cycle after Read(CLE=L, /WE=H, ALE=L)Note : Transition is measured ±200mV from steady state voltage with load.This parameter is sampled and not 100% tested.Confidential256Mbit (32Mx8Bit)NAND FLASH * Status Read Cycle (During Ready State)* Status Read Cycle (During Busy State)Preliminary Confidential25256Mbit (32Mx8Bit)NAND FLASH * READ1 OPERATION (READ ONE PAGE)* READ1 Operation (Intercepted by /CE)Preliminary Confidential26256Mbit (32Mx8Bit)NAND FLASH * READ2 Operation (Read One Page)Preliminary Confidential27256Mbit (32Mx8Bit)NAND FLASH * Page Program Operation* Copy-Back Program OperationPreliminary Confidential28256Mbit (32Mx8Bit)NAND FLASH* Block Erase Operation (Erase One Block)* Read ID OperationPreliminary Confidential 2975h 75h256Mbit (32Mx8Bit)NAND FLASH ID DEFINITION TABLE90 ID : Access command =90hValue Description1st byte9Bh Maker Code2nd byte75h Device CodeDEVICE OPERATIONDEVICE OPERATIONPAGE READUpon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with four address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than changed The528bytes of data within the selected page are transferred to the data registers in less than 12us(tR). The system controller can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. /CE must be held low while in busy for AFND5608U1, while /CE is don’t care with AFND5608U1. If /CE goes high before the device returns to Ready, the random read operation is interrupted and Busy returns to Ready as the defined by tCRY. Since the operation was aborted, the serial page read does not output valid data. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time bysequentially pulsing /RE, high to low transitions of the /RE clock output the data stating from the selected column address up to the last column address.The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area.The spare area of 512 to 527 bytes may be selectively accessed by writing the Read2 command. Address A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. The Read1command(00h/01h) is needed to move the pointer back to the main area. Figure 7 to 10 show typicalsequence and timings for each read operation.Preliminary Confidential30256Mbit (32Mx8Bit)NAND FLASH Figure 7. Read1 OperationPreliminary Confidential31256Mbit (32Mx8Bit)NAND FLASH Figure 8. Read2 OperationPreliminary Confidential32256Mbit (32Mx8Bit)NAND FLASHPAGE PROGRAMTh d i i d b i ll b i b i d ll l i l i l i f The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 bytes, in a single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 2 for main array and 3 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528bytes of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation please refer to the attached technical notes operation, please refer to the attached technical notes.The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the three cycle address input and then serial data loading. The bytes other than those to be programmed do not need to be loaded. The Page Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal write state control automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with /RE and /CE low, to read the status register. The system controller can detect thecompletion of a program cycle by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Status Bit(I/O 0) may be checked(Figure 11). The internal program verifydetects only errors for “1” s that are not successfully programmed to “0”s. The command register remains in Read Status command mode until another valid command is written to the command register.Figure 9. Program Operation g g pBLOCK ERASEThe Erase operation is done on block(16K Bytes) basis. Block address loading is accomplished in threecycles initiated by an Erase Setup command(60h). Only address A14 to A24 is valid while A9 to A13ignored. The Erase Confirm command(D0h) following the block address loading initiates the internalerasing process. This two-step sequence of setup followed by execution command ensures thatmemory contents are not accidentally erased due to external noise conditions. At the rising edge ofPreliminary Confidential /WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When the erase operation is completed, the Status Bit(I/O 0) may be checked.Figure 12 details the sequence.33256Mbit (32Mx8Bit)NAND FLASH Figure 10. Block Erase OperationCopy-Back Programpy p g p q y y p g pThe Copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without using an external memory. Since the time-consuming sequential-reading and its reloading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with “00h” command and the address of the source page moves the whole 528bytes data into the internal buffer. As soon as the device returns to Ready state, Page-Copy data-input command(8Ah) with the address cycles of destination page followed may be written. The Program Confirm command(10h) is not needed to actually begin the programming operation. For backward-compatibility, issuing Program Confirm command during copy-back does not affect correct device operation.Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the same between source and target page“When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external errorBack operations are accumulated over time bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation.”Preliminary Confidential34。

七喜研发部主板测试标准V1.0

主板型号: (板型结构\芯片组)主板测试报告Ver:1.0一、产品名称和版本：二、目的：规范主板测试的项目和步骤，确保测试质量，节约测试时间。

三、适用范围：七喜系列微机所选测的各种主板。

四、指导思想：主要测试与七喜电脑有关的软件和硬件，以确保七喜电脑的质量。

测试软件和硬件的选择要符合生产的需要。

对主板其他指标不作要求，主要参考主板厂家所提供的产品说明和技术测试报告。

___________________________测试结论：测试人员签字：日期：附：（板型结构\芯片组）主板测试数据注：1.测试前，仔细阅读红色备注。

测试后，填写报告并删除所有红色备注及附+。

如需在测试报告中添加注解，请使用蓝色字体。

2.测试中测试软件的得分仅作为参考，不作为测试是否通过的判定依据；以测试软件正常运行并取得测试分数为测试通过的判定依据。

注：1.主板芯片型号要写全，包括表示芯片版本的标识，如9903CD、SL3P7……。

在备注中注明北桥是否有散热片。

2.防火等级从高到低为5V、V-0、V-1，板上的94v-0标识等同于UL认证3.向厂家要求提供证书。

4.主要功放芯片有TL071、TL072、TL074、LM78L、AD8532……，如没有功放，填“无”。

5.请标注跳线位置、序号.6.标注集成显示卡AGP类型，速度7.测试最初版本与最终确认版本8.所支持CPU的STEPING版本9.主板上的ATX20PIN，3.3/12V 6PIN，12V 4PIN，WOL，AOL电源提供口，FAN电源及其他电源接口数量10前置Audio、USB注跳线位置11功能键、功能灯注明是几键几灯注：BIOS测试项目可根据具体情况，进行相关项目的测试。

该测试规范测试BIOS的项目仅供参考。

全部的BIOS可正常更改项目要求确认实现该项目相应完成功能。

针对不同应用范围的主板，测试通知将详细表述BIOS要求。

注：如有其它功能键、功能灯请注明，并进行相关的测试。

K4C560838C-LCD3资料

K4C5608/1638F 256Mb Network-DRAM 256Mb Network-DRAM SpecificationVersion 0.3- 1 -K4C5608/1638F 256Mb Network-DRAM Revision HistoryVersion 0.0 (Dec./ 2003)- First ReleaseVersion 0.1 (Aug./ 2004)- Deleted BL2 and self refreshVersion 0.2 (Nov./ 2004)- Added current value in page 10Version 0.3 (Jan./ 2005)- Modified current value in page 10- 2 -K4C5608/1638F 256Mb Network-DRAM- 3 -General InformationOrganization D4 (400Mbps) DA (366Mbps )D3 (333Mbps )256Mx8K4C560838F-TCD4K4C560838F-TCDA K4C560838F-TCD3256Mx16K4C561638F-TCD4K4C561638F-TCDAK4C561638F-TCD3T : TSOP II (400mil x 875mil)D4 : 400bps/pin (200MHz, CL=4) DA : 366bps /pin (183MHz, CL=4) D3 : 333bps/pin (167MHz, CL=4)C : (Commercial, Normal)08 : x8 16 : x1656 : 256M 8K/64msC : Network-DRAM C : 4th GenerationK 4 C XX XX X X X - X X Memory DRAMSmall Classification Density and Refresh Temperature & PowerPackage Organization VersionInterface (VDD & VDDQ)1. SAMSUNG Memory : K2. DRAM : 43. Small Classification4. Density & Refresh5. Organization 8. Version9. Package10. Temperature & Power 11. Speed3 :4 Bank 6. Bank1 2 3 4 5 6 7 8 9 10 11XX8: SSTL-2(2.5V, 2.5V)7. Interface (VDD & VDDQ) SpeedBankK4C5608/1638F 256Mb Network-DRAM- 4 -• Fully Synchronous Operation Double Data Rate (DDR)Data input/output are synchronized with both edges of DQS. Differential Clock (CK and CK)inputsCS, FN and all address input signals are sampled on the positive edge of CK. Output data (DQs and DQS) is referenced to the crossings of CK and CK.• Fast clock cycle time of 5ns minimum Clock : 200MHz maximum Data : 400Mbps/pin maximum • Quad independent banks operation • Fast cycle and short Iatency • Bidirectional data strobe signal• Distributed Auto-Refresh cycle in 7.8us • Power Down Mode• Variable Write Length Control • Write Latency = CAS Latency - 1• Programmable CAS Latency and Burst Length CAS Latency = 3, 4 Burst Length = 4• Organization K4C561638F-TC : 4,194,304 words x4 banks x 16 K4C560838F-TC : 8,388,608 words x4 banks x 8• Power supply voltage Vdd : 2.5 ± 0.15V VddQ : 2.5 ± 0.15V• 2.5V CMOS I/O comply with SSTL-2 (Strong / Normal / Weaker / Weakest)• Package 400X875mil, 66pin TSOP II, 0.65mm pin pitch (TSOP II 66-P-400-0.65)ItemK4C560838/1638F-TCD4 (400Mbps)DA (366Mbps)D3 (333Mbps)t CK Clock Cycle Time (Min.)CL=3 5.5ns 6ns 6.5ns CL=45ns 5.5ns 6ns t RC Random Read/Write Cycle Time (Min.)25ns 27.5ns 30ns t RAC Random Access Time (Max.)22ns 24ns 26ns I DD1S Operating Current (Single bank) (Max.)T.B.D T.B.D T.B.D I DD2P Power Down Current (Max.)T.B.DT.B.DT.B.DKey FeatureK4C5608/1638F 256Mb Network-DRAM- 5 -Pin NamesPinNameA0 to A14Address Input BA0, BA1Bank AddressDQ0 to DQ7 (x8)Data Input/Output DQ0 to DQ15 (x16)CS Chip Select FN Function Control PD Power Down Control CK, (CK)Clock InputDQS (X8)Write/Read Data Strobe UDQS/LDQS (X16)Vdd Power(+2.5V)Vss Ground VddQ Power (+2.5V)(for I/O buffer)VssQ Ground(for I/O buffer)V REF Reference Voltage NC1,NC2No Connection123456789101112131415161718192021222324252627282930313233666564636261605958575655545352515049484746454443424140393837363534400mil Width 875mil Length66Pin TSOP II0.65mm Lead PitchVdd Vdd DQ0 DQ0VddQ VddQ DQ1 NC 2DQ2 DQ1VssQ VssQ DQ3 NC 2DQ4 DQ2VddQ VddQ DQ5 NC 2DQ6 DQ3VssQ VssQ DQ7 NC 2NC 1 NC 1VddQ VddQ LDQS NC 2NC 1 NC 1Vdd Vdd NC 1 NC 1NC 2 NC 2A14 A14A13 A13FN FN CS CS NC 1 NC 1BA0 BA0BA1 BA1A10 A10A0 A0A1 A1A2 A2A3 A3Vdd VddVss Vss DQ7 DQ15VssQ VssQ NC 2 DQ14DQ6 DQ13VddQ VddQ NC 2 DQ12DQ5 DQ11VssQ VssQ NC 2 DQ10DQ4 DQ9VddQ VddQ NC 2 DQ8NC 1 NC 1VssQ VssQ DQS UDQS NC 1 NC 1VREF VREF Vss Vss NC 2 NC 2CK CK CK CK PD PD NC 1 NC 1A12 A12A11 A11A9 A9A8 A8A7 A7A6 A6A5 A5A4 A4Vss VssK4C561638F-TC K4C560838F-TCPin Assignment (Top View)K4C5608/1638F 256Mb Network-DRAM- 6 -Package Outline Drawing (TSOP II 66-P-400-0.65)Unit in mmK4C5608/1638F 256Mb Network-DRAM- 7 -Block DiagramCK CK DLL CLOCK BUFFERCOMMAND DECODERCS FNCONTROL GENERATORSIGNAL ADDRESS BUFFERMODEREGISTERUPPER ADDRESS LATCHLOWER ADDRESS LATCHCOLUMN DECODERR O W D E C O D E RBANK #3BANK #2BANK #1BANK #0MEMORY CELL ARRAYD A T A C O N T R O L A N D L A T C H C I R C U I TBURST COUNTERREAD DATA BUFFERWRITE DATA BUFFERDQ BUFFER A0 to A14BA0, BA1REFRESH COUNTERWRITE ADDRESSLATCH ADDRESS COMPARATORDQSDQ0 to DQnTo Each BlockNote : The K4C560838F-TC configuration is 4 Bank of 32768X256X 8 of cell array with the DQ pins numbered DQ0-7 The K4C561638F-TC configuration is 4 BanK of 32768X128X16 of cell array with the DQ pins numbered DQ0-15.K4C5608/1638F 256Mb Network-DRAM Absolute Maximum RatingsSymbol Parameter Rating Units NotesVdd Power Supply Voltage-0.3 to 3.3VVddQ Power Supply Voltage (for I/O buffer)-0.3 to Vdd + 0.3VV IN Input Voltage-0.3 to Vdd + 0.3VV OUT DQ pin Voltage-0.3 to VddQ + 0.3VV REF Input Reference Voltage-0.3 to Vdd + 0.3VT OPR Operating Temperature0 to 70O CT STG Storage Temperature-55 to 150O CT SOLDER Soldering Temperature(10s)260O CP D Power Dissipation1WI OUT Short Circuit Output Current± 50mACaution : Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device.The device is not meant to be operated under conditions outside the limits described in the operational section of this specifi-cation. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability. Recommanded DC,AC Operating Conditions (Notes : 1) (Ta = 0 to 70 ×°C) Symbol Parameter Min Typ Max Units Notes Vdd Power Supply Voltage 2.35 2.5 2.65VVddQ Power Supply Voltage (for I/O Buffer) 2.35 2.5 2.65VV REF Input Reference Voltage VddQ/2*96%VddQ/2VddQ/2*104%V2 V IH (DC)Input DC high Voltage V REF+0.2-VddQ+0.2V5 V IL(DC)Input DC Low Voltage-0.1-V REF-0.2V5 V ICK (DC)Differential Clock DC Input Voltage-0.1-VddQ+0.1V10 V ID (DC)Input Differential Voltage. CK and CK Inputs (DC)0.4-VddQ+0.2V7,10 V IH (AC)Input AC High Voltage V REF+0.35 -VddQ+0.2V3,6 V IL (AC)Input AC Low Voltage-0.1-V REF-0.35V4,6 V ID (AC)Input Differential Voltage. CK and CK Inputs (AC)0.7-VddQ+0.2V7,10 V X (AC)Differential AC Input Cross Point Voltage VddQ/2-0.2-VddQ/2+0.2V8,10 V ISO (AC)Differential Clock AC Middle Level VddQ/2-0.2-VddQ/2+0.2V9,10- 8 -K4C5608/1638F 256Mb Network-DRAM- 9 -1. All voltages are referenced to Vss, VssQ.2. V REF is expected to track variations in VddQ DC level of the transmitting device. Peak to peak AC noise on V REF may not exceed ± 2% of V REF (DC).3. Overshoot Iimit : V IH (max.) = VddQ + 0.9V with a pulse width <= 5ns4. Undershoot Iimit : V IL (min.) = -0.9V with a pulse width <= 5ns5. V IH (DC) and V IL (DC) are levels to maintain the current logic state.6. V IH (AC) and V IL (AC) are levels to change to the new logic state.7. V ID is magnitude of the difference between CK input level and CK input level. 8. The value of Vx(AC) is expected to equal VddQ/2 of the transmitting device. 9. V ISO means [V ICK (CK) + V ICK 10. Refer to the figure below.Notes :11. In the case of external termination, VTT(Termination Voltage) should be gone in the range of V REF (DC) ± 0.04V.Pin Capacitance (Vdd, VddQ = 2.5V, f = 1MHz, Ta = 25×°C )Note : These parameters are periodically sampled and not 100% tested.2 The NC 2 pins have additional capacitance for adjustment of the adjacent pin capacitance. 1 The NC 2 pins have Power and Ground clamp.Symbol ParameterMin Max Units C IN Input Pin Capacitance2.5 4.0pF C INC Clock Pin (CK, CK) Capacitance 2.5 4.0pF C I/O I/O Pin (DQ, DQS) Capacitance3.0 6.0pF C NC 1NC1 Pin Capacitance - 1.5pF C NC 2NC2 Pin Capacitance4.06.0pFCLKV SS V ID (AC)0 V DifferentialV ISO VSSV ID (AC)K4C5608/1638F 256Mb Network-DRAM- 10 -DC Characteristics and Operating Conditions (Vdd, VddQ = 2.5V ± 0.15V, Ta = 0~70×°C )Notes : 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of t CK , t RC and I RC . 2. These parameters depend on the output loading. The specified values are obtained with the output open.3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.ItemSymbolMaxUnits NotesD4(400Mbps)DA(366Mbps)D3(333Mbps)Operating Current t CK = min, I RC =minRead/Write command cyclingOV<=V IN <=V IL(AC) (max.) V IH(AC)(min.) <=V IN <=VddQ 1 bank operation, Burst Length = 4Address change up to 2 times during minimum I RC .I DD1S 300290280mA1, 2Standby Currentt CK =min, CS = V IH , PD = V IH ,0V<=V IN <=V IL(AC)(max.) V IH(AC)(min.)<=V IH <=VddQ All Banks : inactive stateOther input signals are changed one time during 4*t CK I DD2N 10095901Standby (Power Down) Currentt CK =min, CS = V IH , PD = V IL (Power Down)0V<=V IN <=VddQAll Banks : inactive stateI DD2P 4545401Auto-Refresh Currentt CK = min, I REFC = min, t REFI = min Auto-Refresh command cycling0V<=V IN <=V IL (AC) (max.), V IH (AC) (min.) <=V IN <=VddQ Address change up to 2 times during minimum I REFC .I DD51051051001ItemSymbolMinMaxUnitNotesInput Leakage Current(0V<=V IN <=VddQ, All other pins not under test = 0V)I LI -55uA Output Leakage Current(Output disabled, 0V<=V OUT <=VddQ)I LO -55uA V REF CurrentI REF -55uANormal Output DriverOutput Source DC Current V OH = VddQ - 0.4V I OH (DC)-10-mA3Output Sink DC Current V OL =0.4VI OL (DC)10-3Strong Output DriverOutput Source DC Current V OH = VddQ - 0.4V I OH (DC)-11-3Output Sink DC Current V OL =0.4VI OL (DC)11-3Weaker Output DriverOutput Source DC Current V OH = VddQ - 0.4V I OH (DC)-8-3Output Sink DC Current V OL =0.4VI OL (DC)8-3Weakest Output DriverOutput Source DC Current V OH = VddQ - 0.4V I OH (DC)-7-3Output Sink DC Current V OL =0.4VI OL (DC)7-3K4C5608/1638F 256Mb Network-DRAM- 11 -AC Characteristics and Operating Conditions (Notes : 1, 2)SymbolItemD4(400Mbps)DA(366Mbps)D3(333Mbps)Units NotesMinMaxMinMaxMinMaxt RC Random Cycle Time 25-27.5-30-ns3t CK Clock Cycle Time CL = 3 5.57.567.5 6.57.53CL = 457.5 5.57.567.53t RAC Random Access Time -22-24-263t CH Clock High Time 0.45*t CK -0.45*t CK -0.45*t CK -3t CL Clock Low Time0.45*t CK -0.45*t CK -0.45*t CK -3t CKQS DQS Access Time from CLK -0.650.65-0.750.75-0.850.853, 8t QSQ Data Output Skew from DQS -0.4-0.45-0.54t AC Data Access Time from CLK -0.650.65-0.750.75-0.850.853, 8t OH Data Output Hold Time from CLK -0.650.65-0.750.75-0.850.853, 8t QSPRE DQS(Read) Preamble Pulse Width 0.9*t CK -0.2 1.1*t CK +0.20.9*t CK -0.2 1.1*t CK +0.20.9*t CK -0.2 1.1*t CK +0.23t HP CLK half period ( minium of Actual t CH , t CL )min(t CH , t CL )-min(t CH , t CL )-min(t CH , t CL )-t QSP DQS(Read) Pulse Widtht HP -0.55-t HP -0.6-t HP -0.65-4t QSQV Data Output Valid Time from DQS t HP -0.55-t HP -0.6t HP -0.65-4t DQSS DQS(Write) Low to High Setup Time 0.75*t CK 1.25*t CK0.75*t CK 1.25*t CK0.75*t CK 1.25*t CK3t DSPREDQS(Write) Preamble Pulse Width0.4*t CK-0.4*t CK-0.4*t CK-4t DSPRES DQS First Input Setup Time 0-0-0-3t DSPREH DQS First Low Input Hold Time 0.25*t CK -0.25*t CK -0.25*t CK -3t DSP DQS High or Low Input Pulse Width 0.45*t CK0.55*t CK0.45*t CK 0.55*t CK0.45*t CK 0.55*t CK4t DSS DQS Input Falling Edge to Clock Setup Time CL = 3 1.3- 1.4- 1.5-3, 4CL = 41.3- 1.4-1.5-3, 4t DSPSTDQS(Write) Postamble Pulse Width0.45*t CK-0.45*t CK 0.45*t CK-4t DSPSTH DQS(Write) Postamble Hold Time CL = 3 1.3- 1.4- 1.5-3, 4CL = 41.3- 1.4- 1.5-3, 4t DSSK UDQS - LDQS Skew (x16)-0.5*t CK 0.5*t CK-0.5*t CK 0.5*t CK-0.5*t CK 0.5*t CKt DS Data Input Setup Time from DQS 0.5-0.5-0.6-4t DH Data Input Hold Time from DQS 0.5-0.5-0.6-4t DIPW Data Input pulse Width (for each device) 1.5- 1.5- 1.9-t IS Command / Address Input Setup Time 0.9-0.9-1-3t IH Command / Address Input Hold Time0.9-0.9-1-3t IPW Command / Address Input Pulse Width (for each device) 2.0- 2.0- 2.2-t LZ Data-out Low Impedance Time from CLK -0.65--0.75--0.85-3, 6, 8t HZ Data-out High Impedance Time from CLK -0.65-0.75-0.853, 7, 8t QSLZ DQS-out Low Impedance Time from CLK -0.65--0.75--0.85-3, 6, 8t QSHZ DQS-out High Impedance Time from CLK -0.650.65-0.750.75-0.850.853, 7, 8t QPDH Last Output to PD High Hold Time 0-0-0-t PDEX Power Down Exit Time 2-2-2-3t T Input Transition Time0.110.110.11t FPDLPD Low Input Window for Self-Refresh Entry-0.5*t CK5-0.5*t CK5-0.5*t CK53K4C5608/1638F 256Mb Network-DRAM- 12 -AC Characteristics and Operating Conditions (Notes : 1, 2) (Continued)SymbolItemD4(400Mbps)DA(366Mbps)D3(333Mbps)Units NotesMinMaxMinMaxMinMaxt REFI Auto-Refresh Average Interval 0.47.80.47.80.47.8us5t PAUSE Pause Time after Power-up 200-200-200-I RC Random Read/Write Cycle Time (Applicable to Same Bank)CL = 35-5-5-CycleCL = 45-5-5-I RCD RDA/WRA to LAL Command Input Delay (Applicable to Same Bank)111111I RAS LAL to RDA/WRA Command Input Delay (Applicable to Same Bank)CL = 34-4-4-CL = 44-4-4-I RBD Random Bank Access Delay (Applicable to Other Bank)2-2-2-I RWD LAL following RDA to WRA Delay (Applicable to Other Bank)BL = 43-3-3-I WRD LAL following WRA to RDA Delay (Applicable to Other Bank)1-1-1-I RSC Mode Register Set Cycle Time CL = 35-5-5-CL = 45-5-5-I PD PD Low to Inactive State of Input Buffer -1-1-1I PDA PD High to Active State of Input Buffer -1-1-1I PDV Power down mode valid from REF commandCL = 315-15-15-CL = 418-18-18-I REFC Auto-Refresh Cycle TimeCL = 315-15-15-CL = 418-18-18-I LOCKDLL Lock-on Time (Applicable to RDA command)200-200-200-K4C5608/1638F 256Mb Network-DRAM- 13 -AC Test ConditionsSymbol ParameterValue Units NotesV IH (min)Input high voltage (minimum)V REF + 0.35V V IL (max)Input low voltage (maximum)V REF - 0.35V V REF Input reference voltage VddQ/2V V TT Termination voltageV REF V V SWING Input signal peak to peak swing 1.0V V R Differential clock input reference level V X(AC)V V ID (AC)Input differential voltage 1.5V SLEW Input signal minimum slew rate1.0V/ns V OTROutput timing measurement reference voltageVddQ/2VIH min (AC)IL max (AC)V VddQZ=50ΩR T =50ΩV TT CL=30pFV REFMeasurement PointOutputOutput Load Circuit(SSTL_2)Slew=(V IH min (AC) - V IL max (AC))/∆TNotes : 1. Transition times are measured between V IH min (DC) and V IL max (DC). Transition (rise and fall) of input signals have a fixed slope.2. If the result of nominal calculation with regard to t CK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., t DQSS = 0.75*t CK , t CK = 5ns, 0.75*5ns =3.75ns is rounded up to 3.8ns.)4. These parameters are measured from signal transition point of DQS crossing V REF level.5. The t REFI (MAX.) applies to equally distributed refresh method.The t REFI (MIN.) applies to both burst refresh method and distributed refresh method.In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400ns always. Inother words, the number of Auto- Refresh cycles which can be performed within 3.2us (8X400ns) is to 8 times in the maximum.6. Low Impedance State is speified at VddQ/2± 0.2V from steady state.7. High Impedance State is specified where output buffer is no longer driven.8. These parameters depend on the clock jitter. These parameters are measured at stable clock.=0.5*VddQK4C5608/1638F 256Mb Network-DRAM- 14 -Power Up Sequence1. As for PD, being maintained by the low state (<0.2V) is desirable before a power-supply injection.2. Apply Vdd before or at the same time as VddQ.3. Apply VddQ before or at the same time as V REF .4. Start clock (CK, CK) and maintain stable condition for 200us (min.).5. After stable power and clock, apply DESL and take PD = H.6. Issue EMRS to enable DLL and to define driver strength. (Note : 1)7. Issue MRS for set CAS Latency (CL), Burst Type (BT), and Burst Length (BL). (Note : 1)8. Issue two or more Auto-Refresh commands. (Note:1)9. Ready for normal operation after 200 clocks from Extended Mode Register programming. (Note : 2)Note : 1. Sequence 6, 7 and 8 can be issued in random order. 2. L=Logic Low, H = Logic HighHi-ZV DDV DDQV REF∼∼∼∼∼∼∼∼∼∼∼∼∼∼∼2.5V(TYP)2.5V(TYP)1.25V(TYP)EMRSMRSAuto Refresh cycleNomal OperationK4C5608/1638F 256Mb Network-DRAM- 15 -CK CKCSFNA0-A14BA0.BA1DQSDQ(Input)Basic Timing DiagramsTiming of the CK, /CKRefer to the Command Truth Table.Input Timingt CKIH V IH(AC)V IL(AC)ILCKCK CKV IHV ILV ID(AC)CKK4C5608/1638F 256Mb Network-DRAM- 16 -t CHt CLtCKCKCK Input (Control &Addresses)DQS DQDQS DQNote : The correspondence of LDQS, UDQS to DQ. (K4C561638F-TC)LDQS DQ0 to 7UDQSDQ8 to 15Read Timing (Burst Length = 4)K4C5608/1638F 256Mb Network-DRAM- 17 -CKCK Input (Control &Addresses)DQS (Input)DQ (Input)Write Timing (Burst Length = 4)DQS (Input)DQ (Input)Note. The correspondence of LDQS, UDQS to DQ. (K4C561638F-TC)LDQS DQ0 to 7UDQSDQ8 to 15CKCK Input (Control &Addresses)t t tREFI, tPAUSE, Ixxxx Timingt t t t PAUSE,I Note. "I XXXX "means "I RC ", "I RCD ", "I RAS ", etc.K4C5608/1638F 256Mb Network-DRAM- 18 -DSSK CKCK Input (Control &Addresses)LDQSDQ0 ~ 7Write Timing (x16 device) (Burst Length = 4)CAS latency = 3DSSK DSSK DSSK DSSKUDQSDQ8 ~ 15LDQSDQ0 ~ 7CAS latency = 4UDQSDQ8 ~ 15DSSK DSSK DSSKK4C5608/1638F 256Mb Network-DRAM Function Truth Table (Notes : 1,2,3)Command Truth Table (Notes : 4)•The First CommandSymbol Function CS FN BA1-BA0A14-A9A8A7A6-A0 DESL Device Deselect H X X X X X X RDA Read with Auto-close L H BA UA UA UA UA WRA Write with Auto-close L L BA UA UA UA UA •The Second Command (The next clock of RDA or WRA command)Symbol Function CS FN BA1-BA0A14-A13A12-A11A10-A9A8A7A6-A0 LAL Lower Address Latch (x16)H X X V V X X X LA LAL Lower Address Latch (x8)H X X V X X X LA LA REF Auto-Refresh L X X X X X X X X MRS Mode Register Set L X V L L L L V V Notes : 1. L = Logic Low, H = Logic High, X = either L or H, V = Valid (Specified Value), BA = Bank Address, UA = Upper Address, LA = Lower Address.2. All commands are assumed to issue at a valid state.3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input whereCLK goes to High.4. Operation mode is decided by the comination of 1st command and 2nd command refer to "STATE DIAGRAM" and thecommand table below.Read Command TableCommand (Symbol)CS FN BA1-BA0A14-A9A8A7A6-A0Notes RDA (1st)L H BA UA UA UA UALAL (2nd)H X X X X LA LA5 Notes : 5. For x16 device, A7 is "X" (either L or H).- 19 -K4C5608/1638F 256Mb Network-DRAM- 20 -Write Command TableK4C561638F-TCCommand (Symbol)CS FN BA1-BA0A14A13A12A11A10-A9A8A7A6-A0WRA (1st)L L BA UA UA UA UA UA UA UA UA LAL (2nd)HXXLVWOLVW1UVW0UVW1XXXLAK4C560838F-TCNote : 6. A14 to A11 are used for variable Write Length (VW) control at Write Operation.Command (Symbol)CS FN BA1-BA0A14A13A12A11A10-A9A8A7A6-A0WRA (1st)L L BA UA UA UA UA UA UA UA UA LAL (2nd)HXXVWOVW1XXXXLALAVW Truth TableNote : 7. For x16 device, LVW0 and LVW1 control DQ0-DQ7, UVW0 and UVW1 control DQ8-DQ15.Function VW0VW1BL = 4ReservedL L Write All Words H L Write First Two Words L H Write First One WordHHMode Register Set Command Truth TableNote : 8. Refer to "Mode Register Table".Command (Symbol)CS FN BA1-BA0A14-A9A8A7A6-A0NotesRDA (1st)L H X X X X X MRS (2nd)LXVLLVV8元器件交易网K4C5608/1638FFunction Truth Table (Continued)Auto-Refresh Command TableFunction Active Auto-Refresh Command (Symbol) WRA(1st) REF(2nd) Current State Standby Active PD CS n-1 H H n H H L L L X X X FN256Mb Network-DRAMBA1-BA0 A14-A9 X XA8 X XA7 X XA6-A0 X XNotesPower Down TableFunction Power Down Entry Power Down Continue Power Down Exit Command (Symbol) PDEN PDEX Current State Standby Power Down Power Down PD CS n-1 H L L n L L H H X H X X X X X X X X X X X X X X X X X X 11 10 FN BA1-BA0 A14-A9 A8 A7 A6-A0 NotesNotes : 9. PD has to be brought to Low within tFPDL from REF command. 10. PD should be brought to Low after DQ’s state turned high impedance. 11. When PD is brought to High from Low, this function is executed asynchronously.- 21 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FFunction Truth Table (Continued)Current State PD n-1 H H H H H L H H H H L H H H H L H H H H H L H H H H H L H H H H H L H H H H H L H L L L n H H H L L X H H L L X H H L L X H H H L L X H H H L L X H H H L L X H H H L L X X L H H CS H L L H L X H L H L X H L H L X H L L H L X H L L H L X H L L H L X H L L H L X X X H L FN X H L X X X X X X X X X X X X X X H L X X X X H L X X X X H L X X X X H L X X X X X X X Address X BA, UA BA, UA X X X LA Op-Code X X X LA X X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X BA, UA BA, UA X X X X X X X Command DESL RDA WRA PDEN LAL MRS/EMRS PDEN REF (Self) LAL REF PDEN REF (Self) DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN RDEX -256Mb Network-DRAMAction NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down state Begin read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh entry Invalid Continue burst read to end Illegal Illegal Illegal Illegal Invalid Data write & continue burst write to end Illegal Illegal Illegal Illegal Invalid NOP-> Idle after IREFC Illegal Illegal Self-Refresh entry Illegal Refer to Self-Refreshing state Nop-> Idle after IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode Exit Power Down Mode->Idle after tPDEX Illegal 13 13 NotesIdle12Row Active for ReadRow Active for WriteRead13 13WriteAuto-RefreshingMode Register Accessing14Power DownNotes : 12. Illegal if any bank is not idle. 13. Illegal to bank in specified states : Function may be Legal in the bank indicated by bank Address (BA). 14. Illegal if tFPDL is not satisfied.- 22 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FMode Register TableRegular Mode Register (Notes : 1)Address Register BA1*1 0 BA0*1 0 A14-A8 0 A7*3 TM256Mb Network-DRAMA6-A4 CLA3 BTA2-A0 BLA7 0 1Test Mode (TM) Regular (Default) Test Mode EntryA3 0 1Burst Type (BT) Sequential InterleaveA6 0 0 0 1 1 1A5 0 1 1 0 0 1A4 X 0 1 0 1 XCAS Latency (CL) Reserved *2 Reserved *2 3 4 Reserved *2 Reserved *2A2 0 0 0 0 1A1 0 0 1 1 XA0 0 1 0 1 XBurst Length (BL) Reserved *2 Reserved *2 4 Reserved *2Extended Mode Register (Notes : 4)Address Register BA1*4 0 BA0*4 1 A14-A7 0 A6 DIC A5-A2 0 A1 DIC A0 DSA6 0 0 1 1A1 0 1 0 1Output Driver Impedance Control (DIC) Normal Output Driver Strong Output Driver Weaker Output Driver Weakest Output DriverNote : 1. Regular Mode Register is Chosen Using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0"(Low state). Because test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the Combination of BA0 = 1 and BA1 = 0.A0 0 1DLL Switch (DS) DLL Enable DLL Disable- 23 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FState Diagram256Mb Network-DRAMPDEX (PD = H) PDEN (PD = L) Standby (Idle)Power DownPD = H AutoRefresh WRAMode Register RDAREFMRSActive (Restore)ActiveLALLALWrite (Buffer)ReadCommand Input Automatic Return The second command at Active state must be issued 1clock after RDA or WRA command input- 24 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FTiming DiagramsSingle Bank Read Timing (CL = 3)0 CK CKIRC = 5 cycles256Mb Network-DRAM1234567891011IRC = 5 cyclesCommandRDALALDESLRDALALDESLRDALALIRCD = 1 cycleIRAS = 4 cyclesIRCD = 1 cycleIRAS = 4 cyclesDQS (Output)Hi-ZHi-ZHi-ZCL = 3CL = 3DQ (Output)Hi-ZQ0 Q1 Q2 Q3Hi-ZQ0 Q1 Q2 Q3Hi-ZSingle Bank Read Timing (CL = 4)0 CK CKIRC = 5 cycles IRC = 5 cycles1234567891011CommandRDALALDESLRDALALDESLRDALALIRCD = 1 cycleIRAS = 4 cyclesIRCD = 1 cycleIRAS = 4 cyclesDQS (Output)Hi-ZHi-ZCL = 4CL = 4DQ (Output)Hi-ZQ0 Q1 Q2 Q3Hi-ZQ0 Q1 Q2- 25 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FSingle Bank Write Timing (CL = 3)0 CK CKIRC = 5 cycles256Mb Network-DRAM1234567891011IRC = 5 cyclesCommandWRALALDESLIRAS = 4 cyclesWRALALDESLIRAS = 4 cyclesWRALALIRCD = 1 cycleIRCD = 1 cycleIRCD = 1 cycletDQSStDQSSDQS (Input)WL = 2 WL = 2DQ (input)D0 D1 D2 D3D0 D1 D2 D3Single Bank Write Timing (CL = 4)0 CK CKIRC = 5 cycles IRC = 5 cycles1234567891011CommandWRALALDESLIRAS = 4 cyclesWRALALDESLIRAS = 4 cyclesWRALALIRCD = 1 cycleIRCD = 1 cycleIRCD = 1 cycleDQS (Input)WL = 3 WL = 3DQ (input)tDQSSD0 D1 D2 D3tDQSSD0 D1 D2 D3Note :means "H" or "L"- 26 -REV. 0.3 Jan. 2005元器件交易网K4C5608/1638FSingle Bank Read-Write Timing (CL = 3)0 CK CKIRC = 5 cycles256Mb Network-DRAM1234567891011IRC = 5 cyclesCommandRDALALDESLWRALALDESLRDALALIRCD = 1 cycleIRAS = 4 cyclesIRCD = 1 cycleIRAS = 4 cycles tDQSSDQSHi-ZHi-ZHi-ZCL = 3WL = 2DQHi-ZQ0 Q1 Q2 Q3Hi-ZD0 D1 D2 D3Hi-ZSingle Bank Read-Write Timing (CL = 4)0 CK CKIRC = 5 cycles IRC = 5 cycles1234567891011CommandRDALALDESLWRALALDESLRDALALIRCD = 1 cycle Hi-ZIRAS = 4 cyclesIRCD = 1 cycleIRAS = 4 cyclesDQSHi-ZHi-ZCL = 4WL = 3DQHi-ZQ0 Q1 Q2 Q3Hi-ZD0 D1 D2 D3Hi-Z- 27 -REV. 0.3 Jan. 2005。

UC5608中文资料

•Complies with SCSI, SCSI-2 and SPI-2 Standards•6pF Channel Capacitance duringDisconnect•100µA Supply Current in Disconnect Mode•Meets SCSI Hot Plugging Capability •−650mA Sourcing Current forTermination•+200mA Sinking Current for Active Negation•Provides Active Termination for 18 Lines •Logic Command Disconnects allTermination Lines•Trimmed Termination Current to 5%•Trimmed Impedance to 5%•Current Limit and Thermal Shutdown Protection The UC5608 provides 18 lines of active termination for a SCSI (Small Computer Systems Interface) parallel bus. The SCSI standard recom-mends active termination at both ends of the bus cable.The UC5608 is pin-for-pin compatible with its predecessors, the UC5601 and UC5602 - 18 Line Active T erminator. Parametrically the UC5608 has a 5% tolerance on impedance and current compared to a 3% tolerance on the UC5601 and the sink current is increased from 20 to 200mA. The low side clamps have been removed. Custom power packages are utilized to allow normal operation at full power conditions (2 Watts).When in disconnect mode the terminator will disconnect all terminat-ing resistors and disable the regulator, greatly reducing standby power. The output channels remain high impedance even without T ermpwr applied.Internal circuit trimming is utilized to trim the impedance to a 5% toler-ance and, most importantly, to trim the output current to a 5% toler-ance, as close to the max SCSI spec as possible, which maximizes noise margin in fast SCSI operation.Other features include 4.0 to 5.25V T ermpwr, thermal shutdown and current limit.This device is offered in low thermal resistance versions of the indus-try standard 28 pin wide body SOIC, 28 pin wide body TSSOP, and 28 pin PLCC, as well as 24 pin DIP.UC560818-Line Low Capacitance SCSI Active TerminatorFEATURES DESCRIPTIONBLOCK DIAGRAMCircuit Design Patented3/97UDG-94047* PWP package pin 23 serves as signal ground; pins 7, 8, 9,20, 21 and 22 serve as heatsink/ground.TSSOP-28 (Top View)PWP PackageABSOLUTE MAXIMUM RATINGSTermpwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V Regulator Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to +150°C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to +150°C Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +300°C RECOMMENDED OPERATING CONDITIONSTermpwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V to 5.25V Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +5V Disconnect Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to TermpwrUnless otherwise specified all voltages are with respect to Ground. Currents are posi-tive into, negative out of the specified terminal.Consult Packaging Section of Unitrode Integrated Circuits databook for thermal limita-tions and considerations of packages.CONNECTION DIAGRAMSPLCC-28 (Top View)QP Package* QP package pins 12 - 18 serve as both heatsink and signal ground.* DWP package pin 28 serves as signal ground; pins 7, 8, 9,20, 21, 22 serve as heatsink/ground.SOIC-28 (Top View)DWP Package Note: Drawings are not to scale.DIL-24 (Top View)N or J PackagePARAMETERTEST CONDITIONSMINTYP MAX UNITS Supply Current Section Termpwr Supply CurrentAll termination lines = Open 1725mA All termination lines = 0.5V 400430mA Power Down ModeDISCNCT = Open100150µA Output Section (Terminator Lines)Terminator Impedance ∆I LINE = -5mA to -15mA 104.5110115.5Ohms Output High Voltage V TRMPWR = 4V (Note 1) 2.652.93.0V Max Output Current V LINE = 0.5V T J = 25°C -20.3-21.5-22.4mA 0°C < T J < 70°C -19.8-21.5-22.4mA Max Output CurrentV LINE = 0.5V, TRMPWR = 4V (Note 1)T J = 25°C -19.5-21.5-22.4mA 0°C < T J < 70°C -19.0-21.5-22.4mA V LINE = 0.2V, TRMPWR = 4V to 5.25V0°C < T J < 70°C -21.6-24.0-25.4mA Output LeakageDISCNCT = 4V TRMPWR = 0V to 5.25V REG = 0V V LINE = 0 to 4V10400nA V LINE = 5.25V 100µA TRMPWR = 0V to 5.25V, REG = Open V LINE = 0V to 5.25V10400nA Output Capacitance DISCNCT = Open (Note 2)67pF Regulator SectionRegulator Output Voltage 2.8 2.93V Regulator Output Voltage All Termination Lines = 4V 2.8 2.93V Line Regulation TRMPWR = 4V to 6V1020mV Drop Out Voltage All Termination Lines = 0.5V 1.0 1.2V Short Circuit CurrentV REG = 0V -450-650-950mA Sinking Current Capability V REG = 3.5V100200500mA Thermal Shutdown170°C Thermal Shutdown Hysteresis 10°C Disconnect Section Disconnect Threshold1.1 1.41.7VELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for T A = 0°C to 70°C. TRMPWR =4.75V, DISCNCT = Ground. T A = T J .Note 1: Measuring each termination line while other 17 are low (0.5V).Note 2: Guaranteed by design. Not 100% tested in production.Figure 1: Typical SCSI Bus ConfigurationAPPLICATION INFORMATIONUDG-94048UNITRODE CORPORATION7 CONTINENTAL BLVD. • MERRIMACK, NH 03054TEL. (603) 424-2410 • FAX (603) 424-3460IMPORTANT NOTICETexas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK.In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.Copyright © 1999, Texas Instruments Incorporated。

KKX485D资料

TECHNICAL DATAKK X485Low-Power, Slew-Rate-Limited RS-485/RS-422TransceiversGeneral DescriptionThe KK X485 is low-power transceivers for RS-485 and RS- 422 communication. IC contains one driver and one receiver. The driver slew rates of the KK X485 is not limited, allowing them to transmit up to 2.5Mbps.These transceivers draw between 120µA and 500µA of supply current when unloaded or fully loaded with disabled drivers. All parts operate from a single 5V supply. Drivers are short-circuit current limited and are protected againstexcessive power dissipation by thermal shutdown circuitry that places the driver outputs into a high-impedance state. The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit. The KK X485 is designed for half-duplex applications.FeaturesLow Quiescent Current: 300µA-7V to +12V Common-Mode Input Voltage Range Three-State Outputs30ns Propagation Delays, 5ns SkewFull-Duplex and Half-Duplex Versions Available Operate from a Single 5V SupplyAllows up to 32 Transceivers on the Bus Data rate: 2,5 MbpsCurrent-Limiting and Thermal Shutdown for Driver Overload ProtectionABSOLUTE MAXIMUM RATINGSSupply Voltage (V CC) 12V Continuous Power Dissipation (T A= +70°C) Control Input Voltage -0.5V to (V CC + 0.5V) 8-Pin Plastic DIP (derate 9.09mW/°C above+70°C) 727mWDriver Input Voltage (DI) -0.5V to (V CC+ 0.5V) 8-Pin SOP (derate 5.88mW/°C above +70°C)471mWDriver Output Voltage (A, B) -8V to +12.5V Operating Temperature Ranges 0°C to +70°C Receiver Input Voltage (A, B) -8V to +12.5V Storage Temperature Range -65°C to +160°C Receiver Output Voltage (RO) -0.5V to (V CC+0.5V) Lead Temperature (soldering, 10sec) +300°C DC ELECTRICAL CHARACTERISTICS(V CC = 5V ±5%, T A = T MIN to T MAX, unless otherwise noted.) (Notes 1, 2)DC ELECTRICAL CHARACTERISTICS (continued)(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)== SWITCHING CHARACTERISTICS(V CC = 5V ±5%, T A = T MIN to T MAX , unless otherwise noted.) (Notes 1, 2)PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSt PLH R DIFF = 54Ω10 30 60 Driver Input to Output t PHL C L1 = C L2 = 100pF10 30 60 ns Driver Output Skew to Outputt SKEW R DIFF = 54Ω, CL1 = CL2 = 100pF 5 10 ns Driver Enable to Output High t ZH C L = 100pF, S2 closed 40 70 ns Driver Enable to Output Low t ZL C L = 100pF, S1 closed 40 70 ns Driver Disable Time from Low t LZ C L = 15pF, S1 closed 40 70 ns Driver Disable Time from High t HZ C L = 15pF, S2 closed 40 70 ns| tPLH - tPHL | Differential t SKD R DIFF = 54Ω13 ns Receiver SkewC L1 = C L2 100pF Receiver Enable to Output Low t ZL C RL = 15pF, S1 closed 20 50 ns Receiver Enable to Output High t ZH C RL = 15pF, S2 closed 20 50 ns Receiver Disable Time from Lowt LZ C RL = 15pF, S1 closed 20 50 ns Receiver Disable Time from Hight HZC RL = 15pF, S2 closed2050nsMaximum Data Rate f MAX 2.5 MbpsOperation timing diagrams of ILX 485Table of ILX 485 operationTransmitting ReceivingInputs Outputs X Inputs OutputsRE DE DI Z Y RE DE A-B ROX110100+0.2V1X 1 0 1 0 0 0 -0.2V 00 0 X Z Z 0 0 open 11 0 X Z Z 1 0 X Z X-don’t careZ-high impedance。

第8章处理器核心电路设计和底层软件移植

L=27
CCCR[4:0] =00001
最终的CCCR寄存器的值应当配置为0x00000161
注二十页，共七十八页。
2. CKEN寄存器
CKEN(Clock Enable Register)寄存器是一个控制外部设备时钟使能的寄存器。它对嵌入式系统的电量消耗有着决定性的作用；对于那些没有用到的外设，应当关闭其时钟供应。
现在你正浏览到当前第二十二页，共七十八页。
3. ICMR寄存器
ICMR(Interrupt Controller Mask Register) 寄存器是中断使能寄存器。1代表使能，0代表屏蔽。
一般来说，PXA255处理器在Bootloader启动阶段必须屏蔽所有中断，所以ICMR寄器应当设置为 0x00000000。
下面就以异步静态存储器(Flash)和同步动态存储器(SDRAM)为例，说明PXA2XX系统的存储器扩展原理。
7 现在你正浏览到当前第七页，共七十八页。
1．异步静态存储器接口设计原理如图8-3所示，采用两片Intel的E28F128J3A-150
Flash芯片，构成了32 MB的F1ash存储器。这里的Flash 芯片是16位的，故采用两块并联的方法为处理器提供32 位的数据总线支持。
1. CCCR寄存器
CCCR(Core Clock Configuration Register)寄存器控制着内存、LCD、DMA控制器所使用的时钟。这些时钟都是由处理器的3.6864MHz钟振倍频上去的，控制倍频比例的参数有三个，见表4-2。
表8-2 CCCR控制倍频比例的参数
名称
使用方法
MSCx十分重要，因为它记录了有关于存储器的几个重要参数，见P197表8-4所列。

多功能数码复合机理光1911复印机

夏普4018详细参数切换到传统表格版基本参数复印功能打印功能扫描功能其它特性基本参数∙产品类型：数码复合机∙颜色类型：黑白∙涵盖功能：复印/打印/扫描∙速度类型：低速∙最大原稿尺寸：A3∙进纸盘容量：标配纸盒：250页，手送纸盘：100页∙内存容量：16MB∙耗材描述：AR-205DR-C感光鼓，AR-205DU-C感光鼓组件AR-021ST-C墨粉盒，AR-022ST-C墨粉盒∙双面器：手动∙网络功能：不支持∙接口类型：USB2.0复印功能∙复印速度：18cpm∙复印分辩率：600×600dpi∙预热时间：4.5秒∙首页复印时间：7.2秒∙连续复印页数：1-999页∙缩放范围：25-400%（以1%为单位）∙复印倍率：50%，70%，81%，86%，100%，115%，122%，141%，200% ∙灰度等级：256级打印功能∙打印控制器：标准配置∙打印速度：18ppm∙打印分辨率：600×600dpi ∙打印语言：SPLC扫描功能∙扫描控制器：标准配置∙扫描分辨率：600×600dpi∙输出格式：BMP，TIFF，PDF其它特性∙主机尺寸：590×550×495mm∙重量：30.1kg∙电源：AC 220V（±10V），50Hz∙功率：1200W∙系统平台：Windows 2000/XP/vISTA/7东芝181详细参数切换到传统表格版基本参数复印功能打印功能扫描功能其它特性复印机附件保修信息基本参数∙产品类型：数码复合机∙颜色类型：黑白∙涵盖功能：复印/打印/扫描∙速度类型：低速∙最大原稿尺寸：A3∙进纸盘容量：标配纸盒：250页旁路纸盘：100页最大容量：600页∙出纸盘容量：250页∙介质重量：纸盒：64-80g/m²旁路供纸：64-80g/m²（连接供纸），50-163g/m²（单张供纸）∙内存容量：标配：32MB，最大：96MB∙耗材描述：墨粉PS-ZT1810C5k：5900页，PS-ZT1810C510：10000页，PS-ZT1810C：24500页感光鼓OD2320C，70000页载体D2320∙双面器：手动∙网络功能：不支持网络打印∙接口类型：USB2.0复印功能∙复印方式：间接电子成像方式∙感光材料：OPC∙显影系统：双组分磁穗显影∙定影系统：卤素灯（2 个）∙曝光控制：自动加7级手动曝光∙复印速度：18cpm∙复印分辩率：2400×600dpi∙原稿类型：单/多张书本和三维物体∙复印尺寸：纸盒：A3，A4，A4-R，B4，B5，B5-R，FOLIO，8K，16K，16K-R，LD，LG，LT，LTR，COMP旁路供纸：A3，A4，A4-R，A5-R，B4，B5，B5-R，FOLIO，8K，16K，16K-R，LD，LG，LT，LT-R，ST-R，COMP∙预热时间：25秒∙首页复印时间：7.6秒∙连续复印页数：1-999页∙缩放范围：25-400%（以1%为单位）∙无图像区域：前端消边：3±2mm后端/两侧消边：2±2mm∙灰度等级：256级∙复印其它性能：一次扫描多次复印，电子分页，作业插入，自动作业启动，自动更换纸盒打印功能∙打印控制器：标准配置∙打印速度：18ppm∙打印分辨率：600×600dpi ∙打印语言：GDI扫描功能∙扫描控制器：标准配置∙扫描幅面：A3∙扫描分辨率：600×600dpi ∙输出格式：TIFF∙扫描其它性能：TWAIN扫描其它特性∙主机尺寸：600×462.5×643mm∙主机安装空间：948×643mm∙重量：31.8kg∙电源：220-240V（±10%），50/60Hz，8A∙功率：1500W∙系统平台：Windows 2000/XP/Server 2003/2008/Vista∙环境参数：工作温度：10-30℃，工作湿度：20-85%（无凝露）∙上市日期：2009年12月复印机附件∙包装清单：主机 x1 操作手册 x1电源线 x1安装报告 x1CD-ROM（2张） x1∙可选配件：MY-1027-C 第二纸盒 x1 KK-1660C 操作手册盒 x1MH-3600 简易工作台 x1MR-2020C 自动单面输稿器 x1MY-1028C 纸盒 x1GC-1240C 64MB内存 x1保修信息∙保修政策：全国联保∙质保时间：1年∙质保备注：购机后1年或复印量达到规定条件先满足者为准∙客服电话：800-820-8068∙电话备注：周一至周五：9:00-18:00（节假日休息）∙详细内容：东芝复印机在致力于为全球用户提供高品质，高性能产品的同时，更注重所销售产品的售后服务，在全国建立以授权维修站为基础的覆盖全国各地的维修服务网络，以百分之百的用户满意为目标，为东芝复印机用户提供良好保障。

瑞博华 200Ksps 12 位 32 通道 AD 4 通道 DA 板 4 通道脉冲计数 8 通道数

PCI总线200Ksps/12位32通道AD4通道DA板4通道脉冲计数8通道数字输入/8通道数字输出RBH7272使用说明书北京瑞博华控制技术有限公司二00七年十月200Ksps/12位32通道AD4通道DA板4通道脉冲计数（1个旋转编码器）8通道数字输入/8通道数字输出RBH7272使用说明书一、性能特点：本板采用PCI总线接口。

本板通过采用高速高精度AD芯片、高精度的仪器放大器、高密度CPLD逻辑芯片、精细地布线以及优良的制版工艺，实现了高速、高精度实时数据采集，具有以下性能特点：1、AD高精度：综合误差小于＋/-1LSB 。

2、4通道脉冲功能:第一通道脉冲与第二通道脉冲可以构成一个旋转编码器输入,实时直接给出正向与反向脉冲数;第一通道同时输出脉冲的瞬态周期,时间分辨率为1微秒;第二、第三、第四通道输出16位的计数值，输入最高脉冲频率为采样频率×255，如采样频率10000，则输入最高脉冲频率为2.55MHz。

3、开关量同步采集输入：8路开关量与4路脉冲量合成第一通道与模拟量同步采集。

便于用户对开关量的高速采集。

可以用于外部同步触发等功能。

4、DA通道数:4通道独立锁存,精度12位5、AD高速度：多通道采集速度达到200Ksps（Sample Per Second），单通道方式也能够达到70Ksps以上，特别适合于工业控制中的数据采集。

6、程控放大器功能，可以设置放大倍数为1、2、4、8或1、10、100、1000。

7、AD硬件定时：板上提供硬件定时器,可以根据需要发出定时中断,采集软件在定时中断程序中采集,从而保证准确地时间基准，适于大部分的工业实时控制和高速数据采集的应用，特别是在WINDOWS95/98/2000的环境下，由于PC系统很难提供高精度的定时，采用本板的定时器，能够提供高精度的定时，同时能够实现高精度的数据采集，因此，在WINDOWS环境下采用本板具有特别的优点。

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256Mbit SDRAM8M x 8bit x 4 BanksSynchronous DRAMLVTTLRevision 1.1May. 2003* Samsung Electronics reserves the right to change products or specification without notice.Rev. 1.1 May. 2003Revision HistoryRevision 0.0 (Jan. , 2002)- First releaseRevision 0.1(May., 2003)- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.Rev. 1.1 May. 2003Rev. 1.1 May. 2003V DDDQ0 V DDQN.CDQ1V SSQN.CDQ2 V DDQN.CDQ3V SSQN.CV DDN.CWECASRASCSBA0BA1 A10/APA0A1A2A3V DD 123456789101112131415161718192021222324252627545352515049484746454443424140393837363534333231302928PIN CONFIGURATION (Top view)V SSDQ7V SSQN.CDQ6V DDQN.CDQ5V SSQN.CDQ4V DDQN.CV SSN.C/RFUDQMCLKCKEA12A11A9A8A7A6 A5 A4 V SS54Pin TSOP (II) (400mil x 875mil) (0.8 mm Pin pitcH)PIN FUNCTION DESCRIPTIONPin Name Input FunctionCLK System clock Active on the positive going edge to sample all inputs.CS Chip select Disables or enables device operation by masking or enabling all inputs exceptCLK, CKE and DQMCKE Clock enable Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby.A0 ~ A12Address Row/column addresses are multiplexed on the same pins.Row address : RA0 ~ RA12, Column address : CA0 ~ CA9BA0 ~ BA1Bank select address Selects bank to be activated during row address latch time.Selects bank for read/write during column address latch time.RAS Row address strobe Latches row addresses on the positive going edge of the CLK with RAS low.Enables row access & precharge.CAS Column address strobe Latches column addresses on the positive going edge of the CLK with CAS low.Enables column access.WE Write enable Enables write operation and row precharge.Latches data in starting from CAS, WE active.DQM Data input/output mask Makes data output Hi-Z, t SHZ after the clock and masks the output.Blocks data input when DQM active.DQ0 ~7Data input/output Data inputs/outputs are multiplexed on the same pins.V DD/V SS Power supply/ground Power and ground for the input buffers and the core logic.V DDQ/V SSQ Data output power/ground Isolated power supply and ground for the output buffers to provide improved noiseimmunity.N.C/RFU No connection/reserved for future useThis pin is recommended to be left No Connection on the device.Rev. 1.1 May. 2003Rev. 1.1 May. 2003ABSOLUTE MAXIMUM RATINGSParameter Symbol Value Unit Voltage on any pin relative to Vss V IN , V OUT -1.0 ~ 4.6V Voltage on V DD supply relative to Vss V DD , V DDQ-1.0 ~ 4.6V Storage temperature T STG -55 ~ +150°C Power dissipation P D 1W Short circuit currentI OS50mAPermanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Note :DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = 0 to 70°C)Parameter Symbol Min Typ Max Unit NoteSupply voltage V DD , V DDQ3.0 3.3 3.6V Input logic high voltage V IH 2.0 3.0V DD +0.3V 1Input logic low voltage V IL -0.300.8V 2Output logic high voltage V OH 2.4--V I OH = -2mA Output logic low voltage V OL --0.4V I OL = 2mAInput leakage currentI LI-10-10uA31. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.3. Any input 0V ≤ V IN ≤ V DDQ .Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.Notes :1. -75/7C only specify a maximum value of 3.5pF2. -75/7C only specify a maximum value of3.8pF 3. -75/7C only specify a maximum value of 6.0pFNotes :CAPACITANCE (V DD = 3.3V, T A = 23°C, f = 1MHz, V REF =1.4V ± 200 mV)PinSymbol Min Max Unit Note ClockC CLK 2.5 4.0pF 1RAS, CAS, WE, CS, CKE, DQM C IN 2.5 5.0pF 2Address C ADD 2.5 5.0pF 2DQ 0 ~ DQ 15C OUT4.06.5pF3DC CHARACTERISTICS(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)Parameter Symbol Test ConditionVersionUnit Note -7C-75-1H-1LOperating current (One bank active)I CC1Burst length = 1t RC ≥ t RC(min)I O = 0 mA100909090mA1Precharge standby cur-rent in power-down modeI CC2P CKE ≤ V IL(max), t CC = 10ns2mA I CC2PS CKE & CLK ≤ V IL(max), t CC = ∞2Precharge standby cur-rent in non power-down modeI CC2NCKE ≥ V IH(min), CS ≥ V IH(min), t CC = 10nsInput signals are changed one time during 20ns20mA I CC2NSCKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞Input signals are stable10Active standby current in power-down modeI CC3P CKE ≤ V IL(max), t CC = 10ns6mA I CC3PS CKE & CLK ≤ V IL(max), t CC = ∞6Active standby current in non power-down mode (One bank active)I CC3NCKE ≥ V IH(min), CS ≥ V IH(min), t CC = 10nsInput signals are changed one time during 20ns30mA I CC3NSCKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞Input signals are stable25mAOperating current (Burst mode)I CC4I O = 0 mAPage burst4banks Activated.t CCD = 2CLKs110110100100mA1Refresh current I CC5t RC ≥ t RC(min)220200190190mA2Self refresh current I CC6CKE ≤ 0.2V C3mA3 L 1.5mA41. Measured with outputs open.2. Refresh period is 64ms.3. K4S560832D-TC**4. K4S560832D-TL**5. Unless otherwise noticed, input swing level is CMOS(V IH/V IL=V DDQ/V SSQ).Notes :Rev. 1.1 May. 2003Rev. 1.1 May. 2003AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, T A = 0 to 70°C)Parameter Value Unit AC input levels (Vih/Vil)2.4/0.4V Input timing measurement reference level 1.4V Input rise and fall timetr/tf = 1/1ns Output timing measurement reference level 1.4VOutput load conditionSee Fig. 23.3V1200Ω870ΩOutput50pFV OH (DC) = 2.4V, I OH = -2mA V OL (DC) = 0.4V, I OL = 2mAVtt = 1.4V50ΩOutput50pFZ0 = 50Ω(Fig. 2) AC output load circuit(Fig. 1) DC output load circuit OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)ParameterSymbolVersionUnitNote-7C-75-1H -1L Row active to row active delay t RRD (min)15152020ns 1RAS to CAS delay t RCD (min)15202020ns 1Row precharge time t RP (min)15202020ns 1Row active timet RAS (min)45455050ns 1t RAS (max)100us Row cycle timet RC (min)60657070ns 1Last data in to row precharge t RDL (min)2CLK 2, 5Last data in to Active delayt DAL (min) 2 CLK + tRP-5Last data in to new col. address delay t CDL (min)1CLK 2Last data in to burst stopt BDL (min)1CLK 2Col. address to col. address delay t CCD (min)1CLK 3Number of valid output dataCAS latency=32ea4CAS latency=211. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle timeand then rounding off to the next higher integer.2. Minimum delay is required to complete write.3. All parts allow every cycle column address change.4. In case of row precharge interrupt, auto precharge and read burst stop.5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP .Notes :Rev. 1.1 May. 2003DQ BUFFER OUTPUT DRIVE CHARACTERISTICSParameterSymbol Condition Min TypMax Unit Notes Output rise timetrhMeasure in linear region : 1.2V ~ 1.8V 1.374.37Volts/ns3Output fall time tfh Measure in linear region : 1.2V ~ 1.8V 1.30 3.8Volts/ns 3Output rise time trh Measure in linear region : 1.2V ~ 1.8V 2.8 3.9 5.6Volts/ns 1,2 Output fall timetfhMeasure in linear region : 1.2V ~ 1.8V2.02.95.0Volts/ns1,21. Rise time specification based on 0pF + 50 Ω to V SS , use these values to design to.2. Fall time specification based on 0pF + 50 Ω to V DD , use these values to design to.3. Measured into 50pF only, use these values to characterize to.4. All measurements done with respect to V SS .Notes :AC CHARACTERISTICS (AC operating conditions unless otherwise noted)ParameterSymbol-7C-75-1H-1L Unit NoteMinMax Min Max Min Max Min Max CLK cycle timeCAS latency=3t CC7.510007.51000101000101000ns1CAS latency=27.5101012CLK to valid output delay CAS latency=3t SAC 5.4 5.466ns1,2CAS latency=2 5.4667Output data hold timeCAS latency=3t OH3333ns 2CAS latency=23333CLK high pulse width t CH 2.5 2.533ns 3CLK low pulse width t CL 2.5 2.533ns 3Input setup time t SS 1.5 1.522ns 3Input hold time t SH 0.80.811ns 3CLK to output in Low-Z t SLZ 1111ns2CLK to output in Hi-ZCAS latency=3t SHZ 5.4 5.466nsCAS latency=25.46671. Parameters depend on programmed CAS latency.2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.Notes :I OH Characteristics (Pull-up)Voltage 100MHz133MHzMin100MHz133MHzMax66MHzMin(V)I (mA)I (mA)I (mA)3.45 -2.43.3 -27.33.0 0.0 -74.1 -0.72.6-21.1-129.2 -7.52.4-34.1-153.3-13.32.0-58.7-197.0-27.51.8-67.3-226.2-35.51.65-73.0-248.0-41.11.5-77.9-269.7-47.91.4-80.8-284.3-52.41.0-88.6-344.5-72.50.0-93.0-502.4-93.0 IBIS SPECIFICATIONI OL Characteristics (Pull-down)Voltage 100MHz133MHzMin100MHz133MHzMax66MHzMin(V)I (mA)I (mA)I (mA) 0.0 0.0 0.0 0.0 0.427.5 70.217.7 0.6541.8107.526.90.8551.6133.833.31.058.0151.237.6 1.470.7187.746.6 1.572.9194.448.0 1.6575.4202.549.5 1.877.0208.650.7 1.9577.6212.051.53.080.3219.654.2 3.4581.4222.654.9-100-200-300-400-500-600030.51 1.52 2.5 3.5VoltagemA25020015010050030.51 1.52 2.5 3.5VoltagemA66MHz and 100MHz/133MHz Pull-up66MHz and 100MHz/133MHz Pull-downI OH Min (100MHz)I OH Max (66 and 100MHz)I OH Min (66MHz)I OL Min (100MHz)I OL Max (100MHz)I OL Min (66MHz)Rev. 1.1 May. 2003V DD Clamp @ CLK, CKE, CS, DQM & DQV DD (V)I (mA)0.00.00.20.00.40.00.60.00.70.00.80.00.90.01.0 0.231.2 1.341.4 3.021.6 5.061.8 7.352.0 9.832.212.482.415.302.618.31V SS Clamp @ CLK, CKE, CS, DQM & DQ V SS (V)I (mA)-2.6-57.23-2.4-45.77-2.2-38.26-2.0-31.22-1.8-24.58-1.6-18.37-1.4-12.56-1.2 -7.57-1.0 -3.37-0.9 -1.75-0.8 -0.58-0.7 -0.05-0.6 0.0-0.4 0.0-0.2 0.00.0 0.020151050312VoltagemAI (mA)VoltagemAI (mA)Minimum V DD clamp current(Referenced to V DD)Minimum V SS clamp current-10-20-30-40-30-2-1-50-60Rev. 1.1 May. 2003K4S560832DCMOS SDRAMRev. 1.1 May. 2003SIMPLIFIED TRUTH TABLE(V=Valid, X=Don't care, H=Logic high, L=Logic low)CommandCKEn-1CKEnCSRASCASWEDQMBA 0,1A 10/APA 11,A 12,A 9 ~ A 0NoteRegisterMode register set H X L L L L X OP code1,2RefreshAuto refreshHH L L L H XX3Self refreshEntry L 3ExitL H L H H H X X3HX X X 3Bank active & row addr.H X L L H H X V Row address Read &column address Auto precharge disable HXLHLHXVL Column address (A 0 ~ A 9)4Auto precharge enable H4,5Write &column address Auto precharge disable H X L H L L X VL Column address (A 0 ~ A 9)4Auto precharge enableH 4,5Burst stop H X L H H L X X6PrechargeBank selection HXL L H L XV L XAll banksXHClock suspend or active power downEntry H L H X X X X XLV V V Exit L H X X X X X Precharge power down modeEntryHLH X X X XXLH H H ExitL HH X X X X LV VVDQMH VX 7No operation commandHXH X X X XXLHHHNotes :X1. OP Code : Operand codeA 0 ~ A 11 & BA 0 ~ BA 1 : Program keys. (@ MRS)2. MRS can be issued only at all banks precharge state.A new command can be issued after 2 CLK cycles of MRS.3. Auto refresh functions are as same as CBR refresh of DRAM.The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state.4. BA 0 ~ BA 1 : Bank select addresses.If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank B is selected. If BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst.New row active of the associated bank can be issued at t RP after the end of burst.6. Burst stop command is valid at every burst length.7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)元器件交易网。