EDA Power Distribution System Design For High Speed Boards The integrity of Power Distribut

E D AOnBoard Technology June 2004 - page 58Power Distribution System Design For High Speed BoardsThe integrity of Power Distribu-tion Systems (PDS) is becoming very critical as the clock frequen-cies and power consumption of high-end ASICs/microprocessors continue to increase rapidly. In fact, as more functionality is in-tegrated into modern ASICs and high-end microprocessors, they are consuming increasingly more power than ever before. This fact, coupled with faster operating fre-quencies and shorter clock edge rates, make the design of PDS ever more challenging. Moreover, as the core supply voltages are low-ered to around a volt and half, only very small percentage of ripple on the Power Supply voltages can be tolerated.Consider the following example: a high end processor or a modern Network Search Engine ASIC will have transient power requirements of 25A on a supply of 1.6V/1.2V with total allowable ripple voltage less than 60mV over a frequency range of DC to a hundreds of MHz. The PDS design should be ad-equate to cater to the power sup-ply needs of the devices over a wide frequency spectrum. Failing to do so, the high speed boards would behave unpredictably. In general, the PDS design for high speed and high transient power boards extends beyond just decoupling by thumb rules which is often the only design measure considered adequate.Design methodology There are two design method-ologies or approaches that can be followed for PDS design: empiri-cal and tool (Cadence Specctra-quest)-based. The criteria for both approaches is to set target imped-ances that need to be met over the complete frequency spectrum of interest, ranging from DC to sev-eral hundreds of MHz. References to practical experiences with a live project, that used Spectraquest power integrity tool, are made wherever relevant.Target impedance Target impedance is defined as the ratio of voltage tolerance to tran-sient current. For example: for a supply voltage of 1.2V with 5% maximum ripple tolerance require-ment and transient current of 20A,the target impedance will be 3m Ω (1.2 X 5%/20A). The PDS should have an impedance less than the target impedance over the entire frequency spectrum of interest or the upper cut off frequency. The upper cut off frequency is deter-mined by thefrequency that cannot escape the substrateparasitics of the device. Accord-ing to the generalrule of thumb,this is half the rise time of the transient current pulse. Thus if the transient cur-rent pulse has a rise time of 1ns, the upper cut-off frequency could be 500MHz. This limit could be further reduced by the substrate parasitics and varies from device to device.The PDS consists of switching regulators or voltage regulator modules (VRM), decoupling ca-pacitors, PCB and the device being decoupled, by virtue of its ability to filter out high frequency noise through substrate parasitics. Each of the above components of the PDS has a sphere of influence in a particular frequency band, as il-lustrated in Figure 1.The high current switching power supplies, with their slow load re-sponse times (typically of an A/µs), are effective from low frequencies to over hundreds of KHz.Bulk capacitors are effective from hundreds of KHz to a couple of by Vishnu Jwalapuram,WiproFigure 1 – Sphere of influence of components in particular frequency bandsFigure 2 – Loop formed by capacitor ESL, power planes, vias and connecting tracesE D AOnBoard Technology June 2004 - page 59MHz. In this range of frequencies, the equivalent series resistance (ESR) ofthe capacitors plays a dominating role with respect to the other parasitics. Capacitors with low ESR, high capacitance and flat impedance response are preferred. Several vendors offer multiple anode capacitors with very low ESR, less than 10m Ω, which exhibit excellent flat imped-ance versus frequency response. The amount of bulk capacitance required in this frequency range iscalculated by:C = I dt/dVwhere dt is the slowest rise time ofthe transient current. For example if there is a load transient current requirement of 20A to which the switching supply responds in 20µs and the PDS must remain within 5% of the supply voltage of 1.2V, this requires a bulk capacitance of 6666µF to supply the required current to the load as the power supply ramps up. The user needs to use several bulk capacitors in parallel to meet the capacitance value and the combined ESR of the combi-nation to meetthe target im-pedance.Ceramic ca-pacitors play a dominantrole in the fre-quency range from several tens of MHz to hun-dreds of MHz. Capacitors with low equivalent series inductance (ESL) should be chosen for effective de-coupling in this frequency band. The maximum allowable Induc-tance in this frequency range is given by:L = V dI/dtwhere dt is the fastest rise time of the transient current. For a tran-sient current requirement of 20A with rise time of 1ns and with PDS that must remain within 5% of the supply voltage of 1.2V, the maxi-mum allowable inductance is 3pH. PCB Power and GND plane pairs filter frequencies from close to a GHz and over, as they form em-bedded capacitance.Mounted inductance The mounted Inductance of the loop formed by the capacitor ESL,power p lanes, v iasand the connect-ing traces need to be minimisedfor the effective performance of the PDS at high frequencies. The ESL referred to above is only a part of the total loop inductance of the PDS as shown in Figure 2.Thecapacitor ESL can be minimised by choosing capacitors with low ESL from dif-ferent vendors. The length of the traces connecting the capacitor pads to the vias can be minimised either by building the via in the pads or routing the traces (Figure 3). Conventional routing of the traces from the capacitor pads to the vias (parallel to the length of capacitor) will increase the loop area. Though vias in the pad are a better option, this solution comes with an additional premium in terms of manufacture and assem-bly of the board. Mounted induc-tance can also be minimised by us-ing a PCB stack up that has Power and GND planes adjacent to the component layer.One of the following approaches can be followed for the design of PDS.Empirical approachThis is a simple and less time consuming approach and suits the majority of applications. With this approach, the target imped-ance of the PDS based on the load transient current requirement is determined first and then the necessary bulk capacitance for the lowest frequency component is calculated. For bulk capacitors, high capacitance, low ESR capaci-tors should be chosen to reduce ripple voltages. The maximum al-lowable inductance for the highest frequency component (fastest rise time) of the circuit must be found, and capacitors with the lowestESL must be chosen to reduce theFigure 3 – Mini-mising the length of traces con-necting capacitor pads to vias Figure 4 – Results of Single-Node simulation for a 1.2V power plane, 20A transient current and 5% ripple toler-ance Figure 5 – Results of a Multi-Node simulationE D AOnBoard Technology June 2004 - page 60number needed in parallel to meet the target impedance.Approach using Specctraquest The power distribution analyses can be done using the Cadence Specctraquest Power Integrity tool. The tool supports two simu-lation modes, Single-Node and Multi-Node simulations, akin to pre-layout and post-layout simu-lations of signal integrity. The Single-Node simulation validates whether the number of capacitors that have been chosen can main-tain the target impedance over the frequency band of interest. Al-though decoupling capacitors over entire frequency range are consid-ered in Single-Node simulations, their placement is not. Multi-Node simulation considers the place-ment of decoupling capacitors, board stack up, mounted induc-tance, loop inductance as well as noise source and power supply module placement.The output of a Single-Node simu-lation is a BOM-like report of ca-pacitors and a graph showing the response of the PDS over a range of frequencies. The output of the Multi-Node simulations is a graph showing the response of PDS after capacitor placement. The criterion for satisfactory performance is to get all the curves in the graph below the target impedance. The graph of Figure 4 shows the re-sults of Single-Node simulation for a 1.2V power plane, 20A transient current, 5% ripple tolerance.The blue graph shows the imped-ance of the power plane withoutthe decoupling capacitors andthe black one shows the imped-ance after considering the effectof the decoupling capacitors and the response of the switching sup-ply or VRM. The cut off frequency is shown by the dotted line and stands at 276MHz. The Single-Node simulation doesn’t take into account the placement and the corresponding parasitics, which include the ESL and mounted in-ductance.Table 1 shows some of the impor-tant parameters of the report filegenerated from Single Node simu-lations. The Single-Node simulation gives a complete list of decoupling capaci-tors that need to be placed around the device in question (Table 2). Once the Single-Node simulation has been performed and the tar-get impedance requirements are met, all the capacitors need to beplaced around the device being decoupled. The Multi-Node simu-lations need to be performed after placing all the capacitors around the device.The graph of Figure 5 shows the results of a Multi-Node simula-tion. Multi-Node simulations take into account the capacitors and the transient current sourceplacement, parasitics, including mounted inductance, ESL and the effective decoupling radius of the capacitor etc. The tool divides theentire power plane area around thedevice into zones or grids and pro-duces a wave for each of the zones (the graph reports many of these waves). These zones are user de-fined rectangular or square areas on the power plane. If the wave is under the target impedance in the graph, the decoupling is adequate for that particular zone. If any one of the waves exceeds the target impedance limit, as shown in thegraph, the capacitors need to bere-arranged to keep the impedancebelow this limit. The Power Integ-rity Analyses on the device need tobe performed at the beginning ofthe layout phase, before routing.Practical considerations The question of when to do the comprehensive Power Integrity Analyses using EDA tools is a tricky issue. One guideline is the differ-ence in the rate at which the power supply responds to the transient load current requirement. Gener-ally all the switching power sup-plies respond slowly (in an A/µs) against several Amps per nanosec-ond requirements of advanced high end ASICs or microprocessors.Another important practical con-sideration is the limit imposed by the vendor on the total capacitanceand the combined ESR at the in-ternal switching frequency of the power supply at the output of the module. EDA tools may not con-sider this limit and, exceeding it,may break the power supply intooscillations.The cost of decoupling is another factor that should be taken into consideration right from the start of ASIC design stage. For example decoupling a 20A/ns transient cur-rent (with a power supply respond-ing in 20µs) requires close to 600 caps to filter the frequencies up to 300MHz on the board. This could add up an additional cost for de-coupling. Table 1 – Important parameters from the report generated from a Single-Node simulationTable 2 – Sample table of decoupling capacitors.。