数字电子技术(课件)lec15
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2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
2
Lecture 15: Latches and Flip-Flops Basics
Inverter Bistable Circuit Look at the following circuit:
U4
Lecture 15: Latches and Flip-Flops Basics Chapter 7 Outline 7-1 7-2 **** 7-3 7-4 Latches Lecture 15 Edge-Triggered Flip-Flops Lecture 16 Flip-Flop Evolution Flip-Flop Operating Characteristics Flip-Flop Applications
Chapter 7 Latches, Flip-Flops, and Timers
11
Lecture 15: Latches and Flip-Flops Basics
Active-LOW S-R Latch Example If the S and R waveforms shown below are applied to the inputs of the active-LOW latch, determine the waveform on the Q output. Assume Q is initially “0”.
2012-3-28
我们如何用SR锁存器来解决 我们如何用 锁存器来解决 这个问题呢？ 这个问题呢？
Chapter 7 Latches, Flip-Flops, and Timers
13
Lecture 15: Latches and Flip-Flops Basics An Application of SR Latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
10
Lecture 15: Latches and Flip-Flops Basics
Three modes of latch operation and invalid condition
2012-3-28
Active high
S
R
Basic S-R latch
The latch will not change until EN is HIGH; but as long as it remains HIGH, the output is controlled by the state of the S and R inputs.
锁存器具有消除开关触点振荡的功能。 锁存器具有消除开关触点振荡的功能。
对于图(a)所示的简单电路， 对于图 所示的简单电路， 所示的简单电路 当开关从位置1切换到位置 切换到位置2 当开关从位置 切换到位置 其触点会发生振荡现象， 时，其触点会发生振荡现象， 从而导致输出电压的波动。 从而导致输出电压的波动。
Definition of Latches
The latch is a type of temporary storage device that has two stable states (bistable). Active-HIGH input latch The S-R (Set-Reset) latch S- (SetLogic expression reset
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
6
Lecture 15: Latches and Flip-Flops Basics
Active-LOW Input Latches
• S-R latch
Logic expression
Qn+1 = S + RQn S + R =1
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
1
Lecture 15: Latches and Flip-Flops Basics
Key Knowledge in Lecture 15 1. Concept of bistable circuit and its usage as a latch; 2. The state transition equations and diagrams of various types of latches and flip-flops, including R-S latch, D latch, and J-K flip-flop; 3. Three modes of latch operation and invalid condition; 4. Concept of edge triggered flip-flops; 5. Output waveform analysis of latches and flip-flops. Difficult Topics: 1. State transition equations of basic latches; 2. Output waveform analysis of latches and flip-flops.
0 0 1 1
2012-3-28
0 1 0 1
× 1 0 1
1 0 1 ×
9
Chapter 7 Latches, Flip-Flops, and Timers
Lecture 15: Latches and Flip-Flops Basics
Negative-OR Equivalent NAND Gate Latch
1. State transition truth table
2. State transition equation
Q = S + RQ S + R =1
n+ 1 n
Qn
s
SR
00 01
x x 1 1
11
0 1
10
0 0
Can be derived through
0 1
2012-3-28
Q n +1 S = 0 an R = 0 d RQn is n allow ot ed. Chapter 7 Latches, Flip-Flops, and Timers
Active-LOW input latch
S⋅R =0
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
7
Lecture 15: Latches and Flip-Flops Basics
Function Description of Basic Latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
15
Lecture 15: Latches and Flip-Flops Basics
The Gated S-R latch
A gated latch has an enable input EN.
Qn+1 = S + RQn S ⋅ R = 0
set
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
5
Lecture 15: Latches and Flip-Flops Basics
Two Versions of SET-RESET (S-R) Latches
锁存器具有消除开关触点振荡的功能。 锁存器具有消除开关触点振荡的功能。
对于图(a)所示的简单电路， 对于图 所示的简单电路， 图(b)的电路增加了一个 锁 所示的简单电路 的电路增加了一个SR锁 的电路增加了一个 当开关从位置1切换到位置 切换到位置2 当开关从位置 切换到位置 存器， 存器，即使开关触点发生振 其触点会发生振荡现象， 荡现象，输出却保持稳定。 时，其触点会发生振荡现象， 荡现象，输出却保持稳定。 从而导致输出电压的波动。 从而导致输出电压的波动。
8
Lecture 15: Latches and Flip-Flops Basics
Function Description of Basic Latches
3. State transition diagram
4. State transition excitation table Qn Qn+1 R S D D
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
3
Lecture 15: Latches and Flip-Flops Basics
Modification on Inverter Bistable Circuit Engineers improved the previous circuit by adding the controlled inputs.
不允许R和 同时 不允许 和S同时 接高电平， 接高电平，即： 要求R·S=0。 要求 。
GND
J1
J2
Key = S
Qn+1 = S +Qn + R = SR + RQ = S + RQ
n n
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
4
Lecture 15: Latches and Flip-Flops Basics
Notice that the S = 0, R = 0 condition is avoided.
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
12
Lecture 15: Latches and Flip-Flops Basics An Application of SR Latches
U4
-
VCC
+ V
U3
5V
+
4.116 DC 10MΩ
0.027 DC 10MΩ
V
GND
GND
Q
U1A
7402N*
Q
U1B
7402N
To know more about the circuit See demo Reset key
写出Q 写出 n+1的表达式
Key = R
Inverter replaced by NOR gate Set key-Βιβλιοθήκη VCC+ V
U3
+
4.116 DC 10MΩ
5V
0.027 DC 10MΩ
V
GND
GND
This circuit has no practical value
U5A
7404N*
U5B
7404N
See demo
The propagation delay of left inverter is smaller, so when the initial 0 level is on the input, it will output a high voltage faster than the right inverter, thus force the right inverter outputs a 0 logic level, and stays in this state forever.
Notice
不只是简单地更换了逻辑门！！ 不只是简单地更换了逻辑门！！ Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback that is characteristic of all latches and flip-flops. Open file F07-01 and verify the operation of both latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
14
Lecture 15: Latches and Flip-Flops Basics
The 74LS279 Set-Reset Latch
This is a quad S-R latch.
Notice that two of the latches each have two S inputs.
Chapter 7 Latches, Flip-Flops, and Timers
2
Lecture 15: Latches and Flip-Flops Basics
Inverter Bistable Circuit Look at the following circuit:
U4
Lecture 15: Latches and Flip-Flops Basics Chapter 7 Outline 7-1 7-2 **** 7-3 7-4 Latches Lecture 15 Edge-Triggered Flip-Flops Lecture 16 Flip-Flop Evolution Flip-Flop Operating Characteristics Flip-Flop Applications
Chapter 7 Latches, Flip-Flops, and Timers
11
Lecture 15: Latches and Flip-Flops Basics
Active-LOW S-R Latch Example If the S and R waveforms shown below are applied to the inputs of the active-LOW latch, determine the waveform on the Q output. Assume Q is initially “0”.
2012-3-28
我们如何用SR锁存器来解决 我们如何用 锁存器来解决 这个问题呢？ 这个问题呢？
Chapter 7 Latches, Flip-Flops, and Timers
13
Lecture 15: Latches and Flip-Flops Basics An Application of SR Latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
10
Lecture 15: Latches and Flip-Flops Basics
Three modes of latch operation and invalid condition
2012-3-28
Active high
S
R
Basic S-R latch
The latch will not change until EN is HIGH; but as long as it remains HIGH, the output is controlled by the state of the S and R inputs.
锁存器具有消除开关触点振荡的功能。 锁存器具有消除开关触点振荡的功能。
对于图(a)所示的简单电路， 对于图 所示的简单电路， 所示的简单电路 当开关从位置1切换到位置 切换到位置2 当开关从位置 切换到位置 其触点会发生振荡现象， 时，其触点会发生振荡现象， 从而导致输出电压的波动。 从而导致输出电压的波动。
Definition of Latches
The latch is a type of temporary storage device that has two stable states (bistable). Active-HIGH input latch The S-R (Set-Reset) latch S- (SetLogic expression reset
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
6
Lecture 15: Latches and Flip-Flops Basics
Active-LOW Input Latches
• S-R latch
Logic expression
Qn+1 = S + RQn S + R =1
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
1
Lecture 15: Latches and Flip-Flops Basics
Key Knowledge in Lecture 15 1. Concept of bistable circuit and its usage as a latch; 2. The state transition equations and diagrams of various types of latches and flip-flops, including R-S latch, D latch, and J-K flip-flop; 3. Three modes of latch operation and invalid condition; 4. Concept of edge triggered flip-flops; 5. Output waveform analysis of latches and flip-flops. Difficult Topics: 1. State transition equations of basic latches; 2. Output waveform analysis of latches and flip-flops.
0 0 1 1
2012-3-28
0 1 0 1
× 1 0 1
1 0 1 ×
9
Chapter 7 Latches, Flip-Flops, and Timers
Lecture 15: Latches and Flip-Flops Basics
Negative-OR Equivalent NAND Gate Latch
1. State transition truth table
2. State transition equation
Q = S + RQ S + R =1
n+ 1 n
Qn
s
SR
00 01
x x 1 1
11
0 1
10
0 0
Can be derived through
0 1
2012-3-28
Q n +1 S = 0 an R = 0 d RQn is n allow ot ed. Chapter 7 Latches, Flip-Flops, and Timers
Active-LOW input latch
S⋅R =0
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
7
Lecture 15: Latches and Flip-Flops Basics
Function Description of Basic Latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
15
Lecture 15: Latches and Flip-Flops Basics
The Gated S-R latch
A gated latch has an enable input EN.
Qn+1 = S + RQn S ⋅ R = 0
set
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
5
Lecture 15: Latches and Flip-Flops Basics
Two Versions of SET-RESET (S-R) Latches
锁存器具有消除开关触点振荡的功能。 锁存器具有消除开关触点振荡的功能。
对于图(a)所示的简单电路， 对于图 所示的简单电路， 图(b)的电路增加了一个 锁 所示的简单电路 的电路增加了一个SR锁 的电路增加了一个 当开关从位置1切换到位置 切换到位置2 当开关从位置 切换到位置 存器， 存器，即使开关触点发生振 其触点会发生振荡现象， 荡现象，输出却保持稳定。 时，其触点会发生振荡现象， 荡现象，输出却保持稳定。 从而导致输出电压的波动。 从而导致输出电压的波动。
8
Lecture 15: Latches and Flip-Flops Basics
Function Description of Basic Latches
3. State transition diagram
4. State transition excitation table Qn Qn+1 R S D D
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
3
Lecture 15: Latches and Flip-Flops Basics
Modification on Inverter Bistable Circuit Engineers improved the previous circuit by adding the controlled inputs.
不允许R和 同时 不允许 和S同时 接高电平， 接高电平，即： 要求R·S=0。 要求 。
GND
J1
J2
Key = S
Qn+1 = S +Qn + R = SR + RQ = S + RQ
n n
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
4
Lecture 15: Latches and Flip-Flops Basics
Notice that the S = 0, R = 0 condition is avoided.
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
12
Lecture 15: Latches and Flip-Flops Basics An Application of SR Latches
U4
-
VCC
+ V
U3
5V
+
4.116 DC 10MΩ
0.027 DC 10MΩ
V
GND
GND
Q
U1A
7402N*
Q
U1B
7402N
To know more about the circuit See demo Reset key
写出Q 写出 n+1的表达式
Key = R
Inverter replaced by NOR gate Set key-Βιβλιοθήκη VCC+ V
U3
+
4.116 DC 10MΩ
5V
0.027 DC 10MΩ
V
GND
GND
This circuit has no practical value
U5A
7404N*
U5B
7404N
See demo
The propagation delay of left inverter is smaller, so when the initial 0 level is on the input, it will output a high voltage faster than the right inverter, thus force the right inverter outputs a 0 logic level, and stays in this state forever.
Notice
不只是简单地更换了逻辑门！！ 不只是简单地更换了逻辑门！！ Notice that the output of each gate is connected to an input of the opposite gate. This produces the regenerative feedback that is characteristic of all latches and flip-flops. Open file F07-01 and verify the operation of both latches
2012-3-28
Chapter 7 Latches, Flip-Flops, and Timers
14
Lecture 15: Latches and Flip-Flops Basics
The 74LS279 Set-Reset Latch
This is a quad S-R latch.
Notice that two of the latches each have two S inputs.