09-48-1024;中文规格书,Datasheet资料

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PSD4235G2-70U;PSD4235G2-90U;PSD4235G2-90UI;中文规格书,Datasheet资料

February 2009 Rev 41/129PSD4235G2Flash in-system programmable (ISP)for 16-bit MCUs (5 V supply)Features■Dual bank Flash memories– 4 Mbit of Primary Flash memory (8 uniform sectors, 32K x 16)–256 Kbit Secondary Flash memory with 4 sectors–Concurrent operation: read from onememory while erasing and writing the other ■64 Kbit SRAM■PLD with macrocells–Over 3000 gates of PLD: CPLD and DPLD –CPLD with 16 output macrocells (OMCs) and 24 input macrocells (IMCs)–DPLD - user defined internal chip select decoding ■7 L/O ports with 52 I/O pins–52 individually configurable I/O port pins that can be used for the following functions:–MCU I/Os –PLD I/Os–Latched MCU address output –Special function l/Os–l/O ports may be configured as open-drain outputs ■In-system programming (ISP) with JTAG –Built-in JTAG compliant serial port allows full-chip In-System Programmability–Efficient manufacturing allow easy product testing and programmingUse low cost FlashLINK cable with PC■Page register–Internal page register that can be used to expand the microcontroller address space by a factor of 256–Programmable power management ●High endurance–100,000 Erase/write c ycles of Flash memory–1,000 Erase/WRITE Cycles of PLD –15 Y ear Data Retention ■Single supply voltage –5V ±10%■Memory speed–70ns Flash memory and SRAM access time ■Packages are ECOPACK ®Contents PSD4235G2Contents1Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1In-system programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.1First time programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.1.2Inventory build-up of pre-programmed devices . . . . . . . . . . . . . . . . . . . 121.1.3Expensive sockets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.2.1Simultaneous READ and WRITE to Flash memory . . . . . . . . . . . . . . . . 131.2.2Complex memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.2.3Separate Program and Data space . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131.3PSDsoft™ Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163PSD architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.1Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.2PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.3I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.4MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.5ISP via JTAG port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.6In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.7In-application programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.8Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223.9Power management unit (PMU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4Development system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5PSD register description and address offsets . . . . . . . . . . . . . . . . . . . 266Register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286.1Data-In registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . 286.2Data-out registers - port A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . 286.3Direction registers - ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . 286.4Control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2/129PSD4235G2Contents6.5Drive registers - Ports A, B, D, E, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.6Drive registers - Ports C and F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296.7Enable-Out registers - Ports A, B, C, F . . . . . . . . . . . . . . . . . . . . . . . . . . 296.8Input macrocells registers- ports A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . 296.9Output macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.10Mask macrocells A/B registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.11Flash Memory Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306.12Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.13JTAG Enable register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.15PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316.16PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326.17VM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336.18Memory_ID0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346.19Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Detailed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.1Memory blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357.2Primary Flash memory and Secondary Flash memory description . . . . . 367.2.1Memory block Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.2.2Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367.3Memory operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.1Power-up condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398.2Reading Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.3Read memory contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.4Read Primary Flash identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408.5Read Memory Sector Protection status . . . . . . . . . . . . . . . . . . . . . . . . . . 408.6Reading the Erase/Program status bits . . . . . . . . . . . . . . . . . . . . . . . . . . 408.7Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.8Toggle flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . 418.9Error flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428.10Erase timeout flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . 423/129Contents PSD4235G29Programming Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.1Data polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439.2Data toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449.3Unlock Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4510Erasing Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.1Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4710.2Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4810.3Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4811Specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.1Flash Memory Sector Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.2Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4911.3Reset (RESET) pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5013Memory Select signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.1Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.2Memory Select configuration for MCUs with separateProgram and Data spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5113.3Separate space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.4Combined space modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5213.580C51XA memory map example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 14Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 15Memory ID registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 16PLDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 17Decode PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5918Complex PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6118.1Output macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6218.2Product Term Allocator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 4/129PSD4235G2Contents18.3Loading and Reading the output macrocells (OMC) . . . . . . . . . . . . . . . . 6418.4The OMC Mask register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.5The output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6418.6Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6518.7External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6719MCU bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6919.1PSD interface to a multiplexed bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7019.2PSD interface to a non-multiplexed 8-bit bus . . . . . . . . . . . . . . . . . . . . . . 7119.3Data Byte Enable reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7119.4MCU bus interface examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7219.580C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7319.6MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7419.780C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7519.8H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7619.9MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7719.10C16x family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7720I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.1General port architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8020.2Port operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8120.3MCU I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.4PLD I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.5Address Out mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8220.6Address In mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.7Data Port mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.8Peripheral I/O mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8420.9JTAG in-system programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.10MCU Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8520.11Port Configuration registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.12Control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.13Direction register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8620.14Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8820.15Data In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 885/129Contents PSD4235G26/12920.16Data Out register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.17Output macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.18Mask macrocell register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.19Input macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 20.20Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 20.21Ports A, B and C - functionality and structure . . . . . . . . . . . . . . . . . . . . . 89 20.22Port D - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 20.23Port E - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 20.24Port F - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 20.25Port G - functionality and structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9221Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9421.1Automatic Power-down (APD) Unit and Power-down mode . . . . . . . . . . . 9521.2Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9521.3Other power saving options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.4PLD power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9621.5PSD Chip Select input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.6Input clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9721.7Input control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9822Power-on Reset, Warm Reset and Power-down . . . . . . . . . . . . . . . . . . 9922.1Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.2Warm Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9922.3I/O pin, register and PLD status at Reset . . . . . . . . . . . . . . . . . . . . . . . . . 9922.4Reset of Flash Memory Erase and Program cycles . . . . . . . . . . . . . . . . . 9923Programming in-circuit using the JTAG serial interface . . . . . . . . . . 10123.1Standard JTAG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10123.2JTAG extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10223.3Security and Flash memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . 102 24Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 25Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105PSD4235G2Contents 26DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 27Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 28Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Appendix A Pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 29Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1287/129List of tables PSD4235G2 List of tablesTable 1.Pin names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.Pin description (for the LQFP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.PLD I/O. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 4.JTAG signals on port E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 5.Methods of programming different functional blocks of the PSD . . . . . . . . . . . . . . . . . . . . 23 Table 6.Register address offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 7.Data-In registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 8.Data-Out registers - Ports A, B, C, D, E, F, G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 9.Direction registers - Ports A, B, C, D, E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 10.Control registers - Ports E, F, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 11.Drive registers - Ports A, B, D, E, G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 12.Drive registers - Ports C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 13.Enable-Out registers - Ports A, B, C, F. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 14.Input macrocell registers - Port A, B, C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Table 15.Output macrocells A register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 16.Output macrocells B register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 17.Mask macrocells A register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 18.Mask macrocells B register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 19.Flash Memory Protection register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Table 20.Flash Boot Protection register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 21.JTAG Enable register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 22.Page register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 23.PMMR0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 24.PMMR2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 25.VM register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Table 26.Memory_ID0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 27.Memory_ID1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 28.Memory block size and organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 29.Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 30.Status bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 31.Status bits for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Table 32.DPLD and CPLD inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Table 33.Output macrocell Port and Data bit Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Table 34.MCUs and their control signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Table 35.16-bit data bus with BHE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Table 36.16-bit data bus with WRH and WRL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 37.16-bit data bus with SIZ0, A0 (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 38.16-bit data bus with LDS, UDS (Motorola MCU). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Table 39.Port operating modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Table 40.Port operating mode settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 41.I/O port latched address output assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 42.Port Configuration registers (PCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 43.Port Pin Direction Control, output Enable P.T. not defined. . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 44.Port Pin Direction Control, output Enable P.T. defined. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 45.Port direction assignment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 46.Drive register pin assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 47.Port Data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 48.Effect of Power-down mode on ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 8/129PSD4235G2List of tables Table 49.PSD timing and standby current during Power-down mode. . . . . . . . . . . . . . . . . . . . . . . . 96 Table 50.APD counter operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table 51.Status During Power-On Reset, Warm Reset and Power-down mode. . . . . . . . . . . . . . . . 99 Table 52.JTAG port signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Table 53.Absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Table 54.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode on). . . . . . . 107 Table 55.Example of PSD typical power calculation at V CC = 5.0V (with Turbo mode off). . . . . . . 108 Table 56.Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 57.AC signal letters for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 58.AC signal behavior symbols for PLD timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Table 59.AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 60.Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Table 61.DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Table 62.CPLD Combinatorial timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Table 63.CPLD macrocell Synchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Table 64.CPLD macrocell Asynchronous clock mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Table 65.Input macrocell timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Table 66.Program, WRITE and Erase times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Table 67.READ timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 Table 68.WRITE timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Table 69.Port F Peripheral Data Mode Read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 70.Port F Peripheral Data Mode Write timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 71.Reset (RESET) timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Table 72.Power-down timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Table 73.ISC timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Table 74.LQFP80 - 80-lead plastic thin, quad, flat package mechanical data. . . . . . . . . . . . . . . . . 124 Table 75.Ordering information scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Table 76.PSD4235G2 LQFP80. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Table 77.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1289/129。

09201;中文规格书,Datasheet资料

• • • • • •
Premium metal expansion wrist strap Comfortable, designed not to pinch or pull hair Durable metal band Long wearing, easy to clean Superior contact with skin For reliable removal of generated static charges Non-flaking or scratching laminated insulator on all external surfaces Protects wearers from electrical hazards; provides many years of product life Medical grade 300 series stainless steel used for all metal parts Eliminates allergic skin reaction for most people UL Listed Note: This product is not recommended for use on equipment with operating voltage exceeding 250 VAC. CAUTION: The ESD Series is for electrostatic control. It will not reduce or increase your risk of receiving electric shock when using or working on electrical equipment. Follow the same precautions you would use without wrist straps, including: • Make certain that equipment having a grounding type plug is properly grounded. • Make certain that you are not in contact with grounded objects other than through the ESD Series. Date coded Providing lot tractability to ensure quality control Superior resistor connection strain relief Superior reliability. Greatly exceeds ESD S1.1 Bending Life Test. Tested at over 1,000,000 cycles vs. the 16,000 requirement Covered by one or more of the following patents: Wristband: 5,036,423; 5,568,351 Coil Cord: 5,951,337 Superior warranty See details of 1 year Limited Warranty at /Warranty.aspx Made in America

AD2S1205WSTZ;AD2S1205YSTZ;ADW71205WSTZ-RL;ADW71205WSTZ;ADW71205YSTZ;中文规格书,Datasheet资料

12-Bit RDCwith Reference OscillatorAD2S1205 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2007–2010 Analog Devices, Inc. All rights reserved.FEATURESComplete monolithic resolver-to-digital converter (RDC) Parallel and serial 12-bit data portsSystem fault detection±11 arc minutes of accuracyInput signal range: 3.15 V p-p ± 27%Absolute position and velocity outputs1250 rps maximum tracking rate, 12-bit resolution Incremental encoder emulation (1024 pulses/rev) Programmable sinusoidal oscillator on boardSingle-supply operation (5.00 V ± 5%)−40°C to +125°C temperature rating44-lead LQFP4 kV ESD protectionQualified for automotive applications APPLICATIONSAutomotive motion sensing and controlHybrid-electric vehiclesElectric power steeringIntegrated starter generator/alternatorIndustrial motor controlProcess control FUNCTIONAL BLOCK DIAGRAMFigure 1.GENERAL DESCRIPTIONThe AD2S1205 is a complete 12-bit resolution tracking resolver-to-digital converter that contains an on-board programmable sinusoidal oscillator providing sine wave excitation for resolvers.The converter accepts 3.15 V p-p ± 27% input signals on the Sin and Cos inputs. A Type II tracking loop is employed to track the inputs and convert the input Sin and Cos information into a digital representation of the input angle and velocity. The maximum tracking rate is a function of the external clock frequency. The performance of the AD2S105 is specified across a frequency range of 8.192 MHz ± 25%, allowing a maximum tracking rate of 1250 rps. PRODUCT HIGHLIGHTS1.Ratiometric Tracking Conversion. The Type II trackingloop provides continuous output position data withoutconversion delay. It also provides noise immunity andtolerance of harmonic distortion on the reference andinput signals.2.System Fault Detection. A fault detection circuit can senseloss of resolver signals, out-of-range input signals, inputsignal mismatch, or loss of position tracking.3.Input Signal Range. The Sin and Cos inputs can acceptdifferential input voltages of 3.15 V p-p ± 27%.4.Programmable Excitation Frequency. Excitation frequencyis easily programmable to 10 kHz, 12 kHz, 15 kHz, or 20 kHz by using the frequency select pins (the FS1 and FS2 pins).5.Triple Format Position Data. Absolute 12-bit angular positiondata is accessed via either a 12-bit parallel port or a 3-wire serial interface. Incremental encoder emulation is in standard A-quad-B format with direction output available.6.Digital Velocity Output. 12-bit signed digital velocity accessedvia either a 12-bit parallel port or a 3-wire serial interface.AD2S1205Rev. A | Page 2 of 20TABLE OF CONTENTSFeatures .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Resolver Format Signals ................................................................... 8 Theory of Operation ........................................................................ 9 Fault Detection Circuit ................................................................ 9 Monitor Signal .............................................................................. 9 Loss of Signal Detection .............................................................. 9 Signal Degradation Detection .................................................. 10 Loss of Position Tracking Detection ........................................ 10 Responding to a Fault Condition ............................................. 10 False Null Condition .................................................................. 10 On-Board Programmable Sinusoidal Oscillator .................... 11 Synthetic Reference Generation ............................................... 11 Charge-Pump Output ................................................................ 11 Connecting the Converter ........................................................ 11 Clock Requirements ................................................................... 12 Absolute Position and Velocity Output ................................... 12 Parallel Interface ......................................................................... 12 Serial Interface ............................................................................ 14 Incremental Encoder Outputs .................................................. 16 Supply Sequencing and Reset ................................................... 16 Circuit Dynamics ........................................................................... 17 Loop Response Model ............................................................... 17 Sources of Error .......................................................................... 18 Connecting to the DSP .............................................................. 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 20 Automotive Products .. (20)REVISION HISTORY5/10—Rev. 0 to Rev. AChanges to Features Section............................................................ 1 Changes to Input Bias Current Parameter and InputImpedance Parameter ...................................................................... 3 Changes to Table 2 ............................................................................ 5 Changes to Loss of Signal Detection Section ................................ 9 Changes to Connecting the Converter Section and Figure 5 ... 11 Change to t 6 Max Value in Table 6 ............................................... 13 Changes to t 9 and t 10 Max Values Table 7 .................................... 15 Changes to Ordering Guide .......................................................... 20 Added Automotive Products Section .......................................... 20 1/07—Revision 0: Initial VersionAD2S1205SPECIFICATIONSAV DD = DV DD = 5.0 V ± 5% at −40°C to +125°C, CLKIN = 8.192 MHz ± 25%, unless otherwise noted.Rev. A | Page 3 of 20AD2S12051 The voltages for Sin, SinLO, Cos, and CosLO relative to AGND must be between 0.2 V and AV DD.Rev. A | Page 4 of 20AD2S1205Rev. A | Page 5 of 20ABSOLUTE MAXIMUM RATINGSTable 2.Parameter RatingSupply Voltage (V DD ) −0.3 V to +7.0 VSupply Voltage (AV DD ) −0.3 V to +7.0 VInput Voltage −0.3 V to V DD + 0.3 VOutput Voltage Swing −0.3 V to V DD + 0.3 VInput Current to Any Pin Except Supplies 1 ±10 mAOperating Temperature Range (Ambient) −40°C to +125°C Storage Temperature Range −65°C to +150°C1Transient currents of up to 100 mA do not cause latch-up.Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stressrating only; functional operation of the device at these or anyother conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods may affectdevice reliability. ESD CAUTIONAD2S1205Rev. A | Page 6 of 2006339-002PIN CONFIGURATION AND FUNCTION DESCRIPTIONSR E F O U T44R E F B Y P43C o s L O40S i n L O38A G N D42A G N D36A V D D39E X C35E X C34C o s41S i n37DV DD 1RD 2CS 3SAMPLE4RDVEL 5SOE 6DB11/SO 7DB10/SCLK8DB99DB810DB71133FS232FS131LOT 30DOS 29AD2S1205TOP VIEW (Not to Scale)DIR 28NM 27B 26A 25CPO 24DGND23DB 612D B 513D B 414D B 315D G N D16D V D D17D B 218D B 119D B 020X T A L O U T21C L K I N22Figure 2. Pin ConfigurationAD2S1205Rev. A | Page 7 of 20AD2S1205Rev. A | Page 8 of 20RESOLVER FORMAT SIGNALS06339-003V b = V s × Sin(ωt) × Sin(θ)(A) CLASSICAL RESOLVERs × Sin(ωt) × Cos(θ)V b = V s × Sin(ωt) × Sin(θ)(B)VARIABLE RELUCTANCE RESOLVERs × Sin(ωt) × Cos(θ)Figure 3. Classical Resolver vs. Variable Reluctance ResolverA classical resolver is a rotating transformer that typically has a primary winding on the rotor and two secondary windings on the stator. A variable reluctance resolver, on the other hand, has the primary and secondary windings on the stator and no windings on the rotor, as shown in Figure 3; however, the saliency in this rotor design provides the sinusoidal variation in the secondary coupling with the angular position. For both designs, the resolver output voltages (S3 − S1, S2 − S4) are as follows:Sinθt Sin E S1S30×ω=−)( (1)Cosθt Sin E S4S20×ω=−)(where:θ is the shaft angle.Sin(ωt) is the rotor excitation frequency. E 0 is the rotor excitation amplitude.The stator windings are displaced mechanically by 90° (see Figure 3). The primary winding is excited with an ac reference. The amplitude of subsequent coupling onto the secondary windings is a function of the position of the rotor (shaft) relative to the stator. The resolver therefore produces two output voltages (S3 − S1, S2 − S4), modulated by the sine and cosine of the shaft angle. Resolver format signals refer to the signals derived from the output of a resolver, as shown in Equation 1. Figure 4 illustrates the output format. 06339-0040°R2 – R4(REFERENCE)90°180°θ270°360°Figure 4. Electrical Resolver RepresentationAD2S1205Rev. A | Page 9 of 20THEORY OF OPERATIONThe AD2S1205’s operation is based on a Type II tracking closed-loop principle. The digitally implemented tracking loop continually tracks the position and velocity of the resolver without the need for external convert and wait states. As the resolver moves through a position equivalent to the least significant bit weighting, the tracking loop output is updated by 1 LSB.The converter tracks the shaft angle (θ) by producing an output angle (ϕ) that is fed back and compared with the input angle (θ); the difference between the two angles is the error, which is driven towards 0 when the converter is correctly tracking the input angle. T o measure the error, S3 − S1 is multiplied by Cosϕ and S2 − S4 is multiplied by Sinϕ to giveS4 S2for )(S1S3for )(00−×−×SinφCosθωt Sin E CosφSinθωt Sin E (2)The difference is taken, giving)()(0SinφCosθCos Sinθωt Sin E −φ× (3)This signal is demodulated using the internally generated synthetic reference, yielding)(0φ−φSin CosθCos SinθE (4)Equation 4 is equivalent to E 0Sin (θ − ϕ), which is approximately equal to E 0(θ − ϕ) for small values of θ − ϕ, where θ − ϕ is the angular error. The value E 0(θ − ϕ) is the difference between the angular error of the rotor and the digital angle output of the converter. A phase-sensitive demodulator, some integrators, and a compen-sation filter form a closed-loop system that seeks to null the error signal. If this is accomplished, ϕ equals the resolver angle, θ, within the rated accuracy of the converter. A Type II tracking loop is used so that constant velocity inputs can be tracked without inherent error.For more information about the operation of the converter, see the Circuit Dynamics section.FAULT DETECTION CIRCUITThe AD2S1205 fault detection circuit can sense loss of resolver signals, out-of-range input signals, input signal mismatch, or loss of position tracking; however, the position indicated by the AD2S1205 may differ significantly from the actual shaft position of the resolver.MONITOR SIGNALThe AD2S1205 generates a monitor signal by comparing the angle in the position register to the incoming Sin and Cos signals from the resolver. The monitor signal is created in a similar fashion to the error signal (described in the Theory of Operation section). The incoming Sinθ and Cosθ signals are multiplied by the Sin and Cos of the output angle, respectively, and then these values are added together:)()(CosφCosθA2SinφSinθA1Monitor ××+××= (5)where:A1 is the amplitude of the incoming Sin signal (A1 × Sinθ). A2 is the amplitude of the incoming Cos signal (A2 × Cosθ).θ is the resolver angle.ϕ is the angle stored in the position register.Note that Equation 5 is shown after demodulation with thecarrier signal Sin(ωt) removed. Also note that for a matchedinput signal (that is, a no fault condition), A1 is equal to A2.When A1 is equal to A2 and the converter is tracking (therefore, θ is equal to ϕ), the monitor signal output has aconstant magnitude of A1 (Monitor = A1 × (Sin 2θ + Cos 2θ) = A1), which is independent of the shaft angle. When A1 does notequal A2, the monitor signal magnitude alternates between A1 and A2 at twice the rate of the shaft rotation. The monitor signal is used to detect degradation or loss of input signals. LOSS OF SIGNAL DETECTIONLoss of signal (LOS) is detected when either resolver input (Sin or Cos) falls below the specified LOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed minimum value. Without the use of external circuitry, the AD2S1205 can detect the loss of up to three of the four connections from the resolver. The addition of two external 68 kΩ resistors, as outlined in Figure 5, ensures that the loss of all 4 connections, that is, complete removal of the resolver, may also be detected. LOS is indicated by both DOS and LOT latching as logic low outputs. The DOS and LOT pins are reset to the no fault state by a rising edge of SAMPLE . The LOS condition has priority over both the DOS and LOT conditions, as shown in . LOS is indicated within 57° of the angular output error (worst case).Table 4AD2S1205Rev. A | Page 10 of 20SIGNAL DEGRADATION DETECTIONDegradation of signal (DOS) is detected when either resolver input (Sin or Cos) exceeds the specified DOS Sin/Cos threshold. The AD2S1205 detects this by comparing the monitor signal to a fixed maximum value. In addition, DOS is detected when the amplitudes of the Sin and Cos input signals are mismatched by more than the specified DOS Sin/Cos mismatch. This is identified because the AD2S1205 continuously stores the minimum and maximum magnitude of the monitor signal in internal registers and calculates the difference between these values. DOS is indicated by a logic low on the DOS pin and is not latched when the input signals exceed the maximum input level. When DOS is indicated due to mismatched signals, the output is latched low until a rising edge of SAMPLE resets the stored minimum and maximum values. The DOS condition has priority over the LOT condition, as shown in . DOS is indicated within 33° of the angular output error (worst case).Table 4LOSS OF POSITION TRACKING DETECTIONLoss of tracking (LOT) is detected when • The internal error signal of the AD2S1205 exceeds 5°. • The input signal exceeds the maximum tracking rate. •The internal position (at the position integrator) differs from the external position (at the position register) by more than 5°.LOT is indicated by a logic low on the LOT pin and is not latched. LOT has a 4° hysteresis and is not cleared until the internal error signal or internal/external position mismatch is less than 1°. When the maximum tracking rate is exceeded, LOT is cleared only if the velocity is less than the maximum tracking rate and the internal/external position mismatch is less than 1°. LOT can be indicated for step changes in position (such as after a RESET signal is applied to the AD2S1205), or for accelerations of >~65,000 rps 2. It is also useful as a built-in test to indicate that the tracking converter is functioningproperly. The LOT condition has lower priority than both the DOS and LOS conditions, as shown in . The LOT and DOS conditions cannot be indicated at the same time. Table 4Table 4. Fault Detection DecodingConditionDOS Pin LOT Pin Order of Priority Loss of Signal (LOS)0 0 1 Degradation of Signal (DOS) 0 1 2 Loss of Tracking (LOT) 1 0 3 No Fault1 1RESPONDING TO A FAULT CONDITIONIf a fault condition (LOS, DOS, or LOT) is indicated by the AD2S1205, the output data is presumed to be invalid. Even if a RESET or SAMPLE pulse releases the fault condition and is not immediately followed by another fault, the output data may be corrupted. As discussed previously, there are some fault conditions with inherent latency. If the device fault is cleared, there may be some latency in the resolver’s mechanical position before the fault condition is reindicated.When a fault is indicated, all output pins still provide data, although the data may or may not be valid. The fault condition does not force the parallel, serial, or encoder outputs to a known state. Response to specific fault conditions is a system-level requirement. The fault outputs of the AD2S1205 indicate that the device has sensed a potential problem with either the internal or external signals of the AD2S1205. It is the responsibility of the system designer to implement the appropriate fault-handling schemes within the control hardware and/or algorithm of a given appli-cation based on the indicated fault(s) and the velocity or position data provided by the AD2S1205.FALSE NULL CONDITIONResolver-to-digital converters that employ Type II tracking loops based on the previously stated error equation (see Equation 4 in the Theory of Operation section) can suffer from a condition known as a false null. This condition is caused by a metastable solution to the error equation when θ − ϕ = 180°. The AD2S1205 is not susceptible to this condition because its hysteresis is implemented external to the tracking loop. As a result of the loop architecture chosen for the AD2S1205, the internal error signal constantly has some movement (1 LSB per clock cycle); therefore, in a metastable state, the converter moves to anunstable condition within one clock cycle. This causes the tracking loop to respond to the false null condition as if it were a 180° step change in input position (the response time is the same, as specified in the Dynamic Performance section of Table 1). Therefore, it is impossible to enter the metastable condition after the start-up sequence if the resolver signals are valid.分销商库存信息:ANALOG-DEVICESAD2S1205WSTZ AD2S1205YSTZ ADW71205WSTZ-RL ADW71205WSTZ ADW71205YSTZ EVAL-AD2S1205SDZ。

0940904030;中文规格书,Datasheet资料

Quick Disconnect, 1 Cut, Cover for female terminal, for (0.50-2.50mm²) 14-20 AWG Wire, Accepts 6.35 x 0.81mm Tab
Documents: Drawing (PDF) Product Specificatio源自 PS-94090-001 (PDF)
General
Product Family Series Crimp Quality Equipment Product Name Type UPC
Physical
Barrel Type Breakaway Circuits (maximum) Color - Resin Gender Glow-Wire Compliant Insulation Lock to Mating Part Material - Resin Net Weight Number of Rows Orientation Packaging Type Polarized to Mating Part Tab Thickness Tab Width Temperature Range - Operating Wire Insulation Diameter Wire Size AWG Wire Size mm² N/A No 1 Natural Female No None None Nylon 0.480/g 1 Straight Bag Yes N/A N/A -40°C to +105°C 2.00-4.30mm 14, 16, 18, 20 0.50-2.50
This document was generated on 08/13/2012
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KAD5510P-12Q48;KAD5510P-17Q48;KAD5510P-21Q48;KAD5510P-25Q48;中文规格书,Datasheet资料

Low Power 10-Bit, 250/210/170/125MSPS ADCKAD5510PThe KAD5510P is a family of low power, high performance 10-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. TheKAD5510P is part of a pin-compatible portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging from 125MSPS to 500MSPS.A serial peripheral interface (SPI) port allows for extensiveconfigurability, as well as fine control of various parameters such as gain and offset.Digital output data is presented in selectable LVDS or CMOS formats. The KAD5510P is available in a 48-contact QFN package with an exposed paddle. Operating from a 1.8V supply, performance isspecified over the full industrial temperature range (-40°C to +85°C).Key Specifications•SNR = 60.7dBFS for f IN = 105MHz (-1dBFS)•SFDR = 86.1dBc for f IN = 105MHz (-1dBFS)•Total Power Consumption-234/189mW @ 250/125MSPS (DDR Mode)Related Literature•See FN6811, KAD5510P-50, “10-Bit, 500MSPS A/D Converter”Features•1.5GHz Analog Input Bandwidth •60fs Clock Jitter•Programmable Gain, Offset and Skew Control •Over-Range Indicator•Selectable Clock Divider: ÷1, ÷2 or ÷4•Clock Phase Selection •Nap and Sleep Modes•Two’s Complement, Gray Code or Binary Data Format •DDR LVDS-Compatible or LVCMOS Outputs •Programmable Built-in Test Patterns •Single-Supply 1.8V Operation •Pb-Free (RoHS Compliant)Applications•Power Amplifier Linearization•Radar and Satellite Antenna Array Processing •Broadband Communications •High-Performance Data Acquisition •Communications Test Equipment •WiMAX and Microwave ReceiversSINGLE-TONE SPECTRUM @ 105MHz (250MSPS)0M 20M 40M 60M 80M 100M 120M-120-100-80-60-40-200FREQUENCY (Hz)Ain = -1.0dBFS SNR = 60.7dBFS SFDR = 85.9dBc SINAD = 60.7dBFSA M P L I T U D E (dB F S )Pin ConfigurationKAD5510P (48 LD QFN)TOP VIEWPin-Compatible FamilyMODELRESOLUTIONSPEED (MSPS)PACKAGEQ48EP Q72EP KAD5514P-25/21/17/1214250/210/170/125XX KAD5512P-5012500X KAD5512P-25/21/17/1212250/210/170/125X X KAD5512HP-25/21/17/1212250/210/170/125XX KAD5510P-5010500XKAD5510P-25/21/17/12 10250/210/170/125X FIGURE 1.PIN CONFIGURATIONA V S SA V D DS D I OS C L K123456789101112363534333231302928272625131415161718192021222324484746454443424140393837C S BS D O O V S SO R PO R N D 4P D 4N O V D D A V D DC L K PC L K NN A P S L PA V D DR E S E T NO V S SO V D DD N CD N CD N CD N CD3P D3N D2P D2N CLKOUTP CLKOUTNRLVDS OVSS D1P D1N D0P D0NAVDD DNC DNC DNC AVSS VINNVINP AVSS AVDD VCM DNC AVSSCONNECT THERMAL PAD TO AVSSPADPin Descriptions - 48 Ld QFNPIN NUMBER LVDS [LVCMOS] NAME LVDS [LVCMOS] FUNCTION 1, 9, 13, 17, 47AVDD 1.8V Analog Supply2, 3, 4, 11, 21, 22,23, 24DNC Do Not Connect5, 8, 12, 48AVSS Analog Ground6, 7VINN, VINP Analog Input Negative, Positive10VCM Common Mode Output14, 15CLKP, CLKN Clock Input True, Complement16NAPSLP Tri-Level Power Control (Nap, Sleep modes)18RESETN Power On Reset (Active Low, see page16) 19, 29, 42OVSS Output Ground20, 37OVDD 1.8V Output Supply25D0N[NC]LVDS DDR Logical Bits 1, 0 Output Complement [NC in LVCMOS]26D0P[D0]LVDS DDR Logical Bits 1, 0 Output True [CMOS DDR Logical Bits 1, 0 in LVCMOS]27D1N[NC]LVDS DDR Logical Bits 3, 2 Output Complement [NC in LVCMOS]28D1P[D1]LVDS DDR Logical Bits 3, 2 Output True [CMOS DDR Logical Bits 3, 2 in LVCMOS]30RLVDS LVDS Bias Resistor (Connect to OVSS with a 10kΩ, 1% resistor)31CLKOUTN[NC]LVDS Clock Output Complement [NC in LVCMOS]32CLKOUTP[CLKOUT]LVDS Clock Output True [LVCMOS CLKOUT]33D2N[NC]LVDS DDR Logical Bits 5, 4 Output Complement [NC in LVCMOS]34D2P[D2]LVDS DDR Logical Bits 5, 4 Output True [CMOS DDR Logical Bits 5, 4 in LVCMOS]35D3N[NC]LVDS DDR Logical Bits 7, 6 Output Complement [NC in LVCMOS]36D3P[D3]LVDS DDR Logical Bits 7, 6 Output True [CMOS DDR Logical Bits 7, 6 in LVCMOS]38D4N[NC]LVDS DDR Logical Bits 9, 8 Output Complement [NC in LVCMOS]39D4P[D4]LVDS DDR Logical Bits 9, 8 Output True [CMOS DDR Logical Bits 9, 8 in LVCMOS]40ORN[NC]LVDS Over Range Complement [NC in LVCMOS]41ORP[OR]LVDS Over Range True [LVCMOS Over Range]43SDO SPI Serial Data Output (4.7kΩ pull-up to OVDD is required) 44CSB SPI Chip Select (active low)45SCLK SPI Clock46SDIO SPI Serial Data Input/OutputPAD (Exposed Paddle)AVSS Analog Ground (Connect to a low thermal impedance analog ground plane withmultiple vias)NOTE:LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection).Ordering InformationPART NUMBER (Notes 1, 2)PARTMARKINGSPEED(MSPS)TEMP. RANGE(°C)PACKAGE(Pb-Free)PKG.DWG.#KAD5510P-25Q48KAD5510P-25 Q48EP-I250-40 to +8548 Ld QFN L48.7x7EKAD5510P-21Q48KAD5510P-21 Q48EP-I210-40 to +8548 Ld QFN L48.7x7EKAD5510P-17Q48 KAD5510P-17 Q48EP-I170-40 to +8548 Ld QFN L48.7x7EKAD5510P-12Q48 KAD5510P-12 Q48EP-I125-40 to +8548 Ld QFN L48.7x7ENOTES:1.These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% mattetin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.2.For Moisture Sensitivity Level (MSL), please see device information page for KAD5510P. For more information on MSL please see techbrief TB363.Table of ContentsAbsolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Thermal Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 User-Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 VCM Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Over Range Indicator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Nap/Sleep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Serial Peripheral Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Indexed Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Global Device Configuration/Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2448 Pin Package Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24SPI Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 PCB Layout Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Split Ground and Power Planes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bypass and Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LVDS Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 LVCMOS Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Unused Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 General PowerPAD Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31Absolute Maximum Ratings Thermal InformationAVDD to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V OVDD to OVSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to 2.1V AVSS to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V Analog Inputs to AVSS. . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Clock Inputs to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to AVDD + 0.3V Logic Input to AVSS . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Logic Inputs to OVSS . . . . . . . . . . . . . . . . . . . . . . . . . . -0.4V to OVDD + 0.3V Thermal Resistance (Typical)θJA(°C/W)θJC(°C/W) 48 Ld QFN (Notes 3, 4) . . . . . . . . . . . . . . . . 250.5 Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below /pbfree/Pb-FreeReflow.asp Recommended Operating ConditionsAVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8V Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°CCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.NOTES:3.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TechBrief TB379.4.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V,OVDD=1.8V, T A=-40°C to +85°C (typical specifications at +25°C), A IN = -1dBFS, f SAMPLE=Maximum Conversion Rate (per speed grade). Boldface limits apply over the operating temperature range, -40°C to +85°C.PARAMETER SYMBOL CONDITIONSKAD5510P-25KAD5510P-21KAD5510P-17KAD5510P-12UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAXDC SPECIFICATIONSAnalog InputFull-Scale AnalogInput RangeV FS Differential 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54 1.40 1.47 1.54V P-P Input Resistance R IN Differential1000100010001000ΩInput Capacitance C IN Differential 1.8 1.8 1.8 1.8pFFull Scale Range Temp. Drift A VTC Full Temp90909090ppm/°CInput Offset Voltage V OS-10±210-10±210-10±210-10±210mV Gain Error E G±0.6±0.6±0.6±0.6% Common-ModeOutput VoltageV CM435535635435535635435535635435535635mVCommon-Mode Input Current (per pin)I CM 2.5 2.5 2.5 2.5µA/MSPSClock InputsInput CommonMode Voltage0.90.90.90.9VCLKP,CLKN InputSwing1.8 1.8 1.8 1.8V Power Requirements1.8V Analog SupplyVoltageAVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V1.8V Digital SupplyVoltageOVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9V1.8V Analog SupplyCurrentI AVDD9096838977826974mA1.8V Digital Supply Current (DDR) (Note 5)IOVDD3mA LVDS3945384536403540mAPower Supply Rejection Ratio PSRR30MHz, 200mV P-Psignal on AVDD-36-36-36-36dBTotal Power DissipationNormal Mode (DDR)P D3mA LVDS234254219242204220189205mW Nap Mode P D8495809178887484mW Sleep Mode P D CSB at logic high26262626mWNap Mode Wakeup Time (Note 6)Sample ClockRunning1111µsSleep Mode Wakeup Time(Note 6)Sample ClockRunning1111msAC SPECIFICATIONSDifferentialNonlinearityDNL-0.5±0.120.5-0.5±0.170.5-0.5±0.170.5-0.5±0.170.5LSB Integral Nonlinearity INL-0.75±0.20.75-0.75±0.30.75-0.75±0.30.75-0.75±0.30.75LSBMinimumConversion Rate(Note 7)f S MIN40404040MSPSMaximumConversion Ratef S MAX250210170125MSPSSignal-to-Noise Ratio SNR f IN = 10MHz60.860.861.061.0dBFSf IN = 105MHz59.560.760.060.960.261.060.261.0dBFSf IN = 190MHz60.660.860.960.9dBFSf IN = 364MHz60.560.660.760.7dBFSf IN = 695MHz59.960.060.160.0dBFSf IN = 995MHz59.159.259.359.2dBFSSignal-to-Noise and Distortion SINAD f IN = 10MHz60.760.860.961.0dBFSf IN = 105MHz59.360.759.960.960.060.960.061.0dBFSf IN = 190MHz60.560.860.860.9dBFSf IN = 364MHz60.460.560.660.4dBFSf IN = 695MHz56.557.356.956.6dBFSf IN = 995MHz49.846.947.749.1dBFSEffective Number of Bits ENOB f IN = 10MHz9.89.89.89.8Bitsf IN = 105MHz9.59.89.69.89.69.89.69.8Bitsf IN = 190MHz9.89.89.89.8Bitsf IN = 364MHz9.79.89.89.7Bitsf IN = 695MHz9.19.29.29.1Bitsf IN = 995MHz8.07.57.67.9BitsPARAMETER SYMBOL CONDITIONSKAD5510P-25KAD5510P-21KAD5510P-17KAD5510P-12UNITS MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAXSpurious-Free Dynamic RangeSFDRf IN = 10MHz 83.082.078.079.0dBc f IN = 105MHz 73.086.173.086.673.084.673.085.8dBc f IN = 190MHz 78.080.181.081.2dBc f IN = 364MHz 76.277.177.972.1dBc f IN = 695MHz 60.861.961.061.1dBc f IN = 995MHz50.247.247.949.4dBc Intermodulation Distortion IMDf IN = 70MHz -86.1-92.1-94.5-95.1dBFS f IN = 170MHz-96.9-87.1-91.6-85.7dBFSWord Error Rate WER 10-1210-1210-1210-12Full Power Bandwidth FPBW1.51.51.51.5GHzNOTES:5.Digital Supply Current is dependent upon the capacitive loading of the digital outputs. IOVDD specifications apply for 10pF load on each digital output.6.See “Nap/Sleep” on page 18 for more details.7.The DLL Range setting must be changed for low speed operation. See “Serial Peripheral Interface” on page 21 for more detail.PARAMETER SYMBOL CONDITIONS KAD5510P-25KAD5510P-21KAD5510P-17KAD5510P-12UNITS MINTYP MAXMINTYP MAX MIN TYP MAX MINTYP MAXDigital Specifications Boldface limits apply over the operating temperature range, -40°C to +85°C.PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INPUTSInput Current High (SDIO, RESETN, CSB, SCLK)I IH V IN = 1.8V0110µA Input Current Low (SDIO, RESETN, CSB, SCLK)I IL V IN = 0V-25-12-5µA Input Voltage High (SDIO, RESETN, CSB, SCLK)V IH 1.17V Input Voltage Low (SDIO, RESETN, CSB, SCLK)V IL0.63V Input Current High (NAPSLP) (Note 9)I IH152540µA Input Current Low (NAPSLP)I IL-4025-15µA Input Capacitance C DI3pF LVDS OUTPUTSDifferential Output Voltage V T3mA Mode620mV P-P Output Offset Voltage V OS3mA Mode950965980mV Output Rise Time t R500ps Output Fall Time t F500ps CMOS OUTPUTSVoltage Output High V OH I OH = -500µA OVDD - 0.3OVDD - 0.1V Voltage Output Low V OL I OL = 1mA0.10.3V Output Rise Time t R 1.8ns Output Fall Time t F 1.4nsTiming DiagramsFIGURE 2.DDR LVDS TIMING DIAGRAM (See “Digital Outputs” on page 18)FIGURE 3.DDR CMOS TIMING DIAGRAM (See “Digital Outputs” on page 18)LATENCY = L CYCLEStDCt PDt At CPDINPINNCLKN CLKPCLKOUTN CLKOUTPODD BITS N-LN-LODD BITS ODD BITS EVEN BITSN-L + 1N-L + 1N-L + 2N-L + 2EVEN BITSEVEN BITS EVEN BITS D[8/6/4/2/0]P D[8/6/4/2/0]NNt DC t PDt AINPINNCLKN CLKOUTCLKPD[8/6/4/2/0]LATENCY = L CYCLESODD BITS N-LN-L ODD BITS ODD BITS EVEN BITSN-L + 1N-L + 1N-L + 2N-L + 2EVEN BITSEVEN BITS EVEN BITS Nt CPD分销商库存信息:INTERSILKAD5510P-12Q48KAD5510P-17Q48KAD5510P-21Q48 KAD5510P-25Q48。

0190990008;中文规格书,Datasheet资料

This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:19099-0008Status:ActiveOverview:Ring Tongue - Spade TerminalsDescription:InsulKrimp™ Snap Spade for 18-22 AWG Wire, Stud Size 5 (M3), Mylar Tape CarrierDocuments:Drawing (PDF)Product Specification PS-19902-011 (PDF)Product Specification PS-19902-009 (PDF)RoHS Certificate of Compliance (PDF)Agency CertificationCSA LR18689ULE32244GeneralProduct Family Ring and Spade Terminals Series19099Crimp Quality Equipment Yes Mil-Spec N/AOverviewRing Tongue - Spade Terminals Product Name InsulKrimp™Type Spade Snap UPC800753088771PhysicalBarrel Type Closed Color - Resin Natural Flammability 94V-0InsulationPVC Material - Plating Mating Tin Net Weight0.578/gPackaging Type Adhesive Tape on Reel Stud Size5 (M3)Wire Insulation Diameter 4.40mm max.Wire Size AWG 18, 20, 22Wire Size mm²0.25 - 1.50Material InfoOld Part NumberAA-2704-05XTReference - Drawing NumbersProduct Specification PS-19902-009, PS-19902-011Sales DrawingAACD20502Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHC Not ReviewedLow-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 19099SeriesApplication Tooling | FAQTooling specifications and manuals are found by selecting the products below.Crimp Height Specifications are then contained in the Application Tooling Specification document.GlobalDescription Product #Crimp Dies for MTA-100 Tape Applicator used in 3BF Press, MTA-105Tape Applicator used in TM-2000™ Press,and ATP-301 Air Crimping Press for Mylar Tape Mounted Terminals 0192880023Mini-Mac™Applicator0638851300This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0190990008。

CS5532-BSZR;CS5534-BSZR;CDB5532U;中文规格书,Datasheet资料

Copyright © Cirrus Logic, Inc. 2008CS5532/34-BS24-bit ∆Σ ADCs with Ultra-low-noise PGIAFeaturesChopper-stabilized PGIA (ProgrammableGain Instrumentation Amplifier, 1x to 64x)– 6 nV/√Hz @ 0.1 Hz (No 1/f noise) at 64x –1200pA Input Current with Gains >1 Delta-sigma Analog-to-digital Converter –Linearity Error: 0.0007% FS–Noise-free Resolution: Up to 23 bits Two- or Four-channel Differential MUX Scalable Input Span via Calibration –±5 mV to differential ±2.5VScalable V REF Input: Up to Analog Supply Simple Three-wire Serial Interface –SPI™ and Microwire™ Compatible –Schmitt Trigger on Serial Clock (SCLK) R/W Calibration Registers Per Channel Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz RejectionPower Supply Configurations–VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V–VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V –VA+ = +3 V; VA- = -3 V; VD+ = +3 VGeneral DescriptionThe CS5532/34 are highly integrated ∆Σ Analog-to-Digi-tal Converters (ADCs) which use charge-balance techniques to achieve 24-bit performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications.To accommodate these applications, the ADCs come as either two-channel (CS5532) or four-channel (CS5534)devices and include a very low-noise, chopper-stabilized instrumentation amplifier (6 nV/√Hz @ 0.1 Hz) with se-lectable gains of 1×, 2×, 4×, 8×, 16×, 32×, and 64×.These ADCs also include a fourth-order ∆Σ modulator followed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100,120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK =4.9152MHz).To ease communication between the ADCs and a micro-controller, the converters include a simple three-wire se-rial interface which is SPI™ and Microwire™ compatible with a Schmitt-trigger input on the serial clock (SCLK).High dynamic range, programmable output rates, and flexible power supply options makes these ADCs ideal solutions for weigh scale and process control applications.ORDERING INFORMATIONSee page 47VA+C1C2VREF+VREF-VD+DIFFERENTIAL 4TH ORDER ∆ΣMODULATORPGIA 1,2,4,8,16PROGRAMMABLE SINC FIR FILTERMUX(CS5534SHOWN)AIN1+AIN1-AIN2+AIN2-AIN3+AIN3-AIN4+AIN4-SERIAL INTERFACELATCHCLOCK GENERATORCALIBRATION SRAM/CONTROLLOGICDGNDCSSDI SDO SCLKOSC2OSC1A1A0/GUARD VA-32,64OCT ‘08TABLE OF CONTENTS1.CHARACTERISTICS AND SPECIFICATIONS (4)ANALOG CHARACTERISTICS (4)TYPICAL RMS NOISE (NV) (7)TYPICAL NOISE-FREE RESOLUTION(BITS) (7)5 V DIGITAL CHARACTERISTICS (8)3 V DIGITAL CHARACTERISTICS (8)DYNAMIC CHARACTERISTICS (9)ABSOLUTE MAXIMUM RATINGS (9)SWITCHING CHARACTERISTICS (10)2.GENERAL DESCRIPTION (12)2.1.Analog Input (12)2.1.1. Analog Input Span (13)2.1.2. Multiplexed Settling Limitations (13)2.1.3. Voltage Noise Density Performance (13)2.1.4. No Offset DAC (14)2.2.Overview of ADC Register Structure and Operating Modes (14)2.2.1. System Initialization (15)2.2.2. Serial Port Interface (22)2.2.3. Reading/Writing On-Chip Registers (23)2.3.Configuration Register (23)2.3.1. Power Consumption (23)2.3.2. System Reset Sequence (23)2.3.3. Input Short (24)2.3.4. Guard Signal (24)2.3.5. Voltage Reference Select (24)2.3.6. Output Latch Pins (24)2.3.7. Offset and Gain Select (25)2.3.8. Filter Rate Select (25)2.4.Setting up the CSRs for a Measurement (27)2.5.Calibration (30)2.5.1. Calibration Registers (30)2.5.2. Performing Calibrations (31)2.5.3. Self Calibration (31)2.5.4. System Calibration (32)2.5.5. Calibration Tips (32)2.5.6. Limitations in Calibration Range (33)2.6.Performing Conversions (33)2.6.1. Single Conversion Mode (33)2.6.2. Continuous Conversion Mode (34)2.6.3. Examples of Using CSRs to Perform Conversions and Calibrations (35)ing Multiple ADCs Synchronously (36)2.8.Conversion Output Coding (36)2.9.Digital Filter (38)2.10.Clock Generator (39)2.11.Power Supply Arrangements (39)2.12.Getting Started (43)2.13.PCB Layout (43)3.PIN DESCRIPTIONS (44)4.SPECIFICATION DEFINITIONS (46)5.ORDERING INFORMATION (47)6.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION (47)7.PACKAGE DRAWINGS (48)LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale) (11)Figure 2. SDO Read Timing (Not to Scale) (11)Figure 3. Multiplexer Configuration (12)Figure 4. Input models for AIN+ and AIN- pins (13)Figure 5. Measured Voltage Noise Density (13)Figure 6. CS5532/34 Register Diagram (14)Figure 7. Command and Data Word Timing (22)Figure 8. Guard Signal Shielding Scheme (24)Figure 9. Input Reference Model when VRS = 1 (25)Figure 10. Input Reference Model when VRS = 0 (25)Figure 11. Self Calibration of Offset (32)Figure 12. Self Calibration of Gain (32)Figure 13. System Calibration of Offset (32)Figure 14. System Calibration of Gain (32)Figure 15. Synchronizing Multiple ADCs (36)Figure 16. Digital Filter Response (WR = 60 Sps) (38)Figure 18. 120 Sps Filter Phase Plot to 120 Hz (38)Figure 17. 120 Sps Filter Magnitude Plot to 120 Hz (38)Figure 19. Z-Transforms of Digital Filters (38)Figure 20. On-chip Oscillator Model (39)Figure 21. CS5532 Configured with a Single +5 V Supply (40)Figure 22. CS5532 Configured with ±2.5 V Analog Supplies (41)Figure 23. CS5532 Configured with ±3 V Analog Supplies (41)Figure 24. CS5532 Configured for Thermocouple Measurement (42)Figure 25. Bridge with Series Resistors (42)LIST OF TABLESTable 1. Conversion Timing – Single Mode (34)Table 2. Conversion Timing – Continuous Mode (35)Table 3. Command Byte Pointer (35)Table 4. Output Coding for 24-bit CS5532 and CS5534 (37)1. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode; Gain = 32)(See Notes 1 and 2.)Notes: 1.Applies after system calibration at any temperature within -40 °C ~ +85 °C.2.Specifications guaranteed by design, characterization, and/or test. LSB is 24 bits.3. This specification applies to the device only and does not include any effects by external parasiticthermocouples. The PGIA contributes 5 nV of offset drift, and the modulator contributes 640/G nV of offset drift, where G is the amplifier gain setting.4.Drift over specified temperature range after calibration at power-up at 25 °C.ParameterMin Typ Max Unit Accuracy Linearity Error -±0.0007±0.0015%FS No Missing Codes 24--Bits Bipolar Offset -±16±32LSB 24Unipolar Offset-±32±64LSB 24Offset Drift(Notes 3 and 4)-640/G +5-nV/°C Bipolar Full-scale Error -±8±31ppm Unipolar Full-scale Error -±16±62ppm Full-scale Drift(Note 4)-2-ppm/°CANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)Notes: 5.The voltage on the analog inputs is amplified by the PGIA, and becomes V CM ± Gain*(AIN+ - AIN-)/2 atthe differential outputs of the amplifier. In addition to the input common mode + signal requirements for the analog input pins, the differential outputs of the amplifier must remain between (VA- + 0.1 V) and (VA+ - 0.1 V) to avoid saturation of the output stage.6.See the section of the data sheet which discusses input models.7.Input current on AIN+ or AIN- (with Gain =1), or VREF+ or VREF- may increase to 250nA if operatedwithin 50mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions.ParameterMin TypMaxUnitAnalog InputCommon Mode + Signal on AIN+ or AIN-Bipolar/Unipolar ModeGain = 1 Gain = 2, 4, 8, 16, 32, 64(Note 5)VA-VA- + 0.7--VA+VA+ - 1.7V V CVF Current on AIN+ or AIN-Gain = 1 (Note 6, 7)Gain = 2, 4, 8, 16, 32, 64--501200--nA pA Input Current Noise Gain = 1 Gain = 2, 4, 8, 16, 32, 64--2001--pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25 °C)-10-pA Off-channel Mux Isolation -120-dB Open Circuit Detect Current 100300-nA Common Mode Rejection dc, Gain = 1dc, Gain = 6450, 60 Hz ---90130120---dB dB dB Input Capacitance -60-pF Guard Drive Output -20-µA Voltage Reference Input Range (VREF+) - (VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 6, 7)-50-nA Common Mode Rejection dc 50, 60 Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full-scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS (Continued)(See Notes 1 and 2.)8.All outputs unloaded. All input CMOS levels.9.Power is specified when the instrumentation amplifier (Gain ≥ 2) is on. Analog supply current is reducedby approximately 1/2 when the instrumentation amplifier is off (Gain = 1).10.Tested with 100 mV change on VA+ or VA-.ParameterMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+, I A-I D+- - 130.5151mA mA Power ConsumptionNormal Mode (Notes 8 and 9)Standby Sleep---70450080--mW mW µW Power Supply Rejection (Note 10)dc Positive Supplies dc Negative Supply--115115--dB dBTYPICAL RMS NOISE (nV)(See notes 11, 12, 13 and 14)Notes:11.The -B devices provide the best noise specifications.12.Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C.13.For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates.14.Word rates and -3dB points with FRS = 0. When FRS = 1, word rates and -3dB points scale by 5/6.TYPICAL NOISE-FREE RESOLUTION(BITS)(See Notes 15 and 16)15.Noise-free resolution listed is for bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2) rounded to the nearest bit. For unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The noise-free resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the noise-free resolution accordingly.16.“Noise-free resolution” is not the same as “effective resolution”. Effective resolution is based on theRMS noise value, while noise-free resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.948.59101526509915 3.88121315213770139307.751718213052991966015.524252942731402771203134364259103198392240628013626051410202050409048012211319436973014502900581096023015927452310302060411082301,920390260470912181036207230145003,84078013602690538010800215004300086000Output Word Rate (Sps)-3 dB Filter Frequency (Hz)Instrumentation Amplifier Gainx64x32x16x8x4x2x17.5 1.942021222323232315 3.8820212222222222307.75192021222222226015.5192021212121211203118192021212121240621717181818181848012217171717171717960230161617171717171,920390161616161616163,840780131313131313135 V DIGITAL CHARACTERISTICS(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 17.)3 V DIGITAL CHARACTERISTICS(T A = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 17.)17.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45--VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-level Input Voltage All Pins Except SCLKSCLK V IH 0.6 VD+(VD+) - 0.45-VD+VD+V Low-level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-level Output Voltage A0 and A1, I out = -1.0 mASDO, I out = -5.0 mA V OH (VA+) - 1.0(VD+) - 1.0--V Low-level Output Voltage A0 and A1, I out = 1.0 mASDO, I out = 5.0 mAV OL --(VA-) + 0.40.4V Input Leakage Current I in -±1±10µA SDO Tri-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS18.The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc 5 filterfollowed by a Sinc 3 filter for the other OWRs. OWR sinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc 5 filter.19.The single conversion mode only outputs fully settled conversions. See Table 1 for more details aboutsingle conversion mode timing. OWR SC is used here to designate the different conversion time associated with single conversions.20.The continuous conversion mode outputs every conversion. This means that the filter’s settling timewith a full scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND = 0 V; See Note 21.)Notes:21.All voltages with respect to ground.22.VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V.23.VD+ and VA- must satisfy {(VD+) - (VA-)} ≤ +7.5 V.24.Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins.25.Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA.26.Total power dissipation, including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2 LSB (Full Scale Step Input)Single Conversion mode (Notes 18, 19, and 20)Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Spst s t s t s1/OWR SC5/OWR sinc5 + 3/OWR5/OWRs s sParameterSymbol Min Typ Max Unit DC Power Supplies(Notes 22 and 23)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current, Any Pin Except Supplies (Notes 24 and 25)I IN --±10mA Output Current I OUT--±25mA Power Dissipation (Note 26)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-) -0.3(VA-) -0.3--(VA+) + 0.3(VA+) + 0.3V V Digital Input VoltageV IND -0.3-(VD+) + 0.3V Ambient Operating Temperature T A -40-85°C Storage Temperature T stg-65-150°CSWITCHING CHARACTERISTICS(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; C L = 50 pF; See Figures 1 and 2.)Notes:27.Device parameters are specified with a 4.9152 MHz clock.28.Specified using 10% and 90% points on waveform of interest. Output loaded with 50pF.29.Oscillator start-up time varies with crystal parameters. This specification does not apply when using anexternal clock source.ParameterSymbol Min Typ MaxUnitMaster Clock Frequency (Note 27)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 28)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL = 4.9152 MHz(Note 29)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150ns分销商库存信息:CIRRUS-LOGICCS5532-BSZR CS5534-BSZR CDB5532U。

7491181024;中文规格书,Datasheet资料

description :33% Umgebungstemperatur / temperature:+20°CTBr 2006-07-31NameDatum / dateE Testbedingungen / test conditions :Freigabe erteilt / general release:D-74638 Waldenburg · Max-Eyth-Straße 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Würth Elektronik eiSos GmbH & Co.KGGeprüft / checked Änderung / modification...............................................Kunde / customerWürth Elektronik....................................................................................................................................................................WK3260B für / for L und / and RLuftfeuchtigkeit / humidity:Off-line transformer WE-UNITD Prüfgeräte / test equipment :Datum / dateUnterschrift / signature ..................................................Kontrolliert / approvedVersion 1description :Off-line transformer WE-UNITDATUM / DATE : 2006-07-31H Schaltbild / SchematicsTBr 2006-07-31NameDatum / dateWürth ElektronikFreigabe erteilt / general release:Kunde / customerDatum / dateUnterschrift / signature ...................................................................................................................................................................................................................Würth Elektronik eiSos GmbH & Co.KGD-74638 Waldenburg · Max-Eyth-Straße 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Version 1Änderung / modification..................................................Geprüft / checked Kontrolliert / approved46This electronic component has been designed and developed for usage in general electronic equipment. Before incorporating this component into any equipment where higher safety and reliability is especially required or if there is the possibility of direct damage or injury to human body, for example in the range of aerospace, aviation, nuclear control, submarine, transportation, (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc, Würth Elektronik eiSos GmbH must be informed before the design-in stage. In addition, sufficient reliability evaluation checks for safety must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.分销商库存信息: WURTH-ELECTRONICS 7491181024。

0428910140;中文规格书,Datasheet资料

This document was generated on 08/20/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:42891-0140Status:ActiveDescription:3.96mm Pitch KK® Solid Header, Vertical, Friction Lock, with Snap-in Plastic Peg PCB Lock, 5 Circuits, 0.76µm Gold (Au) Selective PlatingDocuments:3D ModelProduct Specification PS-08-50 (PDF)Drawing (PDF)RoHS Certificate of Compliance (PDF)GeneralProduct Family PCB Headers Series42891Application Power, Wire-to-Board Product Name KK®UPC756054535707PhysicalBreakawayNo Circuits (Loaded)5Circuits (maximum)5Durability (mating cycles max)100Glow-Wire Compliant No Lock to Mating Part Yes Material - MetalBrass Material - Plating MatingGold Material - Plating Termination Tin Net Weight1.908/g Number of Rows 1Orientation Vertical PC Tail Length 3.56mm PCB Locator Yes PCB RetentionYes PCB Thickness - Recommended 1.60mm Packaging TypeBag Pitch - Mating Interface 3.96mm Plating min - Mating0.762µm Plating min - Termination 2.540µm Polarized to Mating Part No Polarized to PCB Yes Shrouded No StackableYesTemperature Range - Operating 0°C to +75°C Termination Interface: StyleThrough Hole ElectricalCurrent - Maximum per Contact 7A Voltage - Maximum250VSolder Process DataDuration at Max. Process Temperature (seconds)5Lead-free Process CapabilityWave Capable (TH only)Max. Cycles at Max. Process Temperature 1Process Temperature max. C235Material InfoReference - Drawing NumbersSeriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Not Low-HalogenNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 42891SeriesMates With2139 KK® Crimp Housing, 41695 KK®Crimp Housing, 6442 KK® Crimp Housing,2145 PCB Connector, 41815 PCB Connector, 3069 KK® Crimp HousingProduct Specification PS-08-50Sales Drawing SD-42891-001This document was generated on 08/20/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0428910140。

KAC-9648;中文规格书,Datasheet资料

PRODUCT SUMMARYKODAK KAC-9648 IMAGE SENSOR1288 (H) X 1032 (V) COLOR CMOS IMAGE SENSOR DESCRIPTIONThe KODAK KAC-9648 Image Sensor is a high performance, low power, 1/2" SXGA CMOS Active Pixel Sensor capable of capturing color, monochrome, still, or motion images and converting them to a digital data stream.Mega-pixel class image quality is achieved by integrating a high performance analog signal processor comprising of a high speed 10 bit A/D converter, fixed pattern noise elimination circuits and separate color gain amplifiers. The offset and black level can be automatically adjusted on chip using a full loop black level compensation circuit. Furthermore, a programmable smart timing and control circuit allows the user maximum flexibility in adjusting integration time, active window size, gain, frame rate. Various control, timing and power modes are also provided.FEATURES• Video and snapshot operation• Progressive scan read out with horizontal and vertical flip• Programmable exposure with master clock divider, inter row delay, inter frame delay, andpartial frame integration• Four channels of digitally programmable analog gain• Full automatic servo loop for black level & offset adjustment on each gain channel• Horizontal & vertical sub-sampling (2:1 & 4:2) with averaging• Windowing• Programmable pixel clock, inter-frame and inter-line delays• I2C compatible serial control interface Parameter TypicalValue Array Format Total: 1032 x 1312Active: 1032 (V) x 1288 (H)Effective Image Area Total: 6.192mm x 7.872mmActive: 6.192mm x 7.728mmOptical Format 1/2"Pixel Size 6.0 µm x 6.0 µmVideo Outputs 8 & 10 Bit DigitalFrame Rate 18 frames per secondDynamic Range 55 dBShutter Rollingreset FPN 0.2% PRNU 1.7% Sensitivity 2.5V/lux*sFill Factor 49%Color Mosaic Bayer patternMicrolens none Package 48LCC Single Supply 3.0V ± 10%Power Consumption 150mWOperating Temp -10° C to 50° CAPPLICATIONS• Dual Mode Camera• Digital Still Camera• Security Camera• Machine Vision/go/imagersCHIP BLOCK DIAGRAMORDERING INFORMATIONProduct Name DescriptionCatalogNumber4H0723 KAC- 9648-CBA-FB-AA Color (Bayer RGB), Telecentric Microlens, CLCC Package, Clear Cover Glass (no coatings), Standard Grade 3F5386 KEM-3F5386-KAC-96XX Evaluation Board (Main Board)3F5385 KEH-3F5385-KAC-9648 Evaluation Board (Head Board)Please see ISS Application Note “Product Naming Convention” (MTD/PS-0892) for a full description of naming convention used for KODAK image sensors.Address all inquiries and purchase orders to:Image Sensor SolutionsEastman Kodak CompanyRochester, New York 14650-2010Phone: (585) 722-4385Fax: (585) 477-4947E-mail: imagers@©Eastman Kodak Company, 2006. Kodak and Pixelux are trademarks. Revision 2.0分销商库存信息: KODAKKAC-9648。

0190840008;中文规格书,Datasheet资料

This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:19084-0008Status:ActiveOverview:Ring Tongue - Spade TerminalsDescription:Open Barrel Star Ring , Tin-Plated Steel, for 14-18 AWG Wire Range, Stud Size 8 (M4)Documents:Drawing (PDF)Product Specification PS-19902-011 (PDF)Product Specification PS-19902-006 (PDF)RoHS Certificate of Compliance (PDF)Agency CertificationCSA LR18689ULE32244GeneralProduct Family Ring and Spade Terminals Series19084Crimp Quality Equipment Yes Mil-Spec N/AOverviewRing Tongue - Spade Terminals Product Name N/A Type RingUPC800755080223PhysicalBarrel Type Open InsulationNone Material - Plating Mating Tin Net Weight0.758/g Packaging Type Reel Plating min - Mating2.540µm Plating min - Termination 2.540µm Stud Size8 (M4)Termination Interface: Style Crimp or Compression Wire Insulation Diameter N/AWire Size AWG 14, 16, 18Wire Size mm²0.80 - 2.00Material InfoOld Part NumberSRZ-S-4129-08Reference - Drawing NumbersProduct Specification PS-19902-006, PS-19902-011Sales DrawingSD-19084-001Series image - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHCContains SVHC: No Low-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 19084SeriesApplication Tooling | FAQTooling specifications and manuals are found by selecting the products below.Crimp Height Specifications are then contained in the Application Tooling Specification document.GlobalDescription Product #ASP Perishable Tool Kit used in ASP presses that process metal strip product 0190290053Mini-Mac™Applicator0638815600This document was generated on 08/10/2012PLEASE CHECK FOR LATEST PART INFORMATION/分销商库存信息: MOLEX 0190840008。

LTC4449EDCB#TRMPBF;LTC4449EDCB#TRPBF;LTC4449IDCB#TRMPBF;LTC4449IDCB#TRPBF;中文规格书,Datasheet资料

SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
Input Signal (IN)
VIH(TG)
TG Turn-On Input Threshold
VIL(TG)
TG Turn-Off Input Threshold
VIH(BG)
BG Turn-On Input Threshold
FEATURES
n 4V to 6.5V VCC Operating Voltage n 38V Maximum Input Supply Voltage n Adaptive Shoot-Through Protection n Rail-to-Rail Output Drivers n 3.2A Peak Pull-Up Current n 4.5A Peak Pull-Down Current n 8ns TG Rise Time Driving 3000pF Load n 7ns TG Fall Time Driving 3000pF Load n Separate Supply to Match PWM Controller n Drives Dual N-Channel MOSFETs n Undervoltage Lockout n Low Proﬁle (0.75mm) 2mm × 3mm DFN Package
IN = Floating
VCC Rising VCC Falling Hysteresis
4
6.5
V
300
400
μA
l 2.75 3.20 3.65
V
l 2.60 3.04 3.50
V
160
mV

MAXFILTERBRD+;中文规格书,Datasheet资料

_______________________________________________________________ Maxim Integrated Products 1For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, MAXFILTERBRDEvaluates: MAX7408–MAX7415/MAX7418–MAX7425General DescriptionThe MAXFILTERBRD is an unpopulated PCB design to evaluate the MAX7408–MAX7415/MAX7418–MAX7425 5th-order, lowpass, switched-capacitor filters (SCFs).Contact the factory for free samples of the pin-compat-ible MAX7408–MAX7415/MAX7418–MAX7425 SCFs to evaluate these devices.FeaturesS CLK Pad for External Clock Frequency S Lead(Pb)-Free and RoHS Compliant S Proven PCB LayoutOrdering InformationComponent SupplierPart Selection TableComponent List(Suggested Components)19-4884; Rev 0; 8/09+Denotes lead(Pb)-free and RoHS compliant.Note: Contact the factory to order a free sample of any of the SCF parts.µMAX is a registered trademark of Maxim Integrated Products, Inc.Note: Indicate that you are using the MAXFILTERBRD when contacting this component supplier.PART TYPE MAXFILTERBRD+EV KitPARTOPERATING VOLTAGEFILTER TYPEMAX7408CUA+5V Elliptic MAX7409CUA+5V Bessel MAX7410CUA+5V Butterworth MAX7411CUA+5V Elliptic MAX7412CUA+3V Elliptic MAX7413CUA+3V Bessel MAX7414CUA+3V Butterworth MAX7415CUA+3V Elliptic MAX7418CUA+5V Elliptic MAX7419CUA+5V Bessel MAX7420CUA+5V Butterworth MAX7421CUA+5V Elliptic MAX7422CUA+3V Elliptic MAX7423CUA+3V Bessel MAX7424CUA+3V Butterworth MAX7425CUA+3VEllipticDESIGNATIONQTY DESCRIPTIONC1Not installed, 47pF Q 5%, 50V C0G ceramic capacitor (0805)Murata GRM2165C1H470J or similarC20Not installed, 2200pF Q 5%, 50V C0G ceramic capacitor (0805)Murata GRM2165C1H222J or similarC3, C40Not installed, 0.1F F Q 10%, 16V X7R ceramic capacitors (0603)Murata GCM188R71C104K or similarJU1, JU20Not installed, 2-pin headers—shorted by PC traceR1Not installed, 10k I Q 1% resistor (0805)U10Not installed, lowpass SCF (8 F MAX M )See the Part Selection Table —1PCB: MAXFILTERBRD+SUPPLIERPHONE WEBSITEMurata Electronics North America, Inc.770-436-1300MAXFILTERBRD E v a l u a t e s : M A X 7408–M A X 7415/M A X 7418–M A X 74252 ______________________________________________________________________________________Quick StartRequired Equipment• MAXFILTERBRD• Suggested components (see Component List )• 5V or 3V DC power supply (depending on the IC installed)• Function generator (e.g., HP 33120A)• 2-channel digital oscilloscope (e.g., Tektronix TDS3012)ProcedureCaution: Do not turn on power supply until all connec-tions are completed.1) I nstall all suggested components shown in theComponent List onto the MAXFILTERBRD.2) I f the installed IC is the MAX7408–MAX7411 orMAX7418–MAX7421, connect the positive terminal ofthe 5V supply to the VDD pad and the negative termi-nal of the supply to the GND pad closest to the VDDpad. If the installed IC is the MAX7412–MAX7415 or MAX7422–MAX7425, connect the positive terminal of the 3V supply to the VDD pad and the negative terminal of the supply to the GND pad closest to the VDD pad (see Figure 1). Set the function generator to 4V P-P max, 2.2V offset (typ), and 1kHz sine wave, and connect the signal to the IN pad.3) C onnect the first channel of the oscilloscope to theIN pad.4) C onnect the second channel of the oscilloscope tothe OUT pad.5) C onnect the oscilloscope’s ground probe to any GNDpads.6) Turn on the power supply.7) Verify the output on the OUT pad.Figure 1. Filter Evaluation Test Block DiagramMAXFILTERBRDEvaluates: MAX7408–MAX7415/MAX7418–MAX7425_______________________________________________________________________________________ 3Detailed Description of HardwareThe MAXFILTERBRD is an unpopulated PCB design to evaluate the MAX7408–MAX7415/MAX7418–MAX7425 5th-order, lowpass SCFs.Internal ClockThe MAXFILTERBRD uses the internal oscillator when a capacitor is installed on C1. Refer to corresponding installed IC data sheet.For the MAX7409/MAX7410/MAX7413/MAX7414, the frequency can be altered using the following formula:f OSC (kHz) = k/C1 (pF)where k = 30 x 103 and f OSC is the internal oscillator frequency.For the MAX7408/MAX7411/MAX7412/MAX7415, k = 27 x 103.For the MAX7418/MAX7421/MAX7422/MAX7425, k = 87 x 103.For the MAX7419/MAX7420/MAX7423/MAX7424, k = 110 x 103.External ClockAn external clock that matches the specification of the corresponding IC data sheet can be used by cutting the trace of jumper JU2. Drive the CLK pin with a CMOS gate powered from 0 to VDD. Apply the clock signal to the CLK pad.ShutdownThe MAXFILTERBRD is configured for normal operation once the desired IC is installed. The desired IC enters shutdown by cutting the trace of jumper JU1 and driving the IC SHDN pin low through the side of the jumper that is still connected to the part.MAXFILTERBRDE v a l u a t e s : M A X 7408–M A X 7415/M A X 7418–M A X 74254 ______________________________________________________________________________________Figure 2. MAXFILTERBRD SchematicMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 5© 2009 Maxim Integrated ProductsMaxim is a registered trademark of Maxim Integrated Products, Inc.MAXFILTERBRDEvaluates: MAX7408–MAX7415/MAX7418–MAX7425Figure 3. MAXFILTERBRD Component Placement Guide—Component SideFigure 5. MAXFILTERBRD PCB Layout—Solder SideFigure 4. MAXFILTERBRD Component PCB Layout—Component Side Figure 6. MAXFILTERBRD Component Placement Guide—Solder Side分销商库存信息: MAXIM MAXFILTERBRD+。

749118205;中文规格书,Datasheet资料

Bezeichnung :description :A Mechanische Abmessungen / dimensions :A mmB mmC mm Dmm= Marking Pin 1Eigenschaften / propertiesWert / valueEinheit / unittol.Induktivität /inductanceWindungszahlverhältnis /turns ratioDC-Widerstand W1 /DC-resistance W1DC-Widerstand W2 /DC-resistance W2DC-Widerstand W3 /DC-resistance W3Sättigungsstrom Primär/saturation current primaryStreuinduktivität /leakage inductance Hochspannung /hipot test Hochspannung /hipot test 33% Umgebungstemperatur / temperature:+20°CKontaktmaterial / contact plating: V1630FS or equiv.TBr 2009-08-10KSc2009-02-03TBr 2006-07-26NameDatum / dateHV E Testbedingungen / test conditions :Luftfeuchtigkeit / humidity:G Eigenschaften / general specifications :It is recommended that the temperature of the part does Draht / wire:Basismaterial / base material:Ferrit/ ferrite Tränklack / Varnish:Schaltfrequenz / Switching frequency: 132 kHzBetriebstemp. / operating temperature: -40°C - + 125°C Freigabe erteilt / general release:D-74638 Waldenburg · Max-Eyth-Straße 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked Änderung / modification...............................................Kunde / customerWürth Elektronik....................................................................................................................................................................WK3260B für / for L und / and RF Werkstoffe & Zulassungen / material & approvals :Umgebungstemp. / ambient temperature: -40°C - + 85°C max.kV 3mA, 1s W1, Screen => W2, W3max.26max.175µH 0.85max.Spezifikation für Freigabe / specification for releaseDATUM / DATE : 2009-08-10±10%749118205C Lötpad / soldering spec. :B Elektrische Eigenschaften / electrical properties :Kunde / customer :Netzteil-Übertrager WE-UNIT Off-line transformer WE-UNITArtikelnummer / part number :E16Spulenkörper / Bobbin: UL-V0D Prüfgeräte / test equipment :m 26m @ 20°C @ 20°C |dL/L|<10%R DC3L s10 kHz / 0,1V W2, W3 kurzI sat 4.0not exceed 125°C under worst case operating conditions.Cu-Ni-SnVersion 2Version 316,5 max.18,0 max.18,0 max.5,0 ± 0,5Testbedingungen /test conditionsR DC2mHL 0R DC10.94.310 kHz / 0,1 V W1 : W2 : W3 Datum / dateUnterschrift / signature ..................................................Kontrolliert / approvedVersion 1Bauteil für Netzanwendung / Off-line transformerA typ.TR 19 : 1 : 1±3%3mA, 1s W2 => W3HV 1.5kV@ 20°C max.ø1,15 x 2,73 x 3,512,216710ø0,6DACBBezeichnung :Netzteil-Übertrager WE-UNIT description :Off-line transformer WE-UNITDATUM / DATE : 2009-08-10H TBr 2009-08-10KSc2009-02-03TBr 2006-07-26NameDatum / dateUnterschrift / signature Version 3....................................................................................................................................................................Spezifikation für Freigabe / specification for releaseArtikelnummer / part number :749118205Würth ElektronikFreigabe erteilt / general release:Kunde / customerDatum / date..................................................Geprüft / checked Kontrolliert / approved...............................................Würth Elektronik eiSos GmbH & Co.KGVersion 2D-74638 Waldenburg · Max-Eyth-Straße 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Version 1Änderung / modificationKunde / customer:89 34 56W1 120-385VW33,3 - 6V 4,5WW23,3 - 6V 4,5W9This electronic component has been designed and developed for usage in general electronic equipment. Before incorporating thi s component into any equipment where higher safety and reliability is especially required or if there is the possibility of direct damage or injury to human body, for example in the range of aerospace, aviation, nuc lear control, submarine, transportation, (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc, Würth Elektronik eiSos GmbH must be info rmed before the design-in stage. In addition, sufficient reliability evaluation checks for safety must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.分销商库存信息: WURTH-ELECTRONICS 749118205。

0394850004;中文规格书,Datasheet资料

This document was generated on 08/17/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:39485-0004Status:ActiveDescription: 4.00mm Pitch Positive Locking Terminal Block PCB Header, Tin Plating, 4 CircuitsDocuments:3D ModelProduct Specification PS-39484-001 (PDF)Drawing (PDF)RoHS Certificate of Compliance (PDF)GeneralProduct Family Terminal Blocks Series39485ApplicationWire-to-Board Component Type PCB HeaderProduct Name Eurostyle™Pluggable Type Euro Block UPC883906382742PhysicalCircuits (Loaded)4Circuits (maximum)4Color - Resin BlackEntry AngleVertical (Top Entry)Lock to Mating Part YesMaterial - MetalCopper Alloy Material - Plating Mating Tin Material - Resin Nylon Number of Rows 1Orientation Vertical PC Tail Length 3.20mm PCB Retention None Panel MountNoPitch - Mating Interface4.00mm Pitch - Termination Interface 4.00mm Polarized to Mating Part Yes Shrouded No StackableNo Surface Mount Compatible (SMC)YesTemperature Range - Operating -40°C to +140°C Wire Size AWGN/A ElectricalCurrent - Maximum per Contact 10A Voltage - Maximum300VMaterial InfoReference - Drawing NumbersProduct Specification PS-39484-001Sales DrawingSD-39485-001Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHC Not ReviewedLow-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 39485SeriesMates With39484 4.00mm Pitch tin plated plugsThis document was generated on 08/17/2012PLEASE CHECK FOR LATEST PART INFORMATION/分销商库存信息: MOLEX 0394850004。

0424108840;中文规格书,Datasheet资料

This document was generated on 08/30/2012PLEASE CHECK FOR LATEST PART INFORMATIONPart Number:42410-8840Status:ActiveOverview:Modular Plugs - JacksDescription:Modular Jack, Vertical, 8/6, Keyed, Panel StopsDocuments:3D ModelTest Summary TS-42878-001 (PDF)Drawing (PDF)RoHS Certificate of Compliance (PDF)Product Specification PS-42410 (PDF)GeneralProduct Family Modular Jacks/Plugs Series42410Component Type PCB Jack Magnetic NoOverviewModular Plugs - Jacks Performance Category 3Power over Ethernet (PoE)N/A Product Name RJ45UPC800753819825PhysicalBoot Color N/A Color - ResinBlack Durability (mating cycles max)500Inverted / Top Latch N/AJack Height16.38mm Keying to Mating Part Yes Lightpipes/LEDs NoneMaterial - MetalPhosphor Bronze Material - Plating MatingGold Material - Plating Termination TinMaterial - Resin PolyesterOrientation Vertical (Top Entry)PCB Locator Yes PCB RetentionYes PCB Thickness - Recommended 3.18mm Packaging Type TrayPanel MountWith Flange Pitch - Mating Interface1.02mm Pitch - Termination Interface 1.27mm Ports1Positions / Loaded Contacts8/6Surface Mount Compatible (SMC)NoTemperature Range - Operating -40°C to +85°C Termination Interface: Style Through Hole Waterproof / Dustproof No Wire/Cable TypeN/AElectricalCurrent - Maximum per Contact 1.5A Grounding to PCB No Grounding to Panel None ShieldedNoVoltage - Maximum150V AC (RMS)Seriesimage - Reference onlyEU RoHSChina RoHSELV and RoHS Compliant REACH SVHC Not ReviewedLow-Halogen Status Not ReviewedNeed more information on product environmental compliance?Email productcompliance@For a multiple part number RoHS Certificate of Compliance, click herePlease visit the Contact Us section for any non-product compliance questions.Search Parts in this Series 42410SeriesSolder Process DataDuration at Max. Process Temperature (seconds)5Lead-free Process Capability Wave Capable (TH only)Max. Cycles at Max. Process Temperature1Process Temperature max. C235Material InfoReference - Drawing NumbersProduct Specification PS-42410Test Summary TS-42878-001This document was generated on 08/30/2012PLEASE CHECK FOR LATEST PART INFORMATION分销商库存信息: MOLEX 0424108840。