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组合逻辑电路：38译码和83编码
38译码：
library ieee;
use ieee.std_logic_1164.all;
entity DECODER is
PORT(A,B,C: IN STD_LOGIC;
Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
end DECODER;
architecture A of DECODER is
SIGNAL INDA TA :STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
INDA TA<=C&B&A;
PROCESS(INDA TA)
BEGIN
CASE INDA TA IS
WHEN "000"=>Y<="00000001";
WHEN "001"=>Y<="00000010";
WHEN "010"=>Y<="00000100";
WHEN "011"=>Y<="00001000";
WHEN "100"=>Y<="00010000";
WHEN "101"=>Y<="00100000";
WHEN "110"=>Y<="01000000";
WHEN "111"=>Y<="10000000";
WHEN OTHERS=>Y<="00000000";
END CASE;END PROCESS;end A;
83编码
ENTITY Endec8_3 IS
PORT (A : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
EN : IN STD_LOGIC ;
Y : OUT STD_LOGIC_VECTOR( 2 DOWNTO 0)) ;
END Endec8_3 ;
ARCHITECTURE BEHA VE OF Endec8_3 IS
SIGNAL SEL : STD_LOGIC_VECTOR( 8 DOWNTO 0) ;
BEGIN
SEL <= EN & A ;
WITH SEL SELECT
Y<= "000" WHEN "100000001" ,
"001" WHEN "100000010" ,
"010" WHEN "100000100" ,
"011" WHEN "100001000" ,
"100" WHEN "100010000" ,
"101" WHEN "100100000" ,
"110" WHEN "101000000" ,
"111" WHEN "110000000" ,
"000" WHEN OTHERS ;
END BEHA VE ;
用IF-ELSE-IF-END IF语句实现38译码功能
library ieee;
use ieee.std_logic_1164.all;
entity VHDL3 is
port (a,b,c:in bit;
y:out integer range 7 downto 0);
end;
architecture bhv of VHDL3 is
begin
process(a,b,c)
begin
if a='0'and b='0'and c='0' then y<='0';
else if a='0'and b='0'and c='1' then y<='1';
else if a='0'and b='1'and c='0' then y<='2';
else if a='0'and b='1'and c='1' then y<='3';
else if a='1'and b='0'and c='0' then y<='4';
else if a='1'and b='0'and c='1' then y<='5';
else if a='1'and b='1'and c='0' then y<='6';
else if a='1'and b='1'and c='1' then y<='7';
end if;end process; end bhv;
时序逻辑电路：同步计数器与异步计数器
同步计数器：
LIBRARY IEEE;--带时钟使能的同步4位二进制减法计数器；
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY count IS
PORT(clk,clr,en : IN STD_LOGIC;
qa,qb,qc,qd : OUT STD_LOGIC);
END count;
ARCHITECTURE behav OF count IS
SIGNAL count_4 : STD_LOGIC_vector(3 DOWNTO 0);
BEGIN
Qa<=count_4(0);
Qb<=count_4(1);
Qc<=count_4(2);
Qd<=count_4(3);
PROCESS (clk,clr)
BEGIN
IF(clk'EVENT AND clk ='1') THEN
IF(clr='1') THEN
Count_4<="0000";
ELSIF(en='1') THEN
IF(count_4="0000") THEN
count_4<="1111";
ELSE
count_4<=count_4-'1';
END IF;
END IF;
END IF;
END PROCESS;
END behav;
异步计数器LIBRARY IEEE; --带时钟使能的异步4位二进制加法计数器use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY countA IS
PORT(clk,clr,en : IN STD_LOGIC;
qa,qb,qc,qd : OUT STD_LOGIC);
END countA;
ARCHITECTURE example OF countA IS
SIGNAL count_4 : STD_LOGIC_vector(3 DOWNTO 0); BEGIN
Qa<=count_4(0);
Qb<=count_4(1);
Qc<=count_4(2);
Qd<=count_4(3);
PROCESS (clk,clr)
BEGIN
IF(clr='1') THEN
Count_4<="0000";
ELSIF(clk'EVENT AND clk = '1' ) THEN
IF(en='1') THEN
IF(count_4="1111") THEN
count_4<="0000";
ELSE
count_4<=count_4+'1';
END IF;
END IF;
END IF;
END PROCESS;
END example;：
有限状态机：
ppt上的两个图，
moore和mealy机
Moore状态机 Mealy状态机Mealy状态机程序设计举例：
ENTITY Ch6_5_2 is
PORT(
CP : IN STD_LOGIC;
DIN : IN STD_LOGIC;
OP : OUT STD_LOGIC);
END Ch6_5_2;
ARCHITECTURE a OF Ch6_5_2 IS
TYPE STA TE IS (S0,S1,S2,S3);
SIGNAL PresentState : STA TE;
SIGNAL NextState : STA TE;
BEGIN
SwitchToNextState : Process (CP)
BEGIN
IF CP‘evnet AND CP='1' Then
PresentState <= NextState;
END IF;
END PROCESS SwitchToNextState; ChangeStateMode : PROCESS (DIN,PresentState) BEGIN
CASE PresentState IS
WHEN S0 =>
IF DIN = '0' THEN
NextState <= S0; OP <= '0';
ELSE
NextState <= S1; OP <= '1';
END IF;
WHEN S1 =>
IF DIN = '1' THEN
NextState <= S1; OP <= '1';
ELSE
NextState <= S2; OP <= '0';
END IF;
WHEN S2 =>
IF DIN = '1' THEN
NextState <= S2; OP <= '0';
ELSE
NextState <= S3; OP <= '1';
END IF;
WHEN S3 =>
IF DIN = '1' THEN
NextState <= S0; OP <= '1';
ELSE
NextState <= S1; OP <= '0';
END IF;
WHEN OTHERS =>NextState <= S0; OP <= '0'; END CASE;
END PROCESS ChangeStateMode;
END a;
单进程Moore状态机程序设计举例：
Library ieee;
Use ieee.std_logic_1164.all;
Entity moore1 is
Port(datain: in std_logic_vector(1 downto 0);
Clk,rst : in std_logic;