OCP8166 最新资料(2014版)

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GB16916.1验证在额定限制短路电流(Inc)时的配合+试后验证介电性能原始记录模板

数据采集仪
泄漏电流测试仪
耐压机
电压表
环境记录仪
漏电测试仪
要求值
电压实测值(格/V)
电流实测值(kA)
cos
预期波
编号
电压(V)
电流(kA)
cos
AB
BC
CA
平均
A
B
C平均试验线路选用源自□25kA□其他前级短路电流
kA
接地点形式
□负载侧接地□电源侧接地
连接导线规格长度
mm2×m
负载形式
□电阻串联空芯电抗器 □其他：
飞弧测量及飞弧距离
□飞弧检测熔丝□对金属支架□聚乙烯膜mm□栅格mm
飞弧检测熔丝规格
直径mm，长度mm
栅格回路熔丝规格
直径mm，长度mm
试验概况:
□试后耐压试验
试验电压： V 施压时间： s
试品编号
操作顺序
飞弧测量
示波图编号
试品编号
测试部位
聚乙烯膜
熔丝
□选用
□选用
断开
位置
□每极每对接线端子之间
□通过□击穿□闪烙
□通过□击穿□闪烙
□通过□击穿□闪烙
□选用
□选用
□选用
□选用
□选用
□选用
闭合
位置
□极与极之间
□通过□击穿□闪烙
□通过□击穿□闪烙
□通过□击穿□闪烙
□选用
□选用
□选用
□选用
□选用
□选用
□所有极连接在一起与框架之间
□通过□击穿□闪烙
□通过□击穿□闪烙
□通过□击穿□闪烙
□选用
□选用
□选用
□选用
试验过程概况

861分类 - 2014本稿

附件3“861”项目分类标准和依据(2014年)一、八大产业项目分类1.电子信息和家用电器。

（1）电子信息。

主要包括平板显示、LED、集成电路、下一代互联网和物联网、移动通信和软件、云计算。

其中，平板显示包括液晶显示器件、有机发光显示器、激光显示、3D显示、玻璃基板、偏光片、背光源以及平板电视等终端产品；LED 包括外延片、芯片、封装及终端应用产品等；集成电路包括IC制造、封装测试以及集成电路设备制造、关键材料生产等配套产业；下一代互联网和物联网包括传感器、射频器件及中间件、通信模块及元器件等；移动通信包括移动通信网络设备及终端设备等；软件包括软件系统集成及设备等。

（2）家用电器。

主要包括家用制冷器具、家用空气调节器、家用通风电器、家用厨房电器具、家用清洁卫生电器具、家用美容及保健电器具、家用电器专用配件等，以模糊控制、神经网络技术为基础的人工智能产品等新型智能家电。

（3）公共安全。

包括应急处置、信息安全、生产安全、食品安全等。

其中信息安全包括卫星通信系统及设备、城市和农村安全视频监控综合平台、智能视频监控终端设备、语音安全监控装备、搜寻及调查器材、新型技侦装备等；生产安全包括安全监控系统与安全仪器仪表、安全防护设备、防护材料、个体防护用品等；食品安全包括食品安全快速检测设备、果蔬农药残留去除专用设备、数字化X光异物检测机、数字化广泛用途色选机、食品辐照加速器等。

（4）节能产业。

包括节能电机、节能变压器、节能电器、绿色照明产品等。

2.汽车和装备制造。

（1）汽车及关键零部件。

主要包括乘用车、商务车、改装车、专用车和新能源汽车等，以及上下游配套的汽车零部件生产，还包括提升核心零部件（动力总成、电子控制等）的研发和制造等。

（2）新能源汽车。

包括纯电动汽车、燃料电池汽车、混合动力汽车、动力电池、电机及驱动模块等。

其中，纯电动汽车包括蓄电池电动汽车、蓄电池+超级电容电动汽车；混合动力汽车包括内燃机+蓄电池混合动力汽车，内燃机+超级电容混合电动汽车、内燃机+液压节能器混合动力汽车等；电机及驱动模块包括电动机、功率转换器、控制器、各种检测传感器等。

OCS LED照明解决方案 - 2016

隔离式 Triac
OCP8359 20W-50W OCP8358 12W-18W OCP8357 7W-12W

◆ 灿瑞科技LED照明电源驱动IC
隔离式AC-DC
Part No. OCP8150 OCP8151 OCP8152 OCP8153 OCP8155 OCP8153D OCP8155D OCP8156A OCP8157A OCP8158A OCP8159A 控制方式 PSR PSR PSR PSR PSR PSR PSR APFC APFC APFC APFC 输出功率 50W 7W 7W 18W 24W 18W 24W 12W 18W 30W 50W MOS管外置内置内置内置内置内置内置内置内置外置外置恒流精度 ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% ± 3% 典型效率 88% 83% 83% 88% 88% 88% 88% 88% 90% 90% 90% 备注 SOT23-5封装 SOP8-1A/650V SOP8-1A/650V DIP8-2A/650V DIP8-4A/650V DIP8-2A/650V DIP8-4A/650V DIP8-2A/650V DIP8-4A/650V SOT23-6封装 SOP8封装

◆ 灿瑞科技LED照明电源驱动IC
非隔离AC-DC
Part No. 控制方式输出功率 MOS管恒流精度典型效率备注
OCP8161A
OCP8162A OCP8164A OCP8164B OCP8165A OCP8190 OCP8191
Buck+CC
Buck+CC Buck+CC Buck+CC Buck+CC Buck+CC Buck+CC

X84640-1.8资料

元器件交易网Preliminary InformationThis X84160/640/128 device has been acquired by IC MICROSYSTEMS from Xicor, Inc.ICmicTMIC MICROSYSTEMS16K/64K/128KX84160/640/128MPSTM EEPROMAdvanced MPS™ Micro Port Saver EEPROM with Block Lock™ ProtectionFEATURES•Up to 15MHz data transfer rate •20ns Read Access Time •Direct Interface to Microprocessors and Microcontrollers —Eliminates I/O port requirements —No interface glue logic required —Eliminates need for parallel to serial converters •Low Power CMOS —1.8V–3.6V, 2.5V–5.5V and 5V ± 10% Versions —Standby Current Less than 1µA —Active Current Less than 1mA •Byte or Page Write Capable —32-Byte Page Write Mode •New Programmable Block Lock™ Protection —Software Write Protection —Programmable Hardware Write Protection •Block Lock (0, 1/4, 1/2, or all of the array) •Typical Nonvolatile Write Cycle Time: 3ms •High Reliability —100,000 Endurance Cycles —Guaranteed Data Retention: 100 Years •Small Package Options —8-Lead Mini-DIP Package —8, 14-Lead SOIC Packages —8, 20, 28-Lead TSSOP Packages —8-Lead XBGA Packagesbytewide memory control functions, takes a fraction of the board space and consumes much less power. Replacing serial memories, the µPort Saver provides all the serial benefits, such as low cost, low power, low voltage, and small package size while releasing I/Os for more important uses. The µPort Saver memory outputs data within 20ns of an active read signal. This is less than the read access time of most hosts and provides “no-wait-state” operation. This prevents bottlenecks on the bus. With rates to 15MHz, the µPort Saver supplies data faster than required by most host read cycle specifications. This eliminates the need for software NOPs. The µPort Saver memories communicate over one line of the data bus using a sequence of standard bus read and write operations. This “bit serial” interface allows the µPort Saver to work well in 8-bit, 16 bit, 32-bit, and 64-bit systems. The X84160/640/128 provide additional data security features through Block Lock and programmable Hardware Write Protection. These allow some or all of the array to be write protected by software command or by hardware. System Configuration, Company ID, calibration information, or other critical data can be secured against unexpected or inadvertent program operations, leaving the remainder of the memory available for the system or user access A Write Protect (WP) pin prevents inadvertent writes to the memory. Xicor EEPROMs are designed and tested for applications requiring extended endurance. Inherent data retention is greater than 100 years.DESCRIPTIONThe µPort Saver memories need no serial ports or special hardware and connect to the processor memory bus. Replacing bytewide data memory, the µPort Saver usesBLOCK DIAGRAMSystem ConnectionµP µCA15 WPInternal Block Diagram MPSH.V. GENERATION TIMING & CONTROLDSP ASIC RISCPorts SavedP0/CS P1/CLK P2/DIA0 D7CE I/OCOMMAND DECODED0 OE WEOE WEAND CONTROLX DECEEPROM ARRAY 16K x 88K x 8 2K x 8LOGICP3/DOY DECODE DATA REGISTER© Xicor, Inc. 1998 Patents Pending7067 1.1 6/10/98 T10/C0/D31Characteristics subject to change without notice元器件交易网X84160/640/128PIN CONFIGURATIONS: Drawings are to the same scale, actual package sizes are shown in inches:8-LEAD PDIP 8-LEAD SOIC CE I/O WP V SS 1 2 X84160 3 X84640 4 .230 in. 8 7 6 5 V CC NC OE WE .190 in. NC VCC CE I/O 8-LEAD TSSOP 1 2 3 4 8 7 6 5 OE WE WP VSSPIN NAMES.114 in.X84160I/O CE OE WE WPData Input/Output Chip Enable Input Write Enable Input Supply Voltage Ground Output Enable Input Write Protect Input14-LEAD SOIC CE I/O NC NC NC WP V SS 1 2 3 4 5 6 7 .230 in. X84128 14 13 12 11 10 9 8 V CC NC NC NC NC OE WE .390 in.NC NC CE I/O NC NC NC WP VSS NC1 2 3 4 5 6 7 8 9 10X8464020 19 18 17 16 15 14 13 12 11NC NC VCC NC NC NC NC OE WE NC.250 in.roNC NC NC NC VCC NC NC .394 in. NC NC OE WE NC NC NC.252 in. 28-LEAD TSSOP NC NC CE CE CE I/O NC NC NC WP VSS NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 158-LEAD XBGA: Top View VCC 1 8 I/O .238 in. NC WE OE 2 7 CE 3 6 VSS 4 5 WPP2X84128e. 252 in..078 in.PIN DESCRIPTIONS Chip Enable (CE)ol etThe Chip Enable input must be LOW to enable all read/ write operations. When CE is HIGH, the chip is deselected, the I/O pin is in the high impedance state, and unless a nonvolatile write operation is underway, the device is in the standby power mode. Output Enable (OE) The Output Enable input must be LOW to enable the output buffer and to read data from the device on the I/O line.bsWrite Protect (WP) The Write Protect input controls the Hardware Write Protect feature. When WP is LOW and the nonvoltaile bit WPEN is “1”, nonvolatile writes of the X84160/640/128 control register is disabled, but the part otherwise functions normally. When WP is held HIGH, all functions, including nonvolatile write operate normally. WP going LOW while CS is still LOW will interrupt a write to the X84160/640/128 control register. If the internal Write cycle has already been initiated, WP going LOW will have no effect on write. The WP pin function is blocked when the WPEN bit in the control register is “0”. This allows the user to install the X84160/640/128 in a system with WP pin grounded and still be able to write to the control register. The WP pin functions will be enabled when the WPEN bit is set “1”.OWrite Enable (WE) The Write Enable input must be LOW to write either data or command sequences to the device. Data In/Data Out (I/O) Data and command sequences are serially written to or serially read from the device through the I/O pin.du cVCC VSS NC No Connect20-LEAD TSSOPPACKAGE SELECTION GUIDE841608-Lead PDIP 8-Lead SOIC 8-Lead TSSOP 8-Lead CSP/BGA 8-Lead PDIP 8-Lead SOIC 20-Lead TSSOP 8-Lead CSP/BGA 8-Lead PDIP 14-Lead SOIC 28-Lead TSSOP8464084128t.252 in.元器件交易网X84160/640/128DEVICE OPERATION The X84160/640/128 are serial EEPROMs designed to interface directly with most microprocessor buses. Standard CE, OE, and WE signals control the read and write operations, and a single l/O line is used to send and receive data and commands serially. Data Timing Data input on the l/O line is latched on the rising edge of either WE or CE, whichever occurs ﬁrst. Data output on the l/O line is active whenever both OE and CE are LOW. Care should be taken to ensure that WE and OE are never both LOW while CE is LOW. Read Sequence A read sequence consists of sending a 16-bit address followed by the reading of data serially. The address is written by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without a read cycle between the write cycles. The address is sent serially, most signiﬁcant bit ﬁrst, over the I/O line. Note that this sequence is fully static, with no special timing restrictions, and the processor is free to perform other tasks on the bus whenever the device CE pin is HIGH. Once the 16 address bits are sent, a byte of data can be read on the I/O line by issuing 8 separate read cycles (OE and CE LOW, WE HIGH). At this point, writing a ‘1’ will terminate the read sequence and enter the low power standby state, otherwise the device will await further reads in the sequential read mode. Sequential Read The byte address is automatically incremented to the next higher address after each byte of data is read. The data stored in the memory at the next address can be read sequentially by continuing to issue read cycles. When the highest address in the array is reached, the address counter rolls over to address 0000h and reading may be continued indeﬁnitely. Reset Sequence The reset sequence resets the device and sets an internal write enable latch. A reset sequence can be sent at any time by performing a read/write “0”/read operation (see Figs. 1 and 2). This breaks the multiple read or write cycle sequences that are normally used to read from or write to the part. The reset sequence can be used at any time to interrupt or end a sequential read or page load. As soon as the write “0” cycle is complete, the part is reset (unless a nonvolatile write cycle is in progress). The second read cycle in this sequence, and any further read cycles, will read a HIGH on the l/O pin until a valid read sequence (which includes the address) is issued. The reset sequence must be issued at the beginning of both read and write sequences to be sure the device initiates these operations properly.Figure 1. Read SequenceCEObsOEWEol etI/O (IN)"0"A15 A14 A13 A12 A11 A10 A9 A8eP3A7 A6 A5 A4 A3 A2I/O (OUT) RESETWHEN ACCESSING: X84160 ARRAY: A15–A11=0 X84640 ARRAY: A15–A13=0 X84128 ARRAY: A15–A14=0LOAD ADDRESSroA1 A0du cD7 D6 D5 D4 D3 D2 D1 D0READ DATAt7008 FRM F04.1元器件交易网X84160/640/128Figure 2: Write SequenceCEOEWEI/O (IN)"0"A15 A14 A13 A12 A11 A10 A9 A8A7 A6 A5 A4 A3 A2 A1 A0du cD7 D6 D5 D4 D3 D2 D1 D0RESETWHEN ACCESSING: X84160 ARRAY: A15–A11=0 X84640 ARRAY: A15–A13=0 X84128 ARRAY: A15–A14=0LOAD ADDRESSroI/O (OUT)LOAD DATAP4ol etWrite Sequence A nonvolatile write sequence consists of sending a reset sequence, a 16-bit address, up to 32 bytes of data, and then a special “start nonvolatile write cycle” command sequence.epage, where data loading can continue. For this reason, sending more than 256 consecutive data bits will result in overwriting previous data. A nonvolatile write cycle will not start if a partial or incomplete write sequence is issued. The internal write enable latch is reset when the nonvolatile write cycle is completed and after an invalid write to prevent inadvertent writes. Note that this sequence is fully static, with no special timing restrictions. The processor is free to perform other tasks on the bus whenever the chip enable pin (CE) is HIGH. Nonvolatile Write Status The status of a nonvolatile write cycle can be determined at any time by simply reading the state of the l/O pin on the device. This pin is read when OE and CE are LOW and WE is HIGH. During a nonvolatile write cycle the l/O pin is LOW. When the nonvolatile write cycle is complete, the l/O pin goes HIGH. A reset sequence can also be issued during a nonvolatile write cycle with the same result: I/O is LOW as long as a nonvolatile write cycle is in progress, and l/O is HIGH when the nonvolatile write cycle is done.The nonvolatile write cycle is initiated by issuing a special read/write “1”/read sequence. The ﬁrst read cycle ends the page load, then the write “1” followed by a read starts the nonvolatile write cycle. The device recognizes 32byte pages (e.g., beginning at addresses XXXXXX00000 for X84160). When sending data to the part, attempts to exceed the upper address of the page will result in the address counter “wrapping-around” to the ﬁrst address on theObsThe reset sequence is issued ﬁrst (as described in the Reset Sequence section) to set an internal write enable latch. The address is written serially by issuing 16 separate write cycles (WE and CE LOW, OE HIGH) to the part without any read cycles between the writes. The address is sent serially, most signiﬁcant bit ﬁrst, on the l/O pin. Up to 32 bytes of data are written by issuing a multiple of 8 write cycles. Again, no read cycles are allowed between writes.t"1" "0" START NONVOLATILE WRITE7008 FRM F05.1元器件交易网X84160/640/128CONTROL REGISTER The X84160/640/128 has one register that contains control bits for the devices. The control bits, WPEN, BP1, and BP0, are shown in Table 1. To read or change the contents of this register requires a one byte operation to address FFFFh. A read from FFFFh returns the one byte contents of the control register unused bits return 0. Continued reads return undeﬁned data. A write to address FFFFh changes the value of the bits. Unused bits are written as “0”. Writing more than one byte to the control register is a violation and the operation will be aborted. After sending one byte to the control register, a start nonvolatile write cycle will latch in the new state. Table 1 7 WPEN 6 0 5 0 4 0 3 BP1 2 BP0 1 0 0 0 The Write Protect (WP) pin and the nonvolatile Write Protect Enable (WPEN) bit in the Status Register control the programmable hardware write protect feature. Hardware write protection is enabled when WP pin is LOW, and the WPEN bit is “1”. Hardware write protection is disabled when either the WP pin is HIGH or the WPEN bit is “0”. When the chip is hardware write protected, nonvolatile write is disabled to the Control Register, including the Block Protect bits and the WPEN bit itself, as well as the block-protected sections in the memory array. Only the sections of the memory array that are not block-protected can be written.Note: When the WP pin is tied to VSS and the WPEN bit is HIGH, the WPEN bit is write protected. It cannot be changed back to a “0”, as long as the WP pin is held LOW.WPEN 0 1 XWP X LOW HIGHProtected Blocks Protected ProtectedUnprotected Blocks Writable WritableProtectedTable 3. Block Lock ProtectionbsControl Register Bits BP1 0 0 1 1 BP0 0 1 0 1ol etWritableeWPEN: Write Protect Enable Bit The Write-Protect-Enable (WPEN) bit is an enable bit for the WP pin. Table 2Status Register WritableBP1, BP0: Block Protect Bits The Block Protect (BP0 and BP1) bits are nonvolatile and allow the user to select one of four levels of protection. The X84160/640/128 is divided into four segments. One, two, or all four of the segments may be protected. That is, the user may read the segments but will be unable to alter (write) data within the selected segments. The partitioning is controlled as illustrated in table 3 below.Protected WritableX84160 None 0600h–07FFh 0400h–07FFh 0000–07FFhPX84640 None5Array Address Protected X84128 None 3000h–3FFFh 2000h–3FFFh 0000h–3FFFh upper 1/4 upper 1/2 Full Array (Not including the control register.) Array1800h–1FFFh 1000h–1FFFh 0000–1FFFhOrodu ct元器件交易网X84160/640/128Low Power Operation The device enters an idle state, which draws minimal current when: —an illegal sequence is entered. The following are the more common illegal sequences: • Read/Write/Write—any time • Read/Write ‘1’—When writing the address or writing data. • Write ‘1’—when reading data • Read/Read/Write ‘1’—after data is written to device, but before entering the NV write sequence. —the device powers-up; —a nonvolatile write operation completes. While a sequential read is in progress, the device remains in an active state. This state draws more current than the idle state, but not as much as during a read itself. To go back to the lowest power condition, an invalid condition is created by writing a ‘1’ after the last bit of a read operation. Write Protection The following circuitry has been included to prevent inadvertent nonvolatile writes: —The internal Write Enable latch is reset upon power-up. —A reset sequence must be issued to set the internal write enable latch before starting a write sequence. —A special “start nonvolatile write” command sequence is required to start a nonvolatile write cycle.—The internal Write Enable latch is reset and remains reset as long as the WP pin is LOW, which blocks all nonvolatile write cycles. —The internal Write Enable latch resets on an invalid write operation. SYMBOL TABLEroWAVEFORM 6PeObsol etdu cINPUTS Must be steady May change from LOW to HIGH May change from HIGH to LOW Don’t Care: Changes Allowed N/A Will be steadyOUTPUTSWill change from LOW to HIGH Will change from HIGH to LOW Changing: State Not Known Center Line is High Impedancet—The internal Write Enable latch is reset automatically at the end of a nonvolatile write cycle.元器件交易网X84160/640/128ABSOLUTE MAXIMUM RATINGS* Temperature under Bias ...................... –65°C to +135°C Storage Temperature ........................... –65°C to +150°C Terminal Voltage with Respect to VSS .......................................–1V to +7V DC Output Current................................................... 5mA Lead Temperature (Soldering, 10 seconds)..........300°C RECOMMENDED OPERATING CONDITIONS Temperature Commercial Industrial Min. 0°C –40°C Max. +70°C +85°C +125°C *COMMENT Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and the functional operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Supply Voltage X84160/640/128X84160/640/128 – 2.5 X84160/640/128 – 1.8D.C. OPERATING CHARACTERISTICS (VCC = 5V ±10%) (Over the recommended operating conditions, unless otherwise speciﬁed.) Symbol ICC1 Parameter VCC Supply Current (Read) Min.PMax. 12 1 10 10 VCC x 0.3 VCC + 0.5 0.47LimitsroUnits mA Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ 10 MHzICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCC mA µA µA µA V V V V IOL = 2.1mA IOH = –1mAMilitary† –55°C Notes: † Contact factory for Military availabilityISB1 ILI ILO VlL (1) VIH(1)VCC Standby CurrentInput Leakage CurrentOutput Leakage Current Input LOW VoltageInput HIGH VoltagebsVOLOutput LOW Voltage Output HIGH Voltage VCC – 0.8VOHNotes: (1) VIL Min. and VIH Max. are for reference only and are not tested.Ool etICC2VCC Supply Current (Write)e–0.5VCC x 0.7du ctLimits 4.5V to 5.5V 2.5V to 5.5V 1.8V to 3.6V元器件交易网X84160/640/128D.C. OPERATING CHARACTERISTICS (VCC = 2.5V to 5.5V) (Over the recommended operating conditions, unless otherwise speciﬁed.) Symbol Parameter Limits Min. Max. 300 Units Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ VCC = 2.5, 5 MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCCICC1VCC Supply Current (Read)µAICC2 ISB1 ILI ILO VlL(1) VIH(1) VOL VOHVCC Supply Current (Write) VCC Standby Current Input Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC – 0.4 –0.5 VCC x 0.72 1 10 10 VCC x 0.3mA µA µA µA VVCC + 0.5 0.4PMax. 200 1 1 10 10 VCC x 0.3 VCC + 0.5 0.48ol etSymbolParametereD.C. OPERATING CHARACTERISTICS (VCC = 1.8V to 3.6V) (Over the recommended operating conditions, unless otherwise speciﬁed.) Limits Min. Units Test Conditions OE = VIL, WE = VIH, I/O = Open, CE clocking = VCC x 0.1/VCC x 0.9 @ VCC = 1.8V, 4 MHz ICC During Nonvolatile Write Cycle All Inputs at CMOS Levels CE = VCC, Other Inputs = VCC or VSS VIN = VSS to VCC VOUT = VSS to VCCICC1VCC Supply Current (Read)ICC2 ISB1 ILI ILOVCC Supply Current (Write) VCC Standby CurrentbsInput Leakage Current Output Leakage Current Input LOW Voltage Input HIGH Voltage Output LOW Voltage Output HIGH Voltage VCC – 0.2 –0.5 VCC x 0.7VlL(1)OVIH(1) VOL VOHNotes: (1) VIL Min. and VIH Max. are for reference only and are not tested.roV V V µA mA µA µA µA V V V Vdu cIOL = 1mA, VCC = 3V IOH = –400µA, VCC = 3V IOL = 0.5mA, VCC = 2V IOH = –250µA, VCC = 2Vt元器件交易网X84160/640/128CAPACITANCE Symbol CI/O(2) CIN(2) TA = +25°C, f = 1MHz, VCC = 5V Parameter Input/Output Capacitance Input Capacitance Max. 8 6 Units pF pF Test Conditions VI/O = 0V VIN = 0VPOWER-UP TIMING Symbol tPUR(3) tPUW(3) Parameter Power-up to Read Operation Power-up to Write OperationA.C. CONDITIONS OF TEST Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels5nsVCC x 0.5EQUIVALENT A.C. LOAD CIRCUITS5V 2.06KΩ OUTPUT 3.03KΩol eteP3V 2.8K Ω OUTPUT 30pF 5.6K Ω 30pF 2V9VCC x 0.1 to VCC x 0.92.39KΩOUTPUT30pF4.58KΩObsroNotes: (3) Time delays required from the time the VCC is stable until the speciﬁc operation can be initiated. Periodically sampled, but not 100% tested.du cMax. 2 5Notes: (2) Periodically sampled, but not 100% tested.tUnits ms ms元器件交易网X84160/640/128A.C. CHARACTERISTICS (Over the recommended operating conditions, unless otherwise specified.) Read Cycle Limits – X84160/640/128 VCC = 4.5V – 5.5V VCC = 2.5V – 5.5V VCC = 1.8V – 3.6V SymboltRC tCE tOE tOEL tOEH tLOW tHIGH tLZ(4)ParameterRead Cycle Time CE Access Time OE Access Time OE Pulse Width OE High Recovery Time CE LOW Time CE HIGH Time CE LOW to Output In Low Z CE HIGH to Output In High Z OE LOW to Output In Low Z OE HIGH to Output In High Z Output Hold from CE or OE HIGH WE HIGH Setup Time WE HIGH Hold TimeMin.70MaxMin.125Max.Min.25020 20 20 50 20 50 0 0 0 0 0 25 15 35 90 35 90 0du c25 70 25 70 70 180 70 180 0 0 0 25 0 0 25 25 30 30 25t OEH t OHZ HIGH Z t HZro0 0 0 0 25 25tHIGH tWEH tOHtHZ(4) tOLZ(4) tOHZ tOH tWES tWEH(4)P15e25Notes: (4) Periodically sampled, but not 100% tested. tHZ and tOHZ are measured from the point where CE or OE goes HIGH (whichever occurs ﬁrst) to the time when I/O is no longer being driven into a 5pF load.ol ettRC tLOWtCECEbsWEtWES tOEt OELOEOI/Ot OLZ t LZDATA10tMax.Unitsns ns ns ns ns ns ns ns ns ns ns ns ns nsOb so l et ePr od u ctX84160/640/128Write Cycle Limits – X84160/640/128Notes:(5)t NVWC sequence until the self-timed, internal nonvolatile write cycle is completed.(6)Data is latched into the X84160/640/128 on the rising edge of CE or WE, whichever occurs ﬁrst.(7)Periodically sampled, but not 100% tested.Symbol ParameterV CC = 4.5V – 5.5V V CC = 2.5V – 5.5V V CC = 1.8V – 3.6VUnits Min.Max.Min.Max.Min.Max.t NVWC (5)Nonvolatile Write Cycle Time 555ms t WCWrite Cycle Time70125250nst WP WE Pulse Width203550ns t WPH WE HIGH Recovery Time 5090180ns t CS Write Setup Time 000ns t CH Write Hold Time 000ns t CP CE Pulse Width203570ns t CPH CE HIGH Recovery Time 5090180ns t OES OE HIGH Setup Time 252550ns t OEH OE HIGH Hold Time 252550ns t DS (6)Data Setup Time 122030ns t DH (6)Data Hold Time 555ns t WPSU (7)WP HIGH Setup 100100150ns t WPHD (7)WP HIGH Hold100100150nsX84160/640/128CE Controlled Write CycleWE Controlled Write CycleOb soctX84160/640/1288-LEAD XBGA TYPE430±20X84640Z: Bottom ViewNOTE: ALL DIMENSIONS IN µMALL DIMENSIONS ARE TYPICAL VALUES20Ob soctX84160/640/1288-LEAD XBGA TYPEX84128: Bottom ViewNOTE: ALL DIMENSIONS IN µMALL DIMENSIONS ARE TYPICAL VALUES20Ob s octX84160/640/128NO TE:1.ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)2.PACKAGE DIMENSIONS EXCLUDE MOLDING FLASHTYP .8-LEAD PLASTIC DUAL IN-LINE P ACKAGE TYPE PHALF SHOULDER ALL MAX.X84160/640/1288-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE SNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)X84160/640/128PACKAGING INFORMATION14-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE SNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)Ob sou ctX84160/640/128PACKAGING INFORMATIONNOTE:ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)8-LEAD PLASTIC, TSSOP , PACKAGE TYPE V0° – 8°Ob so lt u ctX84160/640/128PACKAGING INFORMATIONNOTE:ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)20-LEAD PLASTIC, TSSOP PACKAGE TYPE V0° – 8Gage Plane Seating PlaneOb so lu ctX84160/640/128PACKAGING INFORMATIONNOTE:ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)28-LEAD PLASTIC, TSSOP PACKAGE TYPE V0° – 8Gage Plane Seating PlaneX84160/640/128LIMITED WARRANTYDevices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied.U.S. PATENTSXicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475;4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967; 4,883, 976. Foreignpatents and additional patents pending.LIFE RELATED POLICYIn situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.Xicor's products are not authorized for use in critical components in life support devices or systems.1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustainlife, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failureof the life support device or system, or to affect its safety or effectiveness.22。

特征库升级技术白皮书V11

特征库升级说明文档 ConplatConplat 特征库升级说明文档Prepared byDate2014-5-5杨兴博拟制日期Reviewed byDate评审人日期DateAuthorized by日期签发2014-5-5 页10页，共1第 Page 1 , Total 10 版权所有，侵权必究 All rights reserved特征库升级说明文档 Conplat Revision Recor修订记录修订版本作者日期Revision 描述Description Date Author version2014-3-20杨兴博初稿完成2014-5-5杨兴博按照文档规范进行修改2014-6-9杨兴博修订最新病毒特征库规格页10页，共22014-5-5 第 Page 2 , Total 10 版权所有，侵权必究 All rights reserved特征库升级说明文档 Conplat目录未定义书签。

错误!特征库简介一、...............................................未定义书签。

错误!特征库升级说明 ........................................... 二、未定义书签。

错误!设备初次启动 ................................................ 1.未定义书签。

! ................................................ 错误软件版本更换2.Conplat主线V100R003B00D013P02、神州一号V100R002B01D083之前版本及其他分支 ......................................................错误!未定义书签。

Conplat主线V100R003B00D013P02、神州一号V100R002B01D083及之后版本错误!未定义书签。

中国信息安全测评中心

中国信息安全测评中心测评公告（2019年第5号）中国信息安全测评中心是经中央批准成立的国家信息安全权威测评机构，主要职能包括：为信息技术安全性提供测评服务；信息安全漏洞分析和信息安全风险评估；信息技术产品、信息系统和工程安全测试与评估；信息安全服务和信息安全人员资质测评；信息安全技术咨询、工程监理与开发服务等。

根据国家职能授权，测评结果定期向社会公布。

特此公告。

中国信息安全测评中心二〇一九年十月附表：通过国家信息安全测评/注册信息安全工程师（CISE）的人员序号姓名证书编号发证日期有效期备注1.李辉CNITSEC2002CISE00029 2019-9-23 2022-9-22 维持2.谭述纲CNITSEC2002CISE00045 2019-9-232022-9-22维持3.杨力CNITSEC2004CISE00280 2019-9-232022-9-22维持4.黄春CNITSEC2004CISE00281 2019-9-232022-9-22维持5.沈勇CNITSEC2004CISE00285 2019-9-232022-9-22维持6.郑毅强CNITSEC2005CISE00388 2019-9-232022-9-22维持7.韩瑜CNITSEC2005CISE00728 2019-9-232022-9-22维持8.冀传坤CNITSEC2007CISE01225 2019-9-232022-9-22维持9.甘洋CNITSEC2007CISE01231 2019-9-232022-9-22维持10.金建新CNITSEC2008CISE01275 2019-9-232022-9-22维持11.颜喜宏CNITSEC2009CISE00174 2019-9-232022-9-22维持12.王喆CNITSEC2009CISE00309 2019-9-232022-9-22维持13.张鹏CNITSEC2009CISE00363 2019-9-232022-9-22维持14.熊文丹CNITSEC2009CISE00379 2019-9-232022-9-22维持15.刘志欣CNITSEC2009CISE00537 2019-9-232022-9-22维持16.冯晓冬CNITSEC2010CISE00014 2019-9-232022-9-22维持17.罗希CNITSEC2010CISE00047 2019-9-232022-9-22维持18.陈森CNITSEC2010CISE00248 2019-9-232022-9-22维持19.张腾标CNITSEC2010CISE00360 2019-9-232022-9-22维持20.赵兆CNITSEC2010CISE00369 2019-9-232022-9-22维持21.杨威CNITSEC2010CISE00424 2019-9-232022-9-22维持22.楼晓CNITSEC2010CISE00479 2019-9-232022-9-22维持23.王旭CNITSEC2010CISE00535 2019-9-232022-9-22维持24.卫威CNITSEC2011CISE00131 2019-9-232022-9-22维持25.凌晨CNITSEC2011CISE00348 2019-9-232022-9-22维持26.石磊CNITSEC2011CISE01033 2019-9-232022-9-22维持27.万京平CNITSEC2012CISE00203 2019-9-232022-9-22维持28.陈游生CNITSEC2012CISE01080 2019-9-232022-9-22维持29.邢振华CNITSEC2012CISE01052 2019-9-232022-9-22维持30.肖伟CNITSEC2012CISE01150 2019-9-232022-9-22维持31.李愿军CNITSEC2012CISE01258 2019-9-232022-9-22维持32.战莹CNITSEC2012CISE01330 2019-9-232022-9-22维持33.颜清华CNITSEC2012CISE01404 2019-9-232022-9-22维持34.韩国峰CNITSEC2012CISE01373 2019-9-232022-9-22维持35.王永琦CNITSEC2012CISE01374 2019-9-232022-9-22维持36.赵春CNITSEC2012CISE01386 2019-9-232022-9-22维持37.唐立忠CNITSEC2012CISE01437 2019-9-232022-9-22维持38.陆晨晖CNITSEC2012CISE01472 2019-9-232022-9-22维持39.杨凯利CNITSEC2013CISE00065 2019-9-232022-9-22维持40.廖谦CNITSEC2013CISE00067 2019-9-232022-9-22维持41.陈烁文CNITSEC2013CISE00119 2019-9-232022-9-22维持42.纪德伟CNITSEC2013CISE00121 2019-9-232022-9-22维持43.梁庆姿CNITSEC2013CISE00122 2019-9-232022-9-22维持44.刘冰琼CNITSEC2013CISE00123 2019-9-232022-9-22维持45.岳志鹏CNITSEC2013CISE00126 2019-9-232022-9-22维持46.张信庆CNITSEC2013CISE00127 2019-9-232022-9-22维持47.韦红金CNITSEC2013CISE00152 2019-9-232022-9-22维持48.常茜茜CNITSEC2013CISE00177 2019-9-232022-9-22维持49.王鹏CNITSEC2013CISE00178 2019-9-232022-9-22维持50.林丰洲CNITSEC2013CISE00192 2019-9-232022-9-22维持51.吴占玉CNITSEC2013CISE00193 2019-9-232022-9-22维持52.段卫东CNITSEC2013CISE00196 2019-9-232022-9-22维持53.张华云CNITSEC2013CISE00200 2019-9-232022-9-22维持54.张亚合CNITSEC2013CISE00251 2019-9-232022-9-22维持55.陈志伟CNITSEC2013CISE00295 2019-9-232022-9-22维持56.王立民CNITSEC2013CISE00313 2019-9-232022-9-22维持57.罗乐CNITSEC2013CISE00529 2019-9-232022-9-22维持58.屈闯CNITSEC2013CISE00496 2019-9-232022-9-22维持59.刘伟CNITSEC2013CISE00513 2019-9-232022-9-22维持60.庄严CNITSEC2013CISE00526 2019-9-232022-9-22维持64.钟振帆CNITSEC2013CISE00675 2019-9-232022-9-22维持65.徐逸飞CNITSEC2013CISE00613 2019-9-232022-9-22维持66.徐志元CNITSEC2013CISE00614 2019-9-232022-9-22维持67.陈曙光CNITSEC2013CISE00624 2019-9-232022-9-22维持68.李烁CNITSEC2013CISE00688 2019-9-232022-9-22维持69.冯伟CNITSEC2013CISE00702 2019-9-232022-9-22维持70.金蕊CNITSEC2013CISE00796 2019-9-232022-9-22维持71.黄海CNITSEC2013CISE00862 2019-9-232022-9-22维持72.霍立磊CNITSEC2013CISE00839 2019-9-232022-9-22维持73.陈仙住CNITSEC2013CISE00891 2019-9-232022-9-22维持74.陈永泉CNITSEC2013CISE00892 2019-9-232022-9-22维持75.黄丽荣CNITSEC2013CISE00895 2019-9-232022-9-22维持76.黄骁婷CNITSEC2013CISE00896 2019-9-232022-9-22维持77.张玮CNITSEC2013CISE00903 2019-9-232022-9-22维持78.郑晓伟CNITSEC2013CISE00904 2019-9-232022-9-22维持79.朱亮CNITSEC2013CISE01141 2019-9-232022-9-22维持80.姚磊CNITSEC2013CISE00931 2019-9-232022-9-22维持81.王蓓CNITSEC2013CISE00968 2019-9-232022-9-22维持82.魏建新CNITSEC2013CISE00972 2019-9-232022-9-22维持83.桑月秋CNITSEC2013CISE01069 2019-9-232022-9-22维持84.刘阳CNITSEC2013CISE01085 2019-9-232022-9-22维持85.马悦CNITSEC2014CISE00900 2019-9-232022-9-22维持86.李平CNITSEC2014CISE00945 2019-9-232022-9-22维持87.陈立治CNITSEC2014CISE00990 2019-9-232022-9-22维持88.罗浪涛CNITSEC2014CISE01150 2019-9-232022-9-22维持89.杨铮CNITSEC2014CISE01243 2019-9-232022-9-22维持90.蔡春景CNITSEC2014CISE01509 2019-9-232022-9-22维持91.郑太海CNITSEC2014CISE01595 2019-9-232022-9-22维持92.邢懿CNITSEC2015CISE00632 2019-9-232022-9-22维持93.余希CNITSEC2015CISE00643 2019-9-232022-9-22维持96.王东CNITSEC2015CISE00939 2019-9-232022-9-22维持97.潘善民CNITSEC2015CISE01053 2019-9-232022-9-22维持98.王陈诚CNITSEC2015CISE01288 2019-9-232022-9-22维持99.张剑峰CNITSEC2015CISE01491 2019-9-232022-9-22维持100.程璋CNITSEC2015CISE01611 2019-9-232022-9-22维持101.王立江CNITSEC2015CISE01678 2019-9-232022-9-22维持102.蒋梦凌CNITSEC2016CISE00016 2019-9-232022-9-22维持103.辜轶峰CNITSEC2016CISE00126 2019-9-232022-9-22维持104.曹渝CNITSEC2016CISE00128 2019-9-232022-9-22维持105.曹宇龙CNITSEC2016CISE00241 2019-9-232022-9-22维持106.皇甫张棣CNITSEC2016CISE00800 2019-9-232022-9-22维持107.李秉CNITSEC2016CISE00251 2019-9-232022-9-22维持108.刘玲丽CNITSEC2016CISE00402 2019-9-232022-9-22维持109.王烜CNITSEC2016CISE00404 2019-9-232022-9-22维持110.陶彦CNITSEC2016CISE00405 2019-9-232022-9-22维持111.王唐林CNITSEC2016CISE00289 2019-9-232022-9-22维持112.段正杰CNITSEC2016CISE00444 2019-9-232022-9-22维持113.黄强CNITSEC2016CISE00446 2019-9-232022-9-22维持114.江明CNITSEC2016CISE00447 2019-9-232022-9-22维持115.李坤CNITSEC2016CISE00448 2019-9-232022-9-22维持116.吕柯露CNITSEC2016CISE00449 2019-9-232022-9-22维持117.张亚珍CNITSEC2016CISE00453 2019-9-232022-9-22维持118.章其星CNITSEC2016CISE00454 2019-9-232022-9-22维持119.张亚强CNITSEC2016CISE00465 2019-9-232022-9-22维持120.蔡翔宇CNITSEC2016CISE00473 2019-9-232022-9-22维持121.文远CNITSEC2016CISE00479 2019-9-232022-9-22维持122.余基飞CNITSEC2016CISE00487 2019-9-232022-9-22维持123.陈远鹏CNITSEC2016CISE00530 2019-9-232022-9-22维持124.方武仪CNITSEC2016CISE00664 2019-9-232022-9-22维持125.孙星CNITSEC2016CISE00679 2019-9-232022-9-22维持129.朱阳阳CNITSEC2016CISE00926 2019-9-232022-9-22维持130.陈滢竹CNITSEC2016CISE00129 2019-9-232022-9-22维持131.王宁CNITSEC2016CISE00898 2019-9-232022-9-22维持132.钟慧CNITSEC2016CISE00936 2019-9-232022-9-22维持133.梁曦CNITSEC2016CISE00938 2019-9-232022-9-22维持134.林麓CNITSEC2016CISE01032 2019-9-232022-9-22维持135.刘晶晶CNITSEC2016CISE01138 2019-9-232022-9-22维持136.董玉君CNITSEC2016CISE01144 2019-9-232022-9-22维持137.孙宣CNITSEC2016CISE01149 2019-9-232022-9-22维持138.孟二飞CNITSEC2016CISE00450 2019-9-232022-9-22维持139.郝尚印CNITSEC2016CISE01222 2019-9-232022-9-22维持140.黄辉CNITSEC2016CISE01238 2019-9-232022-9-22维持141.于亚坤CNITSEC2016CISE01292 2019-9-232022-9-22维持142.刘雪梅CNITSEC2016CISE01293 2019-9-232022-9-22维持143.汤敏杰CNITSEC2016CISE01294 2019-9-232022-9-22维持144.姚梦薇CNITSEC2016CISE01295 2019-9-232022-9-22维持145.江楠CNITSEC2016CISE01297 2019-9-232022-9-22维持146.张琪CNITSEC2016CISE01298 2019-9-232022-9-22维持147.韦震CNITSEC2016CISE01268 2019-9-232022-9-22维持148.邵晋光CNITSEC2016CISE01277 2019-9-232022-9-22维持149.苏彦CNITSEC2016CISE01278 2019-9-232022-9-22维持150.黄维CNITSEC2016CISE01283 2019-9-232022-9-22维持151.林锴CNITSEC2016CISE01342 2019-9-232022-9-22维持152.魏明春CNITSEC2016CISE01320 2019-9-232022-9-22维持153.李辉CNITSEC2016CISE01440 2019-9-232022-9-22维持154.余玲CNITSEC2016CISE01450 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p13 Wessa 2014

Restorative Neurology and Neuroscience32(2014)51–62DOI10.3233/RNN-139007IOS Press51 Bipolar disorder:A neural network perspective on a disorder of emotion and motivationMich`e le Wessa b,∗,Philipp Kanske c and Julia Linke aa Section for Experimental Psychopathology and Neuroimaging,Department of General Psychiatry,University Hospital Heidelberg,Heidelberg,Germanyb Department of Clinical Psychology and Neuropsychology,Institute of Psychology,Johannes Gutenberg-University Mainz,Mainz,Germanyc Department of Social Neuroscience,Max Planck Institute for Human Cognitive and Brain Sciences,Leipzig,GermanyAbstract.Bipolar disorder(BD)is a severe,chronic disease with a heritability of60–80%.BD is frequently misdiagnosed due to phenomenological overlap with other psychopathologies,an important issue that calls for the identiﬁcation of biological and psychological vulnerability and disease markers.Altered structural and functional connectivity,mainly between limbic and prefrontal brain areas,have been proposed to underlie emotional and motivational dysregulation in BD and might represent relevant vulnerability and disease markers.In the present laboratory review we discuss functional and structural neuroimaging ﬁndings on emotional and motivational dysregulation from our research group in BD patients and healthy individuals at risk to develop BD.As a main result of our studies,we observed altered orbitofrontal and limbic activity and reduced connectivity between dorsal prefrontal and limbic brain regions,as well as reduced integrity ofﬁber tracts connecting prefrontal and subcortical brain structures in BD patients and high-risk individuals.Our results provide novel insights into pathophysiological mechanisms of bipolar disorder.The current laboratory review provides a speciﬁc view of our group on altered brain connectivity and underlying psychological processes in bipolar disorder based on our own work,integrating relevantﬁndings from others. Thereby we attempt to advance neuropsychobiological models of BD.Keywords:Vulnerability,behavioral activation system,emotion regulation,amygdala,orbitofrontal cortex,reward,connectivity1.IntroductionBipolar disorder is a severe and chronic mental dis-order that is one of the leading causes of disability worldwide,whose lifetime costs were estimated to be in excess of$45billion in the US alone(Wyatt& Henter,1995).Among the several subtypes of bipolar spectrum disorders,bipolar I disorder is character-ized by recurrent prominent mood swings that lead ∗Corresponding author:Mich`e le Wessa,Ph.D.,Department of Clinical Psychology and Neuropsychology,Institute of Psychology, Johannes Gutenberg-University Mainz,Wallstraße3,55122Mainz, Germany.Tel.:+4961313939259;E-mail:wessa@uni-mainz.de.to alternating phases of mania and depression with interspersed periods of euthymia.Key symptoms of mania include euphoric or irritable mood,ﬂight of ideas,pressure of speech,increased energy,and hyper-activity with an emphasis on pleasurable activities, even if they lead to negative consequences.In contrast, during depressive episodes patients report depressed mood,lack of energy and loss of interests,pessimistic thoughts,and reduced perception of and response to positive stimuli.To date,the diagnosis of bipolar disorder is based on the description of behavioral manifestations.However, due to its overlap with other psychopathological con-ditions,such as unipolar depression,schizophrenia or0922-6028/14/$27.50©2014–IOS Press and the authors.All rights reservedThis article is published online with Open Access and distributed under the terms of the Creative Commons Attribution Non-Commercial License.52M.Wessa et al./Bipolar disorder:A neural network perspectiveimpulse control disorders(Matza et al.,2005;Meyer& Meyer,2009;Mitchell et al.,2010),initial misdiagno-sis is common.This often leads to detrimental effects on the course of this disease(Findling,2009;Stens-land et al.,2008;Stensland et al.,2010)with a more severe and chronic progression in patients with late or misleading diagnosis.Therefore,research aiming at the identiﬁcation of vulnerability markers of bipo-lar disorder that allow an early and valid diagnosis is particularly important.An even more serious con-dition is that in neither of the previously mentioned psychopathologies causal therapy is available.As an ultimate goal it appears therefore essential to determine biological and psychological markers that are common to different pathologies or speciﬁc for a certain illness in order to develop tailored treatments.Further,mark-ers that change during the course of the disease might show potential for improvement under treatment and are therefore important to be identiﬁed.As family and twin studies showed a high heritabil-ity of bipolar disorder of60–80%(McGufﬁn et al., 2003),biological vulnerability factors seem to be of special importance for this disease.The diathesis-stress model,therefore,poses a good framework to develop etiological models that incorporate biological and psy-chological factors associated with the development and maintenance of bipolar disorder.In general,such mod-els assume that the interplay of biological vulnerability factors(Greek:diathesis)with environmental factors (stress)determines the onset and course of the disorder (Jones,2004).In bipolar disorder,neurobiological abnormalities on different levels have been identiﬁed,using various methods ranging from techniques examining intracel-lular and molecular mechanisms to neuroimaging of neural networks(Langan&McDonald,2009).Neu-robiological models of bipolar disorder(Phillips et al., 2008)generally assume a hypoactive dorsal neural sys-tem including the dorsolateral prefrontal,ventrolateral prefrontal,and dorsal anterior cingulate cortex as well as the hippocampus.This dorsal system is relevant for selective attention,planning,performance mon-itoring and voluntary regulation of emotional states in bipolar disorder.It has been hypothesized that the hypoactive dorsal system interacts with a hyperac-tive ventral brain system comprising amygdala,insula, ventral striatum,ventral anterior cingulate cortex and medial orbitofrontal cortex implicated in the detection of emotionally salient stimuli,mediation of autonomic responses to emotional stimuli and the generation of an emotional state(Keener&Phillips,2007).It is assumed that an imbalance and decreased connectivity between these two systems,particularly the ventrolat-eral prefrontal cortex and the amygdala,accounts for mood instability,motivational dysregulation and cog-nitive deﬁcits observed in patients with bipolar disorder (Cahill et al.,2009;Kurtz&Gerraty,2009;Strakowski et al.,2012;Wessa&Linke,2009).Most recently,it has been proposed that impaired white matter development in early life might pre-cede the onset of bipolar disorder.In more detail,it has been hypothesized that the impaired development of white matter results in impaired prefrontal-limbic modulation in two networks:(1)a network originat-ing in the ventrolateral prefrontal cortex and(2)a network starting from ventromedial prefrontal cor-tex.Both networks are similarly organized building iterative feedback loops that process information and modulate activity of the amygdala,the ventral striatum and the thalamus.Whereas theﬁrst network is assumed to be involved in the modulation of external emotional cues such as emotional faces,the second network sup-posedly regulates internal emotional states(Schneider et al.,2012;Strakowski et al.,2012).Although,the simplicity of this hypothesis is rather intriguing,we would like to point out that it neglects motivational aspects of bipolar symptomatol-ogy despite the fact that both emotion and motivation are related.Whereas the focus on emotion implies a certain state of feeling,the emphasis of motiva-tion relates to a certain state of goal pursuit like the achievement of pleasant and the avoidance of unpleas-ant feelings.Yet,to date,most of the existing studies in patients with bipolar disorder have focused on the neural correlates of aberrant emotion processing,mainly operationalized by paradigms that use emotionally evocative stimuli(e.g.,words,faces)during pas-sive viewing,implicit and explicit labeling tasks and response inhibition tasks(Houenou et al.,2011).How-ever,although tightly linked to emotion processing, the investigation of motivational processes,such as the anticipation of positive(reward)and negative con-sequences(punishment)and the response to their delivery has received little attention in theﬁeld.Yet, the evaluation of stimuli as appetitive(reward)or aver-sive(punishment)facilitates approach or avoidance motivation and behavior(Alloy&Abramson,2010). Indeed,motivational dysregulation and altered reward processing have been hypothesized as importantM.Wessa et al./Bipolar disorder:A neural network perspective53mechanisms of the alternating phases of mania and depression and as an endophenotype of bipolar disor-der(Hasler et al.,2006).In the present laboratory review we will provide a speciﬁc view of our group on the structural and func-tional neural mechanisms underlying emotional and motivational dysregulation in bipolar disorder based on our own work.By additionally integrating relevant ﬁndings from other group we attempt to contribute to a further development of neurobiological models of bipolar disorder.2.Motivational processesMost of the structures comprised in neurobiolog-ical models of bipolar disorder are innervated by dopaminergic projections ascending from the ventral tegmental area to the mesolimbic system,includ-ing ventral striatum,amygdala and hippocampus and to the mesocortical system comprising,among oth-ers,the dorsolateral prefrontal,anterior cingulate and orbitofrontal cortex(Depue&Iacono,1989).These dopamine-irrigated structures represent the neural cor-relate of the behavioral activation system that mediates individual differences in the sensitivity and reactivity to appetitive stimuli.High sensitivity of the behavioral activation system is associated with enhanced appet-itive stimulus processing and approach-motivation as well as the diminished processing of aversive stimuli. However,the behavioral activation system might also facilitate active avoidance responses,when safety is perceived as reward,and aggressive behavior,when reward acquisition is blocked(Gray,1987).In the con-text of bipolar disorder,dysregulation model of the behavioral activation system suggests a hypersensi-tive behavioral activation system as vulnerability factor (Alloy&Abramson,2010;Depue&Iacono,1989; Uros´e vic et al.,2008).Extremeﬂuctuations in acti-vation and deactivation of the behavioral activation system might be reﬂected in bipolar symptoms like “excessive involvement in pleasurable activities that have a high potential for painful consequences”dur-ing mania and“markedly diminished...pleasure in all, or almost all,activities”during depression(American Psychiatric Association,2000).On a behavioral level, reduced and delayed responses to more frequently rewarded stimuli(Pizzagalli et al.,2008)as well as longer reaction times for decisions that lead to reward or punishment(Gorrindo et al.,2005;McClure et al.,2005;Rich et al.,2005)were reported,suggesting a general deﬁcit in responding to motivationally relevant stimuli in bipolar disorder patients.However,our own results show a more differenti-ated pattern of reward and punishment processing in bipolar disorder.In euthymic bipolar disorder patients, we observed differential learning from positive and negative consequences depending on the last illness phase of the patients(Linke et al.,2011).Interest-ingly,currently euthymic bipolar patients who last experienced a manic episode showed a bias towards positive consequences,whereas bipolar patients who last experienced a depressive episode showed a bias towards negative consequences.This effect occurred even though patients had been euthymic for up to sixty months.To explain this carry-over effect from symptomatic to euthymic phases,we proposed that affective episodes might represent learning experi-ences during which patients perceive and experience outcomes(failure vs.success)and consequences (reward vs.punishment)mostly in a mood-congruent manner which shapes their perception of self-efﬁcacy as well as their action-outcome expectancies and outcome-consequence expectancies persisting beyond the symptomatic phases.The inﬂuence of action-outcome and outcome-consequence expectancies on personality constructs of generalized self-referential cognitions like control orientations and subjective knowledge(Krampen,1988)further explains the endurance of these biases,which might only be changed by very powerful learning experiences like the next affective episode or psychotherapy.These results correspond to the theoretical framework of the dysregulation model of the behavioral activation sys-tem(Uros´e vic et al.,2008)suggesting that altered expectancies and beliefs inﬂuence the appraisal as well as the creation and selection of events relevant for the behavioral activation system and thus interact with the dysregulation of that system.Furthermore,there is some evidence on brain func-tion and structure underlying this motivational bias. Altered activity of and changed connectivity between brain regions like the orbitofrontal cortex,rostral cin-gulate cortex,amygdala and striatum that are involved in motivation(Diekhof et al.,2008;Ernst et al.,2004) have been reported in patients with bipolar disor-der(for reviews see Blond et al.,2012;Strakowski et al.,2012)and might constitute the neuronal corre-late of differential responses to positive and negative feedback.54M.Wessa et al./Bipolar disorder:A neural network perspectiveIndeed,in a recent study,we observed decreased deactivation in the medial orbitofrontal cortex and greater activation of the amygdala in response to rever-sal of reward contingencies in euthymic patients with bipolar-I disorder and unaffectedﬁrst-degree relatives of bipolar I disorder patients(Linke et al.,2012a see Fig.1).Further,patients and relatives showed greater activation of the medial orbitofrontal cortex in response to reward delivery,whereas only in unaffectedﬁrst-degree relatives of bipolar patients(Linke et al.,2012a) and in healthy individuals carrying a genetic risk vari-ant(CACNA1C rs1006737)for bipolar disorder(Wessa et al.,2010)the amygdala appeared hyperactive in response to reward.However,in euthymic patients with bipolar-I disorder,hyper-activation of amygdala was normalized by psychotropic medication as indi-cated by a signiﬁcant negative correlation between medication load and amygdala activation to reward delivery.Differential activation patterns in medial orbitofrontal cortex during reward delivery and reversal of reward contingencies in BD patients and ﬁrst-degree relatives of bipolar disorder patients might represent different underlying mechanisms:whereas heightened activation of the medial orbitofrontal cor-tex(and amygdala)in response to reward is interpreted as heightened reward sensitivity,reduced deactivation of the medial orbitofrontal cortex and hyper-activation of the amygdala during reversal of reward contingen-cies,observed in both patients with bipolar disorder and healthy relatives of bipolar disorder patients represents an attenuated prediction error signal.Such an attenuated prediction error signal was particularly prominent in unaffected relatives when negative feedback was not followed by a behavioral change, which reminds of clinical symptoms in manic bipolar patients,who continue to pursue immediate rewards despite negative consequences(American Psychiatric Association2000).Interestingly,in a very recent neuropsychological study(Wessa et al.,unpublished manuscript)we observed increased delay aversion scores in healthyﬁrst-degree relatives of bipolar disorder patients,which reﬂect an impulsive behavior, i.e.,the inability to delay and inhibit responses in the context of reward-related decision-making.However, no such effect was present in bipolar disorder patients themselves.This even higher sensitivity to immediate rewards and impulsive behavior in healthy individuals at risk to develop bipolar disorder compared to bipolar patients might be related to medication effects.However,with respect to the prediction error signal and delay aversion we did not observe signiﬁcant correlations with medication load,which of course does not rule out that medication has some effect or that it has a more speciﬁc effect than we were able to detect with a rather global measure like the composite medication load score.Another explanation refers to the fact that bipolar disorder patients in our study were chronic patients with a history of multiple manic and depressive episodes and ideally,during psychotherapy, they already acquired some strategies to regulate their initially increased sensitivity to immediate reward and impulsivity.The convergent results in patients with bipolar dis-order,unaffectedﬁrst-degree relatives of patients with bipolar disorder(Linke et al.,2012a)and carriers of a genome-wide supported genetic risk variant for bipolar disorder(CACNA1C rs1006737,Wessa et al., 2010)strongly suggest that alterations in the medial orbitofrontal cortex and amygdala represent a trait marker for bipolar disorder.On a cautious note,these abnormalities might also contribute to increased ill-ness vulnerability,a proposition that is in line with the above-mentioned dysregulation theory of the behav-ioral activation system(Alloy&Abramson,2010). This theory suggests that a hypersensitive behavioral activation system,which regulates approach motiva-tion and goal-directed behavior and depends(amongst other structures)on the orbitofrontal cortex(Depue and Iacono,1989),mediates vulnerability for bipo-lar disorder.Indeed,further analyses of our data revealed moderate and signiﬁcantly positive correla-tions between the score on the behavioral activation system scale(Carver&White,1994)and neural acti-vation in the medial orbitofrontal cortex in response to reward and reversal of reward contingencies in bipo-lar disorder patients and their relatives.The behavior activation system scale measures dispositional sensi-tivity to the behavioral activation system(Carver& White,1994)and is calculated from questionnaire items loading high on the dimensions‘Drive’,‘Reward Responsiveness’and‘Fun Seeking’.Despite the evidence from our studies,the question whether alterations in the medial orbitofrontal cortex and amygdala in response to reward delivery and rever-sal of reward contingencies represent a vulnerability marker for bipolar disorder has to be further evaluated in longitudinal studies considering conversion rates in high-risk individuals,particularly at young age,to bipolar disorder or other psychopathologies.M.Wessa et al./Bipolar disorder:A neural network perspective55In addition to these potential vulnerability mark-ers for bipolar disorder,we also identiﬁed increased activity in the ventral putamen and lateral orbitofrontal cortex during reversal of reward contingencies.As described earlier,these structures have been subsumed under an external emotional control network in a recently published neurobiological consensus model of bipolar disorder(Strakowski et al.,2012).Further-more,increased activity in lateral orbitofrontal cortex seems to signal punishment and could thus repre-sent a compensatory mechanism in bipolar patients that aides to suppress previously rewarded responses (Cools et al.,2002)and potentially enables adequate performance during euthymia.Such compensatory recruitment of orbitofrontal structures was previously reported by our group for euthymic bipolar disorder patients during the inhibition of responses to emotional compared to neutral faces(Wessa et al.,2007). Taken as a whole,our results support neurobiolog-ical models of bipolar disorder,highlighting the role of the ventral prefrontal cortex and the amygdala as key structures in the development and maintenance of bipolar disorder(Blond et al.,2012;Strakowski et al.,2012).Ourﬁndings add to the existing models in identifying abnormal amygdala and ventral pre-frontal cortex functioning in response to reward as potential vulnerability marker for bipolar disorder.Fur-thermore,our data extend previous results by showing that heightened emotional reactivity in bipolar disorder is not limited to primary emotional cues but also occurs for positive and negative feedback probably leading to motivational dysregulation.3.Emotional processingAs pointed out,the majority of neuroimaging studies in bipolar disorder investigated the recog-nition of or reaction to emotional stimuli,such as emotional faces or words.In line with the clinical observation of an emotional instability and emotional hyper-reactivity in patients with bipolar disorder,an emotion-speciﬁc hyperactivity of ventral-limbic brain structures such as the amygdala,the insula,the anterior cingulate cortex and the orbitofrontal cortex has been repeatedly reported in adult depressed and euthymic bipolar disorder patients(Altshuler et al.,2005; Lawrence et al.,2004;Malhi et al.,2004;Wessa et al.,2007;Yurgelun-Todd et al.,2000).During mania, results are more conﬂicting with a number of studies reporting decreased rather than increased amygdala activity(Chen et al.,2010;Hulvershorn et al.,2012; Lennox,2004).In general,hyper-activation in ventral-limbic brain areas in bipolar disorder patients has been related to diminished top-down control,which is supported by studies showing reduced negative or even increased functional connectivity between the ventrolateral prefrontal cortex/anterior cingulate cortex and the amygdala in manic(Cerullo et al.,2012;Foland et al., 2008),euthymic(Wang et al.,2009)and depressed patients(Versace et al.,2010b).In addition to these task-related abnormal connectivity patterns,a rela-tively reduced negative correlation and decreased low frequency BOLDﬂuctuations between ventral pre-frontal/anterior cingulate cortex and amygdala activity at rest was reported in bipolar disorder patients as compared to healthy controls(Anand et al.,2009; Chepenik et al.,2010).Among other regions(e.g. medial prefrontal cortex,parietal cortex),the dorsal, anterior cingulate and ventrolateral prefrontal cortices have been found to underlie voluntary emotion reg-ulation through attentional control(e.g.distraction) or cognitive change(e.g.reappraisal)(Kanske et al., 2011;McRae et al.,2010).In bipolar disorder patients, hypo-activation of prefrontal structures and reduced negative functional connectivity between ventral pre-frontal and limbic brain areas might therefore lead to a deﬁcit in voluntarily down-regulating exaggerated emotional responses.Until now,however,very few studies have investi-gated neural correlates of voluntary emotion regulation in bipolar disorder although theoretical models,empir-ical data and clinical observations strongly suggest such regulation deﬁcits(Phillips et al.,2008).One major problem in emotion regulation research in bipolar disorder is a very heterogeneous conceptualiza-tion of emotion regulation,and consequently diverse operationalization in experimental research.Emotion regulation is part of a broader concept of emotional processing,including a pre-attentive stage,attention allocation,sensory perception,transient and automatic emotional responses,experience and expression of emotion,higher-level appraisal of emotional stim-uli,andﬁnally the regulation of emotions(Wessa &Linke,2009).From an experimental and clinical neuroscience perspective it is important to make a dis-tinction between these sub-processes in order to be able to validly characterize disturbed or maladaptive processes in psychopathology.56M.Wessa et al./Bipolar disorder:A neural network perspectiveAccording to Gross&Thompson(2007)regula-tion of emotions refers to the process of increasing or decreasing current affect.Such a process may occur consciously or unconsciously on a continuum from effortless and automatic(unconscious)to effort-ful and controlled regulation(conscious).Within their model of emotion regulation,Gross&Thompson (2007),differentiateﬁve types of emotion regula-tion strategies which can be broadly divided into (1)antecedent-focused strategies,occurring before full-blown emotional responses are elicited(situation selection,situation modiﬁcation,attentional deploy-ment,and cognitive change),and(2)response-focused strategies,occurring after emotional responses are gen-erated(response modulation).In experimental emotion regulation research,a focus has been placed on the investigation of a few strategies,particularly on dis-traction as an example for attentional deployment, reappraisal as an example for cognitive change and suppression as an example for response modulation. Whereas distraction refers to directing attention away from the emotional features of the situation to differ-ent,potentially non-emotional aspects of the situation, reappraisal means to change the connotation of a situ-ation or how we think about a situation in order to alter its emotional signiﬁcance.Previous studies in bipolar disorder employed exper-imental paradigms that included cognitive tasks(e.g., response inhibition,n-back task)with concurrently presented emotional stimuli(e.g.,Bertocci et al.,2012; Deckersbach et al.,2008;Elliott et al.,2004;Wessa et al.,2007).To assure successful task performance, study participants had to direct their attention away from the concurrently presented emotional stimulus and to focus on the cognitive task.Likewise,these studies might also be seen as investigating atten-tional deployment as one emotion regulation strategy. However,in their analyses the authors mainly investi-gated the distracting inﬂuence of emotion on cognitive processes,for example by contrasting brain activity associated with the task during the presentation of dis-tracting emotional stimuli versus neutral stimuli.Yet, to determine the neural correlates of the inﬂuence of cognitive task performance on emotional responses, and thus emotion regulation,a comparison between the ‘task+emotion’condition and‘emotion-only’condi-tion would be necessary.Previously,two studies investigated the impact of disturbing emotional information on response inhibition in manic and euthymic bipolar disorder patients,revealing increased ventral prefrontal activ-ity in bipolar patients when trying to inhibit responses to emotional faces compared to the inhibition of responses to neutral faces(Elliott et al.,2004;Wessa et al.,2007).Two more recent studies investigated working memory performance during either mood induction(Deckersbach et al.,2008)or concurrently presented emotional faces(Bertocci et al.,2012).In depressed bipolar disorder patients,Deckersbach et al.(2008)reported increased activation in dorsal ante-rior cingulate and dorsolateral prefrontal cortices while performing the working memory task under sad mood as compared to no mood induction.This might be interpreted as a greater demand for executive control to perform the cognitive task when being in a sad mood.Whereas Bertocci et al.(2012)did notﬁnd such compensatory activity in bipolar disorder patients, but reported elevated activity in the dorsal anterior cingulate cortex during high working memory-load and concurrently presented neutral faces in depressed patients with unipolar depression,suggesting compen-sational recruitment of brain regions belonging to the attentional control network.Interestingly,our group could show a similar effect in patients with unipolar depression not only for dis-traction but also for reappraisal(Kanske et al.,2012). Activity in the regulating control-network includ-ing anterior cingulate cortex and lateral orbitofrontal cortex was increased during both distraction and reap-praisal.In contrast,patients with unipolar depression showed a selective deﬁcit in down-regulating amyg-dala responses to negative emotional stimuli using reappraisal.This down-regulation of amygdala activ-ity was strongest in participants with high habitual use of reappraisal measured with the Cognitive Emo-tion Regulation Questionnaire(CERQ;Garnefski& Kraaij,2007)that assesses the regular use of reap-praisal or suppression as emotion regulation strategy during every-day life.These data are in line with previ-ous studies on cognitive control of emotions in patients with unipolar depression,suggesting a deﬁcit in the ability to down-regulate amygdala activity to negative emotional stimuli(Beauregard et al.,2006),and altered connectivity between the amygdala and prefrontal con-trol regions(Erk et al.,2010;Johnstone et al.,2007). To overcome the described gap in voluntary emo-tion regulation research in bipolar disorder patients, we recently completed a study on the neural correlates of two different voluntary emotion regulation strate-gies,i.e.,distraction and reappraisal,in patients with。

Schaeffler AG Coupa电子竞价系统供应商快速参考指南说明书

Coupa Quick Reference Guide for Suppliers | eAuctionsCoupa电子竞价系统供应商快速参考指南Welcome 欢迎Supplier Quick Reference Guide for Coupa | ContentCoupa 供应商快速参考指南| 内容Getting yourself set-up让你自己准备好Read more about how login to Coupa 阅读更多关于如何登录CoupaParticipating in the eAuction 参加电子竞价Get familiar how to participate in an eAuction熟悉如何参加一个电子竞价Get familiar with our Coupa project and eAuction types熟悉我们的coupa 项目和电子竞价类型Getting you on the road 带你上路English Reverse Auction 英式反向竞价Find more information on how you can enter bids in a English Reverse Auction 找到更多信息关于如何参加一个英式方向竞价Click here 点击这里Dutch Reverse Auction 荷兰式反向竞价Find more information on how you can enter bids in a Dutch Reverse Auction 找到更多信息关于如何参加一个荷兰式方向竞价Japanese Reverse Auction 日式反向竞价Find more information on how you can enter bids in a Japanese Reverse Auction 找到更多信息关于如何参加一个日式方向竞价Starting November 4th Schaeffler will launch a new NPM Purchasing Platform (Coupa) with the aim for Purchasing to become more customer centric and user friendly in line with efficiently working together with their business counterparts. We strive for:为加强以客户为中心，让使用者更友好，业务对应方工作更有效，11月4日开始舍弗勒将上线新的NPM 采购平台（Coupa ）.我们努力：•Intuitive and state-of-the-art system for requestor and purchaser 使用者及采购者直观及最先进的系统•High potential for self-service 潜力大的自助服务•Real-time tracking of supplier activities in Coupa 在Coupa 里实时跟踪供应商活动•Global standards and aligned processes 全球标准及协调一致的流程•Efficiency and effectiveness in decisions based on transparency & data•决策的效率和有效性基于数据且透明At a glance 快速摘要Getting you on the road 带你上路Exciting news for NPM Purchasing*NPM 采购部激动人心的新闻Coupa –working on one global platform Coupa-在一个全球平台上工作As a supplier you will find all the relevant information and access all necessary documents within one place. This will enable you to bid and interact with Schaeffler more effectively.作为一个供应商，你可以在同一个地方找到所有相关信息并可以进入所有必要的文件。

【CUUG内部资料】OCP最新考试题库-1Z0-062(5)

a procedure: CREATE OR REPLACE PROCEDURE create_test_v (v_emp_id NUMBER, v_ename VARCHAR2, v_SALARY NUMBER, v_dept_id NUMBER) IS BEGIN I/NSERT INTO hr.test VALUES (V_emp_id, V_ename, V_salary, V_dept_id); END;
AUTHID CURRENT_USER AS BEGIN
OCP最新考试题库 1015267481 INSERT INTO departments VALUES (v_deptno, v_dname, v_mgr, v_loc);
END; 2、调用该存储过程： CALL create_dept(44, 'Information Technology', 200, 1700);
】 E. Execute FLASHBACK TABLE OCA.EXAM_RESULTS TO BEFORE DROP RENAME TO 料 EXAM_RESULTS; connected as the OCP user. 部资 Correct Answer: C 【CUUG内 -1Z0-062 Section: (none)
能够执行这个存储过程，所以如果是 definer's rights 的话，执行就会出错，因为该模式下只能对 HR.DEPARTMENTS 的表进行操作；可能的情况下是这些用户自己有跟 HR 用户相同的
OCP最新考试题库 1015267481 表名字也叫 DEPARTMENTS，所以当执行这个存储过程的时候，修改的是自己的表，可以实
Explanation（验证过）（解析：因为是删除了用户，而且数据库版本是 11g，没有表恢复功能，但是从恢复工作量

1984866资料

Extract from the onlinecatalogPT 1,5/12-3,5-VOrder No.: 1984866The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1984866PCB terminal block, nominal current: 17.5 A, rated voltage: 160 V, pitch: 3.5 mm, number of positions: 2, mounting type: Soldering, connection method: Screw connection, connection direction from the conductor to the PCB: 90°http://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsLength9 mmHeight7.6 mmPitch 3.5 mmDimension a38.5 mmNumber of positions12Pin dimensions0,9 mmPin spacing 3.5 mm Hole diameter 1.2 mm Screw thread M 2 Tightening torque, min0.25 NmTechnical dataInsulating material group IRated surge voltage (III/3) 2.5 kV Rated surge voltage (III/2) 2.5 kV Rated surge voltage (II/2) 2.5 kV Rated voltage (III/2)200 V Rated voltage (II/2)400 V Connection in acc. with standard EN-VDE Nominal current I N17.5 A Nominal voltage U N160 V Nominal cross section 1.5 mm2 Maximum load current17.5 A Insulating material PA Inflammability class acc. to UL 94V0 Stripping length 5 mmConnection dataConductor cross section solid min.0.2 mm2 Conductor cross section solid max. 1.5 mm2 Conductor cross section stranded min.0.2 mm2 Conductor cross section stranded max. 1.5 mm2 Conductor cross section stranded, with ferrule0.25 mm2 with plastic sleeve min.Conductor cross section stranded, with ferrule0.75 mm2 with plastic sleeve max.Conductor cross section AWG/kcmil min.26 Conductor cross section AWG/kcmil max162 conductors with same cross section, solid min.0.2 mm2 2 conductors with same cross section, solid max.0.34 mm2 2 conductors with same cross section, stranded0.2 mm2 min.2 conductors with same cross section, stranded0.5 mm2max.Certificates / ApprovalsApproval logoCULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-16ULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-16Certification CCA, CUL, SEV, ULAccessoriesItem Designation DescriptionMarking1051993B-STIFT Marker pen, for manual labeling of unprinted Zack strips,smear-proof and waterproof, line thickness 0.5 mm0804073SK 3,5/2,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 10-section markerstrip, 14 identical decades marked 1-10, 11-20 etc. up to 91-100,sufficient for 140 terminal blocks0805030SK 3,5/2,8:SO Marker card, special printing, self-adhesive, labeled acc. tocustomer requirements, 14 identical marker strips per card, max.25-position labeling per strip, color: White0803883SK U/2,8 WH:UNBEDRUCKT Unprinted marker cards, DIN A4 format, pitch as desired,self-adhesive, with 50 stamped marker strips, 185 mm strip length,can be labeled with the CMS system or manually with the M-PEN 0811228X-PEN 0,35Marker pen without ink cartridge, for manual labeling of markers,labeling extremely wipe-proof, line thickness 0.35 mmTools1205037SZS 0,4X2,5Screwdriver, bladed, matches all screw terminal blocks up to 1.5mm² connection cross section, blade: 0.4 x 2.5 mmDrawingsDrilling diagramDimensioned drawingAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。

OCP8169 datasheet ver 1.1_20140622

Non-Isolated, En Dimming Buck High PFCController for LED Lighting Typical Application CircuitGeneral DescriptionThe OCP8169 is a critical conduction mode (CRM)constant current controller IC for single-stage buck LEDLighting. It can accept wide input voltage range of 85Vto 265VAC. OCP8169 works in critica l conductionmode to reduce switching losses. High power factor isachieved by constant on-time operation mode, withwhich the control scheme and the circuit structure areboth simple.In order to reduce the switching losses andimprove EMI performance, OCP8169 turn on the powerMOSFET at valley of drain voltage; the start up currentis rather small (5μA typically) to reduce the standbypower loss further; the maximum switching frequency isclamped to 125kHz to reduce switching losses andimprove EMI performance when the converter isoperated at light load condition.It achieves a total line/load regulation of +/-2.0%.The system operates in the constant on time mode toachieve high power factor. The ON time increases withthe input AC RMS voltage decreasing and the loadincreasing. When the operation condition is withminimum input AC RMS voltage and full load, the ONtime is maximized. On the other hand, when the inputvoltage is at the peak value, the OFF time is maximized.The ISEN input monitors the peak current value.The circuit design implements a compensation schemefor the current overshoot due to the turn-off delay.OCP8169 provides reliable protections such asLED Short Circuit Protection (SCP), Open LEDProtection (OLP), ZCD OVP, VCC OVP/UVLO, OverTemperature (OTP), and High temperature LEDcurrent compensation, etc.The device is available in SOP-8L package and israted over the -40°C to 85°C.Featuresz85V to 265V input rangez Constant Ton regulationz High power factor 0.95 (typ.)z< 20uA start-up currentz Valley switching with F SW limit at 125kHzz Total line/load regulation to ±2.0%z±3.0% Output Current Accuracyz Auto Restart Functionz Integrated LEB Circuitz V IN Supply OVP and ULVO Protectionz LED Open/Short Protectionz Over-temperature protections with restart delayz Cycle-by-Cycle Current Limitz LED Current Soft Startz Over Current Protectionz Small Solution Sizez RoHS and Green Compliantz SOP-8L Packagesz -40℃ to +85 ℃ Temperature RangeApplicationsz General LED Lightingz Down Lightz T8/T10 LED Tubesz E14/E27/PAR30/PAR38/GU10 Lamp Lightz PAR Lampz LED BulbApplicationz Dimmable and Non-Dimmable LED LampsPin ConfigurationSOP-8L(Top View)Figure 1, Pin Assignments of OCP8169Pin Name Pin No.I/O Pin Function SOP-8LCMP 1 I/O Compensation for the buck regulation loopZCD 2 I Zero-crossing detect (I2 current and bias-winding voltage)ISEN 3 I/OSwitching current detect pinGND 4 PGround PinGATE 5 OGate drive for external MOSFETVIN 6 PChip supply voltageEN 7 IEnablepinCT 8 I/O Output Current RegulationBlock DiagramFigure 3, Block Diagram of OCP8169Absolute Maximum Ratings1 (T A=25°C, unless otherwise noted)Parameter Symbol Rating UnitV IN Pin to GND V IN-0.3 to +25.0 VV GATE Pin to GND V GATE-0.3 to +20.0 VAll Other Pins to GND * -0.3 to +6.0 V Operating Temperature Range T OP-40 to +85 ℃Operating Junction Temperature Range T J-40 to +150 ℃Recommended Operating Conditions2Parameter Symbol Rating UnitV IN Pin Voltage to GND V IN+9.0 to +20 VOperating Temperature Range T OP-40 to +85 ℃Maximum Thermal Resistance SOP-8L ΘJA 150 ℃/WMaximum Power Dissipation T A<25°C P D 0.65 W Caution: 1: Stresses above those listed in absolute maximum ratings may cause permanent damage to the device. Functionaloperation at conditions other than the operating conditions specified is not implied. Only one absolute maximum rating should beapplied at any one time.2: The device is not guaranteed to function outside of its operating conditions.Electrical Characteristics(Typical values are at T A = +25℃, V IN = 12V, unless otherwise noted.)Symbol Parameter Conditions Min. Typ. Max. UnitSupplyV IN InputVoltage 9.01218VI Q Operating Current (no switching) - 0.9 1.5 mAI STARTUP Start-upCurrent 1520uA V IN ON UVLO Cut-In Level V IN Rising 14.5 16 17.5 VV IN OFF UVLO Cut-Out Level V IN Falling - 7.5 - VV IN OVP VIN OVP Voltage - 19.5 - VV OCP OCP Shut-Down Count By UVLO - 6.0 - VGate DriverT R Output Rising Time V IN =15V, C L=1nF - 120 - nS T F Output Falling Time V IN =15V, C L=1nF - 50 - nSV GATE H Maximum Gate Voltage V IN-0.3 V IN-0.2 V IN VT SW(MIN)Minimum T SW- 8 - uST OFF(MAX)Maximum T OFF- 50 - uST ON(MAX)Maximum T ON- 28 - uSF OP Maximum Operating Frequency - 125 - KHzCurrent SenseV CL Current Limit Voltage At fast start stage - 800 - mVV CL Current Limit Voltage At fast start-up - 1.72 - VT LEB Leading Edge Blanking Time - 500 - nSV CR Current Regulation Reference - 480 - mVEN and DimmingV EN ON PWM Dimming On 100% 3.0 - 5.0 VV EN OFF PWM Dimming Off 0% - - 0.8 VZCDV ZCD R ZCD Rising Threshold Voltage 1.1 1.2 1.3 VV ZCD F ZCD Falling Threshold Voltage 0.09 0.1 0.11 VT ZCDDELAY ZCD Sense Delay Time1- 2 - uS V OVP ZCD Protection By OVP 2.3 2.5 2.7 VProtectionV GATE H VIN Protection for Gate - 19 - VT RESET Reset Delay Time C COMP=1uF - 4 - S T SD ThermalShutdown -150-℃T SDHS Thermal Shutdown Hysteresis - 20 - ℃T80%The Temperature of 80% outputCurrent-140-℃Note: 1, Guarantee by DesignTypical Characteristics —OCP8169(Typical values are at TA = +25℃, V IN = 12V, unless otherwise noted.)VIN_ON Voltage vs. Temperature VIN_OFF Voltage vs. TemperatureVIN_OVP Voltage vs. TemperatureLED Current vs. Input VoltageVCR_TH Voltage vs. TemperatureStart Up Waveform (CH1=VIN, CH2=VSW)10111213141516 17 18 19 20 ‐40℃‐20℃0℃25℃50℃85℃I n p u t R i s i n g V o l t a g e (V )Temperature(℃)Input Rising Voltage vs. Temperature 6.5 6.7 6.9 7.1 7.3 7.5 7.77.9 8.1 8.3 8.5 ‐40℃‐20℃0℃25℃50℃85℃I n p u t T u r n ‐o f f V o l t a g e (V )Temperature(℃)Input Turn ‐off Voltage vs. Temperature19.019.1 19.2 19.3 19.4 19.5 19.6 19.7 19.8 19.9 20.0 ‐40℃‐20℃0℃25℃50℃85℃I n p u t C l a m p V o l t a g e (V )Temperature(℃)Input Clamp Voltage vs. Temperature IC VCC_CLAMPIC VCC_CLAMP_HYS295.0297.0 299.0 301.0 303.0 305.0 307.0 309.0 311.0 313.0 315.0 85100110132176220260L E D C u r r e n t (m A )Linear Voltage (V)LED Current vs Linear VoltageVCC=12V, 21pcs LED400.0410.0 420.0 430.0 440.0 450.0 460.0 470.0 480.0 490.0 500.0 ‐40℃‐20℃0℃25℃50℃85℃V C S _T H P r o t e c t i o n (m V )Temperature(℃)VC S_TH vs. TemperatureVCC=12VTypical Characteristics—OCP8169(Typical values are at T A = +25℃, V IN = 12V, unless otherwise noted.)Maximum Operation Frequency(CH2=VSW)LED Open Protection Waveform (CH1=VCC, CH2=VCOM)LED Short Circuit Protection Waveform (CH1=VIN, CH2=VCOMP)Functional DescriptionThe OCP8169 is a critical conduction mode (CRM) constant current controller IC for single-stage buck LED Lighting. It can accept wide input voltage range of 85V to 265V AC. O C P 8169 w o r k s i n c r i t i c a l conduction mode to reduce switching losses. High power factor is achieved by constant on-time operation mode, with which the control scheme and the circuit structure are both simple.In order to reduce the switching losses and improve EMI performance, OCP8169 turn on the power MOSFET at valley of drain voltage; the start up current is rather small (5μA typically) to reduce the standby power loss further; the maximum switching frequency is clamped to 125kHz to reduce switching losses and improve EMI performance when the converter is operated at light load condition.It achieves a total line/load regulation of +/-2.0%. The system operates in the constant on time mode to achieve high power factor. The ON time increases with the input AC RMS voltage decreasing and the load increasing. When the operation condition is with minimum input AC RMS voltage and full load, the ON time is maximized. On the other hand, when the input voltage is at the peak value, the OFF time is maximized.The ISEN input monitors the peak current value. The circuit design implements a compensation scheme for the current overshoot due to the turn-off delay.OCP8169 provides reliable protections such as LED Short Circuit Protection (SCP), Open LED Protection (OLP), ZCD OVP , VCC OVP/UVLO, Over Temperature (OTP), and High temperature LED current compensation, etc.Start UpThe input capacitor C IN is charged through the start-up resistor R ST , when the rectified ac input voltage HV is applied. The VIN current consumed by the OCP8169 is only 5μA (typical). While VIN reaches the upper V IN_ON threshold of 16V, the Internal VDDA linear regulator is enabled.When the VDDA regulator is turned on, the external capacitor at the CMP pin begins to charge. The PWM controller, current regulation circuit, protection circuit and gate driver are enabled when the CMP voltage reaches 0.9V. VIN will drop down by internal consumption of IC until the bias winding could supply energy to maintain VIN above 7.5V. The VDDA regulator will remain on until VIN falls to the lower UVLO threshold of 7.5V.Figure 4, Start Up WaveformThe start up resistor R ST and C IN are designed by rules below:(1), Preset start up resistor R ST , make sure that the current through R ST is larger than I STARTUP and smaller thanI QST BULKST Q BULK I VR I <<V Where V BULK is the BUS line V oltage.(2), Select C IN to obtain an ideal start up timer T ST , and ensure the output voltage is built up at one time.ONIN STST BULKINV T I C _ST *)R V (−=(3), If the C IN is not big enough to build up the output voltage at one time. Increase C IN and decease R ST , goInternal Pre-charge Design for Quick Start UpAfter VIN exceeds V IN_ON , V COMP is pre-charged by an internal current source. The PWM block won’t start to output PWM signal until V COMP is over the initial voltage V COMP_ON , which can be programmed by C COMP . Generally, a big capacitance of C COMP is necessary to achieve high power factor and stabilize the system loop (1μF~2μF recommended).Shut DownAfter AC supply or DC BUS is powered off, the energy stored in the BUS capacitor will be discharged. When the auxiliary winding of Flyback transformer can not supply enough energy to VIN pin, VIN will drop down. Once VIN is below V IN-OFF , the IC will stop working and V COMP will be discharged to zero.Constant Current ControlThe switching waveforms are shown in Fig.6.Figure 6, Switching WaveformThe output current I OUT can be represented by,2PKOUT I I =Where the I PK is the peak current of the inductor, the inductor peak current I PK and inductor current discharge time t DIS can be detected by the IC. I OUT can be represented by:SREFOUT R V I *2=Open LED Protection / Over Voltage ProtectionThe controller has 2 safety valves for OLP . One is the detection of VIN; another is the detection of ZCD. When the output is opened, the output voltage increases. The voltage of the bias winding is V OUT X N A / N (turn ration of Bias windings to main winding). Once VIN reaches 19.5V (typical) or ZCD exceeds 2.5V during the turn-off period of power MOSFET with 2us blanking, the controller will shut down power MOSFET. Due to the turn-off of the power stage, there is no energy transferred from transformer, VIN will drop down to 7.5V which triggers SCP , then the controller resume after a hiccup counter finish a cycle. The OLP protection threshold can be expressed the following equation:221_5.2Z Z Z A OVP OUT R R R N N V V +××=When the power MOSFET is turned off, a ringing voltage spike will occur at ZCD pin which may cause mis-trigger of OVP . The controller provides a 2us blanking timer for OVP detection. If the ZCD does not maintain for more than 2us and some fetal failure occurs, other protection circuits will help to cover the safety functions.Short Circuit ProtectionWhen the output is shorted to ground, the output voltage is clamped to zero. The voltage of the bias winding is V OUT X N A / N (turn ration of Bias windings to main winding). So VIN will drop down without bias winding supply. Once VIN drops down below 7.5V, the controller will shut down most of circuits except a hiccup counter with 150uA current consumption.The worst case design of R ST should provide 150uA charge current to maintain in hiccup mode at fault conditions. In high line condition, VIN will climb to higher voltage due to larger charge current. A 19V voltage clamping circuit will keep VIN below 19V which is a safer voltage for chip voltage rating and V GS of power MOSFET. The controller is still charged by VAC through R ST and operates in hiccup mode until the VAC is removed or faults are fixed.ZCD FunctionThe ZCD pin is connected to the auxiliary winding through a resistor divider. The ZCD pin is used for three functions.The first function is to detect the output voltage of secondary side. The internal circuit compares ZCD with 1.2V after 2us blanking time when AC power is applied. Before ZCD > 1.2V which means output voltage is too small for auxiliary winding to establish enough voltage for VIN, the chip will launch larger Gate output width to fasten the output voltage. At this stage, current limit for I SEN is 0.8V.The second function is to detect zero-cross condition of the auxiliary winding voltage after the secondary side current decreases to zero and starts a oscillation ringing which will hit a voltage below zero, the controller starts the next turn-on when ZCD pin is less than 100mV. This function achieves the boundary conduction mode operation to minimize the switching losses and EMI.The three function of ZCD pin is to implement the Open LED Protection by comparing to the internal 2.5V reference.Current Limit of ISEN / Leading Edge Blanking of ISENThe controller is built-in with a cycle-by-cycle current limit circuit to prevent external components from being damage under the failure conditions. When the current sense pin ISEN reaches 1.72V threshold, the controller turned off the power MOSFET. It will not be turned on again until the next cycle starts.In application circuit, when power MOSFET is turned on, a voltage spike may occur at ISEN pin due to circuit parasitic in the power stage. The controller will ignore 500ns leading-edge period at the turn-on of power MOSFET. It is to avoid power MOSFET being turned off by false detection of current-limit at ISEN pin.Over Temperature Protection / High Temperature CompensationThe controller has two states temperature compensation when it experiences a high junction temperature.(1) 140 o C < T JC <150 o C, Only 80% of current will be delivered to LED.(2) 150 o C < T JC , the power MOSFET is turned off. VIN will drop down below 7.5V. The restart mechanisms inhiccup mode resume the operation once the junction temperature is cooled down below 130 o C.Ordering InformationPart Number Driver Capability Package Type Package Qty Temperature EcoPlanLeadOCP8169SAD Controller SOP-8L13-in reel2500pcs/reel-40～85℃Green CuMarking Information SOP-8LPackage Information SOP-8L:Symbol Dimensions In Millimeters Dimensions In Inches Min. Max. Min. Max.A 1.350 1.750 0.053 0.069 A1 0.100 0.250 0.004 0.010 A2 1.350 1.550 0.053 0.061b 0.330 0.510 0.013 0.020c 0.170 0.250 0.006 0.010D 4.700 5.100 0.185 0.200E 3.800 4.000 0.150 0.157 E1 5.800 6.200 0.228 0.244 e 1.270 (BSC) 0.050 (BSC)L 0.400 1.270 0.016 0.050 θ0o8o0o8oPage11 - 11 Ver. 1.1 June. 22, 2014 OCP8169Packing InformationPackage TypeCarrier Width(W) Pitch(P) Reel Size(D) Packing MinimumSOP-8L 12.0±0.1 mm 4.0±0.1 mm 330±1 mm2500pcs Note: Carrier Tape Dimension, Reel Size and Packing Minimum。

API-618-石油化工和天然气工业用往复式压缩机标准的解释重点PPT

上式中令BL= [σ]/9.81, 无油：BL=0.035/9.81=0.00357 kg/mm2
有油：BL=0.07/9.81=0.0713 kg/mm2
关于支承环宽度AGW
上式完全对应于DS-1-2-2-R0 2、在Excel表格中计算AGW时，其给出的公式为：
AGW
a 0.866
(WP
学习体会：
1、气缸需要得到良好的冷却效果，但是又不能过冷造成气体冷凝，因此，冷却剂出口温度最好为(Ts+5K)<=Tc<=(Ts+16K) 2、并没有明文规定非得使用软化水作为冷却剂，使用硬水也是可以的，只要夹套/管道不堵塞，保证足够的冷却剂流量和流速即可。
关于冷却系统
2.11.4.4 当填料使用压力循环来冷却时，卖方应提供装于中体外部的公称规格为125 μm的使用的过滤器或更好的过滤器。
API-618 学习
关于气缸套表面粗糙度
2.6.2.5 有油润滑或无油润滑，活塞带有金属或非金属支承环和支承环的应用场合中，缸套的孔径和无缸套的气缸孔径其表面粗糙度算术平均值（Ra）应在0.2～0.6μm（8～24μin）。在部分客户中，对缸套表面粗糙度等级的理解都有一个误区，那就是：缸套表面粗糙度等级越高，对气缸的工作越有利，其实并不然。表面粗糙度底固然会加剧环的磨损，但如果表面粗糙度过高会使得润滑油（有油工况）和气缸环磨损下的非金属粉末（无油工况）没有足够的空间着床镀膜，这同样会加剧环的磨损。所以，当缸套有表面粗糙度较高的镀层时，着床镀膜过程较难形成，就不得不采用相对耐磨性较好的材料。综上所述，这也就是API618规定Ra0.2～0.6μm为缸套表面粗糙度标准范围的原因所在。
2.11.5 当填料需要冷却时，卖方有责任向买方提供最低限度的数据，如流量、冷却液的流动、压力降和温度以及任何过滤和防腐准则。冷却液通过填料函的压力降不得超过1.7bar( 25lb/in2 )。

OCS LED照明解决方案

灿瑞半导体有限公司
Orient-Chip Semiconductor Co., LTD
LED照明驱动电源解决方案

◆ 灿瑞半导体有限公司简介 ◆ LED照明电源驱动产品和方案介绍
隔离式 AC-DC的PSR+CC/APFC+PSR+CC IC；非隔离式 AC-DC的Buck/ APFC + Buck IC；高压 Linear + CC IC； DC-DC+CC IC；

应用方案
1、OCP8153-7W球灯原理图： 2、电源实物图：
效率＞85% PSR技术
7W省吸收，比同类产品更低的系统成本
内置650V高压 MOS可省RCD网络
PCB Layout注意事项： 1、Vcc旁路电容离芯片尽可能近 2、FB采样电阻远离环路中的动点且靠近芯片为佳 3、励磁回路和退磁回路尽可能短，避免造成EMI干扰 4、电流采样电阻功率地尽可能短，其他小信号地线需要分别连接到Bulk电容地端，避免构成地回路
DC-DC
Part No. OCP2185 OCP2186 控制方式 Buck+CC Buck+CC 输入电压 6V-30V 6V-40V 输出功率 8W 8W 典型效率 92% 92% 恒流精度 ± 3% ± 3%

一、隔离式 AC-DC PSR+CC/APFC+CC

应用方案
1、OCP8150_5W球泡灯方案原理图：
对电感量不敏感
2、方案实物图：
效率＞80%
PSR技术
独有的恒流检测技术，小于2%的恒流精度，小于3%的批量一致性
PCB Layout注意事项： 1、Vcc旁路电容离芯片尽可能近 2、FB采样电阻远离环路中的动点且靠近芯片为佳 3、励磁回路和退磁回路尽可能短，避免造成EMI干扰 4、电流采样电阻功率地尽可能短，其他小信号地线需要分别连接到Bulk电容地端，避免构成地回路

OCP8165最新资料(2014版)

OCP8165 是一款集成了 500V MOSFET 高精度非隔离 LED 恒流驱动芯片，工作在电流临界连续模式，支持全电压输入 AC85V~265V。芯片采用 DIP8 封装形式，内部集成了 500V 开关，利用 CS 脚设定电流，OCP8165 内部工作电流很小(大约 100uA)，无需辅助绕组监测和供电，只需要很少的外围元器件既可优异的输出恒流精度，节约了系统成本和体积。 OCP8165 集成了高精度电流取样电路，使得 LED 的输出电流精度达到±3%以内；实现优异的线电压调整率，线性调整率达到 3%以内。OCP8165 工作在电流临界模式，输出电流不随电感量和 LED 工作电压的变化而变化，实现优异的负载调整率，载调整率 2%以内，同时实现效率 90%以上。 OCP8165 具备完善的保护功能，芯片包括 LED 短路检测，一旦发现短路信号芯片便会进入较低的工作频率以限制输出功率。芯片的保护包括原边电流过流检测、 LED 短路保护、CS 开路保护、欠压锁定和过温保护功能以保证整个系统在恶劣的工作环境中安全可靠的工作。 OCP8165 使用环保材料的 DIP-8L 封装，工作温度范围为-40 度到 85 度之间。
Queiscent Current (uA)
‐40℃ 25℃ 85℃ 7 8 9 10 11 12 13 14 15 16 Input Turn‐off Voltage(V) 电流检测电压 vs. 温度
7
8
9 10 11 12 13 14 15 16 Input Rsing Voltage(V)
θJA
PDMAX(注2) TA TJ TSTO
注 1：最大极限值是指超出该工作范围，芯片有可能损坏。注 2：温度升高最大功耗一定会减小，这也是由 TJMAX, θJA,和环境温度 TA 所决定的。最大允许功耗为 PDMAX = (TJMAX TA)/ θJA 或是极限范围给出的数字中比较低的那个值。

数字芯王牌COM816

数字芯王牌COM816四川海讯电子内部培训资料 TCL 数字芯王牌数字芯王牌COM816-A 数字程控交换机培训大纲电话交换机培训思路: 1、对系统主要特点的了解。

2、硬件连接: 接线方式、板卡、地线。

3、软件连接: 安装软件、上传数据、备份。

4、调试软件: 按照交换机监控和设置进行。

下载数据 5、测试安装使用: 内部通话测试内话打外话测试，包括长途和短途。

外话打内话测试系统主要特点全弹性免拨0出局虚拟网功能) 出局( 免拨出局(虚拟网功能) 分组功能配置灵活接口丰富内外线区别振铃内置式语音信箱含UPS的开关电源的开关电源交换机主机结构主控板CPU 主控板分机控制板ECPU 分机控制板音令板TONE 音令板中继板TRK 中继板TRK 用户板EXT 用户板电源POWER 电源硬件连接按规定连接好电脑和键盘、显示器。

将鼠标插入电脑9针的串口，一般应为 COM2。

将随交换机配置的25针插头插入串口1，如标有字符的应为COM1，如为9针插口，可接25针/9针的转接插座。

通讯线接法如下图。

软件连接话务管理系统的安装: 1、卸载CAD(根据个人经验，会出现与CAD2007的冲突。

) 2、随机向用户提供系统安装光盘，在光盘里的Disk1目录包含SETUP.EXE执行文件，用鼠标双击即可开始安装，然后根据系统提示即可完成安装。

系统权限操作人员等级分为“操作员级”、“管理员级”、“维护员级”，其中以“维护员级”最高。

操作员级可进行话务监控、用户设置及管理、话单查询及结算、用户及中继参数设置等操作。

操作员级出厂工号为2222，出厂密码为2222。

管理员级除以上功能外，还可进行操作员管理、字头表及弹性号码设置等操作。

管理员级出厂工号为 1111，出厂密码为1111。

维护员级除以上功能外，还可进行操作员及管理员管理、串行口设置、系统板级设置、费率设置、折价日及折价时段设置等操作。

维护员级出厂工号为 0000，出厂密码为0000。

StorageTek Tape Analytics 数据参考指南说明书

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C8-6销售团队的有效训练0712(讲义)

C8 销售管理 VOL.01/2007
• 效果原则 • 使用原则 • 最先原则 • 近期原则 • 强度原则 • 重复原则
TM
C8 销售管理 VOL.01/2007
重新检核自己对培训资源的使用是否有效
效益最大化
积极的影响
育苗要耐心
TM
C8 销售管理 VOL.01/2007
成人学习的四大效应
TM
C8 销售管理 VOL.01/2007
自己也能事先展开行动。 9. 能够想出新点子。 10. 对于各种咨讯都很敏感。 11. 能够留给别人良好的第一印象。 12. 充分用语言或文字表达自己的想法。
18. 企划及计划力 19. 统制力 20. 应变力 21. 执着 22. 压力忍耐性 23. 同理心 24. 挑战心 25. 社交性
13. 让对方了解你，帮助你。
• 为了企业的生存与发展 • 市场竞争的需要 • 消除恐惧感和自卑感 • 实现科学的销售 • 加强销售队伍的凝聚力 • 培养高级销售代表的重要手段
TM
C8 销售管理 VOL.01/2007
培训模型
解释
标定期义望目
团队成员是否理解对他
们的期望
评估
提定高义技有巧待
是否有合适的能力和技
巧
推动
TM
C8 销售管理 VOL.01/2007
重新检核自己对培训流程的执行是否到位
系统化
立体化
流程化
TM
C8 销售管理 VOL.01/2007
总结
没有比培训更划算的投资了，让下属成长，可以让经理去做更重要的事情或钓鱼去！
TM
C8 销售管理 VOL.01/2007
课程大纲
一．销售培训的四大误区二．成人学习的四大效应三．销售培训的四大步骤四．销售培训的常用方法五．培训后的辅导与跟踪

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VCC=12V ‐20℃ 0℃ 25℃ 50℃ 85℃
Temperature(℃)
LED Current (mA)
315.0 313.0 311.0 309.0 307.0 305.0 303.0 301.0 299.0 297.0 295.0
85
LED Current vs Linear Voltage
芯片 ISEN 脚采样变压器原边的电流峰值，芯片内部对由于 MOS 管关断延迟造成的原边电流过冲进行了补偿。
OCP8166 提供多种保护，诸如 LED 短路保护（SCP）,LED 开路保护（OLP），ZCD 过压， VIN 过压和欠压，芯片过温保护（OTP）,和高温 LED 电流补偿等等。
RDS(ON) BVDSS
IDSS 保护
MOSFET 开启电阻 MOSFET 击穿电压
MOSFET 漏电
VGATE_H
VIN 及 GATE 脚电压钳位
TRESET
系统重启延迟时间
TSD
过温保护温度
TSDHS
过温保护解除迟滞
T80%
80%电流温度
注: 1, 设计保证
条件
VIN 上升 VIN 下降通过欠压实现
范围
单位
VIN脚对GND电压
VIN
+9.0 to +20
V
最大输出电流
ILED
250
mA
最大输出功率
85~265VAC 220VAC±15%
POMAX
12 18
W W
工作温度范围
TOP
-40 to +85
℃
最大热阻
SOP-8L
ΘJA
150
℃/W
最大功耗
TA<25°C
PD
0.65
W
注: 1, 强制超出极限参数范围可能导致器件的永久性损坏。芯片工作时工作条件不要超过工作条件范围，任何一次应用中任何一
芯片 ISEN 脚采样变压器原边的电流峰值，芯片内部对由于 MOS 管关断延迟造成的原边电流过冲进行了补偿。 OCP8166 提供多种保护，诸如 LED 短路保护（SCP）,LED 开路保护（OLP），ZCD 过压， VIN 过压和欠压，芯片过温保护（OTP）,和高温 LED 电流补偿等等。
启动提供输入 AC 整流以后的高压，输入电容 CIN 通过启动电阻 RSTR 充电。OCP8166 消耗的启动电流只有 5uA(典
19.1
IC VCC_CLAMP_HYS
19.0
‐40℃ ‐20℃ 0℃ 25℃ 50℃ 85℃ Temperature(℃)
基准电压 vs. 温度
530.0 520.0 510.0 500.0 490.0 480.0 470.0 460.0 450.0 440.0 430.0
‐40℃
VC S_TH vs. Temperature
I/O
管脚功能
I/O 原边电流采样 P 芯片供电脚 I 电感电流过零检测（基于辅助绕组电压） I/O 环路补偿脚 P 芯片地 O 内部 MOS 漏端
Page1 - 10
Ver. 1.0 May 20, 2014
典型应用电路
OCP8166
模块框图
图表 1，OCP8166 的典型应用电路
图表 3，OCP8166 模块框图
TSW(MIN) TOFF(MAX) TON(MAX) 电流采样
最小开关周期最大退磁时间最大开启时间
VCL VCL TLEB VREF 电感电流过零检测
CS 脚限流值 CS 脚限流值前沿消隐时间输出电流基准
VZCD_R VZCD_F TZCDDELAY VOVP 输出级
过零检测上升阈值过零检测下降阈值过零检测前沿消隐时间 ZCD 输出过压保护
图 4, 启动波形
启动电阻RST和VIN电容CIN可以根据以下规则设计。
(1), 设置RST电阻的大小，以确保流过它的电流大于启动电流ISTARTUP且小于芯片的工作电流IQ
VBULK IQ
< RST
< VBULK I ST
这里VBULK 是母线上的电压。 (2),设置CIN的大小以获得理想的启动时间 TST,，确保输出电压可以一次建立起来。
-
50
-
uS
-
28
-
uS
-
750
-
mV
-
1.5
-
V
-
500
-
nS
-
480
-
mV
1.1
1.2
1.3
V
0.09 0.1
0.11
V
-
2
-
uS
2.3
2.5
2.7
V
-
-
500
-
-
-
6.5
Ω
-
V
2
uA
-
19
-
V
-
4
-
S
-
150
-
℃
-
20
-
℃
-
140
-
℃
Page3 - 10
Ver. 1.0 May 20, 2014
(除非特别指定，典型值在25度的条件下，电源电压12伏) 最大工作频率 (CH2=VSW)
OCP8166
LED开路保护波形 (CH1=VSW, CH2=VCOM)
LED开路保护波形 (CH1=VSW)
Page5 - 10
Ver. 1.0 May 20, 2014
OCP8166
功能描述
OCP8166 是一款临界导通模式恒流 LED 控制器,适用 85~265VAC 宽输入电压范围应用。OCP8166 在系统环路稳定时芯片固定开启时间以实现高功率因数，芯片在电感电流退为零且功率管 DRAIN 端电压处于谷底时开启功率管，工作在临界导通模式减少开关损耗，使用固定开启时间成就高功率因数，典型值大于 0.95。
该芯片采用 SOP-8L 封装，工作温度范围从-40°C 到 85°C。
非隔离高功率因数 LED 驱动器
主要特点
z 85V 交流到 265V 交流输入电压范围 z 原边固定 Ton 调制 z 高功率因数，典型值大于 0.95 z 集成 500V MOSFET z 最大开关频率限制在 125KHz z 内置 QR 功能，谷底开启 MOS 管，以实现高效率 z ±2.0%以内的负载调整率 z 负载开路/短路保护 z 芯片过温保护及解除后自动恢复 z <20uA 的启动电路 z 逐周期的原边过流限制 z 芯片 VIN 脚的过压及欠压保护 z 内置 CS 脚的前沿消隐 z 负载电流的软启动 z RoHS 绿色环保材料封装 z SOP-8L 封装 z -40℃ to +85 ℃的环境工作温度
用一个闭环系统来调整 Ton 时间，芯片检测输出的平均电流，再把此电流对比一个基准相比得到一个差分电压，差分电压再来调制 Ton 时间，Ton 时间又改变输出电流，通过此闭环系统来实现输出电流的恒定。OCP8166 启动电流很小（5uA typical）以进一步减小系统能量损耗。在轻载或输入交流电压谷底时，芯片最大开关频率被钳位在 125KHz 以减小开关损耗和提高 EMI 性能。
TS TJ TLEAD
-55 to +150 -40 to +150
300
注意: 最大极限值是指超出该工作范围，芯片有可能损坏，因此应保证任何条件下不超出此age2 - 10
Ver. 1.0 May 20, 2014
OCP8166
推荐工作条件（注2）
参数
符号 l
C IN
=
( VBULK R ST
− I ST ) *TST
VIN _ ON
(3)如果CIN不足够大以让输出电压可以一次建立起来，请增大CIN和减小RST, 重复上面的设计直到系统可以一次顺利启动。
内部的快速启动CMP脚预充电设计
当 VIN 高过芯片启动阈值电压 VIN_ON 时，CMP 脚电容将通过一个内部的电流源预充电。芯片直到 CMP 脚电压达到 0.9V 时才会开始开关动作，这个充电时间可以通过设置 CMP 脚电容的大小来设置不同值。通常情况下，为了得到一个理想的功率因数和实现环路稳定 CMP 脚电容需要一个较大的值。 (推荐 1μF~2μF)。
‐40℃ ‐20℃ 0℃ 25℃ 50℃ 85℃ Temperature(℃)
电源过压电压 vs. 温度
Input Turn‐off Voltage(V)
Input Turn‐off Voltage vs. Temperature 8.0 7.9 7.8 7.7 7.6 7.5 7.4 7.3 7.2 7.1 7.0
应用
z 常规 LED 照明 z LED PAR30、PAR38 灯 z LED 日光灯 z LED 筒灯、D 射灯、球泡灯
管脚排列
SOP-8L (外观示意图)
图二，OCP8166 各管脚定义
管脚名字 ISEN
VIN ZCD CMP GND SW
编号 SOP-8L
1 2 3 4 5, 6 7, 8
快速启动阶段启动后
输出过压 VGS=10V, ID=0.5A VGS=0V, ID=250uA VDS=500V, VGS=0V
输出电流降为满载电流80%
最小值典型值最大值单位
9.0
12
18
V
-
0.9
1.5 mA
1
5
20
uA
14.5
16
17.5
V
-
7.5
-
V
-
19.5