KS88C6116中文资料

1PRODUCT OVERVIEWSAM8 PRODUCT FAMILYSamsung's SAM8 family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide range of integrated peripherals, and various mask-programmable ROM sizes. Important CPU features include:—Efficient register-oriented architecture—Selectable CPU clock sources—Idle and Stop power-down mode release by interrupt—Built-in basic timer with watchdog functionA sophisticated interrupt structure recognizes up to eight interrupt levels. Each level can have one or more interrupt sources and vectors. Fast interrupt processing (within a minimum six CPU clocks) can be assigned to specific interrupt levels.KS88C6108/C6116/P6116 MICROCONTROLLERSThe KS88C6108/C6116/P6116 single-chip 8-bit microcontroller is based on the powerful SAM8 CPU architecture. The internal register file is logically expanded to increase the on-chip register space. The KS88C6108/C6116/P6116 have 8/16 K bytes of on-chip program ROM.Following Samsung's modular design approach, the following peripherals were integrated with the SAM8 core:—Four programmable I/O ports (total 28 pins)—One 8-bit basic timer for oscillation stabilization and watchdog functions—One 8-bit general-purpose timer/counter with selectable clock sources—One 8-bit counter with selectable clock sources, including Hsync or Csync input—One 8-bit timer for interval mode—PWM block with seven 8-bit PWM circuits —Sync processor block (for Vsync and Hsync I/O, Csync input, and Clamp signal output)—Multi master IIC-bus with DDC support.The KS88C6108/C6116/P6116 are a versatile microcontroller that is ideal for use in multi-sync monitors or in general-purpose applications that require sophisticated timer/counter, PWM, sync signal processing, and multi-master IIC-bus support withDDC. It is available in a 42-pin SDIP or a 44-pin QFPpackage.Figure 1-1. KS88C6108/C6116/P6116MicrocontrollersFEATURESCPU•SAM8 CPU coreMemory•8/16-Kbyte internal program memory (ROM)•272-byte general-purpose register areaInstruction Set•78 instructions•IDLE and STOP instructions added for power-down modesInstruction Execution Time•500 ns minimum (with 12 MHz CPU clock)Interrupts•Nine interrupt sources•Nine interrupt vectors•Six interrupt levels•Fast interrupt processing for a select levelGeneral I/O•Four I/O ports (total 28 pins):8-Bit Basic Timer•Programmable timer for oscillation stabilization interval control or watchdog timer functions •Three selectable internal clock frequenciesTimer/Counters•One 8-bit general-purpose timer/counter with programmable operating modes and the following clock source options:—Two selectable internal clock frequencies •One 8-bit timer with interval operating mode •One 8-bit counter with the following clock source options:—Two selectable internal clock frequencies—Hsync (or Csync) input from the syncprocessor block—External clock sourcePulse Width Modulator•Seven 8-bit PWM modules:—8-bit basic frame—Four push-pull and three n-channel,open-drain output channels—Selectable clock frequencies: 46.875 kHz at12 MHz fosc.Sync Processor•Detection of sync input signals (Vsync-I, Hsync-I, and Csync-I)•Sync signal separation and output (Hsync-O, Vsync-O, and Clamp-O)•Pseudo sync signal output•Programmable clamp signal outputDDC and Multi-Master IIC-Bus•Serial peripheral interface•Support for display data channel (DDC) Oscillator Frequency• 6 MHz to 12 MHz external crystal oscillator •Interval Max. 12MHz CPU clockOperating Temperature Range•–40°C to + 85°COperating Voltage Range• 4.5 V to 5.5 VPackage Types•42-pin SDIP, 44-pin QFPBLOCK DIAGRAMRESET P1.0k 1.3X IN X OUTMAIN OSCP3.0k 3.7INTERNAL BUSP2.0k 2.7PORT 0P0.0k 0.7/INT0-INT2PORT 28-BIT PWM (7-CH)SYNC PRO-CESSORTIMER 0PORT 1PORT3PWM0PWM1•••PWM6Vsync-I Hsync-I Csync-I Vsync-O Hsync-O Clamp-OT0CAP8-blt Counter (TIMER 1)T1CKDDC and Multi master IIC-busSCL SDAINT0-INT2TESTInterval timer (TIMER 2)SAM8 CPU8/16-KBYTE MASK ROM272-BYTE REGISTER FILEI/O PORT and INTERRUPTCONTROLFigure 1-2. Block DiagramPIN ASSIGNMENTSP3.1P3.0P0.0 / INT0P0.1 / INT1P0.2 / INT2P0.3P0.4 / T0CAPP0.5 / T1CKVDDP0.6P0.7P1.0P1.1P1.2P1.3 P2.0 / PWM0 P2.1 / PWM1 P2.2 / PWM2 P2.3 / PWM3 P2.4 / PWM4 P2.5 / PWM 5KS88C6108/KS88C611642-SDIP(Top View)123456789101112131415161718192021424140393837363534333231302928272625242322P3.2VSS2P3.3P3.4P3.5P3.6P3.7RESETXOUTXINVSS1P2.7 / Csync-IHsync-IVsync-I (VCLK)Clamp-OHsync-OVsync-OSCLSDATESTP2.6 / PWM6Figure 1-3. Pin Assignment Diagram (42-SDIP Package)PIN ASSIGNMENTS (Cont.)P 2.0 / P W M 0P 1.3P 1.2P 1.1P 1.0P 0.7P 0.6V D DP 0.5 / T 1C KP 0.4 / T 0C A P P 0.3P2.1 / PWM1 P2.2 / PWM2 P2.3 / PWM3 P2.4 / PWM4 P2.5 / PWM5N.C.P2.6 / PWM6TEST SDA SCL Vsync-OP0.2 / INT2 P0.1 / INT1 P0.0 / INT0 P3.0 P3.1 NC P3.2 VSS2 P3.3 P3.4 P3.5H s y n c -OC l a m p -OV s y n c -IH s y n c -IP 2.7 / C s y n c -IV S S 1X I NX O U TR E S E TP 3.7P 3.634 35 36 37 38 39 40 41 42 43 4422 21 20 1918 17 16 15 14 13 12KS88C6108/ KS88C6116 44-QFP (Top View)12345678910113332313029282726252423Figure 1-4. Pin Assignment Diagram (44-QFP Package)PIN DESCRIPTIONSTable 1-1. KS88C6108/C6116/P6116 Pin DescriptionsPin NamesPinTypePinDescriptionCircuitTypeSDIP PinNumbersSharedFunctionsP0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7I/O General-purpose, 8-bit I/O port. Sharefunctions include three external interruptinputs, I/O for timers 0 and 1. You canselectively configure port 0 pins to input oroutput mode.D-13456781011INT0INT1INT2T0CAPT1CKP1.0–P1.3I/O General purpose, 8-bit I/O port. You canselectively configure port 1 pins to input orpush-pull output mode.D-112–15–P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7I/O General purpose, 8-bit I/O port. You canselectively configure port 2 pins to input oroutput mode. The port 2 pin circuit aredesigned to push-pull PWM output andCsync signal input.D-1D-1D-1D-1E-1E-1E-1D-11617181920212231PWM0PWM1PWM2PWM3PWM4PWM5PWM6Csync-IP3.0–P3.7I/O General-purpose, 8-bit I/O port. You canselectively configure port 3 pins to input oroutput mode.E2, 1, 42,40–36–Hsync-I Vsync-I Clamp-O Hsync-O Vsync-O SCL SDAIIOOOI/OI/OThe pins are sync processor signal I/O andIIC-bus clock and data I/OAAAAAG-3G-330292827262524–V DDV SS1, V SS2–Power supply pins–932, 41–X IN, X OUT–System clock input and output pins–33, 34–RESET I System reset pin B35–TEST I Factory test pin input0 V: normal operation5 V: factory test mode–23–NOTE:See ‘Pin Circuit Diagrams’ on next two pages for detailed information on circuit types A, B, D-1, E, E-1,and G-3.PIN CIRCUITSVssVddFigure 1-5. Pin Circuit Type AVddNoise Filter280 K ΩRESETFigure 1-6. Pin Circuit Type B (RESET )OutputVssVddOutput DisableData orOther functionDigital Input or TTL InputFigure 1-7. Pin Circuit Type D-1Typical 47-K ΩDataVddOutputPull-upenableInputVssOpen drainOutput DisableVddFigure 1-7. Pin Circuit Type EOutput DisableDataIN/OUTInputVssOpen drain VddFigure 1-8. Pin Circuit Type E-1Output DataVssInputFigure 1-9. Pin Circuit Type G-3NOTES16ELECTRICAL DATAOVERVIEWIn this section, KS88C6108/C6116 electrical characteristics are presented in tables and graphs. The information is arranged in the following order:—Absolute maximum ratings— D.C. electrical characteristics—I/O capacitance— A.C. electrical characteristics—Oscillation characteristics—Oscillation stabilization time—Schmitt trigger characteristicsTable 16-1. Absolute Maximum Ratings(T A = 25°C)Parameter Symbol Conditions Rating Unit Supply voltage V DD–– 0.3 to + 7.0V Input voltage V I1Type C (n-channel, open-drain)– 0.3 to+ 10V V I2All port pins except V I1– 0.3 to V DD + 0.3Output voltage V O All output pins– 0.3 to V DD + 0.3V Output currentHighI OH One I/O pin active– 10mAAll I/O pins active– 60Output currentLowI OL1One I/O pin active+ 30mAI OL2Total pin current except port 3+ 100I OL3Sync-processor I/O pins and IIC-busclock and data pins+ 150OperatingtemperatureT A–– 40 to + 85°CStoragetemperatureT STG–– 65 to + 150°CTable 16-2. D.C. Electrical Characteristics(T A= – 40°C to + 85°C, V DD = 4.5 V to 5.5 V)Parameter Symbol Conditions Min Typ Max Unit Input HighvoltageV IH1All input pins except V IH2 and V IH30.8 V DD–V DD VV IH2X IN, X OUT V DD – 0.5V DDV IH3TTL input (HsyncI, VsyncI and CsyncI) 2.0V DDInput Low voltage V IL1All input pins except V IL2and V IL3––0.2 V DD V V IL2X IN, X OUT0.4V IL3TTL input (HsyncI, VsyncI and CsyncI)0.8Output High voltage V OH1V DD= 4.5 V to 5.5 VI OH = – 8 mA Port 1 onlyV DD – 1.0––VV OH2V DD = 4.5 V to 5.5 VI OH = – 2 mA Ports 0, 2, ClampO, Hand VsyncOV DD – 1.0V OH3V DD = 4.5 V to 5.5 VI OH = – 6 mA, Port 3V DD – 1.0Table 16-2. D.C. Electrical Characteristics (Continued)(T A= – 40°C to + 85°C, V DD = 4.5 V to 5.5 V)Parameter Symbol Conditions Min Typ Max UnitOutput Low voltage V OL1V DD= 4.5 V to 5.5 VI OL = 8 mA, port 1 only––0.4VV OL2I OL = 2 mAPort 0, 2, ClampO, HsyncO andVsyncO0.4V OL3I OL = 6 mAPort 3, SCL and SDA0.4Input High leakage current I LIH1V IN = V DDAll input pins except X in, X out––3µAI LIH2V IN = V DDX OUT only––20I LIH3V IN = V DDX IN only2.5620Input Low leakage current I LIL1V IN= 0 VAll input pins except X in, X outand RESET–––3µAI LIL2V IN= 0 V; X OUT only––– 20I LIL3V IN= 0 V; X IN only– 2.5– 6– 20Output High leakage current I LOHL V OUT = V DDAll output pins except port 1––3µAOutput Lowleakage currentI LOL V OUT = 0 V––– 3µAPull-up resistor R L1V IN= 0 V;V DD = 4.5 V to 5.5 VPort 3204780kΩR L2V IN= 0 V;V DD = 4.5 V to 5.5 VRESET only150280480Supply current (NOTE)I DD1V DD= 4.5 V to 5.5 V12 MHz CPU clock–1530mAI DD2Idle mode;V DD = 4.5 V to 5.5 V12 MHz CPU clock510I DD3Stop mode; V DD = 5.0 V110µANOTE: Supply current does not include drawn internal pull–up resistors and external loads of output.Table 16-3. Data Retention Supply Voltage in Stop Mode(T A = – 40 °C to + 85 °C)Parameter Symbol ConditionsMin Typ Max Unit Data retention supply voltage V DDDR Stop mode2–6V Data retention supply currentI DDDRStop mode, V DDDR = 2.0 V––5µANOTES :1. During the oscillator stabilization wait time (t WAIT ), all CPU operations must be stopped.2. Supply current does not include drawn through internal pull–up resistors and external output current loads.V DDRESETEXECUTION OF STOP INSTRUCTIONV DDDRDATA RETENTION MODESTOP MODERESETOCCURSNORMAL OPERATING MODEOSCILLATION STABILIZATIONTIMEt WAITNOTE : t WAIT is the same as 4096 × 32 × 1 / f OSC .≈≈Figure 16-1. Stop Mode Release Timing When Initiated by a ResetTable 16-4. Input/Output Capacitance(T A = –40°C to + 85°C, V DD = 0 V)Parameter Symbol ConditionsMin Typ Max Unit Inputcapacitance C IN f = 1 MHz; unmeasured pins are connected to V SS––10pFOutputcapacitance C OUT I/O capacitanceC IOTable 16-5. A.C. Electrical Characteristics(T A = – 40°C to + 85°C, V DD= 4.5 V to 5.5V)Parameter Symbol Conditions Min Typ Max UnitNoise Filter t NF1H,t NF1L P0.2–P0.0, T0CAP andT1CK (RC delay)300––nst NF2RESET only (RC delay)800––1 t CPUt NF1L t NF1H0.8 V DDt NF20.2 V DDNOTE: The unit t CPU means one CPU clock period.Figure 16-2. Input Timing Measurement Points for P0.0–P0.2, T0CAP and T1CKTable 16-6. Oscillation Characteristics(T A = – 40°C + 85°C)Oscillator Clock CircuitConditionsMin Typ Max Unit Main crystal or ceramicC2C1X IN X OUT V DD = 4.5 V to 5.5 V6–12MHzExternal clock (main)X IN X OUTV DD = 4.5 V to 5.5 V6–12MHzNOTE :The maximum oscillator frequency is 12 MHz. If you use an oscillator frequency higher than 12 MHz, you cannotselect a non-divided CPU clock using CLKCON settings. That is, you must select one of the divide-by values.Table 16-7. Oscillation Stabilization Time(T A = – 40°C + 85°C, V DD = 4.5 V to 5.5 V)Oscillator Test ConditionMin Typ Max Unit Crystal V DD = 4.5 V to 5.5 V ––20msCeramic V DD = 4.5 V to 5.5V––10External clockX IN input High and Low level width (t XH , t XL )25–500ns NOTE :Oscillation stabilization time is the time required for the CPU clock to return to its normal oscillation frequency aftera power-on occurs, or when Stop mode is released.X INt XL t XH1 / f OSCV DD =0.5 V 0.4 VFigure 16-3. Clock Timing Measurement Points for X INV DD V SS V outA B C D V inA : 0.2 V DDB : 0.4 V DDC : 0.6 V DDD : 0.8 V DDFigure 16-4. Schmitt Trigger Characteristics (Normal Port; except TTL Input)NOTES17MECHANICAL DATAOVERVIEWThe KS88C6116 microcontroller is available in a 42-pin SDIP package (Samsung part number 42-SDIP-600) and a 44-QFP package (Samsung part number 44-QFP-1010B).NOTE : Dimensions are in millimeters.42-SDIP-60014.00 =0.20.50 =0.139.10 =0.20 ~ 15 °0.25+0.1 =0.05#121422215.24(1.77)1.00 =0.11.7780.51M I N3.50 =0.23.30 =0.35.08M A XFigure 17-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600)NOTE : Dimensions are in millimeters.44-QFP-1010B13.20 =0.3#44(1.00)#113.20 =0.30.35+0.10- 0.050.10 MAX0~8°0.05 MIN 2.05 =0.102.30 MAX0.80=.200.15+0.10 - 0.0510.00 =0.210.00 =0.20.80Figure 17-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)18KS88P6116 OTPOVERVIEWThe KS88P6116 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the KS88C6108/C6116 microcontrollers. It has an on-chip EPROM instead of masked ROM. The EPROM is accessed by serial data format.The KS88P6116 is fully compatible with the KS88C6108/C6116, both in function and in pin configuration.Because of its simple programming requirements, the KS88P6116 is ideal for use as an evaluation chip for the KS88C6108/C6116.P3.2V SS2/V SS P3.3P3.4P3.5P3.6P3.7RESET /RESET XOUT XIN V SS1/V SS P2.7/Csync-1Hsync-1 Hsync-1 (VCLK)Clamp-O Hsync-O Vsync-O SLC SDA TEST/V PP P2.6/PWM6424140393837363534333231302928272625242322123456789101112131415161718192021KS88P611642-SDIP (Top View)P3.1P3.0P0.0/INT0P0.1/INT1P0.2/INT1P0.3P0.4/T0CAP P0.5/T1CK V DD /VDDP0.6P0.7SCLK /P1.0SDAT /P1.1P1.2P1.3P2.0/PWM0P2.1/PWM1P2.2/PWM2P2.3/PWM3P2.4/PWM4P2.5/PWM5NOTE: The bolds indicate an OTP pin name.Figure 18-1. KS88P6116 Pin Assignments (42-SDIP Package)P 2.0 / P W M 0P 1.3P 1.2P 1.1 / S D A TP 1.0 / S C L KP 0.7P 0.6V D D / V D DP 0.5 / T 1C KP 0.4 / T 0C A P P 0.3P2.1 / PWM1 P2.2 / PWM2 P2.3 / PWM3 P2.4 / PWM4 P2.5 / PWM5N.C.P2.6 / PWM6 V PP /TESTSDA SCL Vsync-OP0.2 / INT2 P0.1 / INT1 P0.0 / INT0 P3.0 P3.1 NC P3.2 VSS2 / VSS P3.3 P3.4 P3.5H s y n c -OC l a m p -OV s y n c -IH s y n c -IP 2.7 / C s y n c -IV S S / V S S 1X I NX O U TR E S E T / R E S E TP 3.7P 3.6KS88P6116 44-QFP (Top View)34 35 36 37 38 39 40 41 42 43 44123456789101122 21 20 1918 17 16 15 14 13 123332313029282726252423NOTE: The bolds indicate an OTP pin name.Figure 18-2. KS88P6116 Pin Assignments (44-QFP Package)Table 18-1. Descriptions of Pins Used to Read/Write the EPROMMain Chip During ProgrammingPin Name Pin Name Pin No.I/O Function P1.1SDAT13 (*30)I/O Serial DATa Pin (Output when reading, Inputwhen writing) Input & Push-pull Output Port canbe assignedP1.0SCLK12 (*29)I Serial CLocK Pin (Input Only Pin)TEST V PP(TEST)23 (*41)I EPROM Cell Writing Power Supply Pin(Indicates OTP Mode Entering) When writing12.5V is applied and when reading 5V isapplied.(Option)RESET RESET35 (*9)I Chip InitializationV DD / V SS1 /V SS2V DD / V SS /V SS9 / 32 / 41(*26 / 6 / 15)I Logic Power Supply Pin. V DD should be tied to5V during programming.NOTE:* means the 44-QFP OTP pin number.Table 18-2. Comparison of KS88P6116 and KS88C6108/C6116 Features Characteristic KS88P6116KS88C6108/C6116 Program Memory16 K byte EPROM16 K byte mask ROMOperating Voltage (V DD) 4.5 V to 5.5 V 4.5 V to 5.5VOTP Programming Mode V DD = 5 V, V PP(TEST)=12.5VPin Configuration42SDIP, 44QFP42SDIP, 44QFPEPROM Programmability User Program 1 time Programmed at the factory OPERATING MODE CHARACTERISTICSWhen 12.5 V is supplied to the V PP(TEST) pin of the KS88P6116, the EPROM programming mode is entered. The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in Table 16-3 below.Table 18-3. Operating Mode Selection CriteriaV DD VPP(TEST)REG/MEMADDRESS(A15-A0)R/W MODE5 V 5 V00000H1EPROM read12.5 V00000H0EPROM program12.5 V00000H1EPROM verify12.5 V10E3FH0EPROM read protection NOTE:"0" means Low level; "1" means High level.D.C. ELECTRICAL CHARACTERISTICSTable 18-4. D.C. Electrical Characteristics(T A= – 40 °C to + 85 °C, V DD = 4.5 V to 5.5 V)Parameter Symbol Conditions Min Typ Max UnitInput High leakage current I LIH1V IN = V DD;All input pins except X in, X out––3µAI LIH2V IN = V DD;X OUT only20I LIH3V IN = V DD;X IN only2.5620Input Low leakage current I LIL1V IN= 0 V;All input pins except X in, X outand RESET–––3µAI LIL2V IN= 0 V; X OUT only––– 20I LIL3V IN= 0 V; X IN only– 2.5– 6– 20Output Highleakage currentI LOH1V OUT = V DD––3µAOutput Lowleakage currentI LOL1V OUT = 0 V––– 3µA Supply current I DD1Normal operating mode;12 MHz CPU clock–1530mAI DD2IDLE mode;12 MHz CPU clock510I DD3Stop mode; V DD = 5.0 V–110µA Data retentionsupply voltageVDDDR Stop mode2–6VData retentionsupply voltageIDDDR Stop mode; VDDDR = 2V––5µASTART Address= First Location V DD=5V, V PP=12.5Vx = 0 Program One 1ms PulseIncrement Xx = 10Verify 1 ByteLast Address V DD = V PP= 5 V Compare All Byte Device Passed Increment AddressVerify ByteDevice FailedPASSFAILNOFAIL YESFAILNOFigure 18-3. OTP Programming AlgorithmNOTE。