FPGA可编程逻辑器件芯片EP1C25F672C8N中文规格书

System Reset and Booting
TWI Master Boot Mode
In TWI master boot mode (BMODE = 0101) the boot kernel reads boot data from I2C memory connected to the TWI0 interface. The Blackfin proces-sor selects the slave EEPROM with the unique ID 0xA0, submits
successive read commands to the device starting at internal address
0x0000, and begins clocking data to the processor. The EEPROM’s device select bits A2–A0 must be 0s (tied low) when present. The I2C EPROM device should comply with Philips I2C Bus Specification version 2.1 and should have the capability to auto increment its internal address counter such that the contents of the memory device can be read sequentially.
Connections are shown in Figure17-21“TWI Master Boot Mode Con-nections” on page17-77.
On the Blackfin processor, in both TWI master and slave boot modes, the upper 512 bytes starting at address 0xFF903E00 either
must not be used or must be booted last. The boot ROM code uses
this space for the TWI boot modes to temporarily hold the serial
data which is then transferred to L1 instruction memory using
DMA. All boot blocks that target the L1 instruction memory or
external memories must have the BFLAG_INDIRECT bit set. Initcodes
can alter the placement of the temporary buffer by modifying the
pTempBuffer and dTempByteCount variables in the ADI_BOOT_DATA
structure.
Figure 17-21. TWI Master Boot Mode Connections
ADSP-BF54x Blackfin Processor Hardware Reference
Programming Examples
R0 = ( SYSCTRL_VRCTL | SYSCTRL_INTVOLTAGE | SYSCTRL_WRITE );
R1 = FP;
R1 += -sizeof(ADI_SYSCTRL_VALUES);
R2 = 0 (z);
IMM32(P4,BFROM_SYSCONTROL);
call(P4);
SP += 12;
(R7:0,P5:0) = [SP++];
unlink;
rts;
__voltage.end:
The previous sequence must also be executed when the V DDINT voltage is applied externally to ensure internal timings can appropriately be adjusted for the constant or changing V DDINT voltage. In this case, replace the SYSCTRL_INTVOLTAGE flag with the SYSCTRL_EXTVOLTAGE flag.
ADSP-BF54x Blackfin Processor Hardware Reference。