16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-

16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital CircuitsMustafa Badaroglu1,2, Marc van Heijningen1, Vincent Gravot1, John Compiet1, Stéphane Donnay1,Marc Engels1, Georges Gielen3, Hugo De Man1,31 IMEC, Leuven, Belgium2 Also Ph.D. student at K.U. Leuven, Belgium3 K.U. Leuven, BelgiumSubstrate noise degrades the performance of analog circuits integrated on the same substrate with digital circuits. In these mixed-signal ICs, the low cost and lower static power consumption of CMOS logic are shadowed by the larger noise generation due to the large rail-to-rail voltages and the sharp current spikes during switching. We have designed and measured a mixed-signal chip, fabricated in a 0.35µm CMOS process on an epi-type substrate, which allows us to compare several low-noise digital designs in CMOS.Alternative logic families have been proposed such as current-mode logic [1] or self-timed logic which show orders of magnitude noise reduction, however with increasing static power and delay sensitivity respectively. A few publications exist about low-noise digital CMOS design, e.g. CMOS gates with guard wiring and on-chip decoupling [2], where 67% noise reduction is achieved, but with considerable area penalty due to the additional circuitry and power rails.The test chip (Figure 16.6.1) contains one reference design (REF) and two digital low-noise designs (LN1, LN2) with the same basic architecture, shown in Figure 16.6.2. LN1 employs an optimized clock tree to make the supply current flatter and LN2 employs a separate substrate bias, dual-supply, and on-chip decoupling. REF has an area of 0.362mm2, a maximum speed of 45MHz and a core power consumption of 112mW at 42MHz and 3.3V. It is possible to disable the I/O pads in order to measure the substrate noise generation from the core logic only. In that case the input is generated by an on-chip 10-bit Pseudo Random Binary Sequencer (PRBS). The noise measurements have been performed with an on-chip noise sensor [4], which is a differential amplifier withone input connected to a quiet ground, the other input capacitively coupled to the substrate and with 3 dB amplification from 20kHz to 1GHz.A large part of the substrate noise is due to the ringing of the damped LC-tank, formed by the on-chip capacitance and the package inductance with series resistance on the supply connection [3][4]. For the used 132-pin ceramic PGA package, an average value of 12nH in series with 1.5Ωis measured for one connection. Decreasing the peak and the slope of the supply current will reduce the substrate noise. To achieve this, LN1 employs a clock tree with different latencies, where each latency is computed using the supply current profile statistics generated with our high-level substrate noise analysis tool SWAN, which also gives an accurate estimate of the supply current [5]. The target during the optimization of the latencies is to flatten the supply current over time (Figure 16.6.3). The timing adjustment is done with the use of a low skew (50ps) delay line formed by small inverters.Substrate biasing is important in order to have a non-floating bulk/well region and latchup prevention. Whereas in traditional CMOS cells VSS and substrate are short-circuited, LN2 uses two supply rails, one for the core and the other for substrate contacts in order to prevent direct coupling of the noisy supply currents into the substrate. The RMS value of the substrate noise scales down linearly with reduced supply voltage. Therefore, the core logic is partitioned into two parts: the slow (non-critical path) and fast (critical path) gates with 2.85V and 3.3V supply respectively. Also decoupling cells have been added to the core supply rails. Individual cells have a 42fF MOS gate capacitance in series with a 10kΩ poly resistance in a total area of 96µm2. Figure 16.6.4 shows the supplies and decoupling cells on the model extracted according to the methodology described in [4]. The amount of decoupling is optimized on this model including extracted models for I/O and supply pads.Figure 16.6.5 shows the comparison of the three designs (REF, LN1 and LN2) with the disabled I/O pads: the measured transients (top) of the substrate noise and their corresponding spectrum (bottom). The RMS value of the noise is 33.8mV, 15.8mV and 11.5mV for REF, LN1 and LN2 respectively. The largest substrate noise peaks in the spectrum are 19 dBmV, 13 dBmV and 11 dBmV at the 3rd, 2nd and fundamental clock harmonics for REF, LN1 and LN2 respectively. The frequency shift and the attenuation of the ringing in LN2 are due to on-chip decoupling and the fast/slow supply distribution. The spectral peaks are 35-40 dB above the substrate noise floor at the first four clock harmonics.Clock dependency of substrate noise is shown in Figure 16.6.6. The substrate noise generated by LN1 and LN2 is lower than REF, by a factor of 2 when averaged over clock frequency. Figure 16.6.6 also shows the resonant behavior at some clock frequencies. Two core supply pairs have been used for each design to have the same inductance. Note that LN1 shows less resonance due to the reduced slope of the supply current. On the other hand, a perfect linearity is measured between the dynamic power and the clock frequency.Table 16.6.1 shows an overview of all designs. At the maximum operating frequency of LN1 we demonstrated a factor of 2.14 reduction in the RMS value of generated substrate noise with only 3% area and 4% power penalty in a 5Kgate synchronous CMOS circuit with an optimized clock tree. These penalties decrease significantly in larger designs as this overhead is generated by the cells in the clock tree and set-up/hold-time fixing module. A factor of 2.94 reduction in noise is achieved for the design with a separate substrate bias, dual-supply, and on-chip decoupling, however with a factor of 1.72 increase in area but with 5% less power at the same frequency.References:[1]Allstot, D. J., et al., “Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signalICs,” IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 40, no.9, pp.553-563, Sep. 1993.[2]Nagata, M., et al., “Reduced Substrate Noise Digital Design for Improving Embedded AnalogPerformance,” ISSCC Digest of Technical Papers, pp.224-225, Feb. 2000.[3]Mathey, K., et al., “Noise Computation in Single Chip Packages,” IEEE Tr. On Components,Packaging, and Manufacturing Tech., Part B, Vol. 19, No. 2, pp.350-360, May 1996.[4]van Heijningen, M., Badaroglu, M., et al., “Substrate Noise Generation in Complex Digital Systems:Efficient Modeling and Simulation Methodology and Experimental Verification,” ISSCC Digest of Technical Papers, pp.342-343, Feb. 2001.[5]van Heijningen, M., Badaroglu, M., et al., “High-Level simulation of substrate noise generationincluding power supply noise coupling,” Proc. of Design Automation Conference, pp.446-451, June 2000.REFLN1NoiseSensorsAnalogCircuitriesLN2FastcellsDecoupling(fast)Decoupling(slow)SlowcellsFigure 16.6.1: Microphotograph of the test chip and its specifications. The chip consists of a reference design and 2 low-noise designs with the same functionality. It also contains 2 substrate noise sensors. The analog circuits in the lower right are not used in the experiments described in this paper.Figure 16.6.2: Architecture of the digital test circuit (IQ demodulator)Figure 16.6.3: Clock tree network (top) and the supply current (bottom) for the first low-noise design (LN1) at Vdd=3.3V and Fclk=40MHzFAST CORE SUPPLYSLOW CORE SUPPLYSUBSTRATE SUPPLYFigure 16.6.4: Chip-level substrate model for the core cells in the second low noise design (LN2)Figure 16.6.5: Measured substrate noise transients (top) and their spectrum (bottom) at Vdd=3.3V and Fclk=42MHzFigure 16.6.6: Comparison of measured RMS (top) and peak-to-peak (bottom) values of the substrate noise voltages versus clock frequencyFeatures REF LN1LN2Area of the core cells0.362mm20.373mm20.528mm2Area of the decoupling cells N/A N/A0.009mm2 for slow cells0.086mm2 for fast cells Total cell area0.362mm20.373mm20.623 mm2 Functional I/O pads222222Core supply pairs222IO supply pairs111Substrate supply pads N/A N/A1Total number of I/O pads282830Measured maximum clock freq.45 MHz42 MHz45 MHzMeasured power consumption(at 3.3V and 42MHz)112mW118mW107mWMeasured substrate noise (at 3.3V and 42MHz)33.8mVRMS142mVpp15.8mVRMS81mVpp11.5mVRMS69mVppNoise reduction w.r.t. REF(at 3.3V and 42MHz)-x2.14 in RMSx1.75 in PPx2.94 in RMSx2.06 in PPTable 16.6.1: Overview of the reference design and the two low-noise designsList of Figure Captions:Figure 16.6.1: Microphotograph of the test chip and its specifications. The chip consists of a reference design and 2 low-noise designs with the same functionality. It also contains 2 substrate noise sensors. The analog circuits in the lower right are not used in the experiments described in this paper.Figure 16.6.2: Architecture of the digital test circuit (IQ demodulator)Figure 16.6.3: Clock tree network (top) and the supply current (bottom) for the first low-noise design (LN1) at Vdd=3.3V and Fclk=40MHzFigure 16.6.4: Chip-level substrate model for the core cells in the second low noise design (LN2)Figure 16.6.5: Measured substrate noise transients (top) and their spectrum (bottom) at Vdd=3.3V andFclk=42MHzFigure 16.6.6: Comparison of measured RMS (top) and peak-to-peak (bottom) values of the substrate noise voltages versus clock frequencyTable 16.6.1: Overview of the reference design and the two low-noise designs11 of 11。