CCM1310中文资料
RCC-M 2007：S 1300 热处理概述
（翻译：卢昆审核：李文秀）S 1300热处理概述S 1310 介绍S 1300中给出的热处理参数均为最小值。
如果需要，为保证适当的制造质量，制造商在这些最小值的基础上可以采用更加严格的标准。
同时可以通过试验结果来选择与焊接操作有关的热处理参数。
S 7500中规定了此类热处理的应用条件。
根据接头类型，预热和后热时需考虑的等效厚度E如下：对接焊T型焊L型焊（角焊）十字型焊S 1320 预热和层间温度定义预热温度是在即将进行焊接时坡口的最低温度，或在多道焊的情况下，即将焊接某一焊道时，下面临近焊道金属的最低温度。
层间温度为即将焊接某一焊道时下面临近金属的最高温度。
预热条件和最大层间温度由制造商确定，主要依据：-待焊接材料的牌号和厚度；-接头类型、试件限制条件和焊接顺序；-所采用的焊接工艺。
最低预热温度应根据试验（1）确定，以便通过降低焊缝的冷却速度来消除或最大限度地减小与相变相关的硬化效应。
整个焊缝在焊接后的热处理（后热或消除应力热处理）前都应保持该预热温度。
最大层间温度应根据试验（2）确定，以避免影响规定的熔敷金属的力学性能。
（1）这些试验是可焊性文件的一部分，如包括第一层焊道的硬度测量和抗裂试验。
（2）例如这些试验可以是根据S 2000或S 5000的焊接填充材料的验收试验或评定试验。
S 1321 碳钢对于大于40mm的等效厚度E（见S 1310规定），建议的预热最低温度为100℃，或若在B、C或D 4000中有规定，则该温度值为强制性要求，适用于非应力消除条件下最小规定抗拉强度Rm小于440 MPa的钢材，如钢材：S 235—S 275—P 235 GH (A37)—P 265 GH (A42)。
对于非应力消除条件下最小规定抗拉强度Rm大于或等于440 MPa的钢材，如钢S 355、P 295 GH (A 48)和P 355 GH (A 52)，则对于等于或大于20mm的等效厚度E（见S 1310规定），建议的最小预热温度为125℃，或若在B、C或D 4000中有规定，该温度值为强制性要求。
南京科远HCSE系列交流伺服用户手册(V1.02)
若在电源和伺服驱动器输入端之间加装接触器，则不允许用此接触器来控制伺服驱动器的启停。一定需要用该接触器控制 伺服驱动器的启停时，间隔不要小于一个小时。频繁的充放电易降低伺服驱动器内电容的寿命。若输出端和电机之间装有接触 器等开关器件，应确保伺服驱动器在无输出时进行通断操作，否则易造成伺服驱动器内模块损坏。 ■ 三相输入改成两相输入
HCSE系列交流伺服 用户手册
(V1.02)
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I
电机机型设置
用户拿到伺服驱动器和电机第一次运行时，请参照适配机型表（如果适配机型表中没有对 应的电机型号，请根据所用电机的额定转速和额定电流，来选择电机机型），确认电机机型设 置是否正确，如果不正确，运行时电机可能会出现振动或误报警现象，不能达到期望的控制效 果。机型参数为Pn223,属于隐藏参数，需要解锁方能进入，在数码管为“run”、”bb”或报 警状态显示界面下，按“上下下下”（一次UP键，三次DOWN键）即可解锁。机型设置正确后， 需重新上电，方可运行电机。以后如果电机型号有变动，则需重新设置。
1314面板按键操作说明1441按键的名称与功能1442基本模式的选择与操作1543状态显示16431位数据显示内容16432省略符号显示内容1644辅助功能模式下的操作fn17441辅助功能执行模式的用户参数一览及其功能17442显示伺服报警记录18443微动jog模式运行18444用户参数设定值进行初始化1945用户参数设定模式下的操作pn20451用户参数的设定2046监视模式下的操作un21461监视模式一览及其功能21462顺序用输入输出信号的监视显示22463指令脉冲计数器反馈脉冲计数器的监视显示2451试运行2452通用功能的设定25521伺服on设定25522超程设定25523伺服off时的停止方法选择2553位置控制运行25531用户参数的设定26532电子齿轮的设定27533编码器反馈信号输出分频系数27534位置指令28535平滑29537外部扭矩限制3054其他31541旋转检测速度31542超速报警功能31543数字输入接脚di输入滤波使能31544伺服控制信号输入input管脚功能配置
CC1310 Skyworks 433MHz PA参考设计说明书
Application ReportSWRA528–May2017 CC1310Skyworks433MHz PA Reference Design Albin Zhang and Richard WallaceABSTRACTThe frequency range426MHz-435MHz is designated for ISM applications in several countries.This frequency range is commonly known as the433MHz band.Each country has their specific frequency band range and the China ISM band defined by SRRC is430MHz-432MHz and433.00MHz-434.79 MHz.CC1310reference design[8]operates from420MHz to510MHz with15dBm output power.If higher output power is required in the433MHz band,TI provides a reference design[3]with Skyworks Solutions.The combination of CC1310wireless MCU[2]and SKY66115-11FEM[4],addresses customers’needs for easy-to-use,long-range,low-power and low-cost solutions serving applications across the Internet of Things(IoT).The reference design covered in this application report can support up to+20dBm TX power with high power efficiency at433MHz.Contents1Introduction (2)2Design (2)3Measurement Results (8)4Summary (11)5References (11)List of Figures1CC1310EM-SKY66115-4051Board (2)2CC1310Block Diagram (3)3Schematic-CC1310EM-SKY66115-4051Rev2_0_x (4)4CC1310EM-SKY66115-4051Layout (5)5DIO Configuration in SmartRF Studio7 (6)6Tx Mode Configuration (7)7Rx mode configuration (8)8Matching of the Antenna With ANT1and ANT2Components (10)9Antenna Bandwidth at VSWR:2 (10)List of Tables1SKY66115-11Truth Table (6)2Conducted Output Power and Harmonics,3.3V (8)3TX Output Power,Current Consumption vs.Power Table,3.3V (9)TrademarksSmartRF is a trademark of Texas Instruments.Cortex is a registered trademark of ARM Limited.Introduction 2SWRA528–May 2017CC1310Skyworks 433MHz PA Reference Design1IntroductionThe design covered in this application note is based on the CC1310from the CC13xx family.It provides a range extension solution with the FEM from Skyworks (SKY66115-11)and a compact on-board helical PCB antenna.Figure 1310EM-SKY66115-4051Board2DesignWhen designing a wireless system,the maximum range between the transmitter and receiver is one of the most important parameters that will dominate the system configuration and installation.In the AMR system,the range is critical so that all households’meters can be read otherwise this must be done manually or adding more concentrators,which is expensive.To achieve a long range the output power can be increased to the maximum limit specified by the regulations and the data rate reduced as much as possible for the application.One of the efficient approaches to increase range is to increase the TX power.2.1CC1310The CC1310has been specifically designed for long range,city-wide low power networks.This is used in home automation,building automation and outdoor wide-area networks.The main advantages of CC1310are high sensitivity (-124dBm with a 0.625kbps data rate),strong co-existence (up to 80dB blocking),lowest power consumption (61µA /MHz ARM Cortex M3).CC1310can be basically split into four low-power sections as shown in Figure 2:•Main CPU with Cortex ®-M3•RF Core with radio controller.The RF core is a highly flexible and capable radio system that interfaces the analog RF and base-band circuits,handles data to and from the system side,and assembles the information bits in a given packet structure. Design •General Peripherals•Sensor ControllerFor more in-depth information on the CC1310,see the CC1310SimpleLink™Ultra-Low-Power Sub-1GHz Wireless MCU Data Sheet(SWRS181).1310Block Diagram2.2SchematicThe RF core of CC1310is highly configurable and the radio front-end can be set to differential or single ended.With a differential output configuration,the maximum output is14dBm.With a single endedoutput,the maximum output is11dBm.Several customers have requested an output power up to20dBm, the CC1310transmitter was configured as a single ended port(RF_P set to Tx)connected to an external FEM with an integrated amplifier,see Figure3.If an output power of14dBm is sufficient then thestandard reference design for420MHz to510MHz can be used[8].The schematic shown in Figure3is a general schematic(Rev2.0.x)to cover the ISM frequency bands from400MHz to510MHz;the BOM is specified for three different ISM frequency bands:•470MHz–510MHz:BOM-CC1310EM-SKY66115-4051Rev2.0.1•420MHz–440MHz:BOM-CC1310EM-SKY66115-4051Rev2.0.2•400MHz–420MHz:BOM-CC1310EM-SKY66115-4051Rev2.0.3Design 4SWRA528–May 2017CC1310Skyworks 433MHz PA Reference DesignThe FEM used is from Skyworks (SKY66115-11).The SKY66115-11consists of an amplifier and a switch contained in the package.It also includes a shutdown mode to minimize power consumption.The transmit path contains an amplifier optimized for saturated performance.SKY66115-11is internally matched for CC1310,which enables optimum transmit output power and efficiency for 50Ωload impedance.The transmit path passes through a low-pass filter before being entering to one side of the SPDT switch.The receive path has a bypass function from the other side of the SPDT switch.The reference design [3]shown in Figure 3is based upon 3.3V supply voltage.Two RF output options are available.Mounting C72,the RF path is routed to the RF connector (J1)that allows an externalantenna or conductive RF testing.Mounting C63,connects the compact PCB antenna.ANT1,ANT2and ANT3compose of the antenna matching circuit.A low-pass filter (C484,C485,C486and L332)is incorporated on the ANT port to provide additional filtering and/or limit unwanted signals from entering the receive path.CC1310can support several RF port options,described in the wiki page [7].For better Rx sensitivity,the reference design adopts a single-end,external-bias RF front-end design.L1is used for the external bias circuit.C11,L11and L12compose a matching circuit to optimize the RX sensitivity.The reference design [3]utilizes noise decoupling on the power and control lines of the SKY66115-11.Figure 3.Schematic -CC1310EM-SKY66115-4051Rev2_0_x Design 2.3LayoutThe design[3]is based on a0.8mm thick,two-layer PCB.The top layer and bottom layer are shown in Figure4.All components are positioned on the top layer apart from the evaluation module(EM)connectors.The CC1310EM-SKY66115-4051is based upon the7x7QFN package.The RF frond-end design can be re-used for5x5QFN and4x4QFN packages.A PCB helical antenna is incorporated in the EM design.The antenna is routed on both the top andbottom layers.It is important to incorporate the matching components(ANT1,ANT2and ANT3)as well if the antenna structure is to be copied to another design.Changing the PCB thickness will change theresonance of the antenna and this would require new antenna matching values for ANT1and ANT2(ANT3:DNM).1310EM-SKY66115-4051LayoutThe top view is shown on the left side;the bottom view is shown on the right side.Design 6SWRA528–May 2017CC1310Skyworks 433MHz PA Reference Design2.4SmartRF™StudioTo evaluate the reference design it is recommended to use the EM on the SmartRF06EB with SmartRF Studio software.The supported functions are continuously being updated and the software can be downloaded [6].With SmartRF studio 7(version 2.4.3),new features have been added to support 433MHz –510MHz reference designs.•Default recommended setting on 430-510MHz band.•DIOs configuration based on the truth table of the FEM.•RF front-end mode configuration.For more information on SmartRF Studio7,see /tool/smartrftm-studio .Figure 5,Figure 6and Figure 7illustrate how to configure the CC1310EM-SKY66115-4051board.2.4.1DIO ConfigurationBased on the truth table of the SKY66115-11shown in Table 1,SmartRF Studio should have the DIO configured as shown in Figure 5.Table 1.SKY66115-11Truth TableDIO_1(CTX):LOW &DIO_30(CSD):HIGH ---->Rx DIO_1(CTX):HIGH &DIO_30(CSD):HIGH ---->Tx DIO_1(CTX):X &DIO_30(CSD):LOW ---->SleepFigure 5.DIO Configuration in SmartRF Studio 7 Design 2.4.2RF Front-End ConfigurationFigure6and Figure7show the configuration of Tx and Rx modes separately.This is configured in the CMD_PROP_RADIO_DIV_SE radio operation commands.For the Tx path configuration shown in Figure6,RF_P is set to single-end option.The txpowerparameters should also be configured based on Table3.For the Rx path shown in Figure7,RF_N is set to single-end option.Figure6.Tx Mode ConfigurationMeasurement Results 8SWRA528–May 2017CC1310Skyworks 433MHz PA Reference DesignFigure 7.Rx mode configuration3Measurement ResultsAll measurements results were performed on the CC1310EM-SKY66115-4051at 433MHz (BOM Rev 2.0.2)EM mounted on the SmartRF06EB.Software control is based on SmartRF Studio 2.4.3.3.1Tx Output Power and HarmonicsThe output power was measured at 433.92MHz.The harmonics were measured up to the 10th harmonic.The txpower register is set to 0x1CC7.Table 2.Conducted Output Power and Harmonics,3.3VHamonics fc 2fc 3fc 4fc 5fc 6fc 7fc 8fc 9fc 10fc Frequency (MHz)433.92867.841301.761735.682169.62603.523037.443471.363905.284339.2Level (dBm)20.5-37-49-55-55-55-55-55-55-55 Measurement Results 3.2Tx Output Power Dynamic Range and Current ConsumptionOutput power and current consumption were measured across the power table at433.92MHz.Theaverage results are shown in Table3.In the CMD_PROP_RADIO_DIV_SETUP,the power can be configured in the txpower register,which is shown in Figure6.Table3.TX Output Power,Current Consumption vs.Power Table,3.3VPower Table0x08C00x00410x10C30x10430x14C40x18C50x18C60x1CC7Output power12.316.31818.919.319.619.820dBm 5262.871.475.978.179.781.682.4mA CurrentconsumptionThe SKY66115-11maximum input power rating on the PIN_TX is limited 1310should limit the TX Power control IB bit of txpower register below0x07.3.3Rx Current ConsumptionThe static Rx current consumption was measured at6.3mA with3.3V power supply.3.4SensitivityThe sensitivity was measured with50kbps datarate setting on CC1310EM-SKY66115-4051at433MHz (BOM Rev2.0.2)to-106.4dBm during normal temperature and3.3V power supply.If the data rate is reduced from50kbps and Long Range Mode utilized,then the following sensitivitylevels can be achieved on the on CC1310EM-SKY66115-4051at433MHz(BOM Rev2.0.2)Ref Design:●5kbps sensitivity:-117dBm● 2.5kbps sensitivity:-119dBm● 1.25kbps sensitivity:-120dBm●0.625kbps sensitivity:-121dBm3.5Antenna DesignThe PCB helical antenna shown in Figure4has been matched to433.92MHz with ANT1:6.8pF and ANT2:91nH.For more information,see Figure8.The antenna is matched for the complete band of470 MHz–510MHz.For more information,see Figure8and Figure9.This antenna design,matching tuning and testing results are based on the CC1310EM-SKY66115-4051 board at433MHz(BOM Rev2.0.2)plugging on the SmartRF06EB board with the free spaceenvironment.In antenna design theory,some of the nearby materials will impact the antennaperformances,for example,grounded conductor,plastic/rubber cases,and so forth.For a realistic product antenna design,it is necessary to consider the mechanical case impacts and do proper tuning.Measurement Results 10SWRA528–May 2017CC1310Skyworks 433MHz PA Reference DesignFigure 8.Matching of the Antenna With ANT1and ANT2ComponentsFigure 9.Antenna Bandwidth at VSWR:2 Summary 11SWRA528–May 2017Submit Documentation Feedback Copyright ©2017,Texas Instruments Incorporated CC1310Skyworks 433MHz PA Reference Design 4SummaryThe CC1310EM-SKY66115-4051reference design at 433MHz (BOM Rev 2.0.2)is a low cost,easy-to-use,high efficiency solution with 20dBm output power for 3.3V supply.Tx current consumption at 20dBm is approximately 82mA.The antenna is also integrated into the PCB that provides a compact,costless antenna solution.5References1.Achieving Optimum Radio Range (SWRA479)2.CC1310SimpleLink™Ultra-Low-Power Sub-1GHz Wireless MCU Data Sheet (SWRS181)3.CC1310EM-SKY66115-4051Reference Design (Rev:2.0.x)(SWRC334)4.SKY66115-11Data Sheet 5.Antenna Quick Guide (SWRA351)6.SmartRF Studio Download 7.CC1310Front-end Configurations Wiki page 13xxEM-7XD-4251Rev1_1_1IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCESTexas Instruments Incorporated(‘TI”)technical,application or other design advice,services or information,including,but not limited to, reference designs and materials relating to evaluation modules,(collectively,“TI Resources”)are intended to assist designers who are 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ADuM1310中文
七、管脚封装图
※ 品选型表
通道 分布 3/0 3/0 2/1 2/1 传输速率 (Mbps) 1 10 1 10 最大传输 延时(ns) 100 50 100 50 最大脉宽 失真(ns) 40 5 40 5 工作温度范 围(℃) -40~105 -40~105 -40~105 -40~105
二、产品特性
� � � � � � � 三通道隔离 电平转换器 传输速率：1M/10Mbps 传输延迟：50ns 瞬态共模抑制能力：25KV/us 隔离电压：2500V 工作温度：-40℃~105℃ 工作电压：3V/5V
� �
SOIC-16 宽体无铅封装
低功耗
7 mA / 通道 @ 0 Mbps 5 V operation 1. 1.7 to 2 Mbps 4.0 mA /通道 @ 10 Mbps 3 V operation 1.0 mA /通道 @ 0 Mbps to 2 Mbps mA/ 2.1 mA /通道@ 10 Mbps
ADuM1 31x ADuM13
5、 直流校正功能
磁隔离器每一通道的两组线圈起到脉冲变压器的作用， 输入端逻辑电平的变化会引起一 个窄脉冲（1ns） ，经过脉冲变压器耦合到解码器，然后再经过一个施密特触发器的波形变换 输出标准的矩形波， 如果输入端逻辑电平超过 1µs 都没有任何变化， 则校正电路会产生一个 适当极性的校正脉冲，以确保变压器直流端输出信号的正确性，如果解码器一端超过 5µs 都没有收到任何校正脉冲，则会认为输入端已经掉电或不工作，由看门狗电定时器电路，将 输出端强行置为默认状态（参看真值表） 。这确保了磁耦可以传输直流信号。
ADuM1 31x ADuM13
当 VDD1=VDD2=3V，TA=25℃ 工作参数 工作电压 符号 VDD1 VDD2 静态工作电流 IDDI(Q) IDDO(Q) 0~2Mbps 时 1310 工作电流 0~2Mbps 时 1311 工作电流 输入电平 IDD1 IDD2 IDD1 IDD2 VIH VIL 输出电平 VOH VOL 最大输出电流 IO1(side1) IO2(side2) -18 -22 VDD1,2-0.1 3.0 0.0 0.1 18 22 1.6 0.4 Min 2.7 2.7 Typ 3.0 3.0 0.25 0.19 1.2 0.8 1.0 0.9 Max 3.6 3.6 0.38 0.33 1.6 1.0 1.6 1.4 单位 V V mA mA mA mA mA mA V V V V mA mA
首个高功率132kHz CCM模式PSR电源方案解析
首个高功率132kHz CCM 模式PSR 电源方案解析2012 年12 月1 日,中国将强制执行新的电器安全标准GB4943.1-2011,该标准要求在海拔2000 米以上使用的设备，其电源的初级侧和次级侧电气间隙要加大(乘以倍增系数1.48),规定必须在不符合严格的爬电距离和电气间隙要求的电源上加贴警告标签。
这对于PSR(初级侧稳压)器件来说是一个好消息,因为PSR 设计不用光耦器和反馈电路。
新安规的挑战不久前，Power Integrations(PI)推出了高功率LinkSwitch-HP IC 系列，其空载功耗30mW，在敞开式设计中输出功率最高可达90W，而在密闭适配器中输出功率最高也可达55W(散热瓶颈)。
PI 市场部资深经理李子俊表示，新的安规标准使得电源设计中变压器、外电容和光耦部分面临挑战，特别是光耦，按新规要选择较大的封装器件，增加了成本。
此次推出的LinkSwitch-HP 系列是目前市场上首个132kHz CCM(连续导通模式)PSR 方案，CCM 模式可以降低输出纹波，这样可以在外围选用较小的输出电容和稳压二极管，从而减低成本。
LinkSwitch-HP 提高了整个负载范围内的效率，并减小变压器和输出滤波器的尺寸，李子俊说，该系列采用了革新性的多模式控制引擎，实现了小于30mW 的空载输入功率，与次级侧稳压(SSR)方案相比，性能相近但BOM 成本更低。
关键特性大约十年前，PI 推出了LinkSwitch 产品系列，采用创新的控制算法并利用主功率变压器和输出二极管的特性来确定从初级侧传输到隔离次级侧的功率量。
这种PSR 方法不用昂贵的光耦器，也不用设计复杂的相关反馈电路，大大减少了元件数，节省空间和成本，并增强了可靠性。
现在，诸如手机充电器等许多低功率应用中基本采用了PSR 方案。
但截止目前，PSR 一直无法满足高功率产。
MAX13103 芯片数据手册说明书
MJD200 (NPN),MJD210 (PNP)Complementary Plastic Power TransistorsNPN/PNP Silicon DPAK For Surface Mount ApplicationsDesigned for low voltage, low−power, high−gain audio amplifier applications.Features•High DC Current Gain•Lead Formed for Surface Mount Applications in Plastic Sleeves (No Suffix)•Low Collector−Emitter Saturation V oltage•High Current−Gain − Bandwidth Product•Annular Construction for Low Leakage •EpoxyMeetsUL94V−*********•NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable•These Devices are Pb−Free and are RoHS CompliantMAXIMUM RATINGSRating Symbol Max UnitCollector−Base Voltage V CB40VdcCollector−Emitter Voltage V CEO25VdcEmitter−Base Voltage V EB8.0VdcCollector Current − Continuous I C 5.0AdcCollector Current − Peak I CM10AdcBase Current I B 1.0AdcTotal Power Dissipation @ T C = 25°C Derate above 25°C P D12.50.1WW/°CTotal Power Dissipation (Note 1) @ T A = 25°CDerate above 25°C P D1.40.011WW/°COperating and Storage JunctionTemperature RangeT J, T stg−65 to +150°C ESD − Human Body Model HBM3B V ESD − Machine Model MM C V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.These ratings are applicable when surface mounted on the minimum padsizes recommended.SILICONPOWER TRANSISTORS5 AMPERES25 VOLTS, 12.5 WATTSDPAKCASE 369CSTYLE 1MARKING DIAGRAMA= Assembly LocationY=YearWW=Work Weekx= 1 or 0G=Pb−Free PackageAYWWJ2x0GSee detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet.ORDERING INFORMATION1BASE3EMITTERCOLLECTOR2,412341BASE3EMITTERCOLLECTOR2,4PNP NPNTHERMAL CHARACTERISTICSCharacteristic Symbol Max Unit Thermal Resistance, Junction−to−Case R q JC10°C/W Thermal Resistance, Junction−to−Ambient (Note 2)R q JA89.3°C/W 2.These ratings are applicable when surface mounted on the minimum pad sizes recommended.ELECTRICAL CHARACTERISTICS(T C = 25°C unless otherwise noted)Characteristic Symbol Min Max Unit OFF CHARACTERISTICSCollector−Emitter Sustaining Voltage (Note 3) (I C = 10 mAdc, I B = 0)V CEO(sus)25−VdcCollector Cutoff Current(V CB = 40 Vdc, I E = 0)(V CB = 40 Vdc, I E = 0, T J = 125°C)V CBO−−100100nAdcm AdcEmitter Cutoff Current (V BE = 8 Vdc, I C = 0)V EBO−100nAdcON CHARACTERISTICSC Current Gain (Note 3),(I C = 500 mAdc, V CE = 1 Vdc) (I C = 2 Adc, V CE = 1 Vdc)(I C = 5 Adc, V CE = 2 Vdc)h FE704510−180−−Collector−Emitter Saturation Voltage (Note 3) (I C = 500 mAdc, I B = 50 mAdc)(I C = 2 Adc, I B = 200 mAdc)(I C = 5 Adc, I B = 1 Adc)V CE(sat)−−−0.30.751.8VdcBase−Emitter Saturation Voltage (Note 3) (I C = 5 Adc, I B = 1 Adc)V BE(sat)− 2.5VdcBase−Emitter On Voltage (Note 3) (I C = 2 Adc, V CE = 1 Vdc)V BE(on)− 1.6VdcDYNAMIC CHARACTERISTICSCurrent−Gain − Bandwidth Product (Note 4)(I C = 100 mAdc, V CE = 10 Vdc, f test = 10 MHz)f T65−MHzOutput Capacitance(V CB = 10 Vdc, I E = 0, f = 0.1 MHz)MJD200MJD210, NJVMJD210T4G C ob−−80120pF3.Pulse Test: Pulse Width = 300 m s, Duty Cycle [ 2%.4.f T = ⎪h fe⎪• f test.Figure 1. Power DeratingT, TEMPERATURE (°C)T CPD,POWERDISSIPATION(WATTS)Figure 2. Switching Time Test Circuit2.51.51T A0.520SCOPEV CCt r, t f≤ 10 nsDUTY CYCLE = 1%D1 MUST BE FAST RECOVERY TYPE, e.g.: 1N5825 USED ABOVE I B≈ 100 mA MSD6100 USED BELOW I B≈ 100 mAR B and R C VARIED TO OBTAIN DESIRED CURRENT LEVELSFOR PNP TEST CIRCUIT,REVERSE ALL POLARITIESI C, COLLECTOR CURRENT (A)1KI C, COLLECTOR CURRENT (A)t,TIME(ns)50030020010050302010510.02Figure 3. Turn−On Time Figure 4. Turn−Off Timet,TIME(ns)32I C , COLLECTOR CURRENT (A)I C , COLLECTOR CURRENT (A)I C , COLLECTOR CURRENT (A)h F E , D C C U R R E N T G A I NFigure 5. DC Current GainFigure 6. “On” VoltageI C , COLLECTOR CURRENT (A)200400100806040IC , COLLECTOR CURRENT (A)Figure 7. Temperature Coefficients202I C , COLLECTOR CURRENT (A)1.61.20.80.4V , V O L T AG E (V O L T S )NPN MJD200PNP MJD210h F E , D C C U R R E N T G A I NV , V O L T A G E (V O L T S )21.61.20.80.4V , T E M P E R A T U R E C O E F F I C I E N T S (m V /C )°θ+ 2.5+ 2+ 1.5+ 10- 0.5- 1- 1.5- 2+ 0.5- 2.5V , T E M P E R A T U R E C O E F F I C I E N T S (m V /C )°θ+ 2.5+ 2+ 1.5+ 10- 0.5- 1- 1.5- 2+ 0.5- 2.5t, TIME (ms)r (t ), T R A N S I E N T T H E R M A L R E S I S T A N C E (N O R M A L I Z E D )Figure 8. Thermal ResponseV CE , COLLECTOR−EMITTER VOLTAGE (V)25Figure 9. Active Region Safe Operating Area13I C , C O LL E C T O R C U R R E N T (A M P )There are two limitations on the power handling ability of a transistor: average junction temperature and second breakdown. Safe operating area curves indicate I C − V CE limits of the transistor that must be observed for reliable operation; i.e., the transistor must not be subjected to greater dissipation than the curves indicate.The data of Figure 9 is based on T J(pk) = 150°C; T C is variable depending on conditions. Second breakdown pulse limits are valid for duty cycles to 10% provided T J(pk)≤ 150°C. T J(pk) may be calculated from the data in Figure 8.At high case temperatures, thermal limitations will reduce the power that can be handled to values less than the limitations imposed by second breakdown.200V R , REVERSE VOLTAGE (V)207010030Figure 10. Capacitance50C , C A P A C I T A N C E (p F )ORDERING INFORMATIONDevice Package Type Shipping†75 Units / RailMJD200G DPAK(Pb−Free)1,800 / Tape & ReelMJD200RLG DPAK(Pb−Free)2,500 / Tape & ReelMJD200T4G DPAK(Pb−Free)75 Units / RailMJD210G DPAK(Pb−Free)1,800 / Tape & ReelMJD210RLG DPAK(Pb−Free)2,500 / Tape & ReelMJD210T4G DPAK(Pb−Free)2,500 / Tape & ReelNJVMJD210T4G*DPAK(Pb−Free)†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.*NJV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP CapablePACKAGE DIMENSIONSDPAK CASE 369C ISSUE DSTYLE 1:PIN 1.BASE2.COLLECTOR3.EMITTER4.COLLECTORǒmm inchesǓSCALE 3:1*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT*DIM MIN MAX MIN MAX MILLIMETERSINCHES D 0.2350.245 5.97 6.22E 0.2500.265 6.35 6.73A 0.0860.094 2.18 2.38b 0.0250.0350.630.89c20.0180.0240.460.61b20.0300.0450.76 1.14c 0.0180.0240.460.61e 0.090 BSC 2.29 BSC b30.1800.215 4.57 5.46L4−−−0.040−−− 1.01L 0.0550.070 1.40 1.78L30.0350.0500.89 1.27Z0.155−−−3.93−−−NOTES:1.DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.2.CONTROLLING DIMENSION: INCHES.3.THERMAL PAD CONTOUR OPTIONAL WITHIN DI-MENSIONS b3, L3 and Z.4.DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR BURRS. MOLDFLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.006 INCHES PER SIDE.5.DIMENSIONS D AND E ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY .6.DATUMS A AND B ARE DETERMINED AT DATUM PLANE H.H 0.3700.4109.4010.41A10.0000.0050.000.13L10.108 REF 2.74 REF L20.020 BSC 0.51 BSC DETAIL AROTATED 90 CW 5ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at /site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。
CC1310无线串口433MHz模块E70-433MS14手册
E70-433MS14用户手册v1.21. 模块介绍 (2)1.1 特点简介 (2)1.2 电气参数 (3)1.3 系列产品 (3)1.4 常见问题 (3)2. 串口模块功能（出厂默认） (4)2.1 定点发射 (4)2.2 广播发射 (4)2.3 广播地址 (4)2.4 监听地址 (4)3. 引脚定义 (5)3.1连接单片机 (6)3.2 模块复位 (6)3.3 AUX详解 (7)4. 工作模式 (8)4.1 模式切换 (8)4.2 一般模式（模式0） (8)4.3 唤醒模式（模式1） (9)4.4 配置模式（模式2） (9)4.5 休眠模式（模式3） (9)4.6 快速通信测试 (9)5. 指令格式 (10)5.1 出厂默认参数 (10)5.2 工作参数读取 (10)5.3 版本号读取 (10)5.4 参数设置指令 (10)6. 二次开发 (12)6.1 引脚定义 (12)6.2 烧录程序 (13)7. 参数配置 (14)8. 定制合作 (15)9. 关于我们 (15)1. 模块介绍1.1 特点简介E70-433MS14是一款基于TI公司CC1310（内置高性能ARM单片机）射频芯片的无线串口模块（UART），透明传输方式，工作在431~440MHz频段（默认433MHz），TTL 电平输出。
模块已内置串口功能，其引脚定义详见下图引脚定义图，引出全部IO，支持用户二次开发，亿佰特亦支持客户制化定制需求。
模块具有软件FEC前向纠错算法，其编码效率较高，纠错能力强，在突发干扰的情况下，能主动纠正被干扰的数据包，大大提高可靠性和传输距离。
在没有FEC的情况下，这种数据包只能被丢弃。
序号产品特点特点描述1 超低功耗接收电流仅为8mA，休眠电流仅为1uA。
可以使用电池供电，功耗优势明显。
2 定点发射支持地址功能，主机可发射数据到任意地址、任意信道的模块，达到组网、中继等应用方式：例如：模块A需要向模块B（地址为0x00 01，信道为0x80）发射数据AA BB CC，其通信格式为：00 01 80 AA BB CC，其中00 01为模块B地址，80为模块B信道，则模块B可以收到AA BB CC（其它模块不接收数据）。
CXA1310AQ中文资料
–1–
E89Z21A78-PS
元器件交易网
CXA1310AQ
Pin Description No. Symbol
I/O signal
Equivalent circuit
Description
1 SAG
2 GND2 3 GND1
4 SYNC
Inputs VIDEO OUT through capacitor
21 150Ω
100µA
Input pin of the sample / hold pulse (active at High)
[∗1]
[∗2]
22
22 DATA
[∗1] MAX 800mV [∗2] MAX 800mV
150µA
CCD signal input pin ∗ External applied voltage
White clip level adjusting pin
6 WC CONT GND∗ 2 to 3.5V∗
6 150Ω
Preset mode
40µA
Control mode ∗ External applied voltage
–2–
元器件交易网
No. Symbol
I/O signal
–5–
元器件交易网
CXA1310AQ
No. Symbol
I/O signal
Equivalent circuit
Description
23 PG
[∗1]
[∗2]
23
[∗1] MAX 800mV [∗2] MAX 800mV
150µA
CCD single input pin
四方远动装置ppt课件
插件类型
• 主CPU插件 • 通信类扩展插件：以太网、串口、现场
总线（LON与CAN ） • 辅助插件：电源、MMI、开入开出、对
时、背板（内部以太网）
CSC-1320站控级通信装置
配置编码
CSC-132
装置系列
远动 故障信息子站 远动及子站一体化 基本型（256M电子盘） 增强型（1G电子盘） 基本型（8M FLASH） 增强型（256M电子盘） 110V DC/AC 220V DC/AC 19英寸机箱 19/2英寸机箱
CSC-1320站控级通信装置
插件类型——串口插件
• 6串口
– RS232/RS485可选 – 20线凤凰端子 – 带通信指示灯（正在试制）
CSC-1320站控级通信装置
插件类型——现场总线插件
• 2路Lonworks＋2路CAN • 20线凤凰端子 • Lonworks节点类型可选择搭配
– MASTER节点 – MMI节点 – 录波MASTER节点
CSC-1320站控级通信装置
主要内容
• 硬件平台 • 软件平台
CSC-1320站控级通信装置
外形结构－前面板
液晶屏 128×240点阵 8行×15列汉字
四方按键
机箱 4U高度 19英寸或19/2英寸
CSC-1320站控级通信装置
外形结构－后面板
插件标识
插件端子
插件把手
CSC-1320站控级通信装置
总线（LON与CAN ） • 助插件：电源、MMI、开入开出、对
时、级联、背板（内部以太网）
CSC-1320站控级通信装置
插件类型——主CPU插件
• 双以太网
– 10/100M自适应 – RJ45端口
UL1310中文版(电源方案下载请到以下网站下载)
UL1310ISB1-55989-589-6 CLASS 2 电源设备安全标准CLASS 2 POWER UNITS目录序文1.范围2.语汇3.组件4.总类装配5.机械集成6.外壳7.抗锈蚀8.开关9.保护装置10.组件11.线圈绝缘12.输入连接13.输出连接14.带电零件的可触性15.带电零件16.消除应变17.内部配线18.电路分隔19.绝缘材料20.印制电路板21.接地措施22.空间设计性能测试23.一般要求24.漏电测试25.暴露在潮湿环境下的漏电测试及耐压测试26.最大输出电压测试27.最大输入测试28.输出电流及电力测试29.防过载装置的校准测试30.全载输出电流测试31.正常温度测试32.耐压测试33.防过热和过载保护装置的耐久力测试34.重复耐压测试35.开关及操控装置的负载及耐久力测试36.次级开关的过载测试37.工作测试38.不正常测试39.绝缘材料测试40.消除应变测试40A.后推力消除测试41.直接插入铜脚固定测试42.输入接触的直接插入式固定测试43.输出连接器安全测试44.滥用测试45.接合导线测试制造及产品测试46.耐压测试47.接地连续性测试额定值48.总类标记49.详细资料规章50.使用手册附录一标准零件前言A.本标准乃根据Underwriters Laboratories Inc. (UL)对产品的基本要求作出以下的限制及标准范围。
此限制基于坚固的工程定理、研究、测试记录和经验，及与制造商、用户、检验部门和一些有特别经验的专业人士磋商及收取信息，解决制作过程及安装上的问题。
他们需要更多的经验和研究来不断求进。
B.由机械工程师观察本标准的要求是继续规范制造商的产品的其中一个状况。
C.若本标准被诊察和测试出有些会损害安全界限的情况，符合本标准原文的产品可以不需要被鉴定是否符合本标准。
D.使用有别于本标准列明的规条之材料或工作程序，可能会根据要求被诊察和测试。
若被发现在本质上大致相同，可能会被鉴定是否符合本标准。
硅传科技 CC1310-TC-009 大功率嵌入式 433M 无线数传模块 V3.1 说明书
CC1310-TC-009大功率嵌入式433M无线数传模块V3.1深圳市硅传科技有限公司地址：深圳市龙华区创业路汇海广场C座13层1305邮编：518109电话**************传真：*************邮箱：**********************网址：https://版本说明目录一、功能介绍 (4)二、应用领域 (4)三、模块特性 (5)四、尺寸示意图 (5)五、引脚说明 (6)六、硬件连接 (7)七、AT指令 (9)7.1 AT+MODE –设置工作模式 (9)7.2 AT+UART –设置串口参数 (9)7.3 AT+TXP –设置设备射频发射功率 (10)7.4 AT+RFRATE –设置设备射频空中波特率 (10)7.5 AT+CH –设置设备射频的工作频道 (11)7.6 AT+FACTORY –参数恢复出厂设置 (11)7.7 AT+RSTSTM –软件复位系统 (11)7.8 AT+GETRSSI –读取RSSI (12)7.9 AT+SNTYPE –设置传感器类型 (12)7.10 AT+NTP –设置传感器节点类型 (13)7.11 AT+SNPT –设置传感器数据上报周期 (13)7.12 AT+GID –设置传感器组ID (14)7.13 AT+SID –设置传感器节点ID (14)7.14 AT+VER –读取固件版本 (15)7.15 AT+EPW –模组供电电压值 (15)7.16 AT+SNTO –设置传感器数据上电延时上报时间 (16)7.17 AT+WTMD –设置射频白化功能 (16)7.18 AT+SCPRD –设置ADC传感器采样检测个数 (17)7.19 AT+BYP –内部PA/LNA Bypass模式 (17)八、电脑端上位机 (19)8.1 上位机操作说明 (19)8.2 传感器应用操作说明 (20)8.3 分组ID和节点ID (21)九、传感器串口数据协议 (22)十、使用注意事项 (23)10.1 上电延时 (23)10.2 AT指令 (23)10.3 透传数据分包机制 (23)10.4 功耗设计 (23)10.5 透传数据吞吐量 (23)十一、附加说明 (24)一、功能介绍CC1310属于德州仪器 (TI) CC26xx 和 CC13xx 系列器件中的经济高效型超低功耗Sub 1GHz的SOC RF器件。
MC13193资料
Freescale Semiconductor Technical DataFreescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products.Document Number: MC13192Rev. 2.9, 08/2005MC13192/MC13193Ordering InformationDevice Device MarkingPackage MC13192MC131931319213193QFN-32QFN-321IntroductionThe MC13192 and MC13193 are short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers. The MC13192/MC13193 contain a complete 802.15.4 physical layer (PHY) modem designed for the IEEE ® 802.15.4 wireless standard which supports peer-to-peer, star, and mesh networking.The MC13192 includes the 802.15.4 PHY/MAC for use with the HCS08 Family of MCUs. The MC13193 also includes the 802.15.4 PHY/MAC plus the ZigBeeProtocol Stack for use with the HCS08 Family of MCUs. With the exception of the addition of the ZigBee Protocol Stack, the MC13193 functionality is the same as the MC13192.When combined with an appropriate microcontroller (MCU), the MC13192/MC13193 provide acost-effective solution for short-range data links and networks. Interface with the MCU is accomplished using a four wire serial peripheral interface (SPI) connection and an interrupt request output which allows for the use of a variety of processors. The software and processorMC13192/MC131932.4 GHz Low Power Transceiver for the IEEE ® 802.15.4 StandardContents1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 12Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . 34Data Transfer Modes . . . . . . . . . . . . . . . . . . . 35Electrical Characteristics . . . . . . . . . . . . . . . 86Functional Description . . . . . . . . . . . . . . . . 127Pin Connections . . . . . . . . . . . . . . . . . . . . . . 158Applications Information . . . . . . . . . . . . . . . 189Packaging Information . . . . . . . . . . . . . . . . . 23Featurescan be scaled to fit applications ranging from simple point-to-point systems, through complete ZigBee™ networking.For more detailed information about MC13192/MC13192 operation, refer to the MC13192/MC13193 Reference Manual, part number MC13192RM.Applications include, but are not limited to, the following:•Remote control and wire replacement in industrial systems such as wireless sensor networks •Factory automation and motor control•Energy Management (lighting, HV AC, etc.)•Asset tracking and monitoringPotential consumer applications include:•Home automation and control (lighting, thermostats, etc.)•Human interface devices (keyboard, mice, etc.)•Remote entertainment control•Wireless toysThe transceiver includes a low noise amplifier, 1.0 mW power amplifier (PA), voltage controlled oscillator (VCO), on-board power supply regulation, and full spread-spectrum encoding and decoding. The device supports 250 kbps Offset-Quadrature Phase Shift Keying (O-QPSK) data in 2.0 MHz channels with5.0 MHz channel spacing per the IEEE 802.15.4 specification. The SPI port and interrupt request output are used for receive (RX) and transmit (TX) data transfer and control.2Features•Recommended power supply range: 2.0 to 3.4 V•16 Channels•0 dBm nominal, programmable from -27 dBm to 4 dBm typical maximum output power•Buffered transmit and receive data packets for simplified use with low cost MCUs•Supports 250 kbps O-QPSK data in 5.0 MHz channels and full spread-spectrum encode and decode (compatible with IEEE Standard 802.15.4)•Three power down modes for power conservation:—<1µA Off current—1 µA Typical Hibernate current—35 µA Typical Doze current (no CLKO)•RX sensitivity of -92 dBm (typical) at 1.0% packet error rate•Four internal timer comparators available to reduce MCU resource requirements•Programmable frequency clock output for use by MCU•Onboard trim capability for 16 MHz crystal reference oscillator eliminates need for external variable capacitors and allows for automated production frequency calibration.•Seven general purpose input/output (GPIO) signalsBlock Diagrams•Operating temperature range: -40 °C to 85 °C•Small form factor QFN-32 Package—RoHS compliant—Meets moisture sensitivity level (MSL) 3—260 °C peak reflow temperature—Meets lead-free requirements3Block DiagramsFigure3 shows a simplified block diagram of the MC13192/MC13193 which is an IEEE Standard 802.15.4 compatible transceiver that provides the functions required in the physical layer (PHY) specification. Figure4 shows the basic system block diagram for the MC13192/MC13193 in an application. Interface with the transceiver is accomplished through a 4-wire SPI port and interrupt request line. The media access control (MAC), drivers, and network and application software (as required) reside on the host processor. The host can vary from a simple 8-bit device up to a sophisticated 32-bit processor depending on application requirements.4Data Transfer ModesThe MC13192/MC13193 has two data transfer modes:1.Packet Mode — Data is buffered in on-chip RAM2.Streaming Mode — Data is processed word-by-wordThe Freescale 802.15.4 MAC software only supports the streaming mode of data transfer. For proprietary applications, packet mode can be used to conserve MCU resources.4.1Packet StructureFigure5 shows the packet structure of the MC13192/MC13193. Payloads of up to 125 bytes are supported. The MC13192/MC13193 adds a four-byte preamble, a one-byte Start of Frame Delimiter (SFD), and a one-byte Frame Length Indicator (FLI) before the data. A two-byte Frame Check Sequence (FCS) is calculated and appended to the end of the data.Data Transfer Modes4.2Receive Path DescriptionIn the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon the baseband energy integrated over a specific time interval. The digital back end performs Differential Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured over a 64 µs period after the packet preamble and stored in RAM.If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is notified that an entire packet has been received via an interrupt.If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word basis.Figure1 shows CCA reported power level versus input power. Note that CCA reported power saturates at about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure2 shows energy detection/LQI reported level versus input power. Note that for both graphs the required IEEEFigureData Transfer Modes4.3Transmit Path DescriptionFor the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then up-converted to the transmit frequency.If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is notified via an interrupt when the whole packet has successfully been transmitted.In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the whole packet is transmitted.Figure3. MC13192 Simplified Block DiagramData Transfer Modes4 bytes 1 byte 1 byte125 bytes maximum 2 bytesPreamble SFD FLI Payload Data FCSFigure5. MC13192/MC13193 Packet StructureElectrical Characteristics5Electrical Characteristics5.1Maximum Ratings5.2Recommended Operating ConditionsTable 1. Absolute Maximum RatingsRatingSymbol Value Unit Power Supply Voltage V BATT, V DDINT3.6Vdc RF Input Power P max 10dBm Junction Temperature T J 125°C Storage Temperature RangeT stg-55 to 125°CNote:Maximum Ratings are those values beyond which damage to the device may occur.Functional operation should be restricted to the limits in the Electrical Characteristics or Recommended Operating Conditions tables.Note:Meets Human Body Model (HBM) = 2 kV and Machine Model (MM) = 200 V except RFIN± = 100 V MM,PAO± = 50 V MM & 1 kV HBM, and VBATT = 100 V MM. RF output pins have no ESD protection.Table 2. Recommended Operating ConditionsCharacteristic SymbolMin Typ Max Unit Power Supply Voltage (V BATT = V DDINT )V BATT, V DDINT 2.0 2.7 3.4Vdc Input Frequencyf in 2.405- 2.480GHz Ambient Temperature Range T A -402585°C Logic Input Voltage Low V IL 0-30% V DDINT V Logic Input Voltage High V IH 70% V DDINT-V DDINT V SPI Clock Rate f SPI --8.0MHz RF Input PowerP max --10dBmCrystal Reference Oscillator Frequency (±40 ppm over operating conditions to meet the 802.15.4 standard.)f ref16 MHz OnlyElectrical Characteristics 5.3DC Electrical CharacteristicsTable3. DC Electrical Characteristics(V BATT, V DDINT = 2.7 V, T A = 25 °C, unless otherwise noted)Characteristic Symbol Min Typ Max Unit Power Supply Current (V BATT + V DDINT)OffHibernateDoze (No CLKO)IdleTransmit Mode (0 dBm nominal output power) Receive Mode I leakageI CCHI CCDI CCII CCTI CCR------0.21.03550030371.06.01028003542µAµAµAµAmAmAInput Current (V IN = 0 V or V DDINT) (All digital inputs)I IN--±1µA Input Low Voltage (All digital inputs)V IL0-30%V DDINTVInput High Voltage (all digital inputs)V IH70%V DDINT-V DDINT VOutput High Voltage (I OH = -1 mA) (All digital outputs)V OH80%V DDINT-V DDINT VOutput Low Voltage (I OL = 1 mA) (All digital outputs)V OL0-20%V DDINTVElectrical Characteristics5.4AC Electrical CharacteristicsNOTEAll AC parameters measured with SPI Registers at default settings except where noted and the following registers over-programmed:Register 08 = 0xFFF7 and Register 11 = 0x20FFTable 4. Receiver AC Electrical Characteristics(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.Parameters measured at connector J6 of evaluation circuit.)Characteristic SymbolMin Typ Max Unit Sensitivity for 1% Packet Error Rate (PER) (-40 to +85 °C)SENS per--92-dBm Sensitivity for 1% Packet Error Rate (PER) (+25 °C)--92-87dBm Saturation (maximum input level)SENS max-10-dBm Channel Rejection for 1% PER (desired signal -82 dBm)+5 MHz (adjacent channel)-5 MHz (adjacent channel)+10 MHz (alternate channel)-10 MHz (alternate channel)>= 15 MHz -----2531424149-----dB dB dB dB dB Frequency Error Tolerance --200kHz Symbol Rate Error Tolerance--80ppmTable 5. Transmitter AC Electrical Characteristics(V BATT , V DDINT = 2.7 V, T A = 25 °C, f ref = 16 MHz, unless otherwise noted.Parameters measured at connector J5 of evaluation circuit.)Characteristic SymbolMin Typ Max Unit Power Spectral Density (-40 to +85 °C) Absolute limit --47-dBmPower Spectral Density (-40 to +85 °C) Relative limit -47-Nominal Output Power 11SPI Register 12 programmed to 0x00BC which sets output power to nominal (0 dBm typical).P out-303dBm Maximum Output Power 22SPI Register 12 programmed to 0x00FC which sets output power to maximum.4dBmError Vector MagnitudeEVM -2035 %Output Power Control Range (-27 dBm to +4 dBm typical)-31-dB Over the Air Data Rate -250-kbps 2nd Harmonic --42-dBc 3rd Harmonic--44-dBcElectrical CharacteristicsFigure6. Parameter Evaluation CircuitFunctional Description6Functional Description6.1MC13192/MC13193 Operational ModesThe MC13192/MC13193 has a number of operational modes that allow for low-current operation.Transition from the Off to Idle mode occurs when RST is negated. Once in Idle, the SPI is active and is used to control the IC. Transition to Hibernate and Doze modes is enabled via the SPI. These modes are summarized, along with the transition times, in Table 6. Current drain in the various modes is listed in Table 3, DC Electrical Characteristics.6.2Serial Peripheral Interface (SPI)The host microcontroller directs the MC13192/MC13193, checks its status, and reads/writes data to the device through the 4-wire SPI port. The transceiver operates as a SPI slave device only. A transaction between the host and the MC13192/MC13193 occurs as multiple 8-bit bursts on the SPI. The SPI signals are:1.Chip Enable (CE) - A transaction on the SPI port is framed by the active low CE input signal. A transaction is a minimum of 3 SPI bursts and can extend to a greater number of bursts.2.SPI Clock (SPICLK) - The host drives the SPICLK input to the MC13192/MC13193. Data is clocked into the master or slave on the leading (rising) edge of the return-to-zero SPICLK and data out changes state on the trailing (falling) edge of SPICLK.NOTEFor Freescale microcontrollers, the SPI clock format is the clock phase control bit CPHA = 0 and the clock polarity control bit CPOL = 0.3.Master Out/Slave In (MOSI) - Incoming data from the host is presented on the MOSI input.4.Master In/Slave Out (MISO) - The MC13192/MC13193 presents data to the master on the MISO output.Table 6. MC13192/MC13193 Mode Definitions and Transition TimesMode DefinitionTransition Time To or From Idle Off All IC functions Off, Leakage only. RST asserted. Digital outputs are tri-stated including IRQ25 ms to Idle Hibernate Crystal Reference Oscillator Off. (SPI not functional.) IC Responds to ATTN. Data is retained.20 ms to IdleDozeCrystal Reference Oscillator On but CLKO output available only if Register 7, Bit 9 = 1 for frequencies of 1 MHz or less. (SPI not functional.) Responds to ATTN and can be programmed to enter Idle Mode through an internal timer comparator.(300 + 1/CLKO) µs to Idle Idle Crystal Reference Oscillator On with CLKO output available. SPI active.Receive Crystal Reference Oscillator On. Receiver On.144 µs from Idle TransmitCrystal Reference Oscillator On. Transmitter On.144 µs from IdleFunctional Description A typical interconnection to a microcontroller is shown in Figure7.Figure7. SPI InterfaceAlthough the SPI port is fully static, internal memory, timer and interrupt arbiters require an internal clock (CLK core), derived from the crystal reference oscillator, to communicate from the SPI registers to internal registers and memory.6.2.1SPI Burst OperationThe SPI port of an MCU transfers data in bursts of 8 bits with most significant bit (MSB) first. The master (MCU) can send a byte to the slave (transceiver) on the MOSI line and the slave can send a byte to the master on the MISO line. Although an MC13192/MC13193 transaction is three or more SPI bursts long, the timing of a single SPI burst is shown in Figure8.Functional Description6.2.2 SPI Transaction OperationAlthough the SPI port of an MCU transfers data in bursts of 8 bits, the MC13192/MC13193 requires that a complete SPI transaction be framed by CE, and there will be three (3) or more bursts per transaction. The assertion of CE to low signals the start of a transaction. The first SPI burst is a write of an 8-bit header to the transceiver (MOSI is valid) that defines a 6-bit address of the internal resource being accessed and identifies the access as being a read or write operation. In this context, a write is data written to theMC13192/MC13193 and a read is data written to the SPI master. The following SPI bursts will be either the write data (MOSI is valid) to the transceiver or read data from the transceiver (MISO is valid).Although the SPI bus is capable of sending data simultaneously between master and slave, theMC13192/MC13193 never uses this mode. The number of data bytes (payload) will be a minimum of 2 bytes and can extend to a larger number depending on the type of access. After the final SPI burst, CE is negated to high to signal the end of the transaction. Refer to the MC13192/MC13193 Reference Manual , part number MC13192RM for more details on SPI registers and transaction types.An example SPI read transaction with a 2-byte payload is shown in Figure 9.Figure 9. SPI Read Transaction DiagramTable 7. SPI Timing SpecificationsSymbol ParameterMin TypMaxUnit T0SPICLK period125nS T1Pulse width, SPICLK low 62.5nS T2Pulse width, SPICLK high62.5nS T3Delay time, MISO data valid from falling SPICLK15nS T4Setup time, CE low to rising SPICLK15nS T5Delay time, MISO valid from CE low 15nS T6Setup time, MOSI valid to rising SPICLK 15nS T7Hold time, MOSI valid from rising SPICLK15nSPin Connections 7Pin ConnectionsTable8. Pin Function DescriptionPin #Pin Name Type Description Functionality1RFIN-RF Input LNA negative differential input.2RFIN+RF Input LNA positive differential input.3Not Used Tie to Ground.4Not Used Tie to Ground.5PAO+RF Output /DCInput Power Amplifier Positive Output. Open drain. Connect to V DDA.6PAO-RF Output/DC Input Power Amplifier Negative Output. Opendrain. Connect to V DDA.7SM Test mode pin. Tie to Ground Tie to Ground for normaloperation8GPIO41Digital Input/ Output General Purpose Input/Output 4.See Footnote 19GPIO31Digital Input/ Output General Purpose Input/Output 3.See Footnote 110GPIO21Digital Input/ Output General Purpose Input/Output 2. Whengpio_alt_en, Register 9, Bit 7 = 1, GPIO2functions as a “CRC Valid” indicator.See Footnote 111GPIO11Digital Input/ Output General Purpose Input/Output 1. Whengpio_alt_en, Register 9, Bit 7 = 1, GPIO1functions as an “Out of Idle” indicator.See Footnote 112RST Digital Input Active Low Reset. While held low, the IC isin Off Mode and all internal information islost from RAM and SPI registers. Whenhigh, IC goes to IDLE Mode, with SPI indefault state.13RXTXEN Digital Input Active High. Low to high transition initiatesRX or TX sequence depending on SPIsetting. Should be taken high after SPIprogramming to start RX or TX sequenceand should be held high through thesequence. After sequence is complete,return RXTXEN to low. When held low,forces Idle Mode.14ATTN Digital Input Active Low Attention. Transitions IC fromeither Hibernate or Doze Modes to Idle.15CLKO Digital Output Clock output to host MCU. Programmablefrequencies of:16 MHz, 8 MHz, 4 MHz, 2 MHz, 1 MHz, 62.5kHz, 32.786+ kHz (default),and 16.393+ kHz.16SPICLK Digital Clock Input External clock input for the SPI interface.Pin Connections17MOSI Digital Input Master Out/Slave In. Dedicated SPI data input.18MISO Digital Output Master In/Slave Out. Dedicated SPI data output.19CE Digital Input Active Low Chip Enable. Enables SPI transfers.20IRQDigital OutputActive Low Interrupt Request.Open drain device.Programmable 40 k Ω internal pull-up.Interrupt can be serviced every 6 µs with <20 pF load.Optional external pull-up must be >4 k Ω.21VDDD Power Output Digital regulated supply bypass.Decouple to ground.22VDDINT Power InputDigital interface supply & digital regulator input. Connect to Battery.2.0 to3.4 V. Decouple to ground.23GPIO51Digital Input/Output General Purpose Input/Output 5.See Footnote 1 24GPIO61Digital Input/Output General Purpose Input/Output 6.See Footnote 1 25GPIO71Digital Input/Output General Purpose Input/Output 7.See Footnote 126XTAL1Input Crystal Reference oscillator input.Connect to 16 MHz crystal and load capacitor.27XTAL2Input/OutputCrystal Reference oscillator output Note:Do not load this pin by using it as a 16 MHz source. Measure 16 MHz output at Pin 15, CLKO, programmed for 16 MHz. See the MC13192/MC13193 Reference Manual for details.Connect to 16 MHz crystal and load capacitor.28VDDLO2Power Input LO2 VDD supply. Connect to VDDA externally.29VDDLO1Power Input LO1 VDD supply. Connect to VDDA externally.30VDDVCO Power Output VCO regulated supply bypass.Decouple to ground.31VBATT Power Input Analog voltage regulators Input. Connect to Battery.Decouple to ground.32VDDAPower OutputAnalog regulated supply Output. Connect to directly VDDLO1 and VDDLO2 externally and to PAO± through a frequency trap.Note : Do not use this pin to supply circuitry external to the chip.Decouple to ground.EPGroundExternal paddle / flag ground.Connect to ground.1The transceiver GPIO pins default to inputs at reset. There are no programmable pullups on these pins. Unused GPIO pins should be tied to ground if left as inputs, or if left unconnected, they should be programmed as outputs set to the low state.Table 8. Pin Function Description (continued)Pin #Pin Name TypeDescriptionFunctionalityPin ConnectionsFigure10. Pin Connections (Top View)Applications Information8Applications Information8.1Crystal Oscillator Reference FrequencyThe IEEE 802.15.4 Standard requires that several frequency tolerances be kept within ± 40 ppm accuracy. This means that a total offset up to 80 ppm between transmitter and receiver will still result in acceptable performance. The MC13192/MC13193 transceiver provides onboard crystal trim capacitors to assist in meeting this performance.The primary determining factor in meeting this specification is the tolerance of the crystal oscillator reference frequency. A number of factors can contribute to this tolerance and a crystal specification will quantify each of them:1.The initial (or make) tolerance of the crystal resonant frequency itself.2.The variation of the crystal resonant frequency with temperature.3.The variation of the crystal resonant frequency with time, also commonly known as aging.4.The variation of the crystal resonant frequency with load capacitance, also commonly known aspulling. This is affected by:a)The external load capacitor values - initial tolerance and variation with temperature.b)The internal trim capacitor values - initial tolerance and variation with temperature.c)Stray capacitance on the crystal pin nodes - including stray on-chip capacitance, stray packagecapacitance and stray board capacitance; and its initial tolerance and variation withtemperature.Freescale has specified that a 16 MHz crystal with a <9 pF load capacitance is required. TheMC13192/MC13193 does not contain a reference divider, so 16 MHz is the only frequency that can be used. A crystal requiring higher load capacitance is prohibited because a higher load on the amplifier circuit may compromise its performance. The crystal manufacturer defines the load capacitance as that total external capacitance seen across the two terminals of the crystal. The oscillator amplifier configuration used in the MC13192/MC13193 requires two balanced load capacitors from each terminal of the crystal to ground. As such, the capacitors are seen to be in series by the crystal, so each must be <18 pF for proper loading.In the reference schematic, the external load capacitors are shown as 6.8 pF each, used in conjunction with a crystal that requires an 8 pF load capacitance. The default internal trim capacitor value (2.4 pF) and stray capacitance total value (6.8 pF) sum up to 9.2 pF giving a total of 16 pF. The value for the stray capacitance was determined empirically assuming the default internal trim capacitor value and for a specific board layout. A different board layout may require a different external load capacitor value. The on-chip trim capability may be used to determine the closest standard value by adjusting the trim value via the SPI and observing the frequency at CLKO. Each internal trim load capacitor has a trim range of approximately 5 pF in 20 fF steps.Initial tolerance for the internal trim capacitance is approximately ±15%.Since the MC13192/MC13193 contains an on-chip reference frequency trim capability, it is possible to trim out virtually all of the initial tolerance factors and put the frequency within 0.12 ppm on aboard-by-board basis.Applications Information A tolerance analysis budget may be created using all the previously stated factors. It is an engineering judgment whether the worst case tolerance will assume that all factors will vary in the same direction or if the various factors can be statistically rationalized using RSS (Root-Sum-Square) analysis. The aging factor is usually specified in ppm/year and the product designer can determine how many years are to be assumed for the product lifetime. Taking all of the factors into account, the product designer can determine the needed specifications for the crystal and external load capacitors to meet the IEEE 802.15.4 specification.8.2Design ExampleFigure11 shows a basic application schematic for interfacing the MC13192/MC13193 with an MCU. Table9 lists the Bill of Materials (BOM).The MC13192/MC13193 has differential RF inputs and outputs that are well suited to balanced printed wire antenna structures. Alternatively, as in the application circuit, a printed wire antenna, a chip antenna, or other single-ended structures can be used with commercially available chip baluns or microstrip equivalents. PAO+ and PAO- require a DC connection to VDDA (the analog regulator output) through AC blocking elements. This is accomplished through the baluns in the referenced design.The 16 MHz crystal should be mounted close to the MC13192/MC13193 because the crystal trim default assumes that the listed KDS Daishinku crystal (see Table10) and the 6.8 pF load capacitors shown are used. If a different crystal is used, it should have a specified load capacitance (stray capacitance, etc.) of 9 pF or less. A second crystal that has been evaluated and also gives acceptable performance is the Toyocom TSX-10A 16 MHZ TN4-26139 (see Table11).VDDA is an analog regulator output used to supply only the onboard PA (PAO+ and PAO-) and VDDLO1 and VDDLO2 pins. VDDA should not be used to power devices external to the transceiver chip. Bypassing capacitors are critical and should be placed close to the device. Unused pins should be grounded as shown. The SPI connections to the MCU include CE, MOSI, MISO, and SPICLK. The SPI can run at a frequency of 8 MHz or less. Optionally, CLKO can provide a clock to the MCU. The CLKO frequency is programmable via the SPI and has a default of 32.786+ kHz (16 MHz / 488). The ATTN line can be driven by a GPIO from the MCU (as shown) or can also be controlled by a switch or other hardware. The latter approach allows the MCU to be put into a sleep mode and then awakened by CLKO when the ATTN line wakes up the MC13192/MC13193. RXTXEN is used to initiate receive, transmit or CCA/ED sequences under MCU control. RXTXEN must be controlled by an MCU GPIO with the connection shown. Device reset (RST) is controlled through a connection to an MCU GPIO.When the MC13192/MC13193 is used in Stream Mode, as with 802.15.4 MAC/PHY software, theMC13192/MC13193 GPIO1 functions as an “Out of Idle” indicator and GPIO2 functions as a “CRC Valid” / Clear Channel Assessment (CCA) result indicator and are not available for general purpose use.。
TC1313-BO0EUNTR资料
TC1313Features•Dual-Output Regulator (500mA Buck Regulator and 300mA Low-Dropout Regulator (LDO))•Total Device Quiescent Current = 57µA (Typ.)•Independent Shutdown for Buck and LDO Outputs•Both Outputs Internally Compensated •Synchronous Buck Regulator:-Over 90% Typical Efficiency- 2.0MHz Fixed-Frequency PWM(Heavy Load)-Low Output Noise-Automatic PWM-to-PFM mode transition-Adjustable (0.8V to 4.5V) and StandardFixed-Output Voltages (0.8V, 1.2V, 1.5V,1.8V,2.5V,3.3V)•Low-Dropout Regulator:-Low-Dropout Voltage=137mV Typ. @200mA-Standard Fixed-Output Voltages(1.5V, 1.8V, 2.5V, 3.3V)•Small 10-pin 3X3 DFN or MSOP Package Options•Operating Junction Temperature Range:--40°C to +125°C•Undervoltage Lockout (UVLO)•Output Short Circuit Protection •Overtemperature ProtectionApplications•Cellular Phones•Portable Computers•USB-Powered Devices•Handheld Medical Instruments•Organizers and PDAs DescriptionThe TC1313 combines a 500mA synchronous buck regulator and 300mA Low-Dropout Regulator (LDO) to provide a highly integrated solution for devices that require multiple supply voltages. The unique combina-tion of an integrated buck switching regulator and low-dropout linear regulator provides the lowest system cost for dual-output voltage applications that require one lower processor core voltage and one higher bias voltage.The 500mA synchronous buck regulator switches at a fixed frequency of 2.0MHz when the load is heavy, providing a low-noise, small-size solution. When the load on the buck output is reduced to light levels, it changes operation to a Pulse Frequency Modulation (PFM) mode to minimize quiescent current draw from the battery. No intervention is necessary for smooth transition from one mode to another.The LDO provides a 300mA auxiliary output that requires a single 1µF ceramic output capacitor, minimizing board area and cost. The typical dropout voltage for the LDO output is 137mV for a 200mA load.The TC1313 is available in either the 10-pin DFN or MSOP package.Additional protection features include: UVLO, overtemperature and overcurrent protection on both outputs.For a complete listing of TC1313 standard parts, consult your Microchip representative.Package Type10-Lead DFN12687910543SHDN2V IN2V OUT2A GNDP GNDL XV IN1SHDN1V FB1/V OUT1NC10-Lead MSOP12687910543SHDN2V IN2V OUT2A GNDP GNDL XV IN1SHDN1V FB1/V OUT1NC500mA Synchronous Buck Regulator,+ 300mA LDO© 2005 Microchip Technology Inc.DS21974A-page 1TC1313DS21974A-page 2© 2005 Microchip Technology Inc.Functional Block DiagramSynchronous Buck RegulatorNDRVPDRVP GNDV IN1L XDriverP GNDControlV OUT1/V FB1V IN2SHDN1V REFLDOV OUT2A GNDA GNDP GNDUndervoltage LockoutUVLOUVLOSHDN2V REF(UVLO)© 2005 Microchip Technology Inc.DS21974A-page 3TC1313Typical Application Circuits10-Lead DFN12687910543SHDN2V IN2V OUT2A GNDP GND L XV IN1SHDN1V OUT1NC4.7µFInput Voltage 4.7µH4.7µF2.1V @1µF3.3V @4.5V to5.5V Adjustable-Output Application121k Ω200k Ω 4.99k Ω33pF 12687910543SHDN2V IN2V OUT2A GNDP GND L X V IN1SHDN1V OUT1NC4.7µF4.7µH4.7µF1.5V @ 500mA1µF2.5V @ 300mA2.7V to 4.2VTC1313V OUT1V OUT2V IN V OUT1V OUT21.0µF*Optional Capacitor V IN2300mA500mANote: Connect DFN package exposed pad to A GND .10-Lead MSOPFixed-Output ApplicationTC1313NoteTC1313DS21974A-page 4© 2005 Microchip Technology Inc.1.0ELECTRICALCHARACTERISTICSAbsolute Maximum Ratings †V IN - A GND ......................................................................6.0V All Other I/O ..............................(A GND - 0.3V) to (V IN + 0.3V)L X to P GND ..............................................-0.3V to (V IN + 0.3V)P GND to A GND ...................................................-0.3V to +0.3V Output Short Circuit Current .................................Continuous Power Dissipation (Note 7)..........................Internally Limited Storage temperature.....................................-65°C to +150°C Ambient Temp. with Power Applied.................-40°C to +85°C Operating Junction Temperature...................-40°C to +125°C ESD protection on all pins (HBM)....................................... 3kV† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied.Exposure to maximum rating conditions for extended periods may affect device reliability.DC CHARACTERISTICSElectrical Characteristics: V IN1= V IN2=SHDN1,2=3.6V,C OUT1=C IN =4.7µF, C OUT2=1µF,L =4.7µH,V OUT1 (ADJ)=1.8V, I OUT1=100ma, I OUT2=0.1mA T A =+25°C. Boldface specifications apply over the T A range of -40°C to +85°C .ParametersSymMinTypMaxUnitsConditionsInput/Output Characteristics Input VoltageV IN 2.7— 5.5V Note 1, Note 2, Note 8Maximum Output Current I OUT1_MAX 500——mA Note 1Maximum Output Current I OUT2_MAX 300——mA Note 1Shutdown CurrentCombined V IN1 and V IN2 Current I IN_SHDN—0.051µA SHDN1=SHDN2=GND Operating I QI Q—57100µA SHDN1=SHDN2=V IN2I OUT1=0mA,I OUT2=0mA Synchronous Buck I Q—38—µA SHDN1 = V IN , SHDN2 = GND LDO I Q —44—µA SHDN1 = GND, SHDN2 = V IN2Shutdown/UVLO/Thermal Shutdown Characteristics SHDN1,SHDN2,Logic Input Voltage Low V IL ——15%V IN V IN1=V IN2=2.7V to 5.5V SHDN1,SHDN2,Logic Input Voltage High V IH 45——%V IN V IN1=V IN2=2.7V to 5.5V SHDN1,SHDN2,Input Leakage Current I IN-1.0±0.011.0µAV IN1=V IN2=2.7V to 5.5V SHDNX =GND SHDNY =V IN Thermal ShutdownT SHD —165—°C Note 6, Note 7Thermal Shutdown Hysteresis T SHD-HYS —10—°C Undervoltage Lockout (V OUT1 and V OUT2)UVLO 2.4 2.55 2.7V V IN1 FallingUndervoltage Lockout Hysteresis UVLO -HYS—200—mVNote 1:The Minimum V IN has to meet two conditions: V IN ≥ 2.7V and V IN ≥ V RX + V DROPOUT , V RX = V R1 or V R2.2:V RX is the regulator output voltage setting.3:TCV OUT2 = ((V OUT2max – V OUT2min ) * 106)/(V OUT2 * D T ).4:Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1mA to the maximum specified output current.5:Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential.6:The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junctiontemperature and the thermal resistance from junction to air. (i.e. T A , T J , θJA ). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.7:The integrated MOSFET switches have an integral diode from the L X pin to V IN , and from L X to P GND . In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is not able to limit the junction temperature for these cases.8:V IN1 and V IN2 are supplied by the same input source.TC1313Synchronous Buck Regulator (V OUT1)Adjustable Output Voltage Range V OUT10.8— 4.5VAdjustable Reference FeedbackVoltage (V FB1)V FB10.780.80.82VFeedback Input Bias Current(I FB1)I VFB1—-1.5—nAOutput Voltage Tolerance Fixed(V OUT1)V OUT1-2.5±0.3+2.5%Note2Line Regulation (V OUT1)V LINE-REG—0.2—%/V V IN = V R+1V to 5.5V,I LOAD = 100mALoad Regulation (V OUT1)V LOAD-REG—0.2—%V IN=V R+1.5V,I LOAD=100mA to500mA (Note1)Dropout Voltage V OUT1V IN – V OUT1—280—mV I OUT1 = 500mA, V OUT1=3.3V(Note5)Internal Oscillator Frequency F OSC 1.6 2.0 2.4MHzStart Up Time T SS—0.5—ms T R = 10% to 90%R DSon P-Channel R DSon-P—450650mΩI P = 100mAR DSon N-Channel R DSon-N—450650mΩI N = 100mAL X Pin Leakage Current I LX-1.0±0.01 1.0μA SHDN = 0V, V IN = 5.5V, L X = 0V,L X = 5.5VPositive Current Limit Threshold+I LX(MAX)—700—mALDO Output (V OUT2)Output Voltage Tolerance (V OUT2)V OUT2-2.5±0.3+2.5%Note2Temperature Coefficient TCV OUT—25—ppm/°C Note3Line RegulationΔV OUT2/ΔV IN-0.2±0.02+0.2%/V(V R+1V) ≤ V IN≤ 5.5VLoad Regulation, V OUT2≥ 2.5VΔV OUT2/I OUT2-0.750.1+0.75%I OUT2 = 0.1mA to 300mA(Note4)Load Regulation, V OUT2 < 2.5VΔV OUT2/I OUT2-0.900.1+0.90%I OUT2 = 0.1mA to 300mA(Note4)Dropout Voltage V OUT2 > 2.5V V IN – V OUT2—137205300500mV I OUT2 = 200mA (Note5)I OUT2=300mAPower Supply Rejection Ratio PSRR—62—dB f = 100Hz, I OUT1 = I OUT2 = 50mA,C IN = 0µFOutput Noise eN— 1.8—µV/(Hz)½ f = 1kHz, I OUT2=50mA,SHDN1=GNDOutput Short Circuit Current (Average)I OUT sc2—240—mA R LOAD2≤ 1ΩDC CHARACTERISTICS (CONTINUED)Electrical Characteristics: V IN1= V IN2=SHDN1,2=3.6V,C OUT1=C IN=4.7µF, C OUT2=1µF,L=4.7µH,V OUT1 (ADJ)=1.8V,I OUT1=100ma, I OUT2=0.1mA T A=+25°C. Boldface specifications apply over the T A range of -40°C to +85°C.Parameters Sym Min Typ Max Units ConditionsNote1:The Minimum V IN has to meet two conditions: V IN≥ 2.7V and V IN≥ V RX + V DROPOUT, V RX = V R1 or V R2.2:V RX is the regulator output voltage setting.3:TCV OUT2 = ((V OUT2max – V OUT2min) * 106)/(V OUT2 * D T).4:Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1mA to the maximum specified output current.5:Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential.6:The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. T A, T J, θJA). Exceeding the maximum allowable powerdissipation causes the device to initiate thermal shutdown.7:The integrated MOSFET switches have an integral diode from the L X pin to V IN, and from L X to P GND. In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is notable to limit the junction temperature for these cases.8:V IN1 and V IN2 are supplied by the same input source.© 2005 Microchip Technology Inc.DS21974A-page 5TC1313DS21974A-page 6© 2005 Microchip Technology Inc.TEMPERATURE SPECIFICATIONSWake-Up Time(From SHDN2 mode), (V OUT2)t WK —31100µs I OUT1 = I OUT2 = 50mA Settling Time(From SHDN2 mode), (V OUT2)t S—100—µsI OUT1 = I OUT2 = 50mAElectrical Specifications: Unless otherwise indicated, all limits are specified for: V IN = +2.7V to +5.5VParametersSymMinTypMaxUnitsConditionsTemperature RangesOperating Junction Temperature Range T J -40—+125°C Steady state Storage Temperature Range T A -65—+150°C Maximum Junction Temperature T J——+150°CTransientThermal Package Resistances Thermal Resistance, 10L-DFNθJA—41—°C/WTypical 4-layer board with Internal Ground Plane and 2 Vias in Thermal PadThermal Resistance, 10L-MSOPθJA—113—°C/WTypical 4-layer board with Internal Ground PlaneDC CHARACTERISTICS (CONTINUED)Electrical Characteristics: V IN1= V IN2=SHDN1,2=3.6V,C OUT1=C IN =4.7µF, C OUT2=1µF,L =4.7µH,V OUT1 (ADJ)=1.8V, I OUT1=100ma, I OUT2=0.1mA T A =+25°C. Boldface specifications apply over the T A range of -40°C to +85°C .ParametersSym Min Typ Max Units ConditionsNote 1:The Minimum V IN has to meet two conditions: V IN ≥ 2.7V and V IN ≥ V RX + V DROPOUT , V RX = V R1 or V R2.2:V RX is the regulator output voltage setting.3:TCV OUT2 = ((V OUT2max – V OUT2min ) * 106)/(V OUT2 * D T ).4:Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1mA to the maximum specified output current.5:Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential.6:The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junctiontemperature and the thermal resistance from junction to air. (i.e. T A , T J , θJA ). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown.7:The integrated MOSFET switches have an integral diode from the L X pin to V IN , and from L X to P GND . In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is not able to limit the junction temperature for these cases.8:V IN1 and V IN2 are supplied by the same input source.TC1313 2.0TYPICAL PERFORMANCE CURVESNote: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN=4.7µF, C OUT2=1µF,L=4.7µH,V OUT1 (ADJ)=1.8V, T A=+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A=+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-1:I Q Switcher and LDOCurrent vs. Ambient Temperature.FIGURE 2-2:I Q Switcher Current vs.Ambient Temperature.FIGURE 2-3:I Q LDO Current vs. AmbientTemperature.FIGURE 2-4:V OUT1 Output Efficiency vs.Input Voltage (V OUT1 = 1.2V).FIGURE 2-5:V OUT1 Output Efficiency vs.I OUT1 (V OUT1 = 1.2V).FIGURE 2-6:V OUT1 Output Efficiency vs.Input Voltage (V OUT1 = 1.8V).Note:The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed hereinare not tested or guaranteed. In some graphs or tables, the data presented may be outside the specifiedoperating range (e.g., outside specified power supply range) and therefore outside the warranted range.© 2005 Microchip Technology Inc.DS21974A-page 7TC1313DS21974A-page 8© 2005 Microchip Technology Inc.Note: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN =4.7µF, C OUT2=1µF,L =4.7µH,V OUT1 (ADJ)=1.8V, T A =+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A =+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-7:V OUT1 Output Efficiency vs. I OUT1 (V OUT1 = 1.8V).FIGURE 2-8:V OUT1 Output Efficiency vs.Input Voltage (V OUT1 = 3.3V).FIGURE 2-9:V OUT1 Output Efficiency vs. I OUT1 (V OUT1 = 3.3V).FIGURE 2-10:V OUT1 vs. I OUT1(VOUT1 = 1.2V).FIGURE 2-11:V OUT1 vs. I OUT1(V OUT1 = 1.8V).FIGURE 2-12:V OUT1 vs. I OUT1(V OUT1 = 3.3V).TC1313 Note: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN=4.7µF, C OUT2=1µF,L=4.7µH,V OUT1 (ADJ)=1.8V, T A=+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A=+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-13:V OUT1 Switching Frequencyvs. Input Voltage.FIGURE 2-14:V OUT1 Switching Frequencyvs. Ambient Temperature.FIGURE 2-15:V OUT1 Adjustable FeedbackVoltage vs. Ambient Temperature.FIGURE 2-16:V OUT1 Switch Resistancevs. Input Voltage.FIGURE 2-17:V OUT1 Switch Resistancevs. Ambient Temperature.FIGURE 2-18:V OUT1 Dropout Voltage vs.Ambient Temperature.© 2005 Microchip Technology Inc.DS21974A-page 9TC1313DS21974A-page 10© 2005 Microchip Technology Inc.Note: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN =4.7µF, C OUT2=1µF,L =4.7µH,V OUT1 (ADJ)=1.8V, T A =+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A =+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-19:V OUT1 and V OUT2 Heavy Load Switching Waveforms vs. Time.FIGURE 2-20:V OUT1 and V OUT2 Light Load Switching Waveforms vs. Time.FIGURE 2-21:V OUT2 Output Voltage vs. Input Voltage (V OUT2 = 1.5V).FIGURE 2-22:V OUT2 Output Voltage vs. Input Voltage (V OUT2 = 1.8V).FIGURE 2-23:V OUT2 Output Voltage vs. Input Voltage (V OUT2 = 2.5V).FIGURE 2-24:V OUT2 Output Voltage vs. Input Voltage (V OUT2= 3.3V).Note: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN=4.7µF, C OUT2=1µF,L=4.7µH,V OUT1 (ADJ)=1.8V, T A=+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A=+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-25:V OUT2 Dropout Voltage vs.Ambient Temperature (V OUT2 = 2.5V).FIGURE 2-26:V OUT2 Dropout Voltage vs.Ambient Temperature (V OUT2 = 3.3V).FIGURE 2-27:V OUT2 Line Regulation vs.Ambient Temperature.FIGURE 2-28:V OUT2 Load Regulation vs.Ambient Temperature.FIGURE 2-29:V OUT2 Power Supply RippleRejection vs. Frequency.FIGURE 2-30:V OUT2 Noise vs. Frequency.Note: Unless otherwise indicated, V IN1= V IN2=SHDN1,2 =3.6V, C OUT1=C IN=4.7µF, C OUT2=1µF,L=4.7µH,V OUT1 (ADJ)=1.8V, T A=+25°C. Boldface specifications apply over the T A range of -40°C to +85°C. T A=+25°C. Adjustable or fixed-output voltage options can be used to generate the Typical Performance Characteristics.FIGURE 2-31:V OUT1 Load Step Responsevs. Time.FIGURE 2-32:V OUT2 Load Step Responsevs. Time.FIGURE 2-33:V OUT1 and V OUT2 Line StepResponse vs. Time.FIGURE 2-34:V OUT1 and V OUT2 StartupWaveforms.FIGURE 2-35:V OUT1 and V OUT2 ShutdownWaveforms.3.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table3-1. TABLE 3-1:PIN FUNCTION TABLE3.1LDO Shutdown Input Pin (SHDN2) SHDN2 is a logic-level input used to turn the LDO regulator on and off. A logic-high (> 45% of V IN) will enable the regulator output. A logic-low (< 15% of V IN) will ensure that the output is turned off.3.2LDO Input Voltage Pin (V IN2)V IN2 is a LDO power-input supply pin. Connect variable-input voltage source to V IN2. Connect V IN1 and V IN2 together with board traces as short as possible. V IN2 provides the input voltage for the LDO regulator. An additional capacitor can be added to lower the LDO regulator input ripple voltage.3.3LDO Output Voltage Pin (V OUT2)V OUT2 is a regulated LDO output voltage pin. Connect a 1µF or larger capacitor to V OUT2 and A GND for proper operation.3.4No Connect Pin (NC)No connection.3.5Analog Ground Pin (A GND)A GND is the analog ground connection. Tie A GND to the analog portion of the ground plane (A GND). See the physical layout information in Section 5.0 “Application Circuits/Issues” for grounding recommendations. 3.6Buck Regulator Output Sense Pin(V FB/V OUT1)For V OUT1 adjustable-output voltage options, connect the center of the output voltage divider to the V FB pin. For fixed-output voltage options, connect the output of the buck regulator to this pin (V OUT1). 3.7Buck Regulator Shutdown InputPin (SHDN1)SHDN1 is a logic-level input used to turn the buck regulator on and off. A logic-high (> 45% of V IN) will enable the regulator output. A logic-low (< 15% of V IN) will ensure that the output is turned off.3.8Buck Regulator Input Voltage Pin(V IN1)V IN1 is the buck regulator power-input supply pin. Connect a variable-input voltage source to V IN1. Connect V IN1 and V IN2 together with board traces as short as possible.3.9Buck Inductor Output Pin (L X) Connect L X directly to the buck inductor. This pin carries large signal-level current; all connections should be made as short as possible.3.10Power Ground Pin (P GND)Connect all large-signal level ground returns to P GND. These large-signal level ground traces should have a small loop area and length to prevent coupling of switching noise to sensitive traces. Please see the physical layout information supplied in Section 5.0“Application Circuits/Issues” for grounding recommendations.3.11Exposed Pad (EP)For the DFN package, connect the EP to A GND with vias into the A GND plane.Pin Function1SHDN2Active Low Shutdown Input for LDO Output Pin2V IN2Analog Input Supply Voltage Pin3V OUT2LDO Output Voltage Pin4NC No Connect5A GND Analog Ground Pin6V FB / V OUT1Buck Feedback Voltage (Adjustable Version)/Buck Output Voltage (Fixed Version) Pin 7SHDN1Active Low Shutdown Input for Buck Regulator Output Pin8V IN1Buck Regulator Input Voltage Pin9L X Buck Inductor Output Pin10P GND Power Ground PinEP ExposedPad For the DFN package, the center exposed pad is a thermal path to remove heat from the device. Electrically, this pad is at ground potential and should be connected to A GND.4.0DETAILED DESCRIPTION4.1Device OverviewThe TC1313 combines a 500mA synchronous buck regulator with a 300mA LDO. This unique combination provides a small, low-cost solution for applications that require two or more voltage rails. The buck regulator can deliver high-output current over a wide range of input-to-output voltage ratios while maintaining high efficiency. This is typically used for the lower-voltage, higher-current processor core. The LDO is a minimal parts-count solution (single-output capacitor), providing a regulated voltage for an auxiliary rail. The typical LDO dropout voltage (137mV @ 200mA) allows the use of very low input-to-output LDO differential voltages, minimizing the power loss internal to the LDO pass transistor. Integrated features include independent shutdown inputs, UVLO, overcurrent and overtemperature shutdown.4.2Synchronous Buck RegulatorThe synchronous buck regulator is capable of supply-ing a 500mA continuous output current over a wide range of input and output voltages. The output voltage range is from 0.8V (min) to 4.5V (max). The regulator operates in three different modes and automatically selects the most efficient mode of operation. During heavy load conditions, the TC1313 buck converter operates at a high, fixed frequency (2.0MHz) using current mode control. This minimizes output ripple and noise (less than 8mV peak-to-peak ripple) while main-taining high efficiency (typically > 90%). For standby or light-load applications, the buck regulator will automat-ically switch to a power-saving Pulse Frequency Modulation (PFM) mode. This minimizes the quiescent current draw on the battery while keeping the buck output voltage in regulation. The typical buck PFM mode current is 38µA. The buck regulator is capable of operating at 100% duty cycle, minimizing the voltage drop from input to output for wide-input, battery-powered applications. For fixed-output voltage applica-tions, the feedback divider and control loop compensa-tion components are integrated, eliminating the need for external components. The buck regulator output is protected against overcurrent, short circuit and over-temperature. While shut down, the synchronous buck N-channel and P-channel switches are off, so the L X pin is in a high-impedance state (this allows for connecting a source on the output of the buck regulator as long as its voltage does not exceed the input voltage).4.2.1FIXED-FREQUENCY PWM MODE While operating in Pulse Width Modulation (PWM) mode, the TC1313 buck regulator switches at a fixed 2.0MHz frequency. The PWM mode is suited for higher load current operation, maintaining low output noise and high conversion efficiency. PFM to PWM mode transition is initiated for any of the following conditions.•Continuous inductor current is sensed•Inductor peak current exceeds 100mA•The buck regulator output voltage has droppedout of regulation (step load has occurred)The typical PFM-to-PWM threshold is 80mA.4.2.2PFM MODEPFM mode is entered when the output load on the buck regulator is very light. Once detected, the converter enters the PFM mode automatically and begins to skip pulses to minimize unnecessary quiescent current draw by reducing the number of switching cycles per second. The typical quiescent current for the switching regulator is less than 38µA. The transition from PWM to PFM mode occurs when discontinuous inductor current is sensed, or the peak inductor current is less than 60mA (typ.). The typical PWM to PFM mode threshold is 30mA. For low input-to-output differential voltages, the PWM to PFM mode threshold can be low due to the lack of ripple current. It is recommended that V IN1 be one volt greater than V OUT1 for PWM to PFM transitions.4.3Low-Dropout Regulator (LDO)The LDO output is a 300mA low-dropout linear regula-tor that provides a regulated output voltage with a single 1µF external capacitor. The output voltage is available in fixed options only, ranging from 1.5V to 3.3V. The LDO is stable using ceramic output capaci-tors that inherently provide lower output noise and reduce the size and cost of the regulator solution. The quiescent current consumed by the LDO output is typically less than 43.7µA, with a typical dropout volt-age of 137mV at 200mA. The LDO output is protected against overcurrent and overtemperature. While oper-ating in Dropout mode, the LDO quiescent current will increase, minimizing the necessary voltage differential needed for the LDO output to maintain regulation. The LDO output is protected against overcurrent and overtemperature.4.4Soft StartBoth outputs of the TC1313 are controlled during startup. Less than 1% of V OUT1 or V OUT2 overshoot is observed during start-up from V IN rising above the UVLO voltage; or SHDN1 or SHDN2 being enabled.4.5Overtemperature ProtectionThe TC1313 has an integrated overtemperature protection circuit that monitors the device junction temperature and shuts the device off if the junction temperature exceeds the typical 165°C threshold. If the overtemperature threshold is reached, the soft start is reset so that, once the junction temperature cools to approximately 155°C, the device will automatically restart.5.0APPLICATION CIRCUITS/ISSUES5.1Typical ApplicationsThe TC1313 500mA buck regulator + 300mA LDO operates over a wide input-voltage range (2.7V to 5.5V)and is ideal for single-cell Li-Ion battery-powered applications, USB-powered applications, three-cell NiMH or NiCd applications and 3V to 5V regulated input applications. The 10-pin MSOP and 3X3 DFN packages provide a small footprint with minimal exter-nal components.5.2Fixed-Output ApplicationA typical V OUT1 fixed-output voltage application is shown in “Typical Application Circuits”. A 4.7µF V IN1 ceramic input capacitor, 4.7µF V OUT1 ceramic capacitor, 1.0µF ceramic V OUT2 capacitor and 4.7µH inductor make up the entire external component solution for this dual-output application. No external dividers or compensation components are necessary.For this application, the input-voltage range is 2.7V to 4.2V, V OUT1=1.5V at 500mA, while V OUT2=2.5V at 300mA.5.3Adjustable-Output ApplicationA typical V OUT1 adjustable-output application is also shown in “Typical Application Circuits”. For this application, the buck regulator output voltage is adjust-able by using two external resistors as a voltage divider. For adjustable-output voltages, it is recom-mended that the top resistor divider value be 200k Ω.The bottom resistor divider can be calculated using the following formula:EQUATION 5-1:Example:For adjustable output applications, an additional R-C compensation is necessary for the buck regulator control loop stability. Recommended values are:An additional V IN2 capacitor can be added to reduce high-frequency noise on the LDO input-voltage pin (V IN2). This additional capacitor (1µF) is not necessary for typical applications.5.4Input and Output Capacitor Selection As with all buck-derived dc-dc switching regulators, the input current is pulled from the source in pulses. This places a burden on the TC1313 input filter capacitor. In most applications, a minimum of 4.7µF is recom-mended on V IN1 (buck regulator input-voltage pin). In applications that have high source impedance, or have long leads (10 inches) connecting to the input source,additional capacitance should be used. The capacitor type can be electrolytic (aluminum, tantalum, POSCAP ,OSCON) or ceramic. For most portable electronic applications, ceramic capacitors are preferred due to their small size and low cost.For applications that require very low noise on the LDO output, an additional capacitor (typically 1µF) can be added to the V IN2 pin (LDO input voltage pin).Low ESR electrolytic or ceramic can be used for the buck regulator output capacitor. Again, ceramic is recommended because of its physical attributes and cost. For most applications, a 4.7µF is recommended.Refer to Table 5-1 for recommended values. Larger capacitors (up to 22µF) can be used. There are some advantages in load step performance when using larger value capacitors. Ceramic materials, X7R and X5R, have low temperature coefficients and are well within the acceptable ESR range required.TABLE 5-1:TC1313 RECOMMENDED CAPACITOR VALUESR TOP =200k ΩV OUT1=2.1V V FB =0.8VR BOT =200k Ω x (0.8V/(2.1V – 0.8V))R BOT =123k Ω (Standard Value =121k Ω)R COMP =4.99k ΩC COMP =33pFR BOTR TOP V FBV OUT1V FB –--------------------------------⎝⎠⎛⎞×= C (V IN1)C(V IN2)C OUT1C OUT2Min 4.7µF none 4.7µF 1µF Maxnonenone22µF10µF。
半导体传感器ADUM1310ARWZ中文规格书
Data SheetADuM1400/ADuM1401/ADuM1402Rev. L | Page 21 of 31ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. Table 13. Parameter Rating Storage Temperature (T ST ) −65°C to +150°C Ambient Operating Temperature (T A )1 −40°C to +105°C Ambient Operating Temperature (T A )2−40°C to +125°C Supply Voltages (V DD1, V DD2)3−0.5 V to +7.0 V Input Voltage (V IA , V IB , V IC , V ID , V E1, V E2)3, 4−0.5 V to V DDI + 0.5 V Output Voltage (V OA , V OB , V OC , V OD )3, 4−0.5 V to V DDO + 0.5 V Average Output Current per Pin 5Side 1 (I O1)−18 mA to +18 mA Side 2 (I O2)−22 mA to +22 mA Common-Mode Transients 6−100 kV/µs to +100 kV/µs 1 Does not apply to ADuM1400W , ADuM1401W , and ADuM1402W automotive grade versions.2 Applies to ADuM1400W , ADuM1401W , and ADuM1402W automotive grade versions.3 All voltages are relative to their respective ground.4 V DDI and V DDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PC Board Layout section.5 See Figure 4 for maximum rated current values for various temperatures.6 This refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Ratings may cause latch-up or permanent damage. Stresses at or above those listed under Absolute MaximumRatings may cause permanent damage to the product. This is astress rating only; functional operation of the product at theseor any other conditions above those indicated in the operationalsection of this specification is not implied. Operation beyondthe maximum operating conditions for extended periods mayaffect product reliability. ESD CAUTIONTable 14. Maximum Continuous Working Voltage 1ParameterMax Unit Constraint AC Voltage, Bipolar Waveform565 V peak 50-year minimum lifetime AC Voltage, Unipolar WaveformBasic Insulation1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 DC VoltageBasic Insulation1131 V peak Maximum approved working voltage per IEC 60950-1 Reinforced Insulation560 V peak Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 1 Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details. Table 15. Truth Table (Positive Logic)V Ix Input 1V Ex Input 1, 2 V DDI State 1 V DDO State 1 V Ox Output 1 Notes HH or NC Powered Powered H LH or NC Powered Powered L XL Powered Powered Z XH or NC Unpowered Powered H Outputs return to the input state within 1 µs of V DDI power restoration. XL Unpowered Powered Z X X Powered Unpowered Indeterminate Outputs return to the input state within 1 µs of V DDO power restoration if the V Ex state is H or NC. Outputs return to a high impedance statewithin 8 ns of V DDO power restoration if the V Ex state is L.1V Ix and V Ox refer to the input and output signals of a given channel (A, B, C, or D). V Ex refers to the output enable signal on the same side as the V Ox outputs. V DDI and V DDO refer to the supply voltages on the input and output sides of the given channel, respectively.2 In noisy environments, connecting V Ex to an external logic high or low is recommended.ADuM1400/ADuM1401/ADuM1402 Data Sheet Rev. L | Page 28 of 31For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and has the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V—still well above the 0.5 V sensing threshold of the decoder.The preceding magnetic flux density values correspond to specific current magnitudes at given distances from theADuM1400/ADuM1401/ADuM1402 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM1400/ ADuM1401/ADuM1402 are extremely immune and can be affected only by extremely large currents operated at highfrequency very close to the component. For the 1 MHz example noted, one would have to place a 0.5 kA current 5 mm away from the ADuM1400/ADuM1401/ADuM1402 to affect the operation of the component.MAGNETIC FIELD FREQUENCY (Hz)M A X I M U M A L L O W A B L E C U R R E N T (k A )1k 10k 100M 100k 1M 10M 03786-020Figure 20. Maximum Allowable Current for Various Current-to-ADuM1400/ADuM1401/ADuM1402 SpacingsNote that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce error voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility. POWER CONSUMPTION The supply current at a given channel of the ADuM1400/ ADuM1401/ADuM1402 isolator is a function of the supply voltage, the data rate of the channel, and the output load of the channel. For each input channel, the supply current is given by I DDI = I DDI (Q ) f ≤ 0.5 f r I DDI = I DDI (D) × (2f − f r ) + I DDI (Q ) f > 0.5 f r For each output channel, the supply current is given by I DDO = I DDO (Q ) f ≤ 0.5 f r I DDO = (I DDO (D ) + (0.5 × 10−3) × C L × V DDO ) × (2f − f r ) + I DDO (Q ) f > 0.5 f r where: I DDI (D), I DDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). C L is the output load capacitance (pF). V DDO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the inputdata rate expressed in units of Mbps. f r is the input stage refresh rate (Mbps). I DDI (Q), I DDO (Q) are the specified input and output quiescent supply currents (mA).To calculate the total V DD1 and V DD2 supply current, the supply currents for each input and output channel corresponding to V DD1 and V DD2 are calculated and totaled. Figure 8 and Figure 9 provide per-channel supply currents as a function of data rate for an unloaded output condition. Figure 10 provides per-channel supply current as a function of data rate for a 15 pF output condition. Figure 11 through Figure 15 provide total V DD1 and V DD2 supply current as a function of data rate for ADuM1400/ADuM1401/ADuM1402 channel configurations.。
TA1310AN资料
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CC1310硬件射频：天线及网上资源的介绍
CC1310硬件射频：天线及网上资源的介绍
CC1310 属于德州仪器(TI) CC26xx 和CC13xx 系列器件中的经济高效型超低功耗 2.4GHz 和低于1GHz 的RF 器件。
™。
它具有极低的有源RF 和微控制器(MCU) 电流消耗，除了灵活的低功耗模式外，可确保卓越的电池使用寿命，适用于由小型纽扣电池供电的远距离操作以及能源采集型应用。
CC1310 是经济高效型、超低功耗无线MCU 中低于1GHz 系列的首款器件。
CC1310 器件在支持多个物理层和RF 标准的平台中将灵活的超低功耗RF 收发器和强大的48MHz Cortex®-M3 微控制器相结合。
专用无线控制器(Cortex®-M0) 处理ROM 或RAM 中存储的低层RF 协议命令，从而确保超低功耗和灵活度。
CC1310 器件不会以牺牲RF 性能为代价来实现低功耗；CC1310 器件具有出色的灵敏度和稳定性（可选择性和阻断）性能。
CC1310 器件是一款高度集成、真正的单片解决方案，其整合了一套完整的RF 系统及一个片上DC-DC 转换器。
传感器可由专用的超低功耗自主MCU 以超低功耗方式进行处理，该MCU 可配置为处理模拟和数字传感器，因此主MCU (Cortex-M3) 能够最大限度地延长休眠时间。
CC1310 电源和时钟管理以及无线系统需要采用特定配置并由软件处理才能正确运行，这一切均已在TI-RTOS 中实现。
TI 建议将此软件框架应用于针对器件的全部应用程序开发过程。
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Series H - Power Entry Modules
2
6
Faston, Straight 55.90 30.20 20.60 40.01 —
— CCM1607-ND
16.41 287.00
958.00
Series P, Chameleon — For General or Medical Applications (See chart for part number break down)
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Power Entry Modules (Cont.)
Rated Current Fig. 120V (Amps)
Termination
Dimensions (mm)
Digi-Key
A
B
C
D
E
F Part No.
Pricing
1
25
100
Series EJS — Enhanced Performance Snap-In Compact RFI Filter IEC Connector Package
EDP Series: These RFI power line filters provide enhanced differential-mode performance for applications requiring more line-to-line protection.
EJT Series: The EJT Series is a power inlet filter designed to attenuate noise up to 1 GHz. This inlet uses an IEC 320/C14 input connector. This product was designed to address the demand for more noise attenuation at higher frequencies in a compact inlet.
10A
6
10
10
6
6
6
Faston Faston Faston Faston Faston Faston
31.50 54.10 58.67 26.92 55.91 — CCM1378-ND 31.50 54.10 58.67 28.50 55.91 — CCM1379-ND 31.50 54.10 58.67 28.50 55.91 — CCM1380-ND 31.50 54.10 58.67 26.92 55.91 — CCM1381-ND 31.50 54.10 58.67 28.50 55.91 — CCM1382-ND 31.50 54.10 58.67 26.92 55.91 — CCM1600-ND
1
3
8
6
10
15
Straight Straight Straight Straight Straight
55.88 27.94 24.38 30.10 34.21 — CCM1252-ND 55.88 27.94 24.38 30.10 34.21 — CCM1253-ND 55.88 27.94 24.38 30.10 34.21 — CCM1254-ND 55.88 27.94 24.38 30.10 34.21 — CCM1255-ND 55.88 27.94 24.38 30.10 34.21 — CCM1256-ND
50.22 40.01 22.76 31.09
CCM1401-ND
30.40 — 22.66 30.61
CCM1402-ND
35.31 — 28.19 35.71
CCM1403-ND
50.01 40.01 29.31 35.71
CCM1404-ND
Pricing
1
25
100
3.23 56.50 189.00 2.35 41.00 137.00 2.47 43.00 144.00 2.86 50.00 167.00 2.86 50.00 167.00
1
16.17 28.90
54.62
20.92 24.40 24.40 31.02 30.50 33.99 30.11 26.14
4.82
Pricing
Corcom
25
100
Part No.
282.50 505.25
955.00
365.75 426.50 426.50 542.25 533.25 594.25 526.25 457.00
Rated Current 120V Fig. (Amps)
RFI Filter Type
Available
Voltage DPSTSel Nhomakorabeaction On/Off
Position Switch
A
Dimensions (mm)
B
C
DE
Digi-Key Part No.
Series J — Power Entry Modules
* Unfiltered † Utilizes 2 5x20 fuses
17.43 23.58 26.45 24.94
304.75 412.25 462.25 436.00
1018.00 1377.00 1544.00 1457.00
Corcom Part No.
1EJS1 3EJS1 6EJS1 10EJS1 15EJS1 20EJS1
6EH4
PS0SXS000 PS000S000 PS0S0SBX0 PS000SS3B PS0SXSS30 PS0SXSS60 PS0S0SSXA PS000SSXB PS0SXDS60 PS0S0SS6A PS0S0SS60 PE0SSS000 PE0SSSS60 PE0SSSSX0 PE0S0SS30
6
Unfiltered
4
11
6
Gen. Purpose
4
—
68.07 38.61 29.72 31.24 — CCM1200-ND
—
69.85 47.50 29.73 40.13 — CCM1201-ND
Series LA — Power Entry Modules
12
5
Gen. Purpose
2
—
EOP Series: A general purpose filter which is effective in removing both common and differential-mode noise for susceptibility applications.
EP Series: The EP/VP series of RFI filters has been developed to reduce conducted noise to acceptable limits for equipment that must comply with requirements of CISPAR in Europe and the FCC specifications in the USA.
Corcom Part No.
6ESRM-P 6ESRM-3 6ESRMC2 6ESRFC3 6ESRF-3
220-240
Fig. 11
C
D B
Fig. 12 A B
C
220-240
Fig. 13
A
DVE
D
C
D B A
Note: Picture shown with switch. Fig. 14
E
10
Faston
31.50 49.02 58.67 26.92 55.91 — CCM1372-ND*
16.38 286.25
956.00
10
Faston
31.50 49.02 58.67 26.92 55.91 — CCM1373-ND*
12.77 223.50
746.00
10
Faston
31.50 54.10 58.67 26.92 55.91 — CCM1374-ND
10B
D
6 10 3
Faston Faston Faston
50.29 50.29 50.29
54.10 54.10 54.10
58.67 58.67 58.67
28.50 28.50 28.50
55.91 55.91 55.91
40.01 40.01 40.01
CCM1383-ND CCM1384-ND CCM1385-ND
19.53 341.50 1141.00
3
Faston
31.50 54.10 58.67 28.50 55.91 — CCM1376-ND
24.35 425.50 1422.00
3
Faston
31.50 54.10 58.67 26.92 55.91 — CCM1377-ND
23.89 417.75 1395.00
MA604
Rated Current 125V Fig. (Amps)
15
15
15
15
15
15
Output Terminals
Mounting Input Style Config.
PC Terminals Quick Disconnect Quick Disconnect Quick Disconnect Quick Disconnect
Flange Flange Snap-In Snap-In Flange
Male Male Male Female Female
Dimensions (mm)