FPGA可编程逻辑器件芯片EP2AGX95EF35I3N中文规格书

CLK (p/n Pins)
Clock Resources
4
5
6
7
8
9
10 11 12 13 14 15
GCLK[0..3] (1) — — — — — — — — — — — —
GCLK[4..7]
v v v v— — — — — — — —
GCLK[8..11]
————
v v v v— — — —
Table 5–3. Clock Input Pin Connectivity to the GCLK Networks for Arria II GZ Devices (Part 1 of 2)
Clock Resources
GCLK[0..3] GCLK[4..7]
CLK (p/n Pins)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 v v v v— — — — — — — — — — — — — — — — v v v v— — — — — — — —
Logic Array Blocks
You can drive up to four signals into each GCLK and RCLK network with logic array block (LAB)-routing to allow internal logic to drive a high fan-out, low-skew signal.
1 You cannot drive Arria II PLLs by internally generated GCLKs or RCLKs. The input clock to the PLL has to come from dedicated clock input pins or PLL-fed GCLKs and RCLKs only.
RCLK [15, 19, 25, 29] — — — — — — v — — — — — — — — — RCLK [14, 18, 24, 28] — — — — — — — v — — — — — — — —
RCLK [35, 41]
— — — — — — — — v — — — — ———
RCLK [34, 40]
RCLK [46, 50, 56, 60] — — — — — — — — — — — — — v — —
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5: Clock Networks and PLLs in Arria II Devices Clock Networks in Arria II Devices
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 — — — — — — — — v v v v— — — — — ——— —— —— —— —— vvvv
Table 5–4 and Table 5–5 list the connectivity between the dedicated clock input pins and RCLKs in Arria II devices. A given clock input pin can drive two adjacent RCLK networks to create a dual-RCLK network.
PLL Clock Outputs
Table 5–2 and Table 5–3 list the connection between the dedicated clock input pins and GCLKs.
Table 5–2. Clock Input Pin Connectivity to GCLK Networks for Arria II GX Devices
Clock Resource RCLK [0, 4, 6, 10]
CLK (p/n Pins) 0 1 2 3 4 5 6 7 8 9 10 11 12 v— — — — — — — — — — — —
13 14 15 ———
RCLK [1, 5, 7, 11]
— v — — — — — — — — — — — ———
B2
R2
R3
T1
T2
GCLK[0..3]
v
v—
—
—
—
—
—
GCLK[4..7]
—
—
v
v
—
—
—
—
GCLK[8..11]
—
—
—
—
v
v
—
—
GCLK[12..15]
—
—
—
—
—
—
v
v
Note to Table 5–9: (1) Only PLL counter outputs C0 - C3 can drive the GCLK networks.
Clock Output Connections
PLLs in Arria II GX devices can drive up to 24 RCLK networks and eight GCLK networks, while PLLs in Arria II GZ devices can drive up to 20 RCLK networks and four GCLK networks. The Quartus II software automatically assigns PLL clock outputs to RCLK or GCLK networks.
Table 5–3. Clock Input Pin Connectivity to the GCLK Networks for Arria II GZ Devices (Part 2 of 2)
Clock Resources
GCLK[8..11] GCLK[12..15]
CLK (p/n Pins)
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5: Clock Networks and PLLs in Arria II Devices Clock Networks in Arria II Devices
Table 5–4. Clock Input Pin Connectivity to RCLK Networks for Arria II GX Devices
Clock Resource
RCLK [12, 14, 16, 18, 20, 22] RCLK [13, 15, 17, 19, 21, 23] RCLK [24..35] RCLK [36, 38, 40, 42, 44, 46] RCLK [37, 39, 41, 43, 45, 47]
— — — — — — — — — v — — — ———
RCLK [33, 37, 39, 43] — — — — — — — — — — v — — — — —
RCLK [32, 36, 38, 42] — — — — — — — — — — — v — — — —
RCL— — — v — — —
Clock Network Sources
In Arria II GX devices, clock input pins, internal logic, transceiver clocks, and PLL outputs can drive the GCLK and RCLK networks, while in Arria II GZ devices, clock input pins, PLL outputs, and internal logic can drive the GCLK and RCLK networks. Table 5–2 through Table 5–5 on page 5–13 list the connectivity between the dedicated clock pins and the GCLK and RCLK networks.
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Chapter 5: Clock Networks and PLLs in Arria II Devices Clock Networks in Arria II Devices
RCLK [2, 8]
— — v — — — — — — — — — — ———
RCLK [3, 9]
— — — v — — — — — — — — — ———
RCLK [13, 17, 21, 23, — — — — v — — — — — — — — — — — 27, 31]
RCLK [12, 16, 20, 22, — — — — — v — — — — — — — — — — 26, 30]
PLL Number
1
2
3
4
5
6
v
—
—
v
—
—
—
—
v
v
—
—
—
v
v
—
v
v
v
v
—
—
—
—
Table 5–9. PLL Connectivity to the GCLK Networks for Arria II GZ Devices (Note 1)
Clock Network