L816BSRC中文资料

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OCP8166 最新资料(2014版)

VCC=12V ‐20℃ 0℃ 25℃ 50℃ 85℃
Temperature(℃)
LED Current (mA)
315.0 313.0 311.0 309.0 307.0 305.0 303.0 301.0 299.0 297.0 295.0
85
LED Current vs Linear Voltage
芯片 ISEN 脚采样变压器原边的电流峰值，芯片内部对由于 MOS 管关断延迟造成的原边电流过冲进行了补偿。
OCP8166 提供多种保护，诸如 LED 短路保护（SCP）,LED 开路保护（OLP），ZCD 过压， VIN 过压和欠压，芯片过温保护（OTP）,和高温 LED 电流补偿等等。
RDS(ON) BVDSS
IDSS 保护
MOSFET 开启电阻 MOSFET 击穿电压
MOSFET 漏电
VGATE_H
VIN 及 GATE 脚电压钳位
TRESET
系统重启延迟时间
TSD
过温保护温度
TSDHS
过温保护解除迟滞
T80%
80%电流温度
注: 1, 设计保证
条件
VIN 上升 VIN 下降通过欠压实现
范围
单位
VIN脚对GND电压
VIN
+9.0 to +20
V
最大输出电流
ILED
250
mA
最大输出功率
85~265VAC 220VAC±15%
POMAX
12 18
W W
工作温度范围
TOP
-40 to +85
℃
最大热阻
SOP-8L
ΘJA

FM24CL16B中文资料

•
198 Champion Court
•
San Jose, CA 95134-1709
• 408-943-2600 Revised April 21, 2014
FM24CL16B
Contents
Pinouts .............................................................................. 3 Pin Definitions .................................................................. 3 Overview............................................................................ 4 Memory Architecture........................................................ 4 I2C Interface ...................................................................... 4 STOP Condition (P)..................................................... 4 START Condition (S)................................................... 4 Data/Address Transfer ................................................ 5 Acknowledge / No-acknowledge ................................. 5 Slave Device Address ................................................. 6 Addressing Overview (Word Address) ........................ 6 Data Transfer .............................................................. 6 Memory Operation............................................................ 6 Write Operation ........................................................... 6 Read Operation ........................................................... 7 Endurance ......................................................................... 8 Maximum Ratings............................................................. 9 Operating Range............................................................... 9 DC Electrical Characteristics .......................................... 9 Data Retention and Endurance ..................................... 10 Capacitance .................................................................... Thermal Resistance........................................................ AC Test Loads and Waveforms..................................... AC Test Conditions ........................................................ AC Switching Characteristics ....................................... Power Cycle Timing ....................................................... Ordering Information...................................................... Ordering Code Definitions ......................................... Package Diagrams.......................................................... Acronyms ........................................................................ Document Conventions ................................................. Units of Measure ....................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC® Solutions ...................................................... Cypress Developer Community................................. Technical Support ..................................................... 10 10 10 10 11 12 13 13 14 16 16 16 17 18 18 18 18 18 18FM2 NhomakorabeaCL16B

恒星芯片B4161A 2.4GHz 19dBm无线芯片板文档说明书

EFR32MG12 2.4 GHz 19 dBm Radio Board BRD4161A Reference ManualRADIO BOARD FEATURES•Wireless SoC:EFR32MG12P432F1024GL125•CPU core: ARM Cortex ®-M4 with FPU •Flash memory: 1024 kB •RAM: 256 kB•Operation frequency: 2.4 GHz •Transmit power: 19 dBm•Integrated PCB antenna, UFL connector (optional).•Touch Slider•Crystals for LFXO and HFXO: 32.768 kHz and 38.4 MHz.The BRD4161A Mighty Gecko Radio Board enables developers to develop Zigbee ®, Thread,Bluetooth ® low energy and proprietary wireless applications. The board con-tains a Mighty Gecko Wireless System on Chip 2.4 GHz and optimized for operation with 19 dBm output power. With the on-board printed antenna and RF connector radi-ated and conducted testing is supported.The BRD4161A Mighty Gecko Radio Board plugs into the Wireless Starter Kit Main-board provided with the Mighty Gecko Starter Kit to get access to display, buttons and additional features from Expansion Boards. With the supporting Simplicity Studio suite of tools, developers can take advantage of graphical wireless application development; mesh networking debug and packet trace; and visual energy profiling and optimization. The board also serves as an RF reference design for applications targeting 2.4 GHz wireless operation with 19 dBm output power.This document contains brief introduction and description of the BRD4161A Radio Board features focusing on the RF sections and performance.| Smart. Connected. Energy-friendly.Rev. 1.00Introduction 1. IntroductionThe EFR32 Mighty Gecko Radio Boards provide a development platform (together with the Wireless Starter Kit Mainboard) for the Silicon Labs EFR32 Mighty Gecko Wireless System on Chips and serve as reference designs for the matching network of the RF inter-face.The BRD4161A Radio Board is designed to operate in the 2400-2483.5 MHz band with the RF matching network optimized to operate with 19 dBm output power.To develop and/or evaluate the EFR32 Mighty Gecko, the BRD4161A Radio Board can be connected to the Wireless Starter Kit Main-board to get access to display, buttons and additional features from Expansion Boards and also to evaluate the performance of the RF interface.2. Radio Board Connector2.1 IntroductionThe board-to-board connector scheme allows access to all EFR32MG12 GPIO pins as well as the RESETn signal. For more informa-tion on the functions of the available pin functions, see the EFR32MG12 data sheet.2.2 Radio Board Connector Pin AssociationsThe figure below shows the pin mapping on the connector to the radio pins and their function on the Wireless Starter Kit Mainboard.GNDF9 / PA3 / VCOM_RTS 3v3VCOM_RTS / PA3 / P36P200Upper RowNC / P38NC / P40PF9 / P42PF11 / P44DEBUG.TMS_SWDIO / PF1 / F0DISP_ENABLE / PD15 / F14UIF_BUTTON0 / PF6 / F12UIF_LED1 / PF4 / F10VCOM_CTS / PA2 / F8DEBUG.RESET / RADIO_#RESET / F4DEBUG.TDO_SWO / PF2 / F2DISP_SI / PC6 / F16VCOM_TXD / PA0 / F6PTI_DATA / PB12 / F20DISP_EXTCOMIN / PD13 / F18USB_VBUS5VBoard ID SCLGNDBoard ID SDAUSB_VREG F7 / PA1 / VCOM_RXD F5 / PA5 / VCOM_ENABLE F3 / PF3 / DEBUG.TDIF1 / PF0 / DEBUG.TCK_SWCLK P45 / PF12P43 / PF10P41 / PF8P39 / NC P37/ PB10 / SENSOR_ENABLE F11 / PF5 / UIF_LED1F13 / PF7 / UIF_BUTTON1F15 / PC8 / DISP_SCLK F17 / PD14 / DISP_SCS F19 / PB13 / PTI_FRAME F21 / PB11 / PTI_CLK GND VMCU_IN PD8 / P0P201Lower RowPD9 / P2PD10 / P4PD11 / P6GNDNCP35 / PA2 / VCOM_CTS P7 / PA9P5 / PA8P3 / PA7P1 / PA6P33 / PA0 / VCOM_TXD P31 / PK2P29 / PK0P27 / PJ14P25 / PI2P23 / PI0P21 / PF14P19 / NC P17 / PC5P15 / PB9P13 / PC11P11 / PB7P9 / PB6VCOM_RXD / P34 / P34BODEN / P32PK1/ P30PJ15 / P28PI3 / P26PI1 / P24PF15 / P22PF13 / P20NC / P18PC4 / P16PB8 / P14PC10 / P12PC9 / P10PD12 / P8Figure 2.1. BRD4161A Radio Board Connector Pin MappingRadio Board Connector3. Radio Board Block Summary3.1 IntroductionThis section gives a short introduction to the blocks of the BRD4161A Radio Board.3.2 Radio Board Block DiagramThe block diagram of the EFR32MG Radio Board is shown in the figure below.Figure 3.1. BRD4161A Block Diagram3.3 Radio Board Block Description3.3.1 Wireless MCUThe BRD4161A Mighty Gecko Radio Board incorporates an EFR32MG12P432F1024GL125 Wireless System on Chip featuring 32-bit Cortex®-M4 with FPU core, 1024 kB of flash memory and 256 kB of RAM and a 2.4 GHz band transceiver with output power up to 19 dBm. For additional information on the EFR32MG12P432F1024GL125, refer to the EFR32MG12 Data Sheet.3.3.2 LF Crystal Oscillator (LFXO)The BRD4161A Radio Board has a 32.768 kHz crystal mounted.3.3.3 HF Crystal Oscillator (HFXO)The BRD4161A Radio Board has a 38.4 MHz crystal mounted.| Smart. Connected. Energy-friendly.Rev. 1.00 | 33.3.4 Matching Network for 2.4 GHzThe BRD4161A Radio Board incorporates a 2.4 GHz matching network which connects the 2.4 GHz TRX pin of the EFR32MG12 to the one on-board printed Inverted-F antenna. The component values were optimized for the 2.4 GHz band RF performace and current con-sumption with 19 dBm output power.For detailed description of the matching network, see Chapter 4.2.1 Description of the 2.4 GHz RF Matching.3.3.5 Inverted-F AntennaThe BRD4161A Radio Board includes a printed Inverted-F antenna (IFA) tuned to have close to 50 Ohm impedance at the 2.4 GHz band.For detailed description of the antenna see Chapter 4.5 Inverted-F Antenna.3.3.6 UFL ConnectorTo be able to perform conducted measurements, Silicon Labs added an UFL connector to the Radio Board. The connector allows an external 50 Ohm cable or antenna to be connected during design verification or testing.Note: By default the output of the matching network is connected to the printed Inverted-F antenna by a series component. It can be connected to the UFL connector as well through a series 0 Ohm resistor which is not mounted by default. For conducted measurements through the UFL connector the series component to the antenna should be removed and the 0 Ohm resistor should be mounted (see Chapter 4.2 Schematic of the RF Matching Network for further details).3.3.7 Radio Board ConnectorsTwo dual-row, 0.05” pitch polarized connectors make up the EFR32MG Radio Board interface to the Wireless Starter Kit Mainboard. For more information on the pin mapping between the EFR32MG12P432F1024GL125 and the Radio Board Connector, refer to Chapter 2.2 Radio Board Connector Pin Associations.3.3.8 Capacitive Touch SliderThe touch slider (T2) utilizes the capacitive touch capability of the Capacitance Sense Module of the EFR32MG12. The slider interpo-lates 4 separate pads to find the exact position of a finger.The figure below shows the pin mapping of the touch slider to the Wireless SoC.Wireless SoCFigure 3.2. Touch Slider Pin MappingRev. 1.00 | 44. RF Section4.1 IntroductionThis section gives a short introduction to the RF section of the BRD4161A.4.2 Schematic of the RF Matching NetworkThe schematic of the RF section of the BRD4161A Radio Board is shown in the following figure.2.4 GHz Matching 2.4 GHz RF OutputSelection & Inverted-F AntennaFigure 4.1. Schematic of the RF Section of the BRD4161A4.2.1 Description of the 2.4 GHz RF MatchingThe 2.4 GHz matching connects the 2G4RF_IOP pin to the on-board printed Inverted-F Antenna. The 2G4RF_ION pin is connected to ground. For higher output powers (13 dBm and above), besides the impedance matching circuitry, it is recommended to use additional harmonic filtering as well at the RF output. The targeted output power of the BRD4161A board is 19 dBm. Therefore, the RF output of the IC is connected to the antenna through a four-element impedance matching and harmonic filter circuitry.For conducted measurements the output of the matching network can also be connected to the UFL connector by removing the series R1 component between the antenna and the output of the matching and adding a 0 Ohm resistor to the R2 resistor position between the output of the matching and the UFL connector.4.3 RF Section Power SupplyOn the BRD4161A Radio Board the power supply pins of the RF section (RFVDD, PAVDD) are directly connected to the output of the on-chip DC-DC converter. This way, by default, the DC-DC converter provides 1.8 V for the entire RF section (for details, see the sche-matic of the BRD4161A).4.4 Bill of Materials for the 2.4 GHz MatchingThe Bill of Materials of the 2.4 GHz matching network of the BRD4161A Radio Board is shown in the following table.| Smart. Connected. Energy-friendly.Rev. 1.00 | 5Table 4.1. Bill of Materials for the BRD4161A 2.4GHz RF Matching Network4.5 Inverted-F AntennaThe BRD4161A Radio Board includes an on-board printed Inverted-F Antenna tuned for the 2.4 GHz band. Due to the design restric-tions of the Radio Board, the input of the antenna and the output of the matching network can't be placed directly next to each other. As a result, a 50 Ohm transmission line was necessary to connect them. With the actual line length the impedance of the antenna at the double-harmonic frequency is transformed closer to a "critical load impedance range" resulting in the radiated level of the harmonic increases.To reduce the harmonic radiation a tuning component was used between the matching network output and the antenna input. For the actual Radio Board design (with the actual transmission line length) a small value inductor was used (instead of the R1 resistor with value of 1.8 nH) to transform the impedance at the double-frequency harmonic away from the critical region while keeping the impe-dance at the funamental close to 50 Ohm. With this the suppression of the radiated double-frequency harmonic increases by approxi-mately 3-4 dB. The resulting impedance and reflection measured at the output of the matcing network are shown in the following figure. As it can be observed the impedance is close to 50 Ohm (the reflection is better than -10 dB) for the entire 2.4 GHz band.Figure 4.2. Impedance and Reflection of the Inverted-F Antenna of the BRD4161A Board Measured from the Matching Output Note: The same value and type of 1.8 nH inductor was used as the one in the matching network (L1). | Smart. Connected. Energy-friendly.Rev. 1.00 | 65. Mechanical DetailsThe BRD4161A Mighty Gecko Radio Board is illustrated in the figures below.Figure 5.1. BRD4161A Top View24 mmConnectorConnector Figure 5.2. BRD4161A Bottom ViewMechanical DetailsRev. 1.00 | 7EMC Compliance 6. EMC Compliance6.1 IntroductionCompliance of the fundamental and harmonic levels is tested against the following standards:• 2.4 GHz:•ETSI EN 300-328•FCC 15.2476.2 EMC Regulations for 2.4 GHz6.2.1 ETSI EN 300-328 Emission Limits for the 2400-2483.5 MHz BandBased on ETSI EN 300-328 the allowed maximum fundamental power for the 2400-2483.5 MHz band is 20 dBm EIRP. For the unwan-ted emissions in the 1 GHz to 12.75 GHz domain the specified limit is -30 dBm EIRP.6.2.2 FCC15.247 Emission Limits for the 2400-2483.5 MHz BandFCC 15.247 allows conducted output power up to 1 Watt (30 dBm) in the 2400-2483.5 MHz band. For spurious emmissions the limit is -20 dBc based on either conducted or radiated measurement, if the emission is not in a restricted band. The restricted bands are speci-fied in FCC 15.205. In these bands the spurious emission levels must meet the levels set out in FCC 15.209. In the range from 960 MHz to the frequency of the 5th harmonic it is defined as 0.5 mV/m at 3 m distance (equals to -41.2 dBm in EIRP).Additionally, for spurious frequencies above 1 GHz, FCC 15.35 allows duty-cycle relaxation to the regulatory limits. For the EmberZNet PRO the relaxation is 3.6 dB. Therefore, the -41.2 dBm limit can be modified to -37.6 dBm.If operating in the 2400-2483.5 MHz band the 2nd, 3rd and 5th harmonics can fall into restricted bands. As a result, for those the -37.6 dBm limit should be applied. For the 4th harmonic the -20 dBc limit should be applied.6.2.3 Applied Emission Limits for the 2.4 GHz BandThe above ETSI limits are applied both for conducted and radiated measurements.The FCC restricted band limits are radiated limits only. Besides that, Silicon Labs applies those to the conducted spectrum i.e., it is assumed that, in case of a custom board, an antenna is used which has 0 dB gain at the fundamental and the harmonic frequencies. In that theoretical case, based on the conducted measurement, the compliance with the radiated limits can be estimated.The overall applied limits are shown in the table below.Table 6.1. Applied Limits for Spurious Emissions for the 2.4 GHz Band | Smart. Connected. Energy-friendly.Rev. 1.00 | 87. RF Performance7.1 Conducted Power MeasurementsDuring measurements, the EFR32MG Radio Board was attached to a Wireless Starter Kit Mainboard which was supplied by USB. The voltage supply for the Radio Board was 3.3 V.7.1.1 Conducted Measurements in the 2.4 GHz bandThe BRD4161A board was connected directly to a Spectrum Analyzer through its UFL connector (the R1 component was removed and a 0 Ohm resistor was soldered to the R2 resistor position). During measurements, the voltage supply for the board was 3.3 V provided by the mainboard. The supply for the radio (RFVDD) was 1.8 V provided by the on-chip DC-DC converter, the supply for the power amplifier (PAVDD) was 3.3 V (for details, see the schematic of the BRD4161A). The transceiver was operated in continuous carrier transmission mode. The output power of the radio was set to 19 dBm.The typical output spectrum is shown in the following figure.Figure 7.1. Typical Output Spectrum of the BRD4161AAs it can be observed, the fundamental is slightly lower than 19 dBm limit and the strongest unwanted emission is the double-frequency harmonic and it is under the -37.6 dBm applied limit.Note: The conducted measurement is performed by connecting the on-board UFL connector to a Spectrum Analyzer through an SMA Conversion Adapter (P/N: HRMJ-U.FLP(40)). This connection itself introduces approximately 0.3 dB insertion loss.RF PerformanceRev. 1.00 | 97.2 Radiated Power MeasurementsDuring measurements, the EFR32MG Radio Board was attached to a Wireless Starter Kit Mainboard which was supplied by USB. The voltage supply for the Radio Board was 3.3 V. The radiated power was measured in an antenna chamber by rotating the DUT 360degrees with horizontal and vertical reference antenna polarizations in the XY , XZ and YZ cuts. The measurement axes are shown inthe figure below.Figure 7.2. DUT: Radio Board with the Wireless Starter Kit Mainboard (Illustration)Note: The radiated measurement results presented in this document were recorded in an unlicensed antenna chamber. Also the radi-ated power levels may change depending on the actual application (PCB size, used antenna, and so on). Therefore, the absolute levels and margins of the final application are recommended to be verified in a licensed EMC testhouse.7.2.1 Radiated Measurements in the 2.4 GHz bandFor the transmitter antenna the on-board printed Inverted-F antenna of the BRD4161A board was used (the R1 component was moun-ted). During measurements, the board was attached to a Wireless Starter Kit Mainboard (BRD4001 (Rev. A02) ) which was supplied through USB. During the measurements the voltage supply for the board was 3.3 V provided by the mainboard. The supply for the radio (RFVDD) was 1.8 V provided by the on-chip DC-DC converter, the supply for the power amplifier (PAVDD) was 3.3 V (for details, see the schematic of the BRD4161A). The transceiver was operated in continuous carrier transmission mode. The output power of the radio was set to 19 dBm based on the conducted measurement.The results are shown in the table below.Table 7.1. Maximums of the measured radiated powers in EIRP [dBm]As it can be observed, thanks to the high gain of the Inverted-F antenna, the level of the fundamental is higher than 19 dBm. The stron-gest harmonic is the double-frequency one and thanks to the additional suppression provided by the instead of the R1 resistor its level is under -50 dBm.RF PerformanceEMC Compliance Recommendations 8. EMC Compliance Recommendations8.1 Recommendations for 2.4 GHz ETSI EN 300-328 complianceAs it was shown in the previous chapter, the radiated power of the fundamental of the BRD4161A Mighty Gecko Radio Board complies with the 20 dBm limit of the ETSI EN 300-328 in case of the conducted measurement but due to the high antenna gain the radiated power is higher than the limit by 2 dB. In order to comply, the output power should be reduced (with different antennas, depending on the gain of the used antenna, the necessary reduction can be different). The harmonic emissions are under the -30 dBm limit. Although the BRD4161A Radio Board has an option for mounting a shielding can, that is not required for the compliance.8.2 Recommendations for 2.4 GHz FCC 15.247 complianceAs it was shown in the previous chapter, the radiated power of the fundamental of the BRD4161A Mighty Gecko Radio Board complies with the 30 dBm limit of the FCC 15.247. The harmonic emissions are under the -37.6 dBm applied limit both in case of the conducted and the radiated measurements. Although the BRD4161A Radio Board has an option for mounting a shielding can, that is not required for the compliance.Document Revision History 9. Document Revision HistoryTable 9.1. Document Revision HistoryBoard Revision History 10. Board Revision HistoryTable 10.1. BRD4161A Radio Board RevisionsErrata 11. ErrataThere are no known errata at present.Table of Contents1. Introduction (1)2. Radio Board Connector (2)2.1 Introduction (2)2.2 Radio Board Connector Pin Associations (2)3. Radio Board Block Summary (3)3.1 Introduction (3)3.2 Radio Board Block Diagram (3)3.3 Radio Board Block Description (3)3.3.1 Wireless MCU (3)3.3.2 LF Crystal Oscillator (LFXO) (3)3.3.3 HF Crystal Oscillator (HFXO) (3)3.3.4 Matching Network for 2.4 GHz (4)3.3.5 Inverted-F Antenna (4)3.3.6 UFL Connector (4)3.3.7 Radio Board Connectors (4)3.3.8 Capacitive Touch Slider (4)4. RF Section (5)4.1 Introduction (5)4.2 Schematic of the RF Matching Network (5)4.2.1 Description of the 2.4 GHz RF Matching (5)4.3 RF Section Power Supply (5)4.4 Bill of Materials for the 2.4 GHz Matching (5)4.5 Inverted-F Antenna (6)5. Mechanical Details (7)6. EMC Compliance (8)6.1 Introduction (8)6.2 EMC Regulations for 2.4 GHz (8)6.2.1 ETSI EN 300-328 Emission Limits for the 2400-2483.5 MHz Band (8)6.2.2 FCC15.247 Emission Limits for the 2400-2483.5 MHz Band (8)6.2.3 Applied Emission Limits for the 2.4 GHz Band (8)7. RF Performance (9)7.1 Conducted Power Measurements (9)7.1.1 Conducted Measurements in the 2.4 GHz band (9)7.2 Radiated Power Measurements (10)7.2.1 Radiated Measurements in the 2.4 GHz band (10)8. EMC Compliance Recommendations (11)8.1 Recommendations for 2.4 GHz ETSI EN 300-328 compliance (11)8.2 Recommendations for 2.4 GHz FCC 15.247 compliance (11)9. Document Revision History (12)10. Board Revision History (13)11. Errata (14)Table of Contents (15)Silicon Laboratories Inc.400 West Cesar Chavez Austin, TX 78701USASimplicity StudioOne-click access to MCU and wireless tools, documentation, software, source code libraries & more. Available for Windows, Mac and Linux!IoT Portfolio /IoTSW/HW/simplicityQuality/qualitySupport and CommunityDisclaimerSilicon Labs intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Labs products. Characterization data, available modules and peripherals, memory sizes and memory addresses refer to each specific device, and "Typical" parameters provided can and do vary in different applications. Application examples described herein are for illustrative purposes only. Silicon Labs reserves the right to make changes without further notice and limitation to product information, specifications, and descriptions herein, and does not give warranties as to the accuracy or completeness of the included information. Silicon Labs shall have no liability for the consequences of use of the information supplied herein. This document does not imply or express copyright licenses granted hereunder to design or fabricate any integrated circuits. The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Labs. A "Life Support System" is any product or system intended to support or sustain life and/or health, which, if it fails, can be reasonably expected to result in significant personal injury or death. Silicon Labs products are not designed or authorized for military applications. Silicon Labs products shall under no circumstances be used in weapons of mass destruction including (but not limited to) nuclear, biological or chemical weapons, or missiles capable of delivering such weapons.Trademark InformationSilicon Laboratories Inc.® , Silicon Laboratories®, Silicon Labs®, SiLabs® and the Silicon Labs logo®, Bluegiga®, Bluegiga Logo®, Clockbuilder®, CMEMS®, DSPLL®, EFM®, EFM32®, EFR, Ember®, Energy Micro, Energy Micro logo and combinations thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZRadio®, EZRadioPRO®, Gecko®, ISOmodem®, Precision32®, ProSLIC®, Simplicity Studio®, SiPHY®, Telegesis, the Telegesis Logo®, USBXpress® and others are trademarks or registered trademarks of Silicon Labs. ARM, CORTEX, Cortex-M3 and THUMB are trademarks or registered trademarks of ARM Holdings. Keil is a registered trademark of ARM Limited. All other products or brand names mentioned herein are trademarks of their respective holders.。

LH28F640BFN-PTTLZ2资料

• Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company.• When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions.(1) The products covered herein are designed and manufactured for the following application areas. When using theproducts covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph(3).• Office electronics• Instrumentation and measuring equipment• Machine tools• Audiovisual equipment• Home appliance• Communication equipment other than for trunk lines(2) Those contemplating using the products covered herein for the following equipment which demands highreliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system.• Control and safety devices for airplanes, trains, automobiles, and other transportation equipment• Mainframe computers• Traffic control systems• Gas leak detectors and automatic cutoff devices• Rescue and security equipment• Other safety devices and safety equipment, etc.(3) Do not use the products covered herein for the following equipment which demands extremely high performancein terms of functionality, reliability, or accuracy.• Aerospace equipment• Communications equipment for trunk lines• Control equipment for the nuclear power industry• Medical equipment related to life support, etc.(4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a salesrepresentative of the company.• Please direct all queries regarding the products covered herein to a sales representative of the company.PAGE 44-Lead SOP Pinout (3)Pin Descriptions (4)Memory Map (5)Identifier Codes and OTP Addressfor Read Operation (6)OTP Block Address Map for OTP Program (7)Bus Operation (8)Command Definitions (9)Functions of Block Lock and Block Lock-Down (11)Block Locking State Transitions uponCommand Write (11)Status Register Definition (12)Extended Status Register Definition (13)PAGE 1 Electrical Specifications (14)1.1 Absolute Maximum Ratings (14)1.2 Operating Conditions (14)1.2.1 Capacitance (15)1.2.2 AC Input/Output Test Conditions (15)1.2.3 DC Characteristics (16)1.2.4 AC Characteristics- Read-Only Operations (17)1.2.5 AC Characteristics- Write Operations (20)1.2.6 Reset Operations (22)1.2.7 Block Erase, Full Chip Erase,(Page Buffer) Program andOTP Program Performance (23)2 Related Document Information (24)CONTENTSLH28F640BFN-PTTLZ2 64Mbit (4Mbit×16) Page Mode Flash MEMORY64M density with 16Bit I/O InterfaceHigh Performance Reads• 90/35ns 8-Word Page ModeLow Power Operation• 2.7V Read and Write Operations• Automatic Power Savings Mode Reduces I CCRin Static ModeEnhanced Code + Data Storage• 5µs Typical Erase/Program SuspendsOTP (One Time Program) Block• 4-Word Factory-Programmed Area• 4-Word User-Programmable AreaHigh Performance Program with Page Buffer• 16-Word Page BufferOperating Temperature 0°C to +70°CFlexible Blocking Architecture• Eight 4K-word Parameter Blocks• One-hundred and twenty-seven 32K-word Main Blocks• Top Parameter LocationCMOS Process (P-type silicon substrate) Enhanced Data Protection Features• Individual Block Lock and Block Lock-Down with Zero-Latency• All blocks are locked at power-up or device reset.• Block E rase, Full Chip E rase, (Page Buffer) Word Program Lockout during Power TransitionsAutomated Erase/Program Algorithms• 3.0V Low-Power 11µs/Word (Typ.)ProgrammingCross-Compatible Command Support• Basic Command Set• Common Flash Interface (CFI)Extended Cycling Capability• Minimum 100,000 Block Erase Cycles44-Lead SOPETOX TM* Flash TechnologyNot designed or rated as radiation hardenedThe product, which is Page Mode Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at V CC=2.7V-3.6V. Its low voltage operation capability greatly extends battery life for portable applications.The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states.The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage.Fast program capability is provided through the use of high speed Page Buffer Program.Special OTP (One Time Program) block provides an area to store permanent code such as a unique number.* ETOX is a trademark of Intel Corporation.Table 1.Pin DescriptionsSymbol Type Name and FunctionA0-A21INPUT ADDRESS INPUTS: Inputs for addresses. 64M: A0-A21DQ0-DQ15INPUT/OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code and identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle.CE#INPUT CHIP ENABLE: Activates the device’s control logic, input buffers, decoders and sense amplifiers. CE#-high (V IH) deselects the device and reduces power consumption to standby levels.RST#INPUT RESET: When low (V IL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (V IH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down.OE#INPUT OUTPUT ENABLE: Gates the device’s outputs during a read cycle.WE#INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first).V CC SUPPLY DE VICE POWE R SUPPLY (2.7V-3.6V): With V CC≤V LKO, all write attempts to the flash memory are inhibited. Device operations at invalid V CC voltage (see DC Characteristics) produce spurious results and should not be attempted.GND SUPPLY GROUND: Do not float any ground pins.NOTES:1. Top parameter device has its parameter blocks at the highest address.2. DQ 15-DQ 2 are reserved for future implementation.3. OTP-LK=OTP Block Lock configuration.4. OTP=OTP Block data.Table 2.Identifier Codes and OTP Address for Read OperationCodeAddress [A 21-A 0]Data [DQ 15-DQ 0]NotesManufacturer Code Manufacturer Code 000000H 00B0H Device CodeTop Parameter Device Code 000001H 00B0H 1Block Lock Configuration CodeBlock is Unlocked Block Address + 2DQ 0 = 02Block is LockedDQ 0 = 12Block is not Locked-Down Block Address + 2DQ 1 = 02Block is Locked-DownDQ 1 = 12OTPOTP Lock000080HOTP-LK 3OTP 000081-000088HOTP4NOTES:1. See DC Characteristics for V IL or V IH voltages.2. X can be V IL or V IH for control pins and addresses.3. RST# at GND±0.2V ensures the lowest power consumption.4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when V CC =2.7V-3.6V.5. Refer to Table 4 for valid D IN during a write operation.6. Never hold OE# low and WE# low at the same timing.7. Refer to Appendix of LH28F640BF series for more information about query code.Table 3.Bus Operation (1, 2)Mode Notes RST#CE#OE#WE#Address DQ 0-15Read Array 6V IH V IL V IL V IH X D OUT Output Disable V IH V IL V IH V IH X High Z Standby V IH V IH X X X High Z Reset3V IL X X X X High Z Read Identifier Codes/OTP 6V IH V IL V IL V IH See Table 2See Table 2Read Query 6,7V IH V IL V IL V IH See AppendixSee Appendix Write4,5,6V IHV ILV IHV ILXD INNOTES:1. Bus operations are defined in Table 3.2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle.X=Any valid address within the device.IA=Identifier codes address (See Table 2).QA=Query codes address. Refer to Appendix of LH28F640BF series for details.BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.OA=Address of OTP block to be read or programmed (See Figure 3).3. ID=Data read from identifier codes. (See Table 2).QD=Data read from query database. Refer to Appendix of LH28F640BF series for details.SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits.WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.OD=Data within OTP block. Data is latched on the rising edge of WE# or CE# (whichever goes high first) during command write cycles.N-1=N is the number of the words to be loaded into a page buffer.4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, and the data within OTP block (See Table 2).The Read Query command is available for reading CFI (Common Flash Interface) information.5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is V IH .6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup.7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of LH28F640BF series for details.8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be acceptedTable mand Definitions (10)CommandBusCycles Req ’d Notes First Bus CycleSecond Bus Cycle Oper (1)Addr (2)Data Oper (1)Addr (2)Data (3)Read Array1Write X FFH Read Identifier Codes/OTP ≥ 24Write X 90H Read IA or OA ID or OD Read Query ≥ 24Write X 98H Read QA QD Read Status Register 211Write BA or WA70H ReadBA or WASRDClear Status Register 1Write X 50H Block Erase 25Write BA 20H Write BA D0H Full Chip Erase 25,8Write X 30H Write X D0H Program25,6Write WA 40H or 10H Write WA WD Page Buffer Program ≥ 45,7Write WA E8H WriteWAN-1Block Erase and (Page Buffer) Program Suspend18Write BA or WA B0H Block Erase and (Page Buffer) Program Resume 18Write BA or WA D0H Set Block Lock Bit 2Write BA 60H Write BA 01H Clear Block Lock Bit 29Write BA 60H Write BA D0H Set Block Lock-down Bit 2Write BA 60H Write BA 2FH OTP Program28WriteOAC0HWriteOAODwhile the block erase operation is being suspended.9. Following the Clear Block Lock Bit command, the selected block is unlocked regardless of lock-down configuration.10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used.11. When the status register data is read, input the address to which the erase or program operation is executed.NOTES:1. DQ 0=1: a block is locked; DQ 0=0: a block is unlocked.DQ 1=1: a block is locked-down; DQ 1=0: a block is not locked-down.2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations.3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is,[01] regardless of the states before power-off or reset operation.4. OTP (One Time Program) block has the lock function which is different from those described above.NOTES:1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command.2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ 0=0), the corresponding block is locked-down and automatically locked at the same time.3. "No Change" means that the state remains unchanged after the command written.Table 5.Functions of Block Lock (4) and Block Lock-DownCurrent StateErase/Program Allowed (2)State DQ 1(1)DQ 0(1)State Name [00]00Unlocked Yes [01](3)01Locked No [10]10Unlocked Yes [11]11LockedNoTable 6.Block Locking State Transitions upon Command Write Current State Result after Lock Command Written (Next State)State DQ 1DQ 0Set Lock (1)Clear Lock (1)Set Lock-down (1)[00]00[01]No Change (3)[11](2)[01]01No Change [00][11][10]10[11]No Change [11](2)[11]11No Change[10]No ChangeTable 7.Status Register DefinitionR R R R R R R R 15141312111098 WSMS BESS BEFCES PBPOPS R PBPSS DPS R 76543210SR.15 - SR.8 = RESERVED FOR FUTUREENHANCEMENTS (R)SR.7 = WRITE STATE MACHINE STATUS (WSMS)1 = Ready0 = BusySR.6 = BLOCK ERASE SUSPEND STATUS (BESS)1 = Block Erase Suspended0 = Block Erase in Progress/CompletedSR.5 = BLOCK ERASE AND FULL CHIP ERASESTATUS (BEFCES)1 = Error in Block Erase or Full Chip Erase0 = Successful Block Erase or Full Chip EraseSR.4 = (PAGE BUFFER) PROGRAM ANDOTP PROGRAM STATUS (PBPOPS)1 = Error in (Page Buffer) Program or OTP Program0 = Successful (Page Buffer) Program or OTP Program SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.2 = (PAGE BUFFER) PROGRAM SUSPENDSTATUS (PBPSS)1 = (Page Buffer) Program Suspended0 = (Page Buffer) Program in Progress/CompletedSR.1 = DEVICE PROTECT STATUS (DPS)1 = Erase or Program Attempted on aLocked Block, Operation Abort0 = UnlockedSR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0".If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, (page buffer) program, set/clear block lock bit, set block lock-down bit, attempt, an improper command sequence was entered.SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block E rase, Full Chip E rase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status.SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and should be masked out when polling the status register.Table 8.Extended Status Register DefinitionR R R R R R R R 15141312111098 SMS R R R R R R R 76543210XSR.15-8 = RESERVED FOR FUTUREENHANCEMENTS (R)XSR.7 = STATE MACHINE STATUS (SMS)1 = Page Buffer Program available0 = Page Buffer Program not availableXSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R)NOTES:After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not.XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status register.1 Electrical Specifications 1.1 Absolute Maximum Ratings *Operating TemperatureDuring Read, Erase and Program......0°C to +70°C (1)Storage TemperatureDuring under Bias...............................-10°C to +80°C During non Bias................................-65°C to +125°C V oltage On Any Pin(except V CC )............................-0.5V to V CC +0.5V (2)V CC Supply V oltage...........................-0.2V to +3.9V (2)Output Short Circuit Current...........................100mA (3)*WARNING: Stressing the device beyond the "AbsoluteMaximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.NOTES:1. Operating temperature is for commercial temperature product defined by this specification.2. All specified voltages are with respect to GND.Minimum DC voltage is -0.5V on input/output pins and -0.2V on V CC pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins is V CC +0.5V which,during transitions, may overshoot to V CC +2.0V for periods <20ns.3. Output shorted for no more than one second. No more than one output shorted at a time.1.2 Operating ConditionsNOTES:1. See DC Characteristics tables for voltage range-specific specification.ParameterSymbol Min.Typ.Max.Unit NotesOperating Temperature T A 0+25+70°C V CC Supply Voltage V CC2.73.03.6V 1Main Block Erase Cycling 100,000Cycles Parameter Block Erase Cycling100,000Cycles1.2.3 DC CharacteristicsNOTES:1. All currents are in RMS unless otherwise noted. Typical values are the reference values at V CC =3.0V and T A =+25°C unless V CC is specified.2. I CCWS and I CCES are specified with the device de-selected. If read or (page buffer) program is executed while in block erase suspend mode, the device ’s current draw is the sum of I CCES and I CCR or I CCW . If read is executed while in (page buffer) program suspend mode, the device ’s current draw is the sum of I CCWS and I CCR .3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when V CC ≤V LKO , and not guaranteed outside the specified voltage.4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (t AVQV ) provide new data when addresses are changed.5. Sampled, not 100% tested.V CC =2.7V-3.6VSymbol ParameterNotes Min.Typ.Max.Unit Test Conditions I LI Input Load Current 1-1.0+1.0µA V CC =V CC Max.,V IN /V OUT =V CC or GND I LO Output Leakage Current 1-1.0+1.0µA I CCS V CC Standby Current1625µAV CC =V CC Max.,CE#=RST#= V CC ±0.2V I CCAS V CC Automatic Power Savings Current 1,4420µA V CC =V CC Max.,CE#=GND±0.2V I CCDV CC Reset Power-Down Current 1420µA RST#=GND±0.2V I CCRAverage V CC Read CurrentNormal Mode11525mAV CC =V CC Max.,CE#=V IL ,OE#=V IH ,f=5MHzAverage V CC ReadCurrentPage Mode8 Word Read 1510mA I CCW V CC (Page Buffer) Program Current 1,52060mA I CCE V CC Block Erase, Full Chip Erase Current1,51030mA I CCWS I CCES V CC (Page Buffer) Program or Block Erase Suspend Current 1,215210µA CE#=V IHV IL Input Low Voltage 5-0.40.4V V IH Input High V oltage 5 2.4V CC + 0.4V V OL Output Low V oltage 50.2V V CC =V CC Min.,I OL =100µA V OH Output High V oltage 5V CC -0.2V V CC =V CC Min.,I OH =-100µAV LKOV CC Lockout Voltage31.5V1.2.4 AC Characteristics - Read-Only Operations(1)V CC=2.7V-3.6V, T A=0°C to +70°CSymbol Parameter Notes Min.Max.Unit t AV AV Read Cycle Time90ns t AVQV Address to Output Delay90ns t ELQV CE# to Output Delay390ns t APA Page Address Access Time35ns t GLQV OE# to Output Delay320ns t PHQV RST# High to Output Delay150ns t EHQZ, t GHQZ CE# or OE# to Output in High Z, Whichever Occurs First220ns t ELQX CE# to Output in Low Z20ns t GLQX OE# to Output in Low Z20ns t OH Output Hold from First Occurring Address, CE# or OE# change20ns NOTES:1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate.2. Sampled, not 100% tested.3. OE# may be delayed up to t ELQV t GLQV after the falling edge of CE# without impact to t ELQV.1.2.5 AC Characteristics - Write Operations (1), (2)NOTES:1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations.2. A write operation can be initiated and terminated with either CE# or WE#.3. Sampled, not 100% tested.4. Write pulse width (t WP ) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of CE# or WE# (whichever goes high first). Hence, t WP =t WLWH =t ELEH =t WLEH =t ELWH .5. Write pulse width high (t WPH ) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling edge of CE# or WE# (whichever goes low last). Hence, t WPH =t WHWL =t EHEL =t WHEL =t EHWL .6. t WHR0 (t EHR0) after the Read Query or Read Identifier Codes/OTP command=t A VQV +100ns.7. Refer to Table 4 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration.V CC =2.7V-3.6V, T A =0°C to +70°CSymbol ParameterNotesMin.Max.Unit t AV AVWrite Cycle Time90ns t PHWL (t PHEL )RST# High Recovery to WE# (CE#) Going Low 3150ns t ELWL (t WLEL )CE# (WE#) Setup to WE# (CE#) Going Low 40ns t WLWH (t ELEH )WE# (CE#) Pulse Width460ns t DVWH (t DVEH )Data Setup to WE# (CE#) Going High 740ns t AVWH (t AVEH )Address Setup to WE# (CE#) Going High 750ns t WHEH (t EHWH )CE# (WE#) Hold from WE# (CE#) High 0ns t WHDX (t EHDX )Data Hold from WE# (CE#) High 0ns t WHAX (t EHAX )Address Hold from WE# (CE#) High 0ns t WHWL (t EHEL )WE# (CE#) Pulse Width High 530ns t WHGL (t EHGL )Write Recovery before Read 30ns t WHR0 (t EHR0)WE# (CE#) High to SR.7 Going "0"3, 6t A VQV +50ns1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance (3)NOTES:1. Typical values measured at V CC =3.0V and T A =+25°C. Assumes corresponding lock bits are not set. Subject to change based on device characterization.2. Excludes external system-level overhead.3. Sampled, but not 100% tested.4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1".5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than t ERES and its sequence is repeated, the block erase operation may not be finished.V CC =2.7V-3.6V, T A =0°C to +70°CSymbolParameterNotes Page BufferCommand is Used or not Used Min.Typ.(1)Max.(2)Unitt WPB 4K-Word Parameter Block Program Time 2Not Used 0.050.3s 2Used 0.030.12s t WMB 32K-Word Main Block Program Time 2Not Used 0.38 2.4s 2Used 0.24 1.0s t WHQV1/t EHQV1Word Program Time 2Not Used 11200µs 2Used 7100µs t WHOV1/t EHOV1OTP Program Time 2Not Used36400µs t WHQV2/t EHQV24K-Word Parameter Block Erase Time2-0.34s t WHQV3/t EHQV332K-Word Main Block Erase Time2-0.65s Full Chip Erase Time280700s t WHRH1/t EHRH1(Page Buffer) Program Suspend Latency Time to Read 4-510µs t WHRH2/t EHRH2Block Erase Suspend Latency Time to Read 4-520µst ERESLatency Time from Block Erase Resume Command to Block Erase Suspend Command5-500µs2 Related Document Information(1)Document No.Document NameFUM00701 LH28F640BF series AppendixNOTE:1. International customers should contact their local SHARP or distribution sales offices.A-1.1.1 Rise and Fall TimeSymbol Parameter Notes Min.Max.Unit t VR V CC Rise Time10.530000µs/V t R Input Signal Rise Time1, 21µs/V t F Input Signal Fall Time1, 21µs/VNOTES:1. Sampled, not 100% tested.2. This specification is applied for not only the device power-up but also the normal operations.A-2 RELATED DOCUMENT INFORMATION(1)Document No.Document Name AP-001-SD-E Flash Memory Family Software DriversAP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, V PP Electric Potential Switching CircuitNOTE:1. International customers should contact their local SHARP or distribution sales office.。

PC816AB中文资料

PC816 Seriess Featuress Applicationsdifferent potentials and impedancess Outline Dimensions(Unit :mm )ISO 2. Compact dual-in-line package 3. High isolation voltage between input and 4. Current transfer ratio(CTR :MIN. 50% at I F =5mA, V CE =5V ) 1. Programmable controllers, computers2. System appliances, measuring instruments3. Signal transmission between circuits of High Collector-emitter Voltage, High Density Mounting Type PhotocouplerPC816:1-channel type PC826:2-channel type PC846:4-channel typeCEO 1. High collector-emitter voltage (V : 70V ) output (V 5. Recognized by UL, file No. E64380g Lead forming type (I type ) and taping reel type (P type ) are also available. (PC816I/PC816P ):5 000V rms )Fig. 3 Peak Forward Current vs. Duty RatioC o l l e c t o r c u r r e n t I C (m A )Collector-emitter voltage V CE (V )Ambient temperature T a (˚C )F (m A )010020050150Ambient TemperatureC (m W )-Fig. 2 Collector Power Dissipation VS.C o l l e c t o r p o w e r d i s s i p a t i o n P F o r w a r d c u r r e n t I 2510205010020050010-300.020204060801000.040.060.080.100.120.140.16200406080555555100Fig. 9 Collector Dark Current vs. Ambient TemperatureFig.11 Frequency ResponseFrequency f (kHz )0125105002001005020R L =10k Ω1k Ω100Ω0.5C E (s a t ) (V )Ambient temperature T a (˚C )C o l l e c t o r d a r k c u r r e n t IC E O (A )Ambient temperature T a (˚C )V o l t a g e g a i n A v (dB )L (k Ω)0.20.10.5120.010.111050R e s p o n s e t i m e (µs )5102050100200500C o l l e c t o r -e m i t t e r s a t u r a t i o n v o l t a g e V C E (s a t ) (V )Forward current I F (mA )123456Fig.12 Collector-emitter Saturation Voltage vs. Forward CurrentTest Circuit for Response TimeInputOutputTest Circuit for Frepuency ResponseFig. 8 Collector-emitter Saturation Voltage vs. Ambient TemperatureC o l l e c t o r -e m i t t e r s a t u r a t i o n v o l t a g e V -3010-1110-1010-910-810-710-610-5-20-10I F =20mA I C =1mAt rt ft dt sV CE =2V I C =2mAT a =25˚C V CE =5V I C =2mA T a =25˚CV CE =20VPlease refer to the chapter “Precautions for Use ”Fig.10 Response Time vs. Load ResistanceLoad resistance R qApplication CircuitsNOTICEq The circuit application examples in this publication are provided to explain representative applications of SHARP devices and are not intended to guarantee any circuit design or license any intellectual property rights. SHARP takes no responsibility for any problems related to any intellectual property right of a third party resulting from the use of SHARP's devices.q Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.SHARP reserves the right to make changes in the specifications, characteristics, data, materials, structure, and other contents described herein at any time without notice in order to improve design or reliability. Manufacturing locations are also subject to change without notice.q Observe the following points when using any devices in this publication. SHARP takes no responsibility for damage caused by improper use of the devices which does not meet the conditions and absolute maximum ratings to be used specified in the relevant specification sheet nor meet the following conditions:(i) The devices in this publication are designed for use in general electronic equipment designs such as:--- Personal computers--- Office automation equipment--- Telecommunication equipment [terminal]--- Test and measurement equipment--- Industrial control--- Audio visual equipment--- Consumer electronics(ii)Measures such as fail-safe function and redundant design should be taken to ensure reliability and safety when SHARP devices are used for or in connection with equipment that requires higher reliability such as:--- Transportation control and safety equipment (i.e., aircraft, trains, automobiles, etc.)--- Traffic signals--- Gas leakage sensor breakers--- Alarm equipment--- Various safety devices, etc.(iii)SHARP devices shall not be used for or in connection with equipment that requires an extremely high level of reliability and safety such as:--- Space applications--- Telecommunication equipment [trunk lines]--- Nuclear power control equipment--- Medical and other life support equipment (e.g., scuba).q Contact a SHARP representative in advance when intending to use SHARP devices for any "specific"applications other than those recommended by SHARP or when it is unclear which category mentioned above controls the intended use.q If the SHARP devices listed in this publication fall within the scope of strategic products described in the Foreign Exchange and Foreign Trade Control Law of Japan, it is necessary to obtain approval to export such SHARP devices.q This publication is the proprietary product of SHARP and is copyrighted, with all rights reserved. Under the copyright laws, no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, in whole or in part, without the express written permission of SHARP. Express written permission is also required before any use of this publication may be made by a third party.q Contact and consult with a SHARP representative if there are any questions about the contents of this publication.。

L816BSRD中文资料

PAGE: 2 OF 5
元器件交易网
Absolute Maximum Ratings at T)=25°C °
Par am et er Power dissipation DC Forward Current VF=14V Reverse Voltage Operating Temperature Storage Temperature Lead Soldering Temperature [1]
Yellow L816BYD
Super Bright Red L816BSRD/B,L816SRC/B
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
PAGE: 5 OF 5
Notes: 1. θ1/2 is the angle from optical centerline where the luminous intensity is 1/2 the optical centerline value.
Electrical / Optical Characteristics at T)=25°C °
BULIT-IN BLINKING IC.
!OPERATION VOLTAGE FROM 3.5V to 14V. !BLINKING FREQUENCY FROM 3.0Hz to 1.5Hz.
Package Dimensions
Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is ±0.25(0.01") unless otherwise noted. 3. Lead spacing is measured where the lead emerge package. 4. Specifications are subject to change without notice.

B5S162861TTR;中文规格书,Datasheet资料

1/9February 2003sHIGH SPEED:t PD =1.25ns (MAX.)at V CC =4.5V T A =85°CsON RESISTANCE BETWEEN TWO PORT:25Ω (TYP)at V CC =5.0V T A =25°C sLOW POWER DISSIPATION:I CC =1uA(MAX.)at T A =25°CsCOMPATIBLE WITH TTL OUTPUTS:V IH =2V(MIN),V IL =0.8V(MAX)sPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsOPERATING VOLTAGE RANGE:V CC (OPR)=4V to 5.5VsPIN AND FUNCTION COMPATIBLE WITH 74SERIES 16861s IMPROVED LATCH-UP IMMUNITY sESD PERFORMANCE:HBM >2000V (MIL STD 883method 3015);MM >200VDESCRIPTIONThe B5S162861is an advanced high-speed CMOS 20-BIT TWO PORT BUS SWITCH fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS tecnology.It is ideal for 4V to 5.5V V CC operations and ultra-low power and low noise applications,typically notebook and docking station.Any nG output control governs two 10-bit BUS SWITCHES.Output Enable inputs (nG)tied together gives full 20-bit operations.When nG is LOW,the switches are on.When nG is HIGH,the switches are in high impedance state.It has ultra high-speed performance at 5V near zero delay with low ON resistance and include 25Ωseries resistor to reduce noise resulting from reflections,thus eliminating the need for an external terminating resistor.All inputs and outputs are equipped with protection circuits against static discharge,giving them 2KV ESD immunity and transient excess voltage.B5S16286120-BIT TWO PORT BUS SWITCH WITH 25ΩSERIES RESISTOR IN OUTPUTThis is preliminary information on a new product now in development are or undergoing evaluation.Details subject to change withoutnotice.ORDER CODESPACKAGE T &RTSSOP48B5S162861TTRPRELIMINARY DATAPIN CONNECTIONOb so l e t ePr od u c t (s ) -d u c t (s)Ob so l e t ePr od u c t (s ) -B5S1628612/9INPUT EQUIVALENT CIRCUITPIN DESCRIPTIONTRUTH TABLEn:0to 9X:"H"or "L"Z:High ImpedanceSCHEMATIC DIAGRAMPIN No SYMBOL NAME QND FUNCTION 1,13NCNot Connected2,3,4,5,6,7,8,9,10,111A0to 1A9Data Inputs 14,15,16,17,18,19,20,21,22,232A0to 2A9Data Inputs34,33,32,31,30,29,28,27,26,252B0to 2B9Data Outputs46,45,44,43,42,41,40,39,38,371B0to 1B9Data Outputs 47,351G ,2G Bus Enable Input(Active Low)12,24GND Ground (0V)36,48V CCPositive Supply VoltageINPUTOUTPUT nG 1An,2An1Bn,2Bn LXBus ON HXZOb so l e t ePr od u c t (s ) -O bs o l e t eP r od u c t (s) B5S1628613/9ABSOLUTE MAXIMUM RATINGSAbsolute Maximum Rating are those value beyond which damage to the device may occour.Functional operation under these condition isnot implied1)I O absolute maximum rating must be observed 2)V O <GND,V O >V CC3)Not more than one output should be tested at one time.Duration of the test should not exceed one second.RECOMMENDED OPERATING CONDITIONS1)V IN from 0.8V to 2V at V CC =3.0VSymbol Parameter²Value Unit V CC Supply Voltage-0.5to +7.0V V I DC Switch and Control Pin Voltage -0.5to +7.0V V O DC Output Voltage (V CC =0V)(note 1)-0.5to +7.0V V O DC Output Voltage (V I/O =Gnd)-0.5to +7.0V I IK DC Input Diode Current (V I/O <0V)-50mA I OK DC Output Diode Current (note 2)-50mA I ODC Output Current (note 3)128mA I CC or I GND DC V CC or Ground Current per Supply Pin±100mA T stgStorage Temperature -65to +150°C T LLead Temperature (10sec)300°CSymbol ParameterValueUnitV CC Supply Voltage 4to 5.5V V I Input Voltage0to 5.5V V O Output Voltage (V CC =0V)0to 5.5V V O Output Voltage 0to 5.5V T op Operating Temperqture-55to 125°Cdt/dv Switch Input Rise and Fall Time0to DCns/V dt/dvControl Input Rise and Fall Time (note 1)0to 10ns/VOb so l e t ePr od u c t (s ) -O bs o l e t eP r od u c t (s) B5S1628614/9DC SPECIFICATION1)This current applies to the control inputs only and represent the current required to switch internal capacitance at the specified frequency.The 1An and 2An inputs generate no significant AC or DC currents as they transition.This parameter is not tested,but is guaranteed by design.AC ELECTRICAL CHARACTERISTICS1)Parameter guaranteed by design 2)X=1,2;n=0..9.SymbolParameterTest ConditionValue UnitV CC (V)T A =25°C-40to 85°C-55to 125°CMin.Typ.Max.Min.Max.Min.Max.V IH High Level Input Voltage 4to 5.5222V V IL Low Level Input Voltage 4to 5.50.80.80.8V V H Input Hysteresis at Con-trol pin4.5to5.5150mVR ONSwitch ON Resistance4.5I ON =64mA V I =0V 2040Ω4.5I ON =48mA V I =0V 2820404.5I ON =15mA V I =2.4V 3520484.0I ON =15mA V I =2.4V2048I I Input Leakage Current0to 5.5V I =5.5V orGND±0.1±1.0±2.0µA I OZ High Impedance Leakage Current 4.5to 5.5V I/O =5.5Vto GND ±1.0±2.0µA V IK Clamp Diode Voltage 4.0to 5.5I I =-18mA -0.7-1.2-1.2V I CC Quiescent Supply Current 5.5V I =V CC orGND 0.11.03.010.0µAI CCDSupply Current per Con-trol Input per MHz (1)5.5V I/O =Open nG=GND;Control Input Toggling 50%Duty Cycle 0.25mA/MHz∆I CC I CC incr.per Input5.5V IC =V CC -2.1V2.5mASymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s =t r (ns)-40to 85°C -55to 125°C Min.Max.Min.Max.t PLH t PHL Propagation Delay Time (1)xAn to xBn,xBn to xAn(2) 4.5to 5.550500 2.5 1.25ns t PZL t PZH Output Enable Time 50500 2.5 1.5 5.5ns t PLZ t PHZOutput Disable Time505002.51.55.5nsOb so l e t ePr od u c t (s )- O bs o B5S1628615/9CAPACITANCE CHARACTERISTICSTEST CIRCUITC L =50pF or equivalent (includes jig and probe capacitance)R L =R 1=500Ωor equivalentR T =Z OUT of pulse generator (typically 50Ω)SymbolParameterTest ConditionValue UnitV CC (V)T A =25°C Min.Typ.Max.C IN Input Capacitance at Control Pin4pF C I/OInput Capacitance at I/O Pin5.0nG=V CC5.5pF TESTSWITCH t PLH ,t PHL Open t PZL ,t PLZ 7V t PZH ,t PHZOpenB5S162861WAVEFORM1:PROPAGATION DELAY(f=1MHz;50%duty cycle)WAVEFORM2:OUTPUT ENABLE AND DISABLE TIME(f=1MHz;50%duty cycle)6/9O b s ol e te Pr o du ct(s)-O bs ol e te Pr o du ct(s)B5S1628619/9Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.© The ST logo is a registered trademark of STMicroelectronics© 2003 STMicroelectronics - Printed in Italy - All Rights ReservedSTMicroelectronics GROUP OF COMPANIESAustralia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States.© 分销商库存信息: STMB5S162861TTR。

GS8161FZ18BD-6.5中文资料

GS8161FZ18/32/36BD18Mb Flow Through Synchronous NBT SRAM5.5 ns–7.5 ns 2.5 V or 3.3 V V DD 2.5 V or 3.3 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 8M devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down• JEDEC-standard 165-bump FP-BGA package• RoHS-compliant 165-bump BGA package availableFunctional DescriptionThe GS8161FZ18/32/36BD is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8161FZ18/32/36BD is configured to operate in Flow Through mode.The GS8161FZ18/32/36BDis implemented with GSI's high performance CMOS technology and is available in JEDEC-standard 165-bump FP-BGA package.Parameter Synopsis-5.5-6.5-7.5UnitFlow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)225255200220185205mA mAGS8161FZ18/32/36BD165 Bump BGA—x18 Commom I/O—Top View (Package D)1234567891011A NC A E1BB NC E3CKE ADV A A A AB NC A E2NC BA CK W G A A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPA CD NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA DE NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA EF NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA FG NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA GH NC MCH NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC JK DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC KL DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC LM DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC MN DQPB NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A NC PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump PitchGS8161FZ18/32/36BD165 Bump BGA—x32 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3CKE ADV A A NC AB NC A E2BD BA CK W G A A NC BC NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH NC MCH NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC NP NC NC A A TDI A1TDO A A A NC PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump PitchGS8161FZ18/32/36BD165 Bump BGA—x36 Common I/O—Top View (Package D)1234567891011A NC A E1BC BB E3CKE ADV A A NC AB NC A E2BD BA CK W G A A NC BC DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB CD DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB DE DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB EF DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB FG DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB GH NC MCH NC V DD V SS V SS V SS V DD NC NC ZZ HJ DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA JK DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA KL DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA LM DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA MN DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA NP NC NC A A TDI A1TDO A A A NC PR LBO NC A A TMS A0TCK A A A A R11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump PitchGS8161FZ18/32/36BD 165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Input Buffer Enable; active lowW I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active high LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8161FZ18/32/36BDK18S A 1SA 0B u r s tC o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QN CD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cA 0–A nE 3E 2E 1WB DB CB BB AGS8161FZ18/32/36BDGS8161FZ18/32/36B NBT SRAM Functional Block DiagramGS8161FZ18/32/36BDClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Flow Through Mode Read and Write OperationsFlow Through NBT SRAMs are equipped with rising-edge-triggered input registers that capture data-in, address, and control input signals, but do not have a data output register like the one found on pipelined NBT SRAMs. Once a read command and an associated read address is clocked into the RAM, the read operation proceeds and, if the Output Enable pin is driven active low, culminates with the read data appearing on the RAM output pins, even if no additional clocks are sent to the RAM.A write operation in a Flow Through NBT SRAM begins when a write command and write address are clocked into the RAM. Next, data-in for that write address must be applied to the input pins and held for capture by the very next rising edge of clock. A write protocol like the one used on Flow Through NBT SRAMs—the capture of the write address and write command on one clock and the capture of the write data-in on the next clock—is often described as a Late Write protocol.It is the combination of the Flow Through read protocol and the Late Write write protocol that allows the Flow Through NBT SRAM to achieve seamless back-to-back, read-write-read transitions on a bi-directional data bus without requiring the user toinsert dead cycles to prevent bus contention during the transition from read to write or write to read.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS8161FZ18/32/36BDGS8161FZ18/32/36BDHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramFlow Through Mode Data I/O State DiagramGS8161FZ18/32/36BDBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved BurstPower Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8161FZ18/32/36BDSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage in V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8161FZ18/32/36BDNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage RangesParameterSymbolMin.Typ.Max.UnitNotes3.3 V Supply Voltage V DD3 3.0 3.3 3.6V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 3.3 V V DDQ I/O Supply Voltage V DDQ3 3.0 3.3V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8161FZ18/32/36BDV DDQ3 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 2.0—V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.8V 1V DDQ I/O Input High Voltage V IHQ 2.0—V DD + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.8V1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.V DDQ2 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low Voltage V IL –0.3—0.3*V DD V 1V DDQ I/O Input High Voltage V IHQ 0.6*V DD —V DD + 0.3V 1,3V DDQ I/O Input Low VoltageV ILQ–0.3—0.3*V DDV1,3Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.3.V IHQ (max) is voltage on V DDQ pins plus 0.3 V.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8161FZ18/32/36BD20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.AC Test ConditionsParameterConditionsInput high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 1Notes:1.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table.DQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig Capacitance(T A = 25= 2.5 V)DC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA ZZ Input Current I IN1V DD ≥ V IN ≥ V IH 0 V ≤ V IN ≤ V IH–1 uA –1 uA 1 uA 100 uA Output Leakage Current I OL Output Disable, V OUT = 0 to V DD –1 uA 1 uA Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V 1.7 V —Output High Voltage V OH3I OH = –8 mA, V DDQ = 3.135 V2.4 V —Output Low VoltageV OLI OL = 8 mA—0.4 VGS8161FZ18/32/36BDGS8161FZ18/32/36BDOperating CurrentsParameterTest ConditionsModeSymbol-5.5-6.5-7.5Unit0to 70°C–40 to 85°C0to 70°C–40to 85°C0 to 70°C–40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open (x32/x36)Flow Through I DD I DDQ 235202452020515215151901520015mA (x18)Flow Through I DD I DDQ 215102251019010200101751018510mA Standby Current ZZ ≥ V DD – 0.2 V —Flow ThroughI SB 405040504050mADeselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Flow Through I DD606550555055mA1.I DD and I DDQ apply to any combination of V DD3, V DD2, V DDQ3, and V DDQ2 operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameterSymbol-5.5-6.5-7.5UnitMinMax Min Max Min Max Flow ThroughClock Cycle Time tKC 5.5— 6.5—7.5—ns Clock to Output Valid tKQ — 5.5— 6.5—7.5ns Clock to Output Invalid tKQX 2.0— 2.0— 2.0—ns Clock to Output in Low-ZtLZ 1 2.0— 2.0— 2.0—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.5—ns Clock LOW Time tKL 1.5— 1.5— 1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 3.0— 3.8ns G to output in Low-Z tOLZ 10—0—0—ns G to output in High-Z tOHZ 1— 2.5— 3.0— 3.8ns ZZ setup time tZZS 25—5—5—ns ZZ hold time tZZH 21—1—1—ns ZZ recoverytZZR20—20—20—nsNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8161FZ18/32/36BDFlow Through Mode Timing (NBT)Write A Write B Write B+1Read CCont Read D Write E Read F Write GD(A)D(B)D(B+1)Q(C)Q(D)D(E)Q(F)D(G)tOLZ tOEtOHZtKQXtKQ tLZtHZtKQX tKQ tLZtHtStHtS tH tStH tStH tStH tStH tStKCtKLtKHABC D EF G*Note: E = High(False) if E1 = 1 or E2 = 0 or E3 = 1CKCKEE*ADVWBnA0–AnDQ GJTAG Port OperationOverviewThe JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with V DD . The JTAG output drivers are powered by V DDQ .Disabling the JTAG PortIt is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either V DD or V SS . TDO should be left unconnected.JTAG Pin DescriptionsPinPin NameI/ODescriptionTCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK.TMSTest Mode SelectInThe TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level.TDI Test Data In InThe TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level.TDO Test Data OutOut Output that is active depending on the state of the TAP state machine. Output changes inresponse to the falling edge of TCK. This is the output side of the serial registers placed betweenTDI and TDO.This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up.GS8161FZ18/32/36BDJTAG Port RegistersOverviewThe various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins.Instruction RegisterThe Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state.Bypass RegisterThe Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM’s JTAG Port to another device in the scan chain with as little delay as possible.Boundary Scan RegisterThe Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM’s input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port’s TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is inCapture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register.Instruction RegisterID Code RegisterBoundary Scan Register120····313029120Bypass RegisterTDITDOTMS TCKTest Access Port (TAP) ControllerM *·1·········Control Signals·* For the value of M, see the BSDL file, which is available at by contacting us at apps@.GS8161FZ18/32/36BDJTAG TAP Block DiagramIdentification (ID) RegisterThe ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put inCapture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins.ID Register ContentsNot UsedGSI Technology JEDEC Vendor ID CodeP r e s e n c e R e g i s t e r Bit #313029282726252423222120191817161514131211109876543210XXXXXXXXXXXXXXXXXXXX00110110011GS8161FZ18/32/36BDTap Controller Instruction SetOverviewThere are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must beimplemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers.When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table.Select DRCapture DRShift DRExit1 DRPause DRExit2 DRUpdate DRSelect IRCapture IRShift IRExit1 IRPause IRExit2 IRUpdate IRTest Logic ResetRun Test Idle 01111111111111111JTAG Tap Controller State DiagramInstruction DescriptionsBYPASSWhen the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facili-tate testing of other devices in the scan path.。

GS816236B-150中文资料

Sleep Mode Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
250 MHz–133 MHz 2.5 V or 3.3 V VDD 2.5 V or 3.3 V I/O
The x18 and x36 parts in this specification are Not Recommended for New Design.
Features
• FT pin for user-configurable flow through or pipeline operation • Single/Dual Cycle Deselect selectable • IEEE 1149.1 JTAG-compatible Boundary Scan • ZQ mode pin for user-selectable high/low output drive • 2.5 V or 3.3 V +10%/–10% core power supply • LBO pin for Linear or Interleaved Burst mode • Internal input resistors on mode pins allow floating mode pins • Default to SCD x18/x36 Interleaved Pipeline mode • Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle • Automatic power-down for portable applications • JEDEC-standard 119-, 165-, and 209-bump BGA package

CS8161YTVA5G中文资料

CS816112 V, 5.0 V Low Dropout Dual Regulator with ENABLEThe CS8161 is a 12 V/5.0 V dual output linear regulator. The 12 V ±5.0% output sources 400 mA and the 5.0 V ±2.0% output sources 200 mA.The on board ENABLE function controls the regulator’s two outputs. When the ENABLE pin is low, the regulator is placed in SLEEP mode. Both outputs are disabled and the regulator draws only 200 nA of quiescent current.The primary output, V OUT1 is protected against overvoltage conditions. Both outputs are protected against short circuit and thermal runaway conditions.The CS8161 is packaged in a 5 lead TO−220 with copper tab. The copper tab can be connected to a heat sink if necessary.Features•Two Regulated Outputs−12 V ±5.0%; 400 mA−5.0 V ±2.0%; 200 mA•Very Low SLEEP Mode Current Drain 200 nA•Fault Protection−Reverse Battery (−15 V)−74 V Load Dump−−100 V Reverse Transient−Short Circuit−Thermal Shutdown•Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.See detailed ordering and shipping information in the package dimensions section on page 9 of this data sheet.ORDERING INFORMATIONFigure 1. Block Diagram V OUT2V INV OUT1 ENABLEGNDABSOLUTE MAXIMUM RATINGSRating Value UnitInput Voltage: Operating RangeOvervoltage Protection −15 to 2674VVInternal Power Dissipation Internally Limited−Junction Temperature Range−40 to +150°C Storage Temperature Range−65 to +150°CLead Temperature Soldering Wave Solder (through hole styles only) (Note 1)Reflow (SMD styles only) (Note 2)260 peak230 peak°C°CESD (Human Body Model) 2.0kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.10 second maximum.2.60 second maximum above 183°CELECTRICAL CHARACTERISTICS for V OUT:(6.0 V ≤ V IN≤ 26 V; I OUT1 = 5.0 mA; I OUT2 = 5.0 mA;−40°C ≤ T J≤ +150°C; −40°C ≤ T A≤ +125°C; unless otherwise specified.)Characteristic Test Conditions Min Typ Max Unit PRIMARY OUTPUT STAGE (V OUT1)Output Voltage, V OUT113 V ≤ V IN≤ 26 V, I OUT1≤ 400 mA11.412.012.6V Dropout Voltage I OUT1 = 400 mA−0.350.6V Line Regulation13 V ≤ V IN≤ 20 V, 5.0 mA ≤ I OUT < 400 mA−−80mV Load Regulation 5.0 mA ≤ I OUT1≤ 400 mA, V IN = 14 V−−80mVQuiescent Current I OUT1≤ 100 mA, No Load on V OUT2I OUT1≤ 400 mA, No Load on V OUT2−−8.0501275mAmARipple Rejection f = 120 Hz, I OUT = 300 m A, V IN = 15.0 V DC, 2.0 V RMS42−−dB Current Limit−0.40− 1.0A Reverse Polarity Input Voltage, DC V OUT1≥ −0.6 V, 10 W Load−−30−18V Reverse Polarity Input Voltage, Transient 1.0% Duty Cycle, t = 100 ms, V OUT≥ −6.0 V, 10 W Load−−80−50V Overvoltage Shutdown−283445V Short Circuit Current−−−700mA SECONDARY OUTPUT (V OUT2)Output Voltage, (V OUT2) 6.0 V ≤ V IN≤ 26 V, I OUT2≤ 200 mA 4.90− 5.10V Dropout Voltage I OUT2≤ 200 mA−0.350.60V Line Regulation 6.0 V ≤ V IN≤ 26 V, 1.0 mA ≤ I OUT≤ 200 mA−−50mV Load Regulation 1.0 mA ≤ I OUT2≤ 200 mA; V IN =14 V−−50mVQuiescent Current I OUT2 = 50 mAI OUT2 = 200 mA −−5.0201035mAmARipple Rejection f = 120 Hz; I OUT = 10 mA, V IN = 15 V, 2.0 V RMS42−−dB Current Limit−200−600mA Short Circuit Current−−−400mA ENABLE FUNCTION (ENABLE)Input ENABLE Threshold V OUT1 OffV OUT1 On−2.001.301.300.80−VVInput ENABLE Current V ENABLE = 5.5 VV ENABLE < 0.8 V80−10−−50010m Am AOTHER FEATURESSleep Mode V ENABLE < 0.4 V−0.250m A Thermal Shutdown−150−210°C Quiescent Current in Dropout I OUT1 = 100 mA, I OUT2 = 50 mA−−60mAPACKAGE PIN DESCRIPTIONPACKAGE LEAD #5 Lead TO−220LEAD SYMBOL FUNCTION1V IN Supply voltage, usually direct from battery.2V OUT1Regulated output 12 V, 400 mA (typ).3GND Ground connection.4ENABLE CMOS compatible input lead; switches outputs on and off.When ENABLE is high V OUT1 and V OUT2 are active.5V OUT2Regulated output 5.0 V, 200 mA (typ).TYPICAL PERFORMANCE CHARACTERISTICS−40Temperature (°C)Output Current (mA)Figure 2. Output Voltage vs. Temperaturefor V OUT1Figure 3. Line Regulation vs. OutputCurrent for V OUT1Output Current (mA)Output Current (mA)Figure 4. Load Regulation vs. OutputCurrent for V OUT1Figure 5. Quiescent Current vs. OutputCurrent for V OUT1V o l t 1L i n e R e g u l a t i o n (m V )L o a d R e g u l a t i o n (m V )12.15012.11012.07012.03011.99011.95011.91011.87011.83011.79011.750151050−5−10−15−20−25−30−35−40501001502002503003504004505005010015020025030035040045050010015020025030035040045050050−202040608010012014016010505101520253035400Output Current (mA)Output Current (mA)Figure 6. Dropout Voltage vs. OutputVoltage for V OUT1Figure 7. Quiescent Current vs. OutputCurrent @ Dropout for V OUT115050D r o p o u t V o l t a g e (m V )Q u i e s c e n t C u r r e n t (m A )6005505004504003503002502001501005005050010015020025030035040045014013012011010090807060504030201000100150200250300350400450500TYPICAL PERFORMANCE CHARACTERISTICS (continued)O u t p u t V o l t a g eOutput Current (mA)Output Current (mA)Figure 10. Load Regulation vs. OutputCurrent for V OUT2Figure 11. Quiescent Current vs. OutputCurrent for V OUT2L o a d R e g u l a t i o n (m V )2586420−2−4−6−8−10−12−14−16−185075100125150175200225250250507510012515017520022525075Output Current (mA)Output Current (mA)Figure 12. Dropout Voltage vs. OutputCurrent for V OUT2Figure 13. Quiescent Current vs. OutputCurrent @ Dropout for V OUT225D r o p o u t V o l t a g e (m V )8007507006506005505004504003503002502001501005000255010012515017520022525005075100125150175200225250TYPICAL PERFORMANCE CHARACTERISTICS (continued)E N A B L E V o l t a g e1.305V ENABLEFigure 16. 12 mA ENABLE Current vs.ENABLE Voltage01.3001.2951.2901.285510152025DEFINITION OF TERMSDropout V oltage − The input−output voltage differential at which the circuit ceases to regulate against further reduction in input voltage. Measured when the output voltage has dropped 100 mV from the nominal value obtained at 14 V input, dropout voltage is dependent upon load current and junction temperature.Input Voltage − The DC voltage applied to the input terminals with respect to ground.Input Output Differential − The voltage difference between the unregulated input voltage and the regulated output voltage for which the regulator will operate.Line Regulation − The change in output voltage for a change in the input voltage. The measurement is made under conditions of low dissipation or by using pulse techniques such that the average chip temperature is not significantly affected.Load Regulation − The change in output voltage for a change in load current at constant chip temperature.Long Term Stability − Output voltage stability under accelerated life−test conditions after 1000 hours with maximum rated voltage and junction temperature.Output Noise Voltage − The rms AC voltage at the output, with constant load and no input ripple, measured over a specified frequency range.Quiescent Current − The part of the positive input current that does not contribute to the positive load current,i.e., the regulator ground lead current.Ripple Rejection − The ratio of the peak−to−peak input ripple voltage to the peak−to−peak output ripple voltage.Temperature Stability of V OUT − The percentage change in output voltage for a thermal variation from room temperature to either temperature extreme.Figure 17. Typical Circuit Waveform14 V 0 V0 V2.0 V 0.8 VV INENABLEV OUT1V OUT260 V12 V5.0 V34 V12 V2.4 V3.0 V26 V12 V0 V12 V5.0 V12 V14V0 VLoad DumpLow V INLine Noise, Etc.V OUT1Short CircuitV OUT1Thermal ShutdownTurn OffTurn On2.4 VV OUT2Short Circuit0 V0 V 0 V5.0 VAPPLICATION DIAGRAMFigure 18. Application Diagram* C 1 required if regulator is located far from power supply filter.** C 2, C 3 required for stability, value may be increased. Capacitor must operate at minimum temperature expected.APPLICATION NOTESSince both outputs are controlled by the same ENABLE,the CS8161 is ideal for applications where a sleep mode is required. Using the CS8161, a section of circuitry such as a display and nonessential 5.0 V circuits can be shut down under microprocessor control to conserve energy.The example in the Applications Diagram (Figure 18)shows an automotive radio application where the display is powered by the 12 V on V OUT1 and the Tuner IC is powered by the 5.0 V on V OUT2. Neither output is required unless both the ignition and the Radio On/Off switch are on.Stability ConsiderationsThe output or compensation capacitor (Application diagram C 2 and C 3) helps determine three maincharacteristics of a linear regulator: startup delay, load transient response and loop stability.The capacitor value and type should be based on cost,availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the cheapest solution, but, if the circuit operates at low temperatures (−25°C to −40°C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information.The values for the output capacitors C2 and C3 shown in the test and applications circuit should work for most applications, however it is not necessarily the best solution. To determine acceptable values for C2 and C3 for a particular application, start with tantalum capacitors of the recommended value on each output and work towards less expensive alternative parts for each output in turn.Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs on the oscilloscope. A decade box connected in series with the capacitor C2 will simulate the higher ESR of an aluminum capacitor.(Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible)Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions.Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature.Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions.Step 5: If the capacitor C2 is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. (A smaller capacitor will usually cost less and occupy less board space.) If the capacitor oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value.Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real work environment. Vary the ESR to reduce ringing.Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations.Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ±20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitors should be less than 50% of the maximum allowable ESR found in step 3 above. Once the value for C2 is determined, repeat the steps to determine the appropriate value for C3.Calculating Power Dissipation in aDual Output Linear RegulatorThe maximum power dissipation for a dual output regulator (Figure 19) isP D(max)+ǊV IN(max)*V OUT1(min)ǋI OUT1(max))ǊV IN(max)*V OUT2(min)ǋI OUT2(max))V IN(max)IQ(1) where:V IN(max) is the maximum input voltage,V OUT1(min) is the minimum output voltage from V OUT1, V OUT2(min) is the minimum output voltage from V OUT2, I OUT1(max) is the maximum output current, for the application,I OUT2(max) is the maximum output current, for the application, andI Q is the quiescent current the regulator consumes at I OUT(max).Once the value of P D(max) is known, the maximum permissible value of R q JA can be calculated:R q JA+150°C*T AP D(2) The value of R q JA can be compared with those in the package section of the data sheet. Those packages with R q JA’s less than the calculated value in equation 2 will keep the die temperature below 150°C.In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.Figure 19. Dual Output Regulator With KeyPerformance Parameters Labeled.V OUT1OUT2 V INHeat SinksA heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air.Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R q JA :R q JA +R q JC )R q CS )R q SA(3)where:R q JC = the junction−to−case thermal resistance,R q CS = the case−to−heatsink thermal resistance, and R q SA = the heatsink−to−ambient thermal resistance.R q JC appears in the package section of the data sheet. Like R q JA , it too is a function of package type. R q CS and R q SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.MARKING DIAGRAMSA = Assembly Location WL = Wafer Lot YY = YearWW = Work WeekG= Pb−Free PackageTO−220 5−LEADCS 8161AWLYWWG1CS8161AWLYWWG1CS 8161AWLYWWG1ORDERING INFORMATION*DevicePackage ShippingCS8161YT5TO−220STRAIGHT 50 Units / Rail CS8161YT5GTO−220STRAIGHT (Pb−Free)CS8161YTVA5TO−220VERTICAL CS8161YTVA5GTO−220VERTICAL (Pb−Free)CS8161YTHA5TO−220HORIZONTAL CS8161YTHA5GTO−220HORIZONTAL (Pb−Free)*Consult your local sales representative for SO−16L package option.PACKAGE DIMENSIONSTO−220CASE 314D−04ISSUE FDETAIL A−ATO−220TVA SUFFIX CASE 314K−01ISSUE ONOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.3.DIMENSION D DOES NOT INCLUDEINTERCONNECT BAR (DAMBAR) PROTRUSION.DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM.DIM MIN MAX MIN MAX MILLIMETERS INCHES A 0.5600.59014.2214.99B 0.3850.4159.7810.54C 0.1600.190 4.06 4.83D 0.0270.0370.690.94E 0.0450.055 1.14 1.40F 0.5300.54513.4613.84G 0.067 BSC 1.70 BSC J 0.0140.0220.360.56K 0.7850.80019.9420.32L 0.3210.3378.158.56M 0.0630.078 1.60 1.98Q 0.1460.156 3.71 3.96S 0.1460.196 3.71 4.98U 0.4600.47511.6812.07W55°°R 0.2710.321 6.888.15CS8161PACKAGE DIMENSIONSTO−220THA SUFFIX CASE 314A−03ISSUE EPACKAGE THERMAL DATAParameterTO−220FIVE LEADUnit R q JC Typical 2.0°C/W R q JATypical50°C/WON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION元器件交易网。

1621B(中文版式)

CS1621RAM映射32×4点阵式液晶显示驱动电路概述CS1621是一种128点阵式存储器映射多功能LCD驱动电路。

CS1621的S/W结构特点，使它适合点阵式LCD显示，包括LCD模块和显示子系统，CS1621具有关闭电源功能。

功能特点z工作电压：2.4V～5.2Vz内部256kHz RC振荡器z外部32kHz晶振或256kHz频率输入z可选择1/2或1/3偏置和1/2、1/3或1/4占空比LCD显示z内部时间基准频率z蜂鸣器驱动信号频率可选择2kHz或4kHzz具有关机指令可减少功耗z内部时基发生器和WDT看门狗定时器z时基或WDT溢出输出z时基/WDT时钟源有八种z32×4 LCD驱动器z内部32×4 bit显示RAMz3端串行接口z内置LCD驱动信号源z可用指令控制操作z数据模式和命令模式指令z R/W地址自动累加z3种数据存取模式z VLCD引脚用来调整LCD工作电压z采用SSOP48（CS1621GO、CS1621BGO）、PDIP48（CS1621BGP）、SKDIP28（CS1621DGP）功能框图注意：CS ：芯片选择BZ ，BZ ：蜂鸣器输出WR，RD ，DATA ：串行接口COM0～COM3，SEG0～SEG31：LCD 输出 IRQ ：时间基准或WDT 溢出输出功能说明1. 工作原理CS1621是一种具有微控制器接口，由存储器映射的32×4点阵式LCD 控制驱动器。

电路上电时清零复位，通过命令端进行工作状态设置，通过片选、读、写端对RAM 数据进行读、写、修改操作，按照一一对应的原则，驱动LCD 显示器。

该电路可用于点阵式LCD 显示驱动，各SEG 端是互相独立的，且容易对RAM 数据进行修改，所以显示点阵内容灵活，可随用户任意定制。

2. 系统结构（1） RAM静态显示存储器（RAM ）结构为32×4位，贮存所显示的数据。

W981216BH中文资料

W981216BH2M × 4 BANKS × 16 BIT SDRAMPublication Release Date: October 2000- 1 - Revision A1GENERAL DESCRIPTIONW981216BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as 2M words × 4 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology, W981216BH delivers a data bandwidth of up to 143M words per second (-7). To fully comply with the personal computer industrial standard, W981216BH is sorted into three speed grades: -7, -75 and -8H. The -7 is compliant to the 143 MHz/CL3 or PC133/CL2 specification, the -75 is compliant to the PC133/CL3 specification, the -8H is compliant to the PC100/CL2 specificationAccesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W981216BH is ideal for main memory in high performance applications.FEATURES• 3.3V ±0.3V Power Supply • Up to 143 MHz Clock Frequency• 2,097,152 Words × 4 banks × 16 bits organization • Auto Refresh and Self Refresh • CAS Latency: 2 and 3• Burst Length: 1, 2, 4, 8, and full page • Burst Read, Single Writes Mode • Byte Data Controlled by DQM • Power-Down Mode• Auto-precharge and Controlled Precharge • 4K Refresh cycles / 64 mS • Interface: LVTTL• Packaged in TSOP II 54 pin, 400 mil - 0.80KEY PARAMETERSSYM.DESCRIPTIONMIN. /MAX.-7(PC133, CL2)-75(PC133, CL3)-8H (PC100)t CK Clock Cycle Time Min. 7 nS 7.5 nS 8 nS t AC Access Time from CLK Max. 5.4 nS 5.4 nS 6 nS t RP Precharge to Active Command Min. 15 nS 20 nS 20 nS t RCD Active to Read/Write Command Min. 15 nS 20 nS 20 nS I CC1 Operation Current (Single bank) Max. 80 mA 75 mA 70 mA I CC4 Burst Operation Current Max. 100 mA 95 mA 90 mA I CC6Self-Refresh CurrentMax.2 mA2 mA2 mAW981216BH- 2 -PIN CONFIGURATIONW981216BHPublication Release Date: October 2000- 3 - Revision A1PIN DESCRIPTIONW981216BH- 4 -BLOCK DIAGRAMW981216BHPublication Release Date: October 2000- 5 - Revision A1ABSOLUTE MAXIMUM RATINGSPARAMETERSYMBOLRATINGUNITInput/Output Voltage V IN, V OUT -0.3 − V CC +0.3 V Power Supply Voltage V CC , V CCQ -0.3 − 4.6 VOperating Temperature T OPR 0 − 70 °C Storage Temperature T STG -55 − 150 °C Soldering Temperature (10s) T SOLDER 260 °CPower DissipationP D 1 W Short Circuit Output CurrentI OUT50mANote: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliabilityof the device.RECOMMENDED DC OPERATING CONDITIONS(T A = 0 to 70°C)PARAMETER SYMBOL MIN. TYP. MAX. UNITPower Supply Voltage V CC 3.0 3.3 3.6 V Power Supply Voltage (for I/O Buffer)V CCQ 3.0 3.3 3.6 V Input High Voltage V IH 2.0 - V CC +0.3 V Input Low VoltageV IL-0.3-0.8VNote: V IH (max) = V CC / V CC Q+1.2V for pulse width < 5 nS V IL (min) = V SS / V SS Q-1.2V for pulse width < 5 nSCAPACITANCE(V CC = 3.3V, f = 1 MHz, T A = 25°C)Note: These parameters are periodically sampled and not 100% tested.W981216BH- 6 -AC CHARACTERISTICS AND OPERATING CONDITION(Vcc = 3.3V ± 0.3V, T A = 0° to 70°C; Notes: 5, 6, 7, 8)PARAMETERSYM.-7(PC133, CL2)-75(PC133, CL3)-8H (PC100)UNITMIN.MAX.MIN.MAX.MIN.MAX.Ref/Active to Ref/Active Command Periodt RC 57 65 68 Active to precharge Command Periodt RAS 42 10000045 10000048 100000nS Active to Read/Write Command Delay Timet RCD 15 20 20 Read/Write(a) toRead/Write(b)Command Period t CCD 1 1 1 Cycle Precharge to Active Command Periodt RP 15 20 20 Active(a) to Active(b) Command Periodt RRD 15 15 20 Write Recovery Time CL* = 2 t WR 7.5 10 10CL* = 3 7 7.5 8 CLK Cycle Time CL* = 2 t CK7.5 1000 10 1000 10 1000CL* = 3710007.5100081000CLK High Level width t CH 2.5 2.5 3 CLK Low Level widtht CL2.52.53Access Time from CLKCL* = 2 t AC5.4 6 6CL* = 35.4 5.4 6 nS Output Data Hold Timet OH 3 3 3 Output Data High Impedance Time t HZ 3 7 3 7.5 3 8 Output Data Low Impedance Time t LZ 0 0 0 Power Down Mode Entry Time t SB 0 7 0 7.5 0 8 Transition Time of CLK (Rise and Fall) t T 0.5 10 0.5 10 0.5 10 Data-in Set-up Time t DS 1.5 1.5 2 Data-in Hold Time t DH 0.8 0.8 1 Address Set-up Time t AS 1.5 1.5 2 Address Hold Time t AH 0.8 0.8 1 CKE Set-up Time t CKS 1.5 1.5 2 CKE Hold Time t CKH 0.8 0.8 1 Command Set-up Time t CMS 1.5 1.5 2 Command Hold Time t CMH 0.8 0.8 1 Refresh Timet REF 64 64 64 mS Mode register Set Cycle Timet RSC141516nS*CL = CAS LatencyW981216BHPublication Release Date: October 2000- 7 - Revision A1DC CHARACTERISTICS(V CC = 3.3V ± 0.3V, T A = 0°− 70°C)PARAMETERSYMBOL MIN. MAX. UNIT NOTESInput Leakage Current(0V ≤ V IN ≤ V CC , all other pins not under test = 0V) I I(L)-55µAOutput Leakage Current(Output disable , 0V ≤ V OUT ≤ V CCQ ) I O(L)-55µALVTTL Output ″H ″ Level Voltage (I OUT = -2 mA )V OH2.4-VLVTTL Output ″L ″ Level Voltage (I OUT = 2 mA )V OL-0.4VW981216BH- 8 -Notes:1. Operation exceeds "ABSOLUTE MAXIMUM RATING" may cause permanent damage to the devices.2. All voltages are referenced to V SS3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t CK and t RC .4. These parameters depend on the output loading conditions. Specified values are obtained with output open.5. Power up sequence is further described in the "Functional Description" section.6. AC Testing ConditionsOutput Reference Level 1.4V/1.4V Output Load See diagram belowInput Signal Levels2.4V/0.4V Transition Time (Rise and Fall) of Input Signal2 nS Input Reference Level1.4V7. Transition times are measured between V IH and V IL .8. t HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.W981216BHPublication Release Date: October 2000- 9 - Revision A1OPERATION MODEFully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands. Table 1 Truth Table (Note (1), (2))Notes:(1) v = valid x = Don't care L = Low Level H = High Level (2) CKEn signal is input level when commands are provided.CKEn-1 signal is the input level one clock cycle before the command is issued. (3) These are state of bank designated by BS0, BS1 signals. (4) Device state is full page burst operation.(5) Power Down Mode can not be entered in the burst cycle.When this command asserts in the burst cycle, device state is clock suspend mode.W981216BH- 10 -FUNCTIONAL DESCRIPTIONPower Up and InitializationThe default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.During power up, all Vcc and VccQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the "NOP" state. The power up voltage must not exceed V C C +0.3V on any of the input pins or Vcc supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.Programming Mode RegisterAfter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RAS, CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.Bank Activate CommandThe Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD ). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC ). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD ). The maximum time that each bank can be held active is specified as t RAS (max).Read and Write Access ModesAfter a bank has been activated , a read or write cycle can be followed. This is accomplished by setting RAS high and CAS low at the clock rising edge after minimum of t RCD delay. WE pin voltage level defines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation among many different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.W981216BHPublication Release Date: October 2000- 11 - Revision A1Burst Read CommandThe Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.Burst Write CommandThe Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.Read Interrupted by a ReadA Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS latency from the interrupting Read Command the is satisfied.Read Interrupted by a WriteTo interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.Write Interrupted by a WriteA burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.Write Interrupted by a ReadA Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.Burst Stop CommandA Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burstW981216BH- 12 -read cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data from the burst write cycle will be ignored.Addressing Sequence of Sequential ModeA column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.Table 2 Address Sequence of Sequential ModeAddressing Sequence of Interleave ModeA column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.Table 3 Address Sequence of Interleave ModeW981216BHPublication Release Date: October 2000- 13 - Revision A1Auto-Precharge CommandIf A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS latency.A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP ) has been satisfied. Issue of Auto-Precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-Precharge function is initiated. The SDRAM automatically enters the precharge operation one clock delay from the last burst write cycle. This delay is referred to as Write t W R . The bank undergoing auto-precharge can not be reactivated until t W R and t RP are satisfied. This is referred to as t DAL , Data-in to Active delay (t DAL = t W R + t RP ). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS (min).Precharge CommandThe Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t RP ).Self Refresh CommandThe Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t AC cycle time plus the Self Refresh exit time.If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode.Power Down ModeThe Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF ) of the device.W981216BH- 14 -The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK . The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + t CK (min).No Operation CommandThe No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.Deselect CommandThe Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don't cares.Clock Suspend ModeDuring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.W981216BHPublication Release Date: October 2000- 15 - Revision A1TIMING WAVEFORMSCommand Input TimingW981216BH- 16 -Timing Waveforms, continuedRead TimingW981216BHPublication Release Date: October 2000- 17 - Revision A1Timing Waveforms, continuedControl Timing of Input / Output DataW981216BH- 18 -Timing Waveforms, continuedMode Register Set CycleW981216BHPublication Release Date: October 2000- 19 - Revision A1OPERATING TIMING EXAMPLEInterleaved Bank Read (Burst Length = 4, CAS Latency = 3)t RCt RASt RPt RASt RCD t RCDt RRDRAaRBdW981216BH- 20 -Operating Timing Example, continedInterleaved Bank Read (Burst Length = 4, CAS Latency = 3, Autoprecharge)(CLK = 100 MHz)t RCt RASt RPt RPt RCDt RRD t RRDW981216BHPublication Release Date: October 2000- 21 - Revision A1Operating Timing Example, continedInterleaved Bank Read (Burst Length = 8, CAS Latency = 3)t RRDW981216BH- 22 -Operating Timing Example, continedInterleaved Bank Read (Burst Length = 8, CAS Latency = 3, Autoprecharge)W981216BHPublication Release Date: October 2000- 23 - Revision A1Operating Timing Example, continedInterleaved Bank Write (Burst Length = 8)RRDW981216BH- 24 -Operating Timing Example, continedInterleaved Bank Write (Burst Length = 8, Autoprecharge)W981216BHPublication Release Date: October 2000- 25 - Revision A1Operating Timing Example, continedPage Mode Read (Burst Length = 4, CAS Latency = 3)W981216BH- 26 -Operating Timing Example, continedPage Mode Read / Write (Burst Length = 8, CAS Latency = 3)W981216BHPublication Release Date: October 2000- 27 - Revision A1Operating Timing Example, continedAuto Precharge Read (Burst Length = 4, CAS Latency = 3)(CLK = 100 MHz)CLKDQCKEDQMA0-A9,A11A10BS1WECASRASCSBS0t RCt RCDW981216BH- 28 -Operating Timing Example, continedAuto Precharge Write (Burst Length = 4)t RCt RP t RPW981216BHPublication Release Date: October 2000- 29 - Revision A1Operating Timing Example, continedAuto Refresh Cycle(CLK = 100 MHz)All Banks Prechage Auto RefreshAuto Refresh (Arbitrary Cycle)t RC t RCW981216BH- 30 -Operating Timing Example, continedSelf Refresh Cyclet SBW981216BHPublication Release Date: October 2000- 31 - Revision A1Operating Timing Example, continedBurst Read and Single Write (Burst Length = 4, CAS Latency = 3)t RCDW981216BH- 32 -Operating Timing Example, continedPowerDown Modet SBNOPW981216BHPublication Release Date: October 2000- 33 - Revision A1Operating Timing Example, continedAutoprecharge Timing (Read Cycle)APAPActActQ0Q6Q7t RPW981216BH- 34 -Operating Timing Example, continedAutoprecharge Timing (Write Cycle)D1D3D7(1) CAS Latency=2When the Auto precharge command is asserted, the period from Bank Activate command to the start of internal precgarging must be at least tRAS (min).represents the Write with Auto precharge command.represents the start of internal precharging.represents the Bank Activate command.Note )W981216BHPublication Release Date: October 2000- 35 - Revision A1Operating Timing Example, continedTiming Chart of Read to Write CycleTiming Chart of Write to Read CycleW981216BH- 36 -Operating Timing Example, continedTiming Chart of Burst Stop Cycle (Burst Stop Command)Timing Chart of Burst Stop Cycle (Precharge Command)PRCGW981216BHPublication Release Date: October 2000- 37 - Revision A1Operating Timing Example, continedCKE/DQM Input Timing (Write Cycle)W981216BH- 38 -Operating Timing Example, continedCKE/DQM Input Timing (Read Cycle)W981216BHPublication Release Date: October 2000- 39 - Revision A1Operating Timing Example, continedSelf Refresh/Power Down Mode Exit TimingW981216BH- 40 -PACKAGE DIMENSION54L TSOP (II)-400 milW981216BHPublication Release Date: October 2000- 41 - Revision A1No. 4, Creation Rd. III,/11F, No. 115, Sec. 3, MinUnit 9Winbond Memory Lab.TEL: 408HeadquartersScience -Based Industrial Park,Hsinchu, TaiwanTEL: 886-3-5770066FAX: 886-3-5796096Voice & Fax -on -demand: 886-2-27197006Taipei Office-Sheng East Rd.,Taipei, TaiwanTEL: 886-2-27190505FAX: 886-2-27197502 Winbond Electronics (H.K.) Ltd.-15, 22F, Millennium City, No. 378 Kwun Tong Rd; Kowloon, Hong Kong TEL: 852-********FAX: 852-********Winbond Electronics North America Corp.Winbond Microelectronics Corp.Winbond Systems Lab.2727 N. First Street, San Jose,CA 95134, U.S.A.-9436666FAX: 408-5441798Note: All data and specifications are subject to change withou t notice.。

北京科瑞兴业 16 位多功能数据采集卡说明书

KPCI-1816 16位多功能数据采集卡使用说明书北京科瑞兴业科技有限公司北京科瑞兴业科技有限公司地址：北京市海淀区知春里28号开源商务写字楼212/213室邮政编码：100086 电话：010-******** 010-******** 传真：010-********Sales E-mail: sgq@ Tech Support E-mail: lilanzhen007@目录第一章概述1、介绍2、应用3、性能和技术指标4、软件支持第二章主要元件位置图、信号输出插座和开关跳线选择定义1、主要元件布局图2、短路套设置3、信号输入输出插座定义4、模拟信号输入连接方式及应注意的问题第三章函数模块调用说明1．A/D 采集过程流程图2．函数说明第四章KPCI-1816的校准、保修和注意事项1. 注意事项2. 校准3. 保修第一章概述一、介绍KPCI-1816是一款PCI总线的16位多功能采集卡，其先进的电路设计使它具有更高的质量和功能。

卡上具有16位16路模拟量采集通道，16位2路模拟量输出通道和16路开关量输入通道以及16路开关量输出通道，同时还有3路计数通道，特别适合需要采集和控制多种信号的用户使用。

KPCI-1816卡上的16位精度的模拟量采集通道和模拟量输出通道，满足了用户在具有高精度要求的场合，完成对模拟量信号的采集和控制。

KPCI-1816卡上带有程控增益放大电路，通过软件可以设定不同的输入范围，±10V, ±5V, ±2.5V, ±1.25V,±0.625V, 0~10V, 0~5V, 0~2.5V, 0~1.25V, 0~0.625V的多种选择，方便了用户对不同信号的测量要求。

KPCI-1816卡的最高采集频率可达200K/S，卡上带有4K容量的FIFO存储，可以完成大量信号的采集和存储，定时触发、软件触发和外触发三种方式，以适应不同场合的数据采集，方便了用户的使用。

75176B中文资料

75176B中⽂资料PACKAGING INFORMATION Orderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SN65176BD ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BDE4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BDR ACTIVE SOIC D82500Green(RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BDRE4ACTIVE SOIC D82500Green(RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BDRG4ACTIVE SOIC D82500Green(RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN65176BP ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N/A for Pkg TypeSN65176BPE4ACTIVE PDIP P850Pb-Free (RoHS)CU NIPDAU N/A for Pkg TypeSN75176BD ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BDE4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BDR ACTIVE SOIC D82500Green(RoHS& no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BDRE4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BDRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BP ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeSN75176BPE4ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeSN75176BPSR ACTIVE SO PS82000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN75176BPSRG4ACTIVE SO PS82000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /doc/7167b986cc22bcd126ff0c93.html /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die andpackage,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak soldertemperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATIONDevice Package Pins Site ReelDiameter(mm)ReelWidth(mm)A0(mm)B0(mm)K0(mm)P1(mm)W(mm)Pin1QuadrantSN65176BDR D8FMX33012 6.4 5.2 2.1812Q1 SN75176BDR D8FMX33012 6.4 5.2 2.1812Q1 SN75176BPSR PS8MLA330168.2 6.6 2.51216Q1TAPE AND REEL BOX INFORMATIONDevice Package Pins Site Length(mm)Width(mm)Height(mm)SN65176BDR D8FMX338.1340.520.64SN75176BDR D8FMX338.1340.520.64SN75176BPSR PS8MLA342.9336.628.58。

S-816资料

(Ta=25°C unless otherwise specified) Absolute Maximum Ratings Unit V VSS−0.3 to VSS+18 V VSS−0.3 to VSS+18 VSS−0.3 to VSS+18 VSS−0.3 to VIN+0.3 50 250 (When not mounted on board) 600*1 −40 to +85 −40 to +125 V V mA mW mW °C °C
Product Name S-816A43AMC-BAST2G S-816A44AMC-BATT2G S-816A45AMC-BAUT2G S-816A46AMC-BAVT2G S-816A47AMC-BAWT2G S-816A48AMC-BAXT2G S-816A49AMC-BAYT2G S-816A50AMC-BAZT2G S-816A51AMC-BBAT2G S-816A52AMC-BBBT2G S-816A53AMC-BBCT2G S-816A54AMC-BBDT2G S-816A55AMC-BBET2G S-816A56AMC-BBFT2G S-816A57AMC-BBGT2G S-816A58AMC-BBHT2G S-816A59AMC-BBIT2G S-816A60AMC-BBJT2G
元器件交易网
Rev.5.1_00
EXTERNAL TRANSISTOR TYPE CMOS VOLTAGE REGULATOR
S-816 Series
The S-816 Series consists of external transistor type positive voltage regulators, which have been developed using the CMOS process. These voltage regulators incorporate an overcurrent protection, and shutdown function. A low drop-out type regulator with an output current ranging from several hundreds of mA to 1 A can be configured with the PNP transistor driven by this IC. Despite the features of the S-816, which is low current consumption, the improvement in its transient response characteristics of the IC with a newly deviced phase compensation circuit made it possible to employ the products of the S-816 Series even in applications where heavy input variation or load variation is experienced. The S-816 Series regulators serve as ideal power supply units for portable devices when coupled with the SOT-23-5 minipackage, providing numerous outstanding features, including low current consumption. Since this series can accommodate an input voltage of up to 16 V, it is also suitable when operating via an AC adapter.

I／O扩展芯片GM8166的原理与应用

I／O扩展芯片GM8166的原理与应用帷誉三很多设计人员在开发单片}几应用系统时常常会遇到1t0口不够用的情况,此时一般采用的解决方案是利用74HC573,74LS164,74LS165,82C55等芯片来实现I/0扩展,但如果待开发的系统需要使用大量的UO口,使用上述器件就将存在PCB面积增大,成本高等缺点.成都国腾微电子有限公司开发的GM8166芯片通过串人并出,并入申出并人并出转换完成IIO口的扩展I/O口为双向口,最高工作频率为】0MHz,可配合MCU完成对多个外围电路的控制和信号采集工作.1/O口最大OC/EN:并行输出,输入允许控制信号,LE:并行输出数据锁存信号;Sel:接入SPI总线控制信号;ModSel:井串/串井转换模式和井口切换模式选择信号SP/Mux:井串和串井转换选择信号或1路输入3路输出和3路输人1路输出模式选择信号M0,Ml:工作方式控制信号,选择工作的I/O端口PData:32位输入/输出数据口Ilt1I¨糕穗,并串转换功能为井口比较紧张的系统通过串口扩展32位并行口井口切换功能可以将1组8位并口扩展成3组8位并口,通过控制信号在3组并口中切换完成输八,输出功能,SPI总线功能使该芯片可以接人SPI总线中作为从设备进行数据收/发,同样完成串并转换的功能.用户在只使用以上三种功能中的一种时.可以将某些不需要的控制引脚接人固定电平,无需占用系统资源. (详细情况查看成都国腾微电子有限公司发布的GM8】66 产品资料】GM8166与MCU接口及编程应用串并转换典型应用单片机扩展UOgl可以通过串行口工作方式O来实现,图2是单片机通过串口扩展b'O口时与GM8166的按I:1框图.此电路利用单片机89C51串口工作方式0来进行单片机的I/0口电路的扩展.GM8166的各个控制引脚由89C51控制,可在GM8166的各工作模式间进行转换.若只需使用一种或几种工作模式,可将不用的控制引脚置入所需电平,无需接八MCU,例如此例中因为只用1片GM8166,所以将CSN固定接地,同时GM8166只工作在串并/并串转换模式下,所以将ModSel引脚固定接地. Sel目『脚固定接高电平.软件示例(以C51为例):,●蕾4?2004.3,下半月I誊哥矗矗t量 #include<reg5lh>/I,O定义}}$$$sbitSP=PI0:串并/并串模式选择信号sbitMl=P1t;工作方式控制信号1sbitMO=P12//工作方式控制信号0sbitOC=P13:,,并行输出/输人允许信号sbitLE=PI4://并行输出数据锁存信号sbitCLK=P31:,数据变量定义}}$,unsignedcharSendBuff_4J={Oxff,0xff,0x67,Oxbc); unsignedcharReceiveBuff【2]={0x00,OxO0}; unsignedchari=O,j---o:/主程序}}$}{}}}$}$,voldmain(void)(SCON=0x00;//设置MCU串行口工作方式为方式0PC0N--0x00;32位串人井出转换/S—P=I;M1=1:M0=I;设定GM8166工作模式为32位的串人并出模式OC=1;∥输出禁止LE=I:,,输出锁存开如r(I_0:l<4:l++)(SBUF=SendBuff【il;发送数据到GM8166while(Tl~0):TI=0;)LE---O:输出数据锁存OC--.O;,,输出允许/16位并人串出转换/S—P=o:M1=1;M0=0设定GM81667-作模式为16位的并入串出模式OCt;并行输入允许CLK--0:CLK=I//并行口数据置人寄存器OC=1;//并行输人禁止for0=O也0¨)(REN=Iwhile(RI一0);ReceiveBuff[jI=SBUF;串行数据输人89C51RI=0:REN--0;))GM8166设计了SPI总线接口,可接人SPI总线作为从设备进行数据传输.使用该功能时Sel和ModSel引脚囡接低电平,其他不用的控制线也可以根据需要接人固定电平.串入井出时工作方式为SPI传输模式中的CPOL--0,CPHA=O时的模式,并人串出时工作方式为SPI 传输模式中的CPOL=I,CPHA=0时的模式,CSN为总线片选信号.因为该芯片并行输人采用同步方式,所以在进行并人串出转换时,CSN置'0'后,必须先将OC/EN信号置'0'时,同时提供一个时钟上升沿,将输八端日数据井行保存到移位寄存器中,然后将Oc,EN信号置'1'.之后主机才能启动传输(此方式和不接人SPI时相同)当用户系统需要的1/O口超过32位时,可用多片GM8166级连实现缎连方法简单,将上一级8166的SDataIq与MCU的串Iq相接,CData口与下一级8166的SData口相接即可.并口切换功能应用GM8166提供并口切换输入,输出功能,利用该项功能,可以实现3路8位IZl的开关切换.以89C51单片机为例,硬件接KI示例目见图3.软件示例(C5l为例):VcSePSP/IqexePl10M1(1srPPocIENP.1LE89C5lG-8166P1.5CLKPData口:O】PO#include<reg51h>,I,O定义十{}$}$}{}{十十}十,sbitMux=PI0;//1路输人3路输出和3路输入I路输出选择信号sbitMI=PII:flGM81~的工作方式控制信号1sbitM0=PI2:GM8166的工作方式控制信号0sbitOC=PI3;//并行输出允许信号sbitLE=P14;并行输出数据锁存信号sbitCLK=Pl^5;,/l耐钟信号,}}}}{}{十+{主程序}}}}}十}}$}$}$}$voidmain(void){1路输八,3路选择输出tMux=0;∥选择l路输入.3路输出模式M1=l:M0=0;//选择1/0115:8]口输出OC=1:,,禁止输出LE=I;,,输出锁存开P0--0xaa;/,TO口输出数据CLK=0:CLK=I;数据置人寄存器LE=O;,,并行输出数据锁存OC=0;并行输出允许开Ml=0:2004.3,下半月?誊昔矗二t暴?65//选择I/O[23:16]口输出//P0口输出数据CLK=I;//数据置入寄存器LE=1;//并行输出数据进入锁存器LE=0;//并行输出数据锁存3路选择输入,1路输出/Mux=1;//选择3路输入,1路输出模式M1=1;M0=1;//选择I/O[31:24]口输入OC=I;//禁止输出LE=1;//输出锁存开CLK=0;CLK=I;//数据置入寄存器LE=0;//并行输出数据锁存OC=0;//并行输出允许开结语GM8166性能稳定,速度高,使用方法灵活,软件编程简单,适合于大多数单片机应用系统使用,可广泛应用于以下领域:通信设备:IC卡话机,雷达控制;安防电路:报警器,消防控制;仪器仪表:电表控制,多路采集;工业控制:印刷机械控制,注塑机控制,机车控制,相机控制;金融机具:POS机,IC卡机具GM8164在LED显示屏,Ic卡话机等I/O密集形应用中.该芯片不足之处在于由于功能多,所以控制线稍显复杂,但使用过程中多数控制线可根据需要接固定电平, 不需要占用MCU资源.其次,32位I/O口只能同为输入口或同为输出口,对于某些应用不太方便.■Il器也能测量100MHz的正弦波.由于方波之中有部分高频波的频率比基本频率高很多倍,因此示波器必须提供远远超过100MHz的输入带宽才可测量100MHz的方波.取样时若带宽不足,便会遗失原来信号的高频部分及振幅.这样,方波便无法以方波的形状显示在示波器的屏幕上.取样率是A/D转换器将模拟信号转为数字信号的速率.取样率越高,高频信号便可更精确地复原.例如,以1GSPS取样率复原的100MHz信号比以500MHz取样率复原的同一信号更接近原来的信号.因此,像ADC081000这类高取样率,高输入带宽及低位错误率(BER)的数字模拟转换器是将高频信号数字化的理想转换器,最适用于系统的设计及测试.测试设备厂商可以利用这款A/D转换器开发成本低廉的高性能测试设备. 直接将射频或中频下变频的数字接收器在工作原理上,数字接收器与超外差接收器非常相似.但多年来A/D转换技术的发展一日千里,令接收器可以更大量采用数字集成电路.当然接收器的数字电路越靠近天线,便越能发挥接收的优势.因此有人认为可将A/D 转换器置于射频系统的输出端,以便直接进行射频取样. 66?2004.3/'F~,q雷号煮品t摹,II,,II,,II,.eepw.corn.en这个设计看似合理,但会产生另一个问题,我们不得不加以考虑.为了能够预先抑制不需要的带外信号,以及满足A/D转换器所要求的频率范围,已接收的信号在输入A/D 转换器之前必须先加以滤波,以及接受自动增益控制.因此很多数字接收器采用折衷的办法,先由输出端的第一及第二中频级将模拟信号转为数字信号,使带外信号还未进入A/D转换器之前先行接受滤波,也确保部分信号在未进入A/D转换器之前先行在模拟级接受自动增益控制,以尽量避免带内信号过驱动A/D转换器,使信号在进行D转换之前可以达到最大的信号增益.此外,我们若采用中频取样及数字接收技术,便无需另外加设中频级如混频器,滤波器及放大器,可以降低成本,而且系统设计工程师若采用可编程数字滤波器取代固定的模拟滤波器,便可充分发挥设计上的灵活性. 由于1.8GHz的ADC081000芯片可提供3dB的带宽,因此最适用于射频或中频的直接取样.这款转换器芯片可大幅减少所需昂贵模拟芯片的数目,有助减低系统的总体成本.此外,即使采用远比尼奎斯特规定还要高的输入频率操作,总谐波失真也可保持在较低的水平,让卫星接收等取样率不足的系统也可正常工作.■。

VersaView 6300B 壁挂箱式 PC 安装指南说明书

安装指南VersaView 6300B 壁挂箱式 PCBulletin 编号 6300B-PBCx、6300B-PBDx环境和机壳信息符合 UL/cUL 标志要求带有 UL/cUL 标志的设备符合 UL 61010-1、UL 61010-2-201、CSA C22.2 No.61010-1 和 CSA C22.2 No.61010-2-201 的要求。

合格证副本可在rok.auto/certifications 上获得。

符合欧盟指令当在欧盟或欧洲经济区安装并带有 CE 标志时，该计算机满足欧盟指令的要求。

符合性声明的副本可在 rok.auto/certifications 网站上查阅。

安装指南遵守这些指南，以确保您的计算机在工作时高度可靠。

•在选择安装地点时，应考虑以下几点：-该地点必须提供充足的电力-场地必须在室内，且无危险性。

-该地点不得使电脑直接暴露在阳光下•计算机可在周围空气温度范围内工作，具体如下：-0...50℃ (32...122°F)，适用于安装英特尔酷睿 i3 处理器的6300B-PBCx 壁挂箱式 PC -0...45℃ (32...113°F)，适用于安装英特尔酷睿 i7 处理器的6300B-PBCx 壁挂箱式 PC -0...50℃ (32...122°F)，适用于安装英特尔酷睿 i3 和 i7 处理器的6300B-PBDx 壁挂箱式 PC周围的空气温度不能超过计算机的最高温度，特别是当计算机安装在机壳中时。

•计算机可以存储在 -10...+60℃ (14...140°F)的周围空气温度范围内。

•周围空气的湿度不得超过 80% 无凝露。

注意：本设备适合在污染等级 2 工业环境、过电压 II 类应用（IEC 60664-1 中有规定）中使用，在海拔 2000 米（6561 英尺）以下使用时不降额。

按照 IEC/EN 61326-1 的规定，本设备属于 1 组、A 类工业设备。

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BULIT-IN BLINKING IC.
!OPERATION VOLTAGE FROM 3.5V to 14V. !BLINKING FREQUENCY FROM 3.0Hz to 1.5Hz.
Package Dimensions
Notes: 1. All dimensions are in millimeters (inches). 2. Tolerance is ±0.25(0.01") unless otherwise noted. 3. Lead spacing is measured where the lead emerge package. 4. Specifications are subject to change without notice.
Notes: 1. θ1/2 is the angle from optical centerline where the luminous intensity is 1/2 the optical centerline value.
ectrical / Optical Characteristics at T)=25°C °
nm
IF
V
VF=3.5V ~ 14V
I
S ON
Supply Current
mA
VF=3.5V ~ 14V
f
Blink Frequency
Hz
F=3.5V ~ 14V
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
λpeak
Peak Wavelength
nm
λD
Dominate Wavelength
nm
∆λ1/2
High Efficiency Red en Spectral Line Halfwidth Greow Yell Super Bright Red Forward Current High Efficiency Red Green Yellow Super Bright Red High Efficiency Red Green Yellow Super Bright Red All
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
PAGE: 1 OF 5
元器件交易网
Selection Guide
P ar t N o . L816BID L816BGD L816BYD L816BSRD/B L816BSRC/B Dic e HIGH EFFICIENCY RED (GaAsP/GaP) GREEN (GaP) YELLOW (GaAsP/GaP) SUPER BRIGHT RED (GaAlAs) SUPER BRIGHT RED (GaAlAs) L en s Ty p e RED DIFFUSED GREEN DIFFUSED YELLOW DIFFUSED RED DIFFUSED WATER CLEAR Iv (m c d ) @ VF=9V Min . 20 20 20 100 500 Ty p . 60 50 40 30 0 80 0 V i ew i n g An g l e 2θ1/2 60 ° 60 ° 60 ° 60 ° 40°
PAGE: 2 OF 5
元器件交易网
Absolute Maximum Ratings at T)=25°C °
Par am et er Power dissipation DC Forward Current VF=14V Reverse Voltage Operating Temperature Storage Temperature Lead Soldering Temperature [1]
S u p er B r i g h t R ed 3 10 55 0.5
Un it s mW mA V
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
PAGE: 3 OF 5
元器件交易网
Notes: 1. 1/10 Duty Cycle, 0.1ms Pulse Width.
H i g h E f f i c i en c y R ed 3 10 55 0.5
Gr een 3 10 55 0.5
Yello w 3 10 55 0.5 -40°C To +70°C -50°C To +100°C 260°C For 5 Seconds
元器件交易网
10mm BLINKING LED LAMPS
L816BID HIGH EFFICIENCY RED L816BGD GREEN L816BYD YELLOW L816BSRC/B SUPER BRIGHT RED L816BSRD/B SUPER BRIGHT RED
High Efficiency Red L816BID
Green L816BGD
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
PAGE: 4 OF 5
元器件交易网
Yellow L816BYD
Super Bright Red L816BSRD/B,L816SRC/B
SPEC NO: DSAA4471 APPROVED: J.Lu
REV NO: V.1 CHECKED:
DATE: OCT/10/2001 DRAWN: X.H.Fu
PAGE: 5 OF 5
Symbol Par am et er D ev i c e High Efficiency Red Green Yellow Super Bright Red High Efficiency Red Green Yellow Super Bright Red Min . 627 565 590 660 625 568 588 640 45 30 35 20 8 8 8 8 22 20 21 25 8 ~ 44 8 ~ 42 8 ~ 43 8 ~ 45 3 ~ 1.5 Ty p . Un it s Tes t Co n d it io n s
Features
!T-1 3/4 PACKAGE !WITH
Description
The High Efficiency Red source color devices are made with Gallium Arsenide Phosphide on Gallium Phosphide Orange Light Emitting Diode. The Green source color devices are made with Gallium Phosphide Green Light Emitting Diode. The Yellow source color devices are made with Gallium Arsenide Phosphide on Gallium Phosphide Yellow Light Emitting Diode. The Super Bright Red source color devices are made with Gallium Aluminum Arsenide Red Light Emitting Diode.