FPGA可编程逻辑器件芯片5CEFA5F23I7N中文规格书

(33) REFCLK performance requires to meet transmitter REFCLK phase noise specification.
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Cyclone V Device Datasheet CV-51002 | 2019.11.27
Table 22. Transceiver Clocks Specifications for Cyclone V GX, GT, SX, and ST Devices
PCIe
30
—
33
30
—
33
30
—
33
kHz
Spread-spectrum downspread
PCIe
—
0 to –
—
—
0 to –
—
—
0 to –
—
—
0.5%
0.5%
0.5%
On-chip termination resistors
—
—
100
—
—
100
—
—
100
—
Ω
continued...
(30) Transceiver Speed Grade 5 covers specifications for Cyclone V GT and ST devices.
—
differential signal(33)
—
400
—
—
400
—
—
400
ps
Duty cycle
—
45
—
55
45
—
55
45
—
55
%
Peak-to-peak differential input voltage
—
200
—
2000
200
—
2000
200
—
2000
mV
Spread-spectrum modulating clock frequency
Max
Input frequency from REFCLK input pins(32)
—
27
—
550
27
—
550
27
—
550
MHz
Rise time
Measure at ±60 mV of
—
differential signal(33)
—
400
—
—
400
—
—
400
ps
Fall time
Measure at ±60 mV of
Table 21. Reference Clock Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30) Transceiver Speed Grade 6
Min
Typ
Max
Min
Typ
Max
Supported I/O standards
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS
Data rate(38)
—
614
—
5000/614
614
—
3125
4(35)
Absolute VMAX for a receiver
—
pin(39)
Cyclone V Device Datasheet CV-51002 | 2019.11.27
Transceiver Performance Specifications
Transceiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
Min
Typ
Max
Min
Typ
Max
fixedclk clock frequency PCIe Receiver Detect
—
125
—
—
(31) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
(32) The reference clock frequency must be ≥ 307.2 MHz to be fully compliance to CPRI transmit jitter specification at 6.144 Gbps. For more information about CPRI 6.144 Gbps, refer to the Transceiver Protocol Configurations in Cyclone V Devices chapter.
15
—
—
µs
continued...
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Cyclone V Device Datasheet CV-51002 | 2019.11.27
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Cyclone V Device Datasheet CV-51002 | 2019.11.27
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Cyclone V Device Datasheet CV-51002 | 2019.11.27
Transceiver Speed Grade 7
Min
Typ
Max
110
—
—
Unit mV
—
85
—
Ω
—
100
—
Ω
—
120
—
Ω
—
150
—
Ω
VCCE_GXBL supply
V
V
—
—
10
µs
—
—
4
µs
—
—
4
µs
tLTR(42) tLTD(43) tLTD_manual(44) tLTR_LTD_manual(45)
Condition —
Transceiver Speed Grade 5(30)
Min
Typ
Max
110
—
—
Transceiver Speed Grade 6
Min
Typ
Maetting 100-Ω setting 120-Ω setting 150-Ω setting 2.5 V PCML, LVPECL,
—
2500
Mbps
—
1.2
V
—
—
V
—
1.6
V
—
—
2.2
V
continued...
(37) The maximum supported clock frequency is 100 MHz if the PCIe hard IP block is enabled or 125 MHz if the PCIe hard IP block is not enabled.
—
—
1.2
—
—
1.2
Absolute VMIN for a receiver
—
pin
–0.4
—
—
–0.4
—
—
Maximum peak-to-peak
—
differential input voltage
VID (diff p-p) before device configuration
—
—
1.6
—
—
7)
Unit
MHz MHz
Table 23. Receiver Specifications for Cyclone V GX, GT, SX, and ST Devices
Symbol/Description
Condition
Transceiver Speed Grade 5(30)
Transceiver Speed Grade 6
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Symbol/Description
Minimum differential eye opening at the receiver serial input pins(40) Differential on-chip termination resistors
VICM (AC coupled)
125
—
Transceiver Reconfiguration
—
Controller IP
(mgmt_clk_clk) clock
frequency
75
—
100/125(3
75
—
100/125(
7)
37)
Transceiver Speed Grade 7
Min
Typ
Max
—
125
—
75
—
100/125(3
1.6
Maximum peak-to-peak
—
differential input voltage
VID (diff p-p) after device configuration
—
—
2.2
—
—
2.2
Transceiver Speed Grade 7
Min
Typ
Max
Unit
614 — –0.4 —
and LVDS 1.5 V PCML
— — — —
—
85
—
—
100
—
—
120
—
—
150
—
VCCE_GXBL supply(34)(35)
—
—
10
—
—
4
—
—
4
15
—
—
—
85
—
—
100
—
—
120
—
—
150
—
VCCE_GXBL supply
0.65/0.75/0.8 (41)
—
—
10
—
—
4
—
—
4
15
—
—
Transceiver Speed Grade 7
Unit
Supported I/O standards
Min
Typ
Max
Min
Typ
Max
Min
Typ
1.2 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL(31), HCSL, and LVDS
(38) To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.
(39) The device cannot tolerate prolonged operation at this absolute maximum.