74LVC245APW
SN74LVC244APWR中文资料
TA –40°C to 85°C
–40°C to 125°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER
QFN – RGY
Reel of 1000
SN74LVC244ARGYR
VFBGA – GQN Reel of 1000
Copyright © 1992–2005, Texas Instruments Incorporated
元器件交易网
SN74LVC244A OCTAL BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCAS414X – NOVEMBER 1992 – REVISED MARCH 2005
at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2 V
at VCC = 3.3 V, TA = 25°C • Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC) • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 250 mA Per JESD 17 • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A)
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
74lvc245中文说明
74LV245是低压硅栅CMOS器件，与74HC245和74HCT245针脚和功能兼容。
74LV245是八位元收发器，在发送和接收方向上都具有非反相3态总线兼容输出。
发送/接收(DIR)输入控制方向，而输出使能(OE)输入则可实现轻松级联。
针脚OE控制输出，因此总线可以得到有效隔离。
特性和优势
•宽工作电压范围：1.0 V至5.5 V
•最适合低压应用：1.0 V至3.6 V
•接受介于VCC = 2.7 V和VCC = 3.6 V之间的TTL输入电平
•VCC = 3.3 V且T amb = 25 °C时的典型输出地弹：< 0.8 V
•VCC = 3.3 V且T amb = 25 °C时的典型高电平输出电压(VOH)欠冲：> 2 V •ESD保护：
o HBM JESD22-A114E超过2000 V
o MM JESD22-A115-A超过200 V
•多种封装选择
•额定温度范围为-40 °C至+85 °C和-40 °C至+125 °C
外形图
显示功能框图
真值表
INPUTS INPUTS/OUTPUT OE DIR An Bn
H=高电压L=低电压X=无输入、Z=高阻态。
74LVC245A; 74LVCH245A 八位总线收发器; 3-state 产品数据手册说明书
74LVC245A; 74LVCH245AOctal bus transceiver; 3-stateRev. 9 — 11 September 2018Product data sheet1. General descriptionThe 74LVC245A; 74LVCH245A are 8-bit transceivers featuring non-inverting 3-state buscompatible outputs in both send and receive directions. The device features an output enable(OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls theoutputs so that the buses are effectively isolated.Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied tothe outputs. These features allow the use of these devices in mixed 3.3 V and 5 V applications.The 74LVCH245A bus hold on data inputs eliminates the need for external pull-up resistors to holdunused inputs.2. Features and benefits• 5 V tolerant inputs/outputs for interfacing with 5 V logic•Wide supply voltage range from 1.2 V to 3.6 V•CMOS low-power consumption•Direct interface with TTL levels•Inputs accept voltages up to 5.5 V•High-impedance when V CC = 0 V•Bus hold on all data inputs (74LVCH245A only)•Complies with JEDEC standard:•JESD8-7A (1.65 V to 1.95 V)•JESD8-5A (2.3 V to 2.7 V)•JESD8-C/JESD36 (2.7 V to 3.6 V)•ESD protection:•HBM JESD22-A114F exceeds 2000 V•MM JESD22-A115B exceeds 200 V•CDM JESD22-C101E exceeds 1000 V•Specified from -40 °C to +85 °C and -40 °C to +125 °C3. Ordering information4. Functional diagram5. Pinning information5.1. Pinning74LVC245A 74LVCH245ADIR V CC A0OE A1B0A2B1A3B2A4B3A5B4A6B5A7B6GND B7001aak2921234567891012111413161518172019Fig. 3.Pin configuration SOT163-1 (SO20),SOT339-1 (SSOP20) and SOT360-1 (TSSOP20)001aak29374LVC245A 74LVCH245AT ransparent top viewB6A6A7B5A5B4A4B3A3B2A2B1A1B0A0OE G N D B 7D I R V C C9128137146155164173182191011120terminal 1 index areaGND (1)(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND.Fig. 4.Pin configuration SOT764-1 (DHVQFN20)5.2. Pin description6. Functional descriptionTable 3. Function selectionH = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high impedance OFF-state.7. Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).[1]The minimum input voltage ratings may be exceeded if the input current ratings are observed.[2]The output voltage ratings may be exceeded if the output current ratings are observed.[3]For SO20 packages: above 70 °C derate linearly with 8 mW/K.For (T)SSOP20 packages: above 60 °C derate linearly with 5.5 mW/K.For DHVQFN20 packages: above 60 °C derate linearly with 4.5 mW/K.8. Recommended operating conditions9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions. Voltages are referenced to GND (ground = 0 V).[1]All typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb = 25 °C.[2]The bus hold circuit is switched off when V I ˃ V CC allowing 5.5 V on the input terminal.[3]For I/O ports the parameter I OZ includes the input leakage current.[4]Valid for data inputs of bus hold parts only (74LVCH245A). Note that control inputs do not have a bus hold circuit.[5]The specified sustaining current at the data input holds the input below the specified V I level.[6]The specified overdrive current at the data input forces the data input to the opposite input state.10. Dynamic characteristicsTable 7. Dynamic characteristicsVoltages are referenced to GND (ground = 0 V). For test circuit see Fig. 7.[1]Typical values are measured at T amb = 25 °C and V CC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively.[2]t pd is the same as t PLH and t PHL.t en is the same as t PZL and t PZH.t dis is the same as t PLZ and t PHZ.[3]Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.[4]C PD is used to determine the dynamic power dissipation (P D in μW).P D = C PD × V CC2 × f i × N + Σ(C L × V CC2 × f o) where:f i = input frequency in MHz; f o = output frequency in MHzC L = output load capacitance in pFV CC = supply voltage in VoltsN = number of inputs switchingΣ(C L × V CC2 × f o) = sum of the outputs.10.1. Waveforms and test circuit11. Package outlineSO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1Fig. 8.Package outline SOT163-1 (SO20)SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1Fig. 9.Package outline SOT339-1 (SSOP20)TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1Fig. 10.Package outline SOT360-1 (TSSOP20)DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;Fig. 11.Package outline SOT764-1 (DHVQFN20)12. Abbreviations13. Revision history14. Legal informationData sheet status[1]Please consult the most recently issued document before initiating orcompleting a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available onthe internet at https://.DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. 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Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitableand fit for the customer’s applications and products planned, as well asfor the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). 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Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.Terms and conditions of commercial sale — Nexperia products aresold subject to the general terms and conditions of commercial sale, as published at /profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. 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Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications.In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications.Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions.TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.Contents1. General description (1)2. Features and benefits (1)3. Ordering information (2)4. Functional diagram (2)5. Pinning information (3)5.1. Pinning (3)5.2. Pin description (3)6. Functional description (3)7. Limiting values (4)8. Recommended operating conditions (4)9. Static characteristics (5)10. Dynamic characteristics (7)10.1. Waveforms and test circuit (8)11. Package outline (10)12. Abbreviations (14)13. Revision history (14)14. Legal information (15)© Nexperia B.V. 2018. All rights reservedFor more information, please visit: Forsalesofficeaddresses,pleasesendanemailto:*************************** Date of release: 11 September 2018Mouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:N experia:74LVC245AD74LVCH245AD74LVCH245ADB74LVCH245APW74LVC245APW74LVC245ABQ,115 74LVC245AD,11274LVC245ADB,11274LVC245ADB,11874LVC245AD,11874LVC245APW,11274LVC245APW,11874LVCH245ABQ,11574LVCH245AD,11274LVCH245ADB,11274LVCH245ADB,118 74LVCH245AD,11874LVCH245APW,11274LVCH245APW,11874LVC245ABX,11574LVCH245ABX,115 74LVCH245APW/AUJ74LVC245APW/AUJ。
SN74LVC8T245DBQR中文资料
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCCA VCCB
Supply voltage range
VI
Input voltage range(2)
VO
Voltage range applied to any output in the high-impedance or power-off state(2)
This 8-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74LVC8T245 is optimized to operate with VCCA and VCCB set at 1.65 V to 5.5 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5.5-V voltage nodes.
Isolation
(1) Input circuits of the data I/Os are always active.
74LVC245A_04中文资料
1/12July 2004s 5V TOLERANT INPUTSs HIGH SPEED: t PD = 6.3ns (MAX.) at V CC = 3V sPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN) at V CC = 3Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 1.65V to 3.6V (1.2V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245sLATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)sESD PERFORMANCE:HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74LVC245A is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for 1.65 to 3.6V CC operations and low power and low noise applications.This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated.It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.All floating bus terminals during High Z State must be held HIGH or LOW.74LVC245ALOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(NOT INVERTED) HIGH PERFORMANCE.Table 1: Order CodesPACKAGE T & R SOP 74LVC245AMTR TSSOP74LVC245ATTR74LVC245A2/12Figure 2: Input And Output Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareZ : High ImpedanceTable 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied1) I O absolute maximum rating must be observed 2) V O< GNDPIN N°SYMBOL NAME AND FUNCTION 1DIR Directional Control 2, 3, 4, 5, 6, 7, 8, 9A1 to A8Data Inputs/Outputs 18, 17, 16, 15, 14, 13, 12, 11B1 to B8Data Inputs/Outputs19GOutput Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTS FUNCTION OUTPUT G DIR A BUSB BUSYn L L OUTPUT INPUT A = B L H INPUT OUTPUT B = A HXZ ZZSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage-0.5 to +7.0V V O DC Output Voltage (High Impedance or V CC = 0V)-0.5 to +7.0V V O DC Output Voltage (High or Low State) (note 1)-0.5 to V CC + 0.5V I IK DC Input Diode Current- 50mA I OK DC Output Diode Current (note 2)- 50mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current per Supply Pin± 100mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°C74LVC245A3/12Table 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.2V to 3.6V 2) V IN from 0.8V to 2V at V CC = 3.0VTable 6: DC SpecificationsSymbol ParameterValue Unit V CC Supply Voltage (note 1) 1.65 to 3.6V V I Input Voltage0 to 5.5V V O Output Voltage (High Impedance or V CC = 0V)0 to 5.5V V O Output Voltage (High or Low State)0 to V CC V I OH , I OL High or Low Level Output Current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or Low Level Output Current (V CC = 2.7 to 3.0V)± 12mA I OH , I OL High or Low Level Output Current (V CC = 2.3 to 2.7V)±8mA I OH , I OL High or Low Level Output Current (V CC = 1.65 to 2.3V)±4mA T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2)0 to 10ns/VSymbolParameterTest ConditionValueUnitV CC (V)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.V IHHigh Level Input Voltage 1.65 to 1.950.65V CC0.65V CC V2.3 to 2.7 1.7 1.72.7 to3.622V ILLow Level Input Voltage1.65 to 1.950.35V CC0.35V CC V 2.3 to 2.70.70.72.7 to 3.60.80.8V OHHigh Level Output Voltage1.65 to 3.6I O =-100 µA V CC -0.2V CC -0.2V1.65I O =-4 mA 1.2 1.22.3I O =-8 mA 1.7 1.72.7I O =-12 mA 2.2 2.23.0I O =-18 mA 2.4 2.43.0I O =-24 mA 2.22.2V OLLow Level Output Voltage1.65 to 3.6I O =100 µA 0.20.2V 1.65I O =4 mA 0.450.452.3I O =8 mA 0.70.72.7I O =12 mA 0.40.43.0I O =24 mA 0.550.55I I Input Leakage Current 3.6V I = 0 to 5.5V ± 5± 5µA I off Power Off Leakage Current0V I or V O = 5.5V 1010µA I OZHigh Impedance Output Leakage Current3.6V I = V IH orV IL V O = 0 to 5.5V ± 10± 10µA I CCQuiescent Supply Current3.6V I = V CC or GND1010µA V I or V O = 3.6 to5.5V± 10± 10∆I CCI CC incr. per Input2.7 to3.6V IH = V CC -0.6V500500µA74LVC245A4/12Table 7: Dynamic Switching Characteristics1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.Table 8: AC Electrical Characteristics1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |2) Parameter guaranteed by designTable 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /n (per circuit)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.V OLP Dynamic Low Level Quiet Output (note 1)3.3C L = 50pFV IL = 0V, V IH = 3.3V0.8V V OLV-0.8SymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.t PLH t PHLPropagation Delay Time1.65 to 1.953010002.0 2.09.0 2.012ns2.3 to 2.730500 2.0 2.08.0 2.010.52.750500 2.5 1.57.3 1.58.83.0 to 3.650500 2.5 1.0 6.3 1.07.6t PZL t PZHOutput Enable Time 1.65 to 1.95301000 2.0 2.012 2.016ns2.3 to 2.730500 2.0 2.09.5 2.012.52.750500 2.5 1.09.0 1.0113.0 to 3.650500 2.5 1.08.5 1.010t PLZ t PHZOutput Disable Time 1.65 to 1.95301000 2.0 2.011 2.014ns2.3 to 2.730500 2.0 2.09.0 2.0122.750500 2.5 2.08.5 2.0103.0 to 3.6505002.52.07.5 2.09.0t OSLH t OSHLOutput To Output Skew Time (note1, 2)2.7 to3.611nsSymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.C IN Input Capacitance4pF C PDPower Dissipation Capacitance (note 1)1.8f IN = 10MHz28pF 2.5303.33474LVC245A5/12Figure 3: Test CircuitR T = Z OUT of pulse generator (typically 50Ω)Table 10: Test Circuit And Waveform Symbol ValueFigure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)SymbolV CC1.65 to 1.95V2.3 to 2.7V 2.7V3.0 to 3.6V C L 30pF 30pF 50pF 50pF R L = R 11000Ω500Ω500Ω500ΩV S 2 x V CC 2 x V CC 6V 6V V IH V CC V CC 2.7V 2.7V V M VCC /2V CC /2 1.5V 1.5V V OH V CC V CC 3.0V 3.0V V X V OL + 0.15V V OL + 0.15V V OL + 0.3V V OL + 0.3V VY V OH - 0.15V V OH - 0.15V V OH - 0.3V V OH - 0.3V t r = t r<2.0ns<2.0ns<2.5ns<2.5ns74LVC245AFigure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)6/1274LVC245A7/12DIM.mm.inch MIN.TYPMAX.MIN.TYP.MAX.A 2.35 2.650.0930.104A10.10.300.0040.012B 0.330.510.0130.020C 0.230.320.0090.013D 12.6013.000.4960.512E 7.47.60.2910.299e 1.270.050H 10.0010.650.3940.419h 0.250.750.0100.030L 0.4 1.270.0160.050k 0°8°0°8°ddd0.1000.004SO-20 MECHANICAL DATA0016022D74LVC245A8/12DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 6.4 6.5 6.60.2520.2560.260E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP20 MECHANICAL DATAcEbA2AE1D1PIN 1 IDENTIFICATIONA1LK e0087225C74LVC245A Tape & Reel SO-20 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T30.4 1.197Ao10.8110.4250.433Bo13.213.40.5200.528Ko 3.1 3.30.1220.130Po 3.9 4.10.1530.161P11.912.10.4680.4769/1274LVC245ATape & Reel TSSOP20 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T22.40.882 Ao 6.870.2680.276 Bo 6.97.10.2720.280 Ko 1.7 1.90.0670.075 Po 3.9 4.10.1530.161 P11.912.10.4680.47610/1274LVC245A Table 11: Revision HistoryDate Revision Description of Changes26-Jul-20044Ordering Codes Revision - pag. 1.11/1274LVC245AInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America12/12。
74LVC245(电压逻辑隔离)
V
0 to 5.5
V
Operating temperature Ta
–40 to 85
°C
Output current
I OH
–12
mA
–24*2
mA
I OL
12
mA
24*2
mA
Input rise / fall time *1
tr, tf
10
ns/V
Notes: 1. This item guarantees maximum limit when one input switches.
Ratings
Unit
Conditions
Supply voltage
VCC
–0.5 to 6.0
V
Input diode current
I IK
–50
mA
Input voltage
VI
–0.5 to 6.0
V
Output diode current
I OK
–50
mA
50
mA
Input / output voltage
Waveform : Refer to test circuit of switching characteristics.
2. duty cycle ≤ 50%
Conditions Data retention At operation T / R, OE Output "H" or "L" Output "Z" or VCC:OFF
2
HD74LVC245A
Recommended Operating Conditions
ST 74LVC245A 数据手册
1/12July 2004s 5V TOLERANT INPUTSs HIGH SPEED: t PD = 6.3ns (MAX.) at V CC = 3V sPOWER DOWN PROTECTION ON INPUTS AND OUTPUTSsSYMMETRICAL OUTPUT IMPEDANCE:|I OH | = I OL = 24mA (MIN) at V CC = 3Vs PCI BUS LEVELS GUARANTEED AT 24 mA sBALANCED PROPAGATION DELAYS:t PLH ≅ t PHLsOPERATING VOLTAGE RANGE:V CC (OPR) = 1.65V to 3.6V (1.2V Data Retention)sPIN AND FUNCTION COMPATIBLE WITH 74 SERIES 245sLATCH-UP PERFORMANCE EXCEEDS 500mA (JESD 17)sESD PERFORMANCE:HBM > 2000V (MIL STD 883 method 3015); MM > 200VDESCRIPTIONThe 74LVC245A is a low voltage CMOS OCTAL BUS TRANSCEIVER (3-STATE) fabricated with sub-micron silicon gate and double-layer metal wiring C 2MOS technology. It is ideal for 1.65 to 3.6V CC operations and low power and low noise applications.This IC is intended for two-way asynchronous communication between data buses and the direction of data transmission is determined by DIR input. The enable input G can be used to disable the device so that the buses are effectively isolated.It has more speed performance at 3.3V than 5V AC/ACT family, combined with a lower power consumption.All inputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.All floating bus terminals during High Z State must be held HIGH or LOW.74LVC245ALOW VOLTAGE CMOS OCTAL BUS TRANSCEIVER(NOT INVERTED) HIGH PERFORMANCE.Table 1: Order CodesPACKAGE T & R SOP 74LVC245AMTR TSSOP74LVC245ATTR74LVC245A2/12Figure 2: Input And Output Equivalent CircuitTable 2: Pin DescriptionTable 3: Truth TableX : Don’t CareZ : High ImpedanceTable 4: Absolute Maximum RatingsAbsolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied1) I O absolute maximum rating must be observed 2) V O< GNDPIN N°SYMBOL NAME AND FUNCTION 1DIR Directional Control 2, 3, 4, 5, 6, 7, 8, 9A1 to A8Data Inputs/Outputs 18, 17, 16, 15, 14, 13, 12, 11B1 to B8Data Inputs/Outputs19GOutput Enable Input 10GND Ground (0V)20V CCPositive Supply VoltageINPUTS FUNCTION OUTPUT G DIR A BUSB BUSYn L L OUTPUT INPUT A = B L H INPUT OUTPUT B = A HXZ ZZSymbol ParameterValue Unit V CC Supply Voltage -0.5 to +7.0V V I DC Input Voltage-0.5 to +7.0V V O DC Output Voltage (High Impedance or V CC = 0V)-0.5 to +7.0V V O DC Output Voltage (High or Low State) (note 1)-0.5 to V CC + 0.5V I IK DC Input Diode Current- 50mA I OK DC Output Diode Current (note 2)- 50mA I O DC Output Current ± 50mA I CC or I GND DC V CC or Ground Current per Supply Pin± 100mA T stg Storage Temperature -65 to +150°C T LLead Temperature (10 sec)300°C74LVC245A3/12Table 5: Recommended Operating Conditions1) Truth Table guaranteed: 1.2V to 3.6V2) V IN from 0.8V to 2V at V CC = 3.0VTable 6: DC SpecificationsSymbol ParameterValue Unit V CC Supply Voltage (note 1) 1.65 to 3.6V V I Input Voltage0 to 5.5V V O Output Voltage (High Impedance or V CC = 0V)0 to 5.5V V O Output Voltage (High or Low State)0 to V CC V I OH , I OL High or Low Level Output Current (V CC = 3.0 to 3.6V)± 24mA I OH , I OL High or Low Level Output Current (V CC = 2.7 to 3.0V)± 12mA I OH , I OL High or Low Level Output Current (V CC = 2.3 to 2.7V)± 8mA I OH , I OL High or Low Level Output Current (V CC = 1.65 to 2.3V)± 4mA T op Operating Temperature-55 to 125°C dt/dvInput Rise and Fall Time (note 2)0 to 10ns/VSymbolParameterTest ConditionValueUnitV CC (V)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.V IHHigh Level Input Voltage 1.65 to 1.950.65V CC0.65V CC V2.3 to 2.7 1.7 1.72.7 to3.622V ILLow Level Input Voltage1.65 to 1.950.35V CC 0.35V CC V2.3 to 2.70.70.72.7 to3.60.80.8V OHHigh Level Output Voltage1.65 to 3.6I O =-100 µA V CC -0.2V CC -0.2V1.65I O =-4 mA 1.2 1.22.3I O =-8 mA 1.7 1.72.7I O =-12 mA 2.2 2.23.0I O =-18 mA 2.4 2.43.0I O =-24 mA 2.22.2V OLLow Level Output Voltage1.65 to 3.6I O =100 µA 0.20.2V 1.65I O =4 mA 0.450.452.3I O =8 mA 0.70.72.7I O =12 mA 0.40.43.0I O =24 mA 0.550.55I I Input Leakage Current 3.6V I = 0 to 5.5V ± 5± 5µA I off Power Off Leakage Current0V I or V O = 5.5V 1010µA I OZHigh Impedance Output Leakage Current3.6V I = V IH orV IL V O = 0 to 5.5V ± 10± 10µA I CCQuiescent Supply Current3.6V I = V CC or GND1010µA V I or V O = 3.6 to5.5V± 10± 10∆I CCI CC incr. per Input2.7 to3.6V IH = V CC -0.6V500500µA74LVC245A4/12Table 7: Dynamic Switching Characteristics1) Number of output defined as "n". Measured with "n-1" outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state.Table 8: AC Electrical Characteristics1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-ing in the same direction, either HIGH or LOW (t OSLH = | t PLHm - t PLHn |, t OSHL = | t PHLm - t PHLn |2) Parameter guaranteed by designTable 9: Capacitive Characteristics1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I CC(opr) = C PD x V CC x f IN + I CC /n (per circuit)SymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.V OLP Dynamic Low Level Quiet Output (note 1)3.3C L = 50pFV IL = 0V, V IH = 3.3V0.8V V OLV-0.8SymbolParameterTest ConditionValueUnitV CC (V)C L (pF)R L (Ω)t s = t r (ns)-40 to 85 °C -55 to 125 °C Min.Max.Min.Max.t PLH t PHLPropagation Delay Time1.65 to 1.953010002.0 2.09.0 2.012ns2.3 to 2.730500 2.0 2.08.0 2.010.52.750500 2.5 1.57.3 1.58.83.0 to 3.650500 2.5 1.0 6.3 1.07.6t PZL t PZHOutput Enable Time 1.65 to 1.95301000 2.0 2.012 2.016ns2.3 to 2.730500 2.0 2.09.5 2.012.52.750500 2.5 1.09.0 1.0113.0 to 3.650500 2.5 1.08.5 1.010t PLZ t PHZOutput Disable Time 1.65 to 1.95301000 2.0 2.011 2.014ns2.3 to 2.730500 2.0 2.09.0 2.0122.750500 2.5 2.08.5 2.0103.0 to 3.6505002.52.07.5 2.09.0t OSLH t OSHLOutput To Output Skew Time (note1, 2)2.7 to3.611nsSymbolParameterTest ConditionValue UnitV CC (V)T A = 25 °C Min.Typ.Max.C IN Input Capacitance4pF C PDPower Dissipation Capacitance (note 1)1.8f IN = 10MHz28pF 2.5303.33474LVC245A5/12Figure 3: Test CircuitR T = Z OUT of pulse generator (typically 50Ω)Table 10: Test Circuit And Waveform Symbol ValueFigure 4: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)SymbolV CC1.65 to 1.95V2.3 to 2.7V 2.7V3.0 to 3.6V C L 30pF 30pF 50pF 50pF R L = R 11000Ω500Ω500Ω500ΩV S 2 x V CC 2 x V CC 6V 6V V IH V CC V CC 2.7V 2.7V V M VCC /2V CC /2 1.5V 1.5V V OH V CC V CC 3.0V 3.0V V X V OL + 0.15V V OL + 0.15V V OL + 0.3V V OL + 0.3V VY V OH - 0.15V V OH - 0.15V V OH - 0.3V V OH - 0.3V t r = t r<2.0ns<2.0ns<2.5ns<2.5ns74LVC245AFigure 5: Waveform - Output Enable And Disable Time (f=1MHz; 50% duty cycle)6/1274LVC245A7/12DIM.mm.inch MIN.TYPMAX.MIN.TYP.MAX.A 2.35 2.650.0930.104A10.10.300.0040.012B 0.330.510.0130.020C 0.230.320.0090.013D 12.6013.000.4960.512E 7.47.60.2910.299e 1.270.050H 10.0010.650.3940.419h 0.250.750.0100.030L 0.4 1.270.0160.050k 0°8°0°8°ddd0.1000.004SO-20 MECHANICAL DATA0016022D74LVC245A8/12DIM.mm.inchMIN.TYPMAX.MIN.TYP.MAX.A 1.20.047A10.050.150.0020.0040.006A20.81 1.050.0310.0390.041b 0.190.300.0070.012c 0.090.200.0040.0079D 6.4 6.5 6.60.2520.2560.260E 6.2 6.4 6.60.2440.2520.260E1 4.34.4 4.480.1690.1730.176e 0.65 BSC0.0256 BSCK 0˚8˚0˚8˚L0.450.600.750.0180.0240.030TSSOP20 MECHANICAL DATAcEbA2AE1D1PIN 1 IDENTIFICATIONA1LK e0087225C74LVC245A Tape & Reel SO-20 MECHANICAL DATAmm.inchDIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992C12.813.20.5040.519D20.20.795N60 2.362T30.4 1.197Ao10.8110.4250.433Bo13.213.40.5200.528Ko 3.1 3.30.1220.130Po 3.9 4.10.1530.161P11.912.10.4680.4769/1274LVC245ATape & Reel TSSOP20 MECHANICAL DATAmm.inch DIM.MIN.TYP MAX.MIN.TYP.MAX.A33012.992 C12.813.20.5040.519 D20.20.795N60 2.362T22.40.882 Ao 6.870.2680.276 Bo 6.97.10.2720.280 Ko 1.7 1.90.0670.075 Po 3.9 4.10.1530.161 P11.912.10.4680.47610/1274LVC245A Table 11: Revision HistoryDate Revision Description of Changes26-Jul-20044Ordering Codes Revision - pag. 1.11/1274LVC245AInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronicsAll other names are the property of their respective owners© 2004 STMicroelectronics - All Rights ReservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America12/12。
74LVC245(电压逻辑隔离)
Waveform : Refer to test circuit of switching characteristics.
2. duty cycle ≤ 50%
Conditions Data retention At operation T / R, OE Output "H" or "L" Output "Z" or VCC:OFF
Note: The absolute maximum ratings are values which must not individually be exceeded, and furthermore, no two of which may be realized at the same time.
4
HD74LVC245A
Switching Characteristics
Ta = –40 to 85°C
Item Propagation delay time
Symbol VCC (V)
t PLH
2.7
t PHL
3.3±0.3
5.0±0.5
Min Typ Max — — 8.0 1.5 — 7.0 — — 5.5
Test Circuit
VCC
VCC
OE Input Pulse Generator Zout = 50 Ω
T/R
See Function Table
S1 A0 B0
Output
500 Ω S2
CL =
450 Ω
50 pF 50 Ω Scope
OPEN *1 See under table GND
Note:
Function Table
74VCX245BQX中文资料
© 2005 Fairchild Semiconductor Corporation DS500167June 1999Revised April 200574VCX245 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs74VCX245Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and OutputsGeneral DescriptionThe VCX245 contains eight non-inverting bidirectional buff-ers with 3-STATE outputs and is intended for bus oriented applications. The T/R input determines the direction of data flow. The OE input disables both the A and B ports by plac-ing them in a high impedance state.The 74VCX245 is designed for low voltage (1.4V to 3.6V)V CC applications with I/O compatibility up to 3.6V.The 74VCX245 is fabricated with an advanced CMOS technology to achieve high-speed operation while main-taining low CMOS power dissipation.Featuress 1.4V to 3.6V V CC supply operation s 3.6V tolerant inputs and outputss Power-off high impedance inputs and outputs s Supports Live Insertion and Withdrawal (Note 1)s t PD3.5 ns max for 3.0V to 3.6V V CC s Static Drive (I OH /I OL )r 24 mA @ 3.0V V CCs Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD performance:Human body model ! 2000V Machine model ! 200Vs Leadless DQFN Pb-Free packageNote 1: To ensure the high impedance state during power up and power down, OE n should be tied to V CC through a pull up resistor. The minimum value of the resistor is determined by the current sourcing capability of the driver.Ordering Code:Pb-Free package per JEDEC J-STD-020B.Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.Note 3: DQFN package available in Tape and Reel only,Logic Symbol Pin DescriptionsOrder Number Package Number Package Description74VCX245WM (Note 2)M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide74VCX245BQX (Note 3)MLP020B Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mm74VCX245MTC (Note 2)MTC2020-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePin Names DescriptionOE Output Enable Input (Active LOW)T/R Transmit/Receive InputA 0–A 7Side A Inputs or 3-STATE OutputsB 0–B 7Side B Inputs or 3-STATE Outputs 274V C X 245Connection DiagramsPin Assignments for SOIC and TSSOPPin Assignment for DQFN(Top Through View)Truth TableH HIGH Voltage Level L LOW Voltage Level X ImmaterialZ High ImpedanceNote 4: Unused bus terminals during HIGH Z State must be held HIGH or LOW.Logic DiagramInputs OutputsOE T/R L L BusB 0–B 7 Data to Bus A 0–A 7L H Bus A 0–A 7 Data to Bus B 0–B 7HXHIGH Z State on A 0–A 7, B 0–B 7 (Note 4)74VCX245Absolute Maximum Ratings (Note 5)Recommended Operating Conditions (Note 7)Note 5: The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the Absolute Maximum Rat-ings. The “Recommended Operating Conditions ” table will define the condi-tions for actual device operation.Note 6: I O Absolute Maximum Rating must be observed.Note 7: Floating or unused inputs must be held HIGH or LOW.DC Electrical CharacteristicsSupply Voltage (V CC ) 0.5V to 4.6V DC Input Voltage (V I ) 0.5V to 4.6V DC Output Voltage (V O )Outputs 3-STATE 0.5V to 4.6V Outputs Active (Note 6)0.5V to V CC 0.5VDC Input Diode Current (I IK ) V I 0V 50 mADC Output Diode Current (I OK ) V O 0V 50 mA V O ! V CC50 mADC Output Source/Sink Current (I OH /I OL )r 50 mA DC V CC or Ground Current r 100 mAStorage Temperature (T STG )65q C to 150q CPower Supply Operating 1.4V to 3.6VInput Voltage 0.3V to 3.6VOutput Voltage (V O )Output in Active States 0V to V CC Output in 3-STATE 0V to 3.6VOutput Current in I OH /I OL V CC 3.0V to 3.6V r 24 mA V CC 2.3V to 2.7V r 18 mA V CC 1.65V to 2.3V r 6 mA V CC 1.4V to 1.6Vr 2 mAFree Air Operating Temperature (T A ) 40q C to 85q CMinimum Input Edge Rate ('t/'V)V IN 0.8V to 2.0V, V CC 3.0V10 ns/VSymbol ParameterConditionsV CC Min MaxUnits(V)V IHHIGH Level Input Voltage2.7 to3.6 2.0V2.3 to 2.7 1.61.65 to 2.30.65 u V CC 1.4 to 1.60.65 u V CCV ILLOW Level Input Voltage2.7 to3.60.8V 2.3 to 2.70.71.65 to 2.30.35 u V CC 1.4 to 1.60.35 u V CCV OHHIGH Level Output VoltageI OH 100 P A 2.7 to 3.6V CC 0.2VI OH 12 mA 2.7 2.2I OH 18 mA 3.0 2.4I OH 24 mA 3.0 2.2I OH 100 P A 2.3 to 2.7V CC 0.2I OH 6 mA 2.3 2.0I OH 12 mA 2.3 1.8I OH 18 mA 2.3 1.7I OH 100 P A 1.65 to 2.3V CC 0.2I OH 6 mA 1.65 1.25I OH 100 P A 1.4 to 1.6V CC 0.2I OH 2 mA1.41.05 474V C X 245DC Electrical Characteristics (Continued)Note 8: Outputs disabled or 3-STATE only.AC Electrical Characteristics (Note 9)Note 9: For C L 50P F, add approximately 300 ps to the AC maximum specification.Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (t OSHL ) or LOW-to-HIGH (t OSLH ).Symbol ParameterConditionsV CC Min Max Units(V)V OLLOW Level Output VoltageI OL 100 P A 2.7 to 3.60.2VI OL 12 mA 2.70.4I OL 18 mA 3.00.4I OL 24 mA 3.00.55I OL 100 P A 2.3 to 2.70.2I OL 12 mA 2.30.4I OL 18 mA 2.30.6I OL 100 P A 1.65 to 2.30.2I OL 6 mA 1.650.3I OL 100 P A 1.4 to 1.60.2I OL 2 mA1.40.35I I Input Leakage Current 0 d V I d 3.6V 1.4 to 3.6r 5.0P A I OZ 3-STATE Output Leakage 0 d V O d 3.6V 1.4 to 3.6r 10P A V I V IH or V IL I OFF I Power-OFF Leakage Current 0 d (V I , V O ) d 3.6V 010P A I CC Quiescent Supply Current V I V CC or GND1.4 to 3.620P A V CC d (V I , V O ) d 3.6V (Note 8) 1.4 to 3.6r 20'I CCIncrease in I CC per InputV IH V CC 0.6V2.7 to3.6750P ASymbol ParameterConditionsV CC T A 40q C to 85q C UnitsFigure (V)Min Max Number t PHL , t PLHPropagation Delay C L 30 pF, R L 500:3.3 r 0.30.6 3.5nsFigures 1, 2A n to B n or B n to A n2.5 r 0.20.8 4.21.8 r 0.15 1.58.4C L 15 pF, R L 2k :1.5 r 0.1 1.016.8Figures 5, 6t PZL , t PZHOutput Enable TimeC L 30 pF, R L 500:3.3 r 0.30.64.5nsFigures 1, 3, 42.5 r 0.20.8 5.61.8 r 0.151.59.8C L 15 pF, R L 2k :1.5 r 0.1 1.019.6Figures 5, 7, 8t PLZ , t PHZOutput Disable TimeC L 30 pF, R L 500:3.3 r 0.30.6 3.6nsFigures 1, 3, 42.5 r 0.20.8 4.01.8 r 0.151.57.2C L 15 pF, R L 2k :1.5 r 0.1 1.014.4Figures 5, 7, 8t OSHL Output to Output Skew C L 30 pF, R L 500:3.3 r 0.30.5nst OSLH(Note 10)2.5 r 0.20.51.8 r 0.150.75C L 15 pF, R L 2k :1.5 r 0.11.574VCX245Dynamic Switching CharacteristicsCapacitanceSymbol ParameterConditionsV CC (V)T A 25q C UnitsTypical V OLPQuiet Output Dynamic Peak V OLC L 30 pF, V IH V CC , V IL 0V1.80.3V2.50.73.31.0V OLVQuiet Output Dynamic Valley V OLC L 30 pF, V IH V CC , V IL 0V1.8 0.3V2.5 0.73.31.0V OHVQuiet Output Dynamic Valley V OHC L 30 pF, V IH V CC , V IL 0V1.8 1.3V2.5 1.73.32.0Symbol ParameterConditionsT A 25q C Units Typical C IN Input Capacitance V I 0V or V CC , V CC 1.8V, 2.5V or 3.3V 6.0pF C I/O Input/Output Capacitance V I 0V or V CC , V CC 1.8V, 2.5V or 3.3V7.0pF C PDPower Dissipation CapacitanceV I 0V or V CC , f 10 MHz, V CC 1.8V, 2.5V or 3.3V20.0pF 674V C X 245AC Loading and Waveforms (VCC 3.3V r 0.3V to 1.8V r 0.15V)FIGURE 1. AC Test CircuitFIGURE 2. Waveform for Inverting and Non-Inverting FunctionsFIGURE 3. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Opent PZL , t PLZ 6V at V CC 3.3V r 0.3V;V CC x 2 at V CC 2.5V r 0.2V; 1.8V r 0.15Vt PZH , t PHZGNDSymbol V CC3.3V r 0.3V2.5V r 0.2V 1.8V r 0.15VV mi 1.5V V CC /2V CC /2V mo 1.5V V CC /2V CC /2V X V OL 0.3V V OL 0.15V V OL 0.15V V YV OH 0.3VV OH 0.15VV OH 0.15V74VCX245AC Loading and Waveforms (VCC 1.5 r 0.1V)FIGURE 5. AC Test CircuitFIGURE 6. Waveform for Inverting and Non-Inverting FunctionsFIGURE 7. 3-STATE Output High Enable and Disable Times for Low Voltage LogicFIGURE 8. 3-STATE Output Low Enable and Disable Times for Low Voltage LogicTEST SWITCH t PLH , t PHL Opent PZL , t PLZ V CC x 2 at V CC 1.5V r 0.1Vt PZH , t PHZGNDSymbol V CC 1.5V r 0.1V V mi V CC /2V mo V CC /2V X V OL 0.1V V YV OH 0.1V 874V C X 245Tape and Reel SpecificationTape Format for DQFNTAPE DIMENSIONS inches (millimeters)REEL DIMENSIONS inches (millimeters)PackageTape Number Cavity Cover Tape DesignatorSection Cavities Status Status Leader (Start End)125 (typ)Empty Sealed BQXCarrier 3000Filled Sealed Trailer (Hub End)75 (typ)EmptySealedTapeSize A B C D N W1W212 mm13.00.0590.5120.795 2.1650.4880.724(330.0)(1.50)(13.00)(20.20)(55.00)(12.4)(18.4) 74VCX245Physical Dimensions inches (millimeters) unless otherwise noted20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" WidePackage Number M20B 1074V C X 245Physical Dimensionsinches (millimeters) unless otherwise noted (Continued)Pb-Free 20-Terminal Depopulated Quad Very-Thin Flat Pack No Leads (DQFN), JEDEC MO-241, 2.5 x 4.5mmPackage Number MLP020BPhysical Dimensions inches (millimeters) unless otherwise noted (Continued)20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm WidePackage Number MTC20Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea-sonably expected to result in a significant injury to the user.2. A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.元器件交易网 74VCX245 Low Voltage Bidirectional Transceiver with 3.6V Tolerant Inputs and Outputs。
SN74LVC245APWT中文资料
FEATURESDESCRIPTION/ORDERING INFORMATION1234567891020191817161514131211DIRA1A2A3A4A5A6A7A8GNDV CCOEB1B2B3B4B5B6B7B8DB, DGV, DW, N, NS, OR PW PACKAGE(TOP VIEW)RGY PACKAGE(TOP VIEW)IRBGNCCSN74LVC245AOCTAL BUS TRANSCEIVERWITH3-STATE OUTPUTS SCAS218T–JANUARY1993–REVISED FEBRUARY2005•Operates From1.65V to3.6V•Inputs Accept Voltages to5.5V•Max t pd of6.3ns at3.3V•Typical V OLP(Output Ground Bounce)<0.8V at V CC=3.3V,T A=25°C•Typical V OHV(Output V OH Undershoot)>2V at V CC=3.3V,T A=25°C•I off Supports Partial-Power-Down ModeOperation•Supports Mixed-Mode Signal Operation on AllPorts(5-V Input/Output Voltage With3.3-V V CC)•Latch-Up Performance Exceeds250mA PerJESD17•ESD Protection Exceeds JESD22–2000-V Human-Body Model(A114-A)–1000-V Charged-Device Model(C101)This octal bus transceiver is designed for1.65-V to3.6-V V CC operation.The SN74LVC245A is designed for asynchronouscommunication between data buses.The devicetransmits data from the A bus to the B bus or fromthe B bus to the A bus,depending on the logic levelat the direction-control(DIR)input.The output-enable(OE)input can be used to disable the device so thebuses effectively are isolated.ORDERING INFORMATIONT A PACKAGE(1)ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP–N Tube of20SN74LVC245AN SN74LVC245ANQFN–RGY Reel of1000SN74LVC245ARGYR LC245ATube of25SN74LVC245ADWSOIC–DW LVC245AReel of2000SN74LVC245ADWRSOP–NS Reel of2000SN74LVC245ANSR LVC245ASSOP–DB Reel of2000SN74LVC245ADBR LC245A–40°C to85°CTube of70SN74LVC245APWTSSOP–PW Reel of2000SN74LVC245APWR LC245AReel of250SN74LVC245APWTTVSOP–DGV Reel of2000SN74LVC245ADGVR LC245AVFBGA–GQN SN74LVC245AGQNRReel of1000LC245AVFBGA–ZQN(Pb-Free)SN74LVC245AZQNR(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at/sc/package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.DESCRIPTION/ORDERING INFORMATION (CONTINUED)GQN OR ZQN PACKAGE(TOP VIEW)1234A B C DEDIROEA1B1To Seven Other ChannelsPin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.SN74LVC245AOCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTSSCAS218T–JANUARY 1993–REVISED FEBRUARY 2005To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Inputs can be driven from either 3.3-V or 5-V devices.This feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment.This device is fully specified for partial-power-down applications using I off .The I off circuitry disables the outputs,preventing damaging current backflow through the device when it is powered down.TERMINAL ASSIGNMENTS1234A A1DIR V CC OE B A3B2A2B1C A5A4B4B3D A7B6A6B5EGNDA8B8B7FUNCTION TABLEINPUTS OPERATION OE DIR L L B data to A bus L H A data to B busHXIsolationLOGIC DIAGRAM (POSITIVE LOGIC)Absolute Maximum Ratings(1)SN74LVC245A OCTAL BUS TRANSCEIVERWITH3-STATE OUTPUTS SCAS218T–JANUARY1993–REVISED FEBRUARY2005over operating free-air temperature range(unless otherwise noted)MIN MAX UNIT V CC Supply voltage range–0.5 6.5VV I Input voltage range(2)–0.5 6.5VV O Voltage range applied to any output in the high-impedance or power-off state(2)–0.5 6.5VV O Voltage range applied to any output in the high or low state(2)(3)–0.5V CC+0.5VI IK Input clamp current V I<0–50mA I OK Output clamp current V O<0–50mA I O Continuous output current±50mAContinuous current through V CC or GND±100mADB package(4)70DGV package(4)92DW package(4)58GQN/ZQN package(4)78θJA Package thermal impedance°C/WN package(4)69NS package(4)60PW package(4)83RGY package(5)37T stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)The value of V CC is provided in the recommended operating conditions table.(4)The package thermal impedance is calculated in accordance with JESD51-7.(5)The package thermal impedance is calculated in accordance with JESD51-5.Recommended Operating Conditions (1)SN74LVC245AOCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTSSCAS218T–JANUARY 1993–REVISED FEBRUARY 2005T A =25°C –40°C TO 85°C UNIT MINMAX MIN MAX Operating1.65 3.61.65 3.6V CCSupply voltageVData retention only 1.51.5V CC =1.65V to 1.95V0.65×V CC0.65×V CCV IHHigh-level input voltageV CC =2.3V to 2.7V 1.7 1.7VV CC =2.7V to 3.6V 22V CC =1.65V to 1.95V0.35×V CC0.35×V CCV IL Low-level input voltage V CC =2.3V to 2.7V 0.70.7V V CC =2.7V to 3.6V0.80.8V I Input voltage 0 5.50 5.5V V OOutput voltage0V CC 0V CC V V CC =1.65V–4–4V CC =2.3V –8–8I OHHigh-level output currentmA V CC =2.7V –12–12V CC =3V –24–24V CC =1.65V44V CC =2.3V 88I OLLow-level output currentmA V CC =2.7V 1212V CC =3V2424∆t/∆v Input transition rise or fall rate1010ns/V (1)All unused inputs of the device must be held at V CC or GND to ensure proper device operation.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs ,literature number SCBA004.Electrical Characteristics Switching CharacteristicsSN74LVC245A OCTAL BUS TRANSCEIVERWITH3-STATE OUTPUTS SCAS218T–JANUARY1993–REVISED FEBRUARY2005over recommended operating free-air temperature range(unless otherwise noted)T A=25°C–40°C TO85°C PARAMETER TEST CONDITIONS V CC UNITMIN TYP MAX MIN MAXI OH=–100µA 1.65V to3.6V V CC–0.2V CC–0.2I OH=–4mA 1.65V 1.29 1.2I OH=–8mA 2.3V 1.9 1.7V OH V2.7V 2.2 2.2I OH=–12mA3V 2.4 2.4I OH=–24mA3V 2.3 2.2I OL=100µA 1.65V to3.6V0.10.2I OL=4mA 1.65V0.240.45V OL I OL=8mA 2.3V0.30.7VI OL=12mA 2.7V0.40.4I OL=24mA3V0.550.55I I Control inputs V I=0to5.5V 3.6V±1±5µAI off V I or V O=5.5V0±1±10µAI OZ(1)V O=0to5.5V 3.6V±1±10µAV I=V CC or GND110I CC I O=0 3.6VµA3.6V≤V I≤5.5V(2)110One input at V CC–0.6V,∆I CC 2.7V to3.6V500500µA Other inputs at V CC or GNDC i Control inputs V I=V CC or GND 3.3V4pFC io A or B ports V I=V CC or GND 3.3V 5.5pF(1)For I/O ports,the parameter I OZ includes the input leakage current.(2)This applies in the disabled state only.over recommended operating free-air temperature range(unless otherwise noted)(see Figure1)T A=25°C–40°C TO85°CFROM TOPARAMETER V CC UNIT (INPUT)(OUTPUT)MIN TYP MAX MIN MAX1.8V±0.15V1612.2112.72.5V±0.2V13.97.818.3t pd A or B B or A ns2.7V1 4.27.117.33.3V±0.3V 1.5 3.8 6.1 1.5 6.31.8V±0.15V1714.8115.32.5V±0.2V1 4.510110.5t en OE A or B ns2.7V1 5.49.319.53.3V±0.3V 1.54.48.3 1.58.51.8V±0.15V17.816.51172.5V±0.2V14919.5t dis OE A or B ns2.7V1 4.48.318.53.3V±0.3V 1.74.17.3 1.77.5t sk(o) 3.3V±0.3V1nsOperating CharacteristicsSN74LVC245AOCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTSSCAS218T–JANUARY 1993–REVISED FEBRUARY 2005T A =25°CTEST PARAMETERV CC TYP UNITCONDITIONS1.8V 42Outputs enabled2.5V 433.3V 45C pdPower dissipation capacitance per transceiverf =10MHzpF 1.8V 1Outputs disabled2.5V 13.3V2PARAMETER MEASUREMENT INFORMATIONFrom Output Under TestLOAD CIRCUITOpen Data InputTiming InputV I0 VV I0 V0 VInputVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMS PULSE DURATIONV OHV OHV OLV OLV I0 V InputOutput Waveform 1S1 at V LOAD (see Note B)Output Waveform 2S1 at GND (see Note B)V OLV OH V LOAD /20 V≈0 VV IVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLINGOutputOutputt PLH /t PHL t PLZ /t PZL t PHZ /t PZHOpen V LOAD GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 Ω.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.All parameters and waveforms are not applicable to all devices.Output Control V I1.8 V ± 0.15 V2.5 V ± 0.2 V2.7 V3.3 V ± 0.3 V1 k Ω500 Ω500 Ω500 ΩV CC R L 2 × V CC 2 × V CC 6 V 6 VV LOAD C L 30 pF 30 pF 50 pF 50 pF0.15 V 0.15 V 0.3 V 0.3 VV ∆V CC V CC 2.7 V 2.7 VV I V CC /2V CC /21.5 V 1.5 VV M t r /t f ≤2 ns ≤2 ns ≤2.5 ns ≤2.5 nsINPUTS SN74LVC245AOCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTSSCAS218T–JANUARY 1993–REVISED FEBRUARY 2005Figure 1.Load Circuit and Voltage WaveformsPACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)SN74LVC245ADBLE OBSOLETE SSOP DB 20None Call TI Call TISN74LVC245ADBR ACTIVE SSOP DB 202000Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LVC245ADGVR ACTIVE TVSOP DGV 202000Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LVC245ADW ACTIVE SOIC DW 2025Pb-Free (RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIM SN74LVC245ADWR ACTIVE SOIC DW 202000Pb-Free (RoHS)CU NIPDAU Level-2-250C-1YEAR/Level-1-235C-UNLIM SN74LVC245AGQNR ACTIVE VFBGA GQN 201000None SNPB Level-1-240C-UNLIM SN74LVC245AN ACTIVE PDIP N 2020Pb-Free (RoHS)CU NIPDAU Level-NC-NC-NC SN74LVC245ANSR ACTIVE SO NS 202000Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM SN74LVC245APW ACTIVE TSSOP PW 2070Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC245APWLE OBSOLETE TSSOP PW 20NoneCall TI Call TISN74LVC245APWR ACTIVE TSSOP PW 202000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC245APWT ACTIVE TSSOP PW 20250Pb-Free (RoHS)CU NIPDAU Level-1-250C-UNLIM SN74LVC245ARGYR ACTIVE QFN RGY 201000Green (RoHS &no Sb/Br)CU NIPDAU Level-2-260C-1YEAR SN74LVC245AZQNRACTIVEVFBGAZQN201000Pb-Free (RoHS)SNAGCULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for newdesigns.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -May not be currently available -please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead (Pb-Free).Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean "Pb-Free"and in addition,uses package materials that do not contain halogens,including bromine (Br)or antimony (Sb)above 0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are 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74LVC245DB中文资料
VI/O
DC input voltagC output voltage range
0
5.5
0
VCC
0
VCC
Tamb
operating ambient temperature range in free air
−40
+85
tr, tf
input rise and fall times
or any other conditions beyond
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
April 1994
3
FUNCTION TABLE
INPUTS INPUTS/OUTPUT
OE DIR
An
L
L A=B
Bn inputs
L H inputs B = A
HX
Z
Z
H = HIGH voltage level L = LOW voltage level X = don’t care Z = high impedance OFF-state
The 74LVC245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. The ’245’ features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. The ’245’ is identical to the ’640’ but has true (non-inverting) outputs.
74xx245中文资料
74
Vcc＝最大
VI=5.5V VI=7V
Vcc＝最大，VIH=2.7V
IIL输入低电平电流
Vcc＝最大，VIL=0.4V
IOS输出短路电流 IOZH输出高阻态时高
电平电流 IOZL输出高阻态时低
电平电流
Icc 电源电流
Vcc＝最大
Vcc＝最大，VIH=2V VIL=最大，VO=2.7V Vcc＝最大，VIH=2V,VIL＝最大
5
5.5
4.75
5
5.25
2
0.7 0.8 -12 -15
12 24
单位 V V V mA mA
参
数
tPLH输出由低到高传输延迟时间 tPHL输出由高到低传输延迟时间 tPZH输出由高阻态到高允许时间 tPZL输出由高阻态到低允许时间 tPHZ输出由高到高阻态禁止时间 tPLZ输出由低到高阻态禁止时间
54/74245
双向总线发送器/接收器(3S)
简要说明: 245 为三态输出的八组总线收发器,其主要电器特性的典型值如下(不同厂家
具体值有差别):
型号
tPLH
54LS245/74LS245
8ns
tphl
PD
8ns
275mW
引出端符号: A B /G DIR
逻辑图:
A 总线端 B 总线端 三态允许端(低电平有效) 方向控制端
测试条件
Vcc =5V CL=45pF RL=667 Ω
Vcc=5V CL=5pF RL=90 Ω
静态特性（TA 为工作环境温度范围）
LS245 最大
12 12 40 40 25 25
单位
ns ns ns ns ns nsቤተ መጻሕፍቲ ባይዱ
sn74lvc827apwr典型运用电路
sn74lvc827apwr典型运用电路SN74LVC827APWR是一款集成电路芯片，它属于SN74LVC系列中的一员。
SN74LVC系列是德州仪器（TI）公司生产的逻辑门系列产品，适用于广泛的电子应用领域。
SN74LVC827APWR是一款高速CMOS设备，其运作电压范围为2V至5.5V，典型工作电流为10μA。
该芯片包含有8个独立的3态非反相缓冲器，适用于驱动电阻负载和充电过电容负载。
SN74LVC827APWR可以应用于各种数字系统中，下面我将详细介绍几个典型的运用电路。
1.数据传输SN74LVC827APWR的3态非反相缓冲器功能使其非常适合用于数据传输。
在许多数字系统中，需要在多个组件之间传输数据。
通过使用SN74LVC827APWR，我们可以实现多个设备之间的高速数据传输，并且可以灵活地控制数据流的方向。
这对于数字系统的灵活性和可扩展性非常重要。
2.性能优化在一些应用中，由于电路延迟和功耗等因素的限制，需要对电路进行性能优化。
SN74LVC827APWR的高速CMOS技术为其提供了优良的性能，并且其低功耗特性也使其在便携式设备中应用广泛。
通过合理的布局和设计，可以充分利用SN74LVC827APWR的性能特点，以实现高性能的数字系统。
3.总线驱动SN74LVC827APWR可以用作总线驱动器，在多个设备之间提供高速数据传输和通信。
在数字系统中，总线通常用于连接不同的设备，例如存储器、外设等。
SN74LVC827APWR通过其缓冲器功能，能够提供高速数据传输，使得总线通信更加可靠和高效。
4.逻辑控制除了数据传输和总线驱动之外，SN74LVC827APWR还可以用作逻辑控制器。
在数字系统中，逻辑控制器常常用于控制各种设备的动作和行为。
SN74LVC827APWR的多个非反相缓冲器可以用于逻辑电平的传递和控制，从而实现对其他设备的逻辑控制。
5.输入/输出接口SN74LVC827APWR的低电平输入特性使其适用于各种输入/输出接口设计。
MC74LCX245中文资料
MC74LCX245Low-Voltage CMOS Octal TransceiverWith 5 V–Tolerant Inputs and Outputs (3–State, Inverting)The MC74LCX245 is a high performance, non–inverting octal transceiver operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V I specification of 5.5 V allows MC74LCX245 inputs to be safely driven from 5 V devices. The MC74LCX245 is suitable for memory address driving and all TTL level bus oriented transceiver applications.Current drive capability is 24 mA at both A and B ports. The Transmit/Receive (T/R) input determines the direction of data flow through the bi–directional transceiver. Transmit (active–HIGH) enables data from A ports to B ports; Receive (active–LOW) enables data from B to A ports. The Output Enable input, when HIGH, disables both A and B ports by placing them in a HIGH Z condition.•Designed for 2.3 to 3.6 V V CC Operation•5 V Tolerant — Interface Capability With 5 V TTL Logic •Supports Live Insertion and Withdrawal•I OFF Specification Guarantees High Impedance When V CC = 0 V •LVTTL Compatible•LVCMOS Compatible•24 mA Balanced Output Sink and Source Capability•Near Zero Static Supply Current in All Three Logic States (10 µA) Substantially Reduces System Power Requirements •Latchup Performance Exceeds 500 mA•ESD Performance: Human Body Model >2000 V; Machine Model >200 VDevice Package Shipping ORDERING INFORMATIONMC74LCX245DW SO–2038 Units/Rail MC74LCX245DWR2SO–201000 Units/ReelMC74LCX245MSOEIAJ–2040 Units/Rail MC74LCX245MEL2000 Units/ReelSOEIAJ–20MC74LCX245DT TSSOP–2075 Units/Rail MC74LCX245DTEL TSSOP–202000 Units/Reel MC74LCX245DTR2TSSOP–202500 Units/ReelB0OE 19T/R 1A0B1A1B2A2B3A3B4A4B5A5B6A6B7A7Figure 1. Pinout (Top View)192018171615142134567V CC 1381291110OE B0B1B2B3B4B5B6B7T/RA0A1A2A3A4A5A6A7GNDH = High Voltage Level L = Low Voltage Level Z = High Impedance StateX = High or Low Voltage Level and Transitions are Acceptable For I CC reasons, Do Not Float InputsFigure 2. Logic DiagramABSOLUTE MAXIMUM RATINGS**Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not implied.1.I O absolute maximum rating must be observed.RECOMMENDED OPERATING CONDITIONSDC ELECTRICAL CHARACTERISTICS2.These values of V I are used to test DC electrical characteristics only.AC CHARACTERISTICS t R = t F = 2.5 ns; R L = 500 Ω3.Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device.The specification applies to any outputs switching in the same direction, either HIGH–to–LOW (t OSHL) or LOW–to–HIGH (t OSLH); parameter guaranteed by design.DYNAMIC SWITCHING CHARACTERISTICS4.Number of outputs defined as “n”. Measured with “n–1” outputs switching from HIGH–to–LOW or LOW–to–HIGH. The remaining output is measured in the LOW state.CAPACITIVE CHARACTERISTICSWAVEFORM 1 – PROPAGATION DELAYSt R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns V CC0 VV OHV OLAn, BnWAVEFORM 2 – OUTPUT ENABLE AND DISABLE TIMESt R = t F = 2.5 ns, 10% to 90%; f = 1 MHz; t W = 500 ns0 V Figure 3. AC WaveformsV OH V HZV OLV CCV LZ Symbol V CC3.3 V ±0.3 V2.7 V 2.5 V ±0.2 VVmi 1.5 V 1.5 V V CC /2Vmo 1.5 V 1.5 V V CC /2V HZ V OL + 0.3 V V OL + 0.3 V V OL + 0.15 V V LZV OH – 0.3 VV OH – 0.3 VV OH – 015 VBn, AnOPENV6V GNDC L = 50 pF at V CC = 3.3 0.3 V or equivalent (includes jig and probe capacitance)C L = 30 pF at V CC = 2.5 0.2 V or equivalent (includes jig and probe capacitance)R L = R 1 = 500 Ω or equivalentR T = Z OUT of pulse generator (typically 50 Ω)Figure 4. Test CircuitSO–20DW SUFFIX CASE 751D–05ISSUE FTSSOP–20DT SUFFIX CASE 948E–02ISSUE ADIM A MIN MAX MIN MAX INCHES 6.600.260MILLIMETERS B 4.30 4.500.1690.177C 1.200.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.270.370.0110.015J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSCM0 8 0 8 ____DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.CONTROLLING DIMENSION: MILLIMETER.DIMENSION A DOES NOT INCLUDE MOLDFLASH, PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.DIMENSION B DOES NOT INCLUDE INTERLEADFLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25(0.010) PER SIDE.DIMENSION K DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.DIMENSION A AND B ARE TO BE DETERMINEDAT DATUM PLANE -W-.6.400.252------SO EIAJ–20M SUFFIX CASE 967–01ISSUE ODIM MIN MAX MIN MAX INCHES --- 2.05---0.081MILLIMETERS 0.050.200.0020.0080.350.500.0140.0200.180.270.0070.01112.3512.800.4860.5045.10 5.450.2010.2151.27 BSC 0.050 BSC 7.408.200.2910.3230.500.850.0200.0331.10 1.500.0430.0590 0.700.900.0280.035---0.81---0.032A 1H E Q 1L E _10 _0 _10 _NOTES:ąă1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.ąă2.CONTROLLING DIMENSION: MILLIMETER.ąă3.DIMENSIONS D AND E DO NOT INCLUDE MOLDFLASH OR PROTRUSIONS AND AREMEASURED AT THE PARTING LINE. MOLDFLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.ąă4.TERMINAL NUMBERS ARE SHOWN FORREFERENCE ONLY.ąă5.THE LEAD WIDTH DIMENSION (b) DOES NOTINCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003)TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIALCONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018).A b c D E e L M ZON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability,including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.PUBLICATION ORDERING INFORMATIONCENTRAL/SOUTH AMERICA:Spanish Phone :303–308–7143 (Mon–Fri 8:00am to 5:00pm MST)Email :ONlit–spanish@Toll–Free from Mexico: Dial 01–800–288–2872 for Access –then Dial 866–297–9322ASIA/PACIFIC : LDC for ON Semiconductor – Asia SupportPhone :303–675–2121 (Tue–Fri 9:00am to 1:00pm, Hong Kong Time)Toll Free from Hong Kong & Singapore:001–800–4422–3781Email : ONlit–asia@JAPAN : ON Semiconductor, Japan Customer Focus Center4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031Phone : 81–3–5740–2700。
SN74LVC8T245QPWRQ1;中文规格书,Datasheet资料
SN74LVC8T245-Q1 SCES815–SEPTEMBER20108-BIT DUAL-SUPPLY BUS TRANSCEIVERWITH CONFIGURABLE VOLTAGE TRANSLATION AND3-STATE OUTPUTSCheck for Samples:SN74LVC8T245-Q1FEATURES DESCRIPTION•Qualified for Automotive Applications This8-bit non-inverting bus transceiver uses twoseparate configurable power-supply rails.The •Control Inputs V IH/V IL Levels Are Referenced toSN74LVC8T245-Q1is optimized to operate with V CCA V CCA Voltageand V CCB set at 1.65V to 5.5V.The A port is •V CC Isolation Feature–If Either V CC Input Is atdesigned to track V CCA.V CCA accepts any supply GND,All Are in the High-Impedance State voltage from1.65V to5.5V.The B port is designed•Fully Configurable Dual-Rail Design Allows to track VCCB .V CCB accepts any supply voltage fromEach Port to Operate Over the Full1.65-V to 1.65V to5.5V.This allows for universal low-voltagebidirectional translation between any of the 1.8-V,5.5-V Power-Supply Range2.5-V,3.3-V,and5.5-V voltage nodes.PW PACKAGEThe SN74LVC8T245-Q1is designed forasynchronous communication between two databuses.The logic levels of the direction-control(DIR)input and the output-enable(OE)input activate eitherthe B-port outputs or the A-port outputs or place bothoutput ports into the high-impedance mode.Thedevice transmits data from the A bus to the B buswhen the B-port outputs are activated,and from the Bbus to the A bus when the A-port outputs areactivated.The input circuitry on both A and B ports isalways active and must have a logic HIGH or LOWlevel applied to prevent excess I CC and I CCZ.The SN74LVC8T245-Q1is designed so that thecontrol pins(DIR and OE)are supplied by V CCA.This device is fully specified for partial-power-downapplications using I off.The I off circuitry disables theoutputs,preventing damaging current backflowthrough the device when it is powered down.The V CC isolation feature ensures that if either V CCinput is at GND,all outputs are in the high-impedancestate.To ensure the high-impedance state during power upor power down,should be tied to V CC through apullup resistor;the minimum value of the resistor isdetermined by the current-sinking capability of thedriver.ORDERING INFORMATION(1)T A PACKAGE(2)ORDERABLE PART NUMBER TOP-SIDE MARKING–40°C to125°C TSSOP–PW Reel of2000SN74LVC8T245QPWRQ1NH245Q(1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TIwebsite at .(2)Package drawings,thermal data,and symbolization are available at //packaging.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.DIROEA1B1SN74LVC8T245-Q1SCES815–SEPTEMBER 2010FUNCTION TABLE (1)(EACH 8-BIT SECTION)CONTROL INPUTS OUTPUT CIRCUITS OPERATION OE DIR A PORT B PORT L L Enabled Hi-Z B data to A bus L H Hi-Z Enabled A data to B busH XHi-ZHi-ZIsolation(1)Input circuits of the data I/Os are always active.LOGIC DIAGRAM (POSITIVE LOGIC)ABSOLUTE MAXIMUM RATINGS (1)over operating free-air temperature range (unless otherwise noted)MINMAX UNIT V CCA Supply voltage range–0.5 6.5VV CCB I/O ports (A port)–0.5 6.5V IInput voltage range (2)I/O ports (B port)–0.5 6.5VControl inputs –0.5 6.5A port –0.5 6.5Voltage range applied to any outputV O V in the high-impedance or power-off state (2)B port –0.56.5A port –0.5V CCA +0.5V O Voltage range applied to any output in the high or low state (2)(3)V B port –0.5V CCB +0.5I IK Input clamp current V I <0–50mA I OK Output clamp current V O <0–50mA I OContinuous output current±50mA Continuous current through each V CCA ,V CCB ,and GND±100mA q JA Package thermal impedance (4)PW package88°C/W T stg Storage temperature range–65150°C(1)Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device.These are stress ratings only,and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3)The output positive-voltage rating may be exceeded up to 6.5V maximum if the output current rating is observed.(4)The package thermal impedance is calculated in accordance with JESD 51-7.2Submit Documentation FeedbackCopyright ©2010,Texas Instruments IncorporatedProduct Folder Link(s):SN74LVC8T245-Q1SN74LVC8T245-Q1 SCES815–SEPTEMBER2010RECOMMENDED OPERATING CONDITIONS(1)(2)(3)(4)V CCI V CCO MIN MAX UNIT V CCA 1.65 5.5 Supply voltage VV CCB 1.65 5.51.65V to1.95V V CCI×0.652.3V to2.7V 1.7High-levelV IH Data inputs(5)V input voltage3V to3.6V24.5V to5.5V V CCI×0.71.65V to1.95V V CCI×0.352.3V to2.7V0.7Low-levelV IL Data inputs(5)V input voltage3V to3.6V0.84.5V to5.5V V CCI×0.31.65V to1.95V V CCA×0.65High-level Control inputs 2.3V to2.7V 1.7V IH V input voltage(referenced to V CCA)(6)3V to3.6V24.5V to5.5V V CCA×0.71.65V to1.95V V CCA×0.35Low-level Control inputs 2.3V to2.7V0.7V IL V input voltage(referenced to V CCA)(6)3V to3.6V0.84.5V to5.5V V CCA×0.3V I Input voltage Control inputs0 5.5V Active state0V CCO V Input/outputV I/Ovoltage3-State0 5.5V1.65V to1.95V–42.3V to2.7V–8I OH High-level output current mA3V to3.6V–244.5V to5.5V–321.65V to1.95V42.3V to2.7V8I OL Low-level output current mA3V to3.6V244.5V to5.5V321.65V to1.95V202.3V to2.7V20Input transitionΔt/Δv Data inputs ns/V rise or fall rate3V to3.6V104.5V to5.5V5T A Operating free-air temperature–40125°C(1)V CCI is the V CC associated with the data input port.(2)V CCO is the V CC associated with the output port.(3)All unused or driven(floating)data inputs(I/Os)of the device must be held at logic HIGH or LOW(preferably V CCI or GND)to ensureproper device operation and minimize power.Refer to the TI application report,Implications of Slow or Floating CMOS Inputs,literature number SCBA004.(4)All unused control inputs must be held at V CCA or GND to ensure proper device operation and minimize power comsumption.(5)For V CCI values not specified in the data sheet,V IH min=V CCI×0.7V,V IL max=V CCI×0.3V.(6)For V CCA values not specified in the data sheet,V IH min=V CCA×0.7V,V IL max=V CCA×0.3V.Copyright©2010,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):SN74LVC8T245-Q1SN74LVC8T245-Q1SCES815–ELECTRICAL CHARACTERISTICS(1)(2)(3)over recommended operating free-air temperature range(unless otherwise noted)T A=25°C T A=-40°C to125°CPARAMETER TEST CONDITIONS V CCA V CCB UNITMIN TYP MAX MIN MAXI OH=–100m A,V I=V IH 1.65V to4.5V 1.65V to4.5V V CCO–0.1I OH=–4mA,V I=V IH 1.65V 1.65V 1.2V OH I OH=–8mA,V I=V IH 2.3V 2.3V 1.9VI OH=–24mA,V I=V IH3V3V 2.4I OH=–32mA,V I=V IH 4.5V 4.5V 3.8I OL=100m A,V I=V IL 1.65V to4.5V 1.65V to4.5V0.1I OL=4mA,V I=V IL 1.65V 1.65V0.45V OL I OL=8mA,V I=V IL 2.3V 2.3V0.3VI OL=24mA,V I=V IL3V3V0.55I OL=32mA,V I=V IL 4.5V 4.5V0.55I I DIR V I=V CCA or GND 1.65V to5.5V 1.65V to5.5V±1±2m A0V0to5.5V±2±11A or BI off V I or V O=0to5.5V m Aport0to5.5V0V±2±11A orB V O=V CCO or GND,I OZ 1.65V to5.5V 1.65V to5.5V±1±6m Aport OE=V IH1.65V to5.5V 1.65V to5.5V20I CCA V I=V CCI or GND,I O=05V0V20m A0V5V–101.65V to5.5V 1.65V to5.5V20I CCB V I=V CCI or GND,I O=05V0V–10m A0V5V20I CCA+I CCB V I=V CCI or GND,I O=0 1.65V to5.5V 1.65V to5.5V40m AOne A port at V CCA–0.6V,A port50DIR at V CCA,B port=openΔI CCA3V to5.5V3V to5.5V m A DIR at V CCA–0.6V,DIR B port=open,50A port at V CCA or GNDOne B port at V CCB–0.6V,ΔI CCB B port3V to5.5V3V to5.5V50m A DIR at GND,A port=openControlC i V I=V CCA or GND 3.3V 3.3V45pFinputsA or BC io V O=V CCA/B or GND 3.3V 3.3V8.510pFport(1)V CCO is the V CC associated with the output port.(2)V CCI is the V CC associated with the input port.(3)All unused control inputs must be held at V CCA or GND to ensure proper device operation and minimize power comsumption.4Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):SN74LVC8T245-Q1SN74LVC8T245-Q1 SCES815–SEPTEMBER2010SWITCHING CHARACTERISTICSover recommended operating free-air temperature range,V CCA=1.8V±0.15V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.725.9 1.313.2111.40.811.1nst PHLt PLHB A0.928.80.827.60.727.40.727.4nst PHLt PHZOE A 1.533.6 1.533.4 1.533.3 1.433.2ns t PLZt PHZOE B 2.436.2 1.917.1 1.716 1.314.3ns t PLZt PZHOE A0.4280.427.80.427.70.427.7ns t PZLt PZHOE B 1.840 1.520 1.216.60.914.8ns t PZLSWITCHING CHARACTERISTICSover recommended operating free-air temperature range,V CCA=2.5V±0.2V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.525.4 1.2130.810.20.68.8nst PHLt PLHB A 1.213.3113.1112.90.912.8nst PHLt PHZOE A 1.413 1.413 1.413 1.413ns t PLZt PHZOE B 2.333.6 1.815 1.714.30.910.9ns t PLZt PZHOE A117.2117.3117.2117.3ns t PZLt PZHOE B 1.732.2 1.518.1 1.214.1111.2ns t PZLCopyright©2010,Texas Instruments Incorporated Submit Documentation Feedback5Product Folder Link(s):SN74LVC8T245-Q1SN74LVC8T245-Q1SCES815–SWITCHING CHARACTERISTICSover recommended operating free-air temperature range,V CCA=3.3V±0.3V(unless otherwise noted)(see Figure1)V CCB=1.8V V CCB=2.5V V CCB=3.3V V CCB=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.525.2 1.112.80.810.30.510.4nst PHLt PLHB A0.811.20.810.20.710.10.610nst PHLt PHZOE A 1.612.2 1.612.2 1.612.2 1.612.2ns t PLZt PHZOE B 2.133 1.714.3 1.512.60.810.3ns t PLZt PZHOE A0.814.10.813.60.813.20.813.6ns t PZLt PZHOE B 1.831.7 1.418.4 1.112.90.910.9ns t PZLSWITCHING CHARACTERISTICSover recommended operating free-air temperature range,V CCA=5V±0.5V(unless otherwise noted)(see Figure1)V CC=1.8V V CC=2.5V V CC=3.3V V CC=5VFROM TO±0.15V±0.2V±0.3V±0.5V PARAMETER UNIT (INPUT)(OUTPUT)MIN MAX MIN MAX MIN MAX MIN MAXt PLHA B 1.525.4112.80.7100.48.2nst PHLt PLHB A0.7110.48.80.38.50.38.3nst PHLt PHZOE A0.39.40.39.40.39.40.39.4ns t PLZt PHZOE B232.7 1.613.7 1.4120.79.7ns t PLZt PZHOE A0.710.90.710.90.710.90.710.9ns t PZLt PZHOE B 1.531.6 1.318.4113.70.910.7ns t PZLOPERATING CHARACTERISTICST A=25°CV CCA=V CCA=V CCA=V CCA=TEST VCCB =1.8V V CCB=2.5V V CCB=3.3V V CCB=5VPARAMETER UNIT CONDITIONSTYP TYP TYP TYPA-port input,B-port output2223C pdA(1)CL =0,B-port input,A-port output12131316f=10MHz,pFA-port input,B-port output13131416t r=t f=1nsC pdB(1)B-port input,A-port output2223(1)Power dissipation capacitance per transceiver6Submit Documentation Feedback Copyright©2010,Texas Instruments IncorporatedProduct Folder Link(s):SN74LVC8T245-Q1V OH V OLLOAD CIRCUIT × V CCOOpenOutput Control (low-level enabling)Output Waveform 1S1 at 2 × V CCO (see Note B)Output Waveform 2S1 at GND (see Note B)0 V0 VV CCI0 VV CCAV CCOVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESVOLTAGE WAVEFORMS PULSE DURATIONVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMESInputt pd t PLZ /t PZL t PHZ /t PZHOpen 2 × V CCO GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR v 10 MHz, Z O = 50 Ω, dv/dt ≥ 1 V/ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .H.V CCI is the V CC associated with the input port.I.V CCO is the V CC associated with the output port.J.All parameters and waveforms are not applicable to all devices.1.8 V ± 0.15 V2.5 V ± 0.2 V3.3 V ± 0.3 V 5 V ± 0.5 V2 k Ω2 k Ω2 k Ω2 k ΩV CCO R L 0.15 V 0.15 V 0.3 V 0.3 VV TP C L 15 pF 15 pF 15 pF 15 pFSN74LVC8T245-Q1SCES815–SEPTEMBER 2010PARAMETER MEASUREMENT INFORMATIONFigure 1.Load Circuit and Voltage WaveformsCopyright ©2010,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):SN74LVC8T245-Q1PACKAG PACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL PeaSN74LVC8T245QPWRQ1ACTIVE TSSOP PW242000Green (RoHS& no Sb/Br)CU NIPDAU Level-1-260C(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.tinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for alllead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable fo Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retard in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TIprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate inf continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical an TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for releasIn no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to CuOTHER QUALIFIED VERSIONS OF SN74LVC8T245-Q1 :•Catalog: SN74LVC8T245•Enhanced Product: SN74LVC8T245-EPNOTE: Qualified Version Definitions://PACKAG Array •Catalog - TI's standard catalog product•Enhanced Product - Supports Defense, Aerospace and Medical ApplicationsTAPE AND REELINFORMATION*All dimensionsare nominalDevicePackage Type Package DrawingPins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LVC8T245QPWRQ1TSSOP PW242000330.016.46.958.31.68.016.0Q1PACKAGE MATERIALS INFORMATION14-Jul-2012Pack Materials-Page 1分销商库存信息:TISN74LVC8T245QPWRQ1。
74LVC_LVCH8T245
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 12 December 2011
3 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
21, 20, 19, 18, 17, 16, 15, 14 data input or output
All GND pins must be connected to ground (0 V).
6. Functional description
Table 3. Function table[1] Input OE[2] L L H X DIR[2] L H X X Input/output[3] An[2] An = Bn input Z Z Bn[2] input Bn = An Z Z Supply voltage VCC(A), VCC(B) 1.2 V to 5.5 V 1.2 V to 5.5 V 1.2 V to 5.5 V GND[3]
2 of 28
NXP Semiconductors
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
DIR OE
A1 B1 VCC(A) VCC(B) to other seven channels
001aai473
74LVC8T245; 74LVCH8T245
8-bit dual supply translating transceiver; 3-state
第三十八节 双向三态门 74LVC245A
一、概述
74LVC245A飞利蒲公司制造的双向三态门缓冲器，输入和输出为5V。它是一个高速，低电源，低电压，COMS设计和COMS兼容的TTL标准，输入驱动设计可以达到3.3或5V和输出能够达到5V。
二、特点
1、输入/输出5V电源
2、COMS低电源消耗
3、TTL标准内部分界面
6
A4
数据输入/输出
7
A5
数据输入/输出
8
A6
数据输入/输出
9
A7
数据输入/输出
10
GND
接地(0 V)
11
B7
数据输入/输出
12
B6
数据输入/输出
13
B5
数据输入/输出
14
B4
数据输入/输出
ห้องสมุดไป่ตู้15
B3
数据输入/输出
16
B2
数据输入/输出
17
B1
数据输入/输出
18
B0
数据输入/输出
19
OE
输入输出可选择
20
VCC
电源电压供电
IC引脚外形图
四、IC内部框图
4、输出性能：总线驱动
5、ICC种类：MSI
6、ESD防静电保护：
HBM EIA/JESD22-A114-A超过2000 V
MM EIA/JESD22-A115-A超过200 V
三、IC引脚
PIN
符号
功能描述
1
DIR
地址控制输入
2
A0
数据输入/输出
3
A1
数据输入/输出
4
A2
数据输入/输出
5
A3
数据输入/输出
74LVC245AQ资料
A1 2
3
A2 A3 4
A4 5
6
A5
7
A6A7 8A8 9The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
© 2006 Integrated Device Technology, Inc.
元器件交易网
IDT74LVC245A 3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND 5 VOLT TOLERANT I/O
2
元器件交易网
IDT74LVC245A 3.3V CMOS OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
PIN CONFIGURATION
DIR 1
A1
2
A2
3
A3
4
A4
5
A5
6
20
VCC
19 OE
18
B1
17
B2
16
B3
15
B4
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Description
Max
Unit
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A7
9 11 B7 SV00016
LOGIC SYMBOL (IEEE/IEC)
G3 3EN1 (BA) 1 3EN2 (AB)
Data inputs/outputs Output enable input (active-Low) Positive supply volt11
ABSOLUTE MAXIMUM RATINGS1
In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V) SYMBOL VCC IIK VI IOK VO IO IGND, ICC Tstg PTOT PARAMETER DC supply voltage DC input diode current DC input voltage DC output diode current DC output voltage; output HIGH or LOW state DC output voltage; output 3-State DC output source or sink current DC VCC or GND current Storage temperature range Power dissipation per package – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP) above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K VI t0 Note 2 VO uVCC or VO t 0 Note 2 Note 2 VO = 0 to VCC CONDITIONS RATING –0.5 to +6.5 –50 –0.5 to +6.5 "50 –0.5 to VCC +0.5 –0.5 to 6.5 "50 "100 –65 to +150 500 500 UNIT V mA V mA V mA mA °C
NOTE: 1. CPD is used to determine the dynamic power dissipation (PD in mW): PD = CPD x VCC2 x fi + S (CL x VCC2 x fo) where: fi = input frequency in MHz; CL = output load capacity in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL x VCC2 x fo) = sum of outputs. 2. The condition is VI = GND to VCC
1998 May 20
2
853-2044 19419
Philips Semiconductors Product specification
Octal bus transceiver with direction pin with 5-volt tolerant inputs/outputs (3-State)
INTEGRATED CIRCUITS
74LVC245A/74LVCH245A Octal bus transceiver with direction pin with 5-volt tolerant inputs/outputs (3-State)
Product specification Supersedes data of 1997 Dec 19 IC24 Data Handbook 1998 May 20
QUICK REFERENCE DATA
SYMBOL tPHL/tPLH CI CI/O CPD PARAMETER Propagation delay An to Bn; Bn to An Input capacitance Input/output capacitance Power dissipation capacitance per buffer Notes 1 and 2 CONDITIONS CL = 50pF VCC = 3.3V TYPICAL 3.6 5.0 10.0 33 UNIT ns pF pF pF
FUNCTION TABLE
INPUTS OE L L H H L X Z DIR L H X
An
INPUTS/OUTPUTS B0 Inputs B=A Z
4 5 6 7 8 9
A=B lnputs Z
= HIGH voltage level = LOW voltage level = Don't care = High impedance OFF-state
74LVC245A 74LVCH245A
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL PARAMETER DC supply voltage (for max. speed performance) VCC VI VO Tamb tr, tf DC supply voltage (for low-voltage applications) DC Input voltage range DC Output voltage range; output HIGH or LOW state DC output voltage range; output 3-State Operating ambient temperature range in free-air Input rise and fall times VCC = 1.2 to 2.7V VCC = 2.7 to 3.6V CONDITIONS MIN 2.7 1.2 0 0 0 –40 0 0 MAX 3.6 V 3.6 5.5 VCC 5.5 +85 20 10 °C ns/V V V UNIT
Philips Semiconductors
Philips Semiconductors Product specification
Octal bus transceiver with direction pin with 5-volt tolerant inputs/outputs (3-State)
DESCRIPTION
The 74LVC245A/74LVCH245A is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3V or 5V devices. In 3-State operation, outputs can handle 5V. These features allow the use of these devices as translators in a mixed 3.3V/5V environment. The 74LVC245A/74LVCH245A is an octal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. The '245' features an output enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE controls the outputs so that the buses are effectively isolated. The '245' is functionally identical to the '640', but the '640' has true (non-inverting) outputs.
SV00208
1998 May 20
3
Philips Semiconductors Product specification
Octal bus transceiver with direction pin with 5-volt tolerant inputs/outputs (3-State)
ORDERING INFORMATION
PACKAGES 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I 20-Pin Plastic Shrink Small Outline (SO) 20-Pin Plastic Shrink Small Outline (SSOP) Type II 20-Pin Plastic Thin Shrink Small Outline (TSSOP) Type I TEMPERATURE RANGE –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C –40°C to +85°C OUTSIDE NORTH AMERICA 74LVC245A D 74LVC245A DB 74LVC245A PW 74LVCH245A D 74LVCH245A DB 74LVCH245A PW NORTH AMERICA 74LVC245A D 74LVC245A DB 7LVC245APW DH 74LVCH245A D 74LVCH245A DB LVCH245APW DH PKG. DWG. # SOT163-1 SOT339-1 SOT360-1 SOT163-1 SOT339-1 SOT360-1