Automatic Processor Lower Bound Formulas for Array Computations
Atmel Studio 6 微控制器开发环境介绍说明书
Atmel® Studio 6 is the integrated development environment (IDE) for developing and debugging embedded applications based on Atmel AVR® and ARM® Cortex™-M microcontrollers (MCUs) in C/C++ and assembly code. The IDE makes editing and debugging source code easier by seamlessly bringing together an intelligent editor with assisted code writing, a wizard for quickly creating new projects, the Atmel Software Framework with free source code library, a GNU C/C++ Compiler, a powerful simulator, and the front-end for all Atmel programmers and in-circuit debuggers.Atmel Studio 6 is free of charge and available for download at /atmelstudio.What’s New in Atmel Studio 6• Support for Atmel ARM Cortex-M based MCUs• Fully integrated Atmel QTouch® Composer• Full support for C++Your Avenue to Atmel AVR and ARM Cortex-M Based MCU DesignDesigners using AVR MCUs are already familiar with our IDE, previously known as AVR Studio® 5. Now, the communityof ARM Cortex-M design engineers can take advantage of the same easy-to-use, professional and highly integrated development platform.Integrated QTouch ComposerFully integrated into Atmel Studio 6, Atmel QTouch Composermakes it easy to build touch functionality into your design.QTouch Composer is the front-end software used to displayand evaluate the data reported from your touch design,making it easy for you to inspect how well your touchimplementation performs. With this integration, you can easilyand seamlessly develop capacitive touch functionality into yourapplication. You won’t need to toggle between different toolsto edit the code in Atmel Studio 6 and fine-tune your touchdesign in QTouch Composer.Atmel Software FrameworkThe Atmel Software Framework contains drivers for all peripherals,communication stacks, graphics, digital signal processing (DSP) and audiolibraries, and nearly 1,000 complete example designs. Using free source codefrom the Atmel Software Framework will accelerate the development of newapplications, while lowering your overall costs.Debugging Made EasyAtmel Studio 6 connects directly to Atmel debuggers and programmers. One of thebiggest advantages of modern MCUs is their ability to send debug data to your PC, givingyou a perfect view of what goes on inside. With a debugger connected, Atmel Studio 6can present the status of all processors, memories, communication interfaces and analoginterfaces in nicely formatted views, giving you access to critical system parameters. Theresimply is no faster way to identify bugs and optimize a design—in the lab or in the field.To learn more or download Atmel Studio 6 free of charge, visit /atmelstudio .© 2012 Atmel Corporation. All rights reserved. / Rev.: 8487B-Studio6-E-A4-09/12Atmel ®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. ARM ®, ARMPowered ® logo and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be the trademarks of others. Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441-0311 F: (+1)(408) 487-2600 | 。
RT9817 产品数据手册说明书
1DS9817-13 April 2022Features●Internally Fixed Threshold 1.2V to 5V in 0.1V Step ●High Accuracy ±1.5%●Low Supply Current 3μA●No External Components Required ●Quick Reset within 20μs●Built-in Recovery Delay Include 0ms, 55ms, 220ms,450ms Options●Low Functional Supply Voltage 0.9V ●CMOS Push-Pull Output●Small SC-82 and SOT-143 Packages●RoHS Compliant and 100% Lead (Pb)-FreePin ConfigurationApplications●Computers ●Controllers●Intelligent Instruments●Critical μP and μC Power Monitoring ●Portable/Battery-Powered EquipmentMicro-Power Voltage Detectors with Manual ResetOrdering InformationGeneral DescriptionThe RT9817 is a micro-power voltage detector with deglitched manual reset input supervising the power supply voltage level for microprocessors (μP) or digital systems. It provides internally fixed threshold levels with 0.1V per step ranging from 1.2V to 5V, which covers most digital applications. It features low supply current of 3μA.The RT9817 performs supervisory function by sending out a reset signal whenever the V DD voltage falls below a preset threshold level. This reset signal will last the whole period before V DD recovering. Once V DD recovered upcrossing the threshold level, the reset signal will be released after a certain delay time. To pull reset signal low manually, just pull the manual reset input (MR) below the specified V IL level. RT9817 is provided in SC-82 and SOT-143 packages.(TOP VIEW)SOT-143Marking Information For marking information, contact our sales representative directly or through a RichTek distributor located in your area, otherwise visit our website for detail.Note :Richtek p roducts are :❝RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.❝Suitable for use in SnPb or Pb-free soldering processes.SC-82RESET/RESET MRRESET/RESET MR RT9817A = 0ms (RESET)B = 55ms (RESET)C = 220ms (RESET)D = 450ms (RESET)E = 0ms (RESET)F = 55ms (RESET)G = 220ms (RESET)H = 450ms (RESET)2DS9817-13 April 2022 Functional Block DiagramTypical Application CircuitFunctional Pin DescriptionRESET/RESETMRPart StatusThe part status values are defined as below :Active : Device is in production and is recommended for new designs. Lifebuy : The device will be discontinued, and a lifetime -buy period is in effect. NRND : Not recommended for new designs.Preview : Device has been announced but is not in production. Obsolete : Richtek has discontinued the production of the device.3DS9817-13 April 2022Absolute Maximum Ratings (Note 1)●Terminal Voltage (with Respect to GND)V DD ------------------------------------------------------------------------------------------------------------------------−0.3V to 6.0V●All Other Inputs --------------------------------------------------------------------------------------------------------−0.3V to V DD +0.3V ●Input Current, I VDD -----------------------------------------------------------------------------------------------------20mA ●Power Dissipation, PD @ T A = 25°CSC-82--------------------------------------------------------------------------------------------------------------------0.25W SOT-143-----------------------------------------------------------------------------------------------------------------0.285W ●Package Thermal Resistance (Note 2)SC-82, θJA ---------------------------------------------------------------------------------------------------------------400°C SOT-143, θJA ------------------------------------------------------------------------------------------------------------350°C ●Lead Temperature (Soldering, 10sec.)---------------------------------------------------------------------------- 260°C●Storage T emperature Range ----------------------------------------------------------------------------------------−65°C to 125°C ●ESD Susceptibility (Note 3)HBM (Human Body Mode)------------------------------------------------------------------------------------------2kV MM (Machine Mode)--------------------------------------------------------------------------------------------------200VElectrical Characteristics(V= 3V, T = 25°C, unless otherwise specified)Recommended Operating Conditions (Note 4)●Junction T emperature Range ----------------------------------------------------------------------------------------−40°C to 125°C ●Ambient T emperature Range ----------------------------------------------------------------------------------------−40°C to 85°CTo be continued4DS9817-13 April 2022Note 1. Stresses listed as the above “Absolute Maximum Ratings ” may cause permanent damage to the device. These are forstress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability.Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board ofJEDEC 51-3 thermal measurement standard.Note 3. Devices are ESD sensitive. Handling precautions are recommended.Note 4. The device is not guaranteed to function outside its operating conditions.5DS9817-13 April 2022Typical Operating CharacteristicsSupply Current vs. Input Voltage01234123456Input Voltage (V)S u p p l y C u r r e n t I D D (u A )Output Voltage vs. Input Voltage012345670123456Input Voltage (V)O u t p u t V o l t a g e (V)Nch Driver Output Current vs. V DS020*********120012345V DS (V)O u t p u t C u r r e n t(m A )Supply Current vs. Input Voltage01234560123456Input Voltage (V)S u p p l y C u r r e n t (u A )Nch Driver Output Current vs. V DS010********600.511.522.533.5V DS (V)O u t p u t C u r r e n t (m A )Nch Driver Output Current vs. V DS00.40.81.21.622.400.30.60.91.21.5V DS (V)O u t p u t C u r r e n t(m A )6DS9817-13 April 2022 Nch Driver Sink Current vs. Input Voltage0102030400.511.522.533.5Input Voltage (V)S i n k C u r r e n t I S I N K (m A )Supply Current vs. Input Voltage01234123456Input Voltage (V)S u p p l y C u r re n t (u A )Power-Down Reset Delay vs. Temperature051015202530354045-50-25255075100125Temperature P o w e r -D o w n R e s e t D e l a y (u s)(°C)Power-Down Reset Delay vs. Temperature051015202530354045-50-25255075100125Temperature P o w e r -D o w n R e s e t D e l a y (u s )(°C)Power-Down Reset Delay vs. Temperature03691215-50-25255075100125Temperature P o w e r -D o w n R e s e t D e l a y (u s )(°C)Nch Driver Sink Current vs. Input Voltage0102030405012345Input Voltage (V)S i n k C u r r e n t I S I N K (m A )7DS9817-13 April 2022Output Delay Time vs. Load Capacitance0.010.111010010000.00010.00100.01000.1000 1.0000Load Capacitance (uF)O u t p u t D e l a y T i m e (m s )Power-Up Reset Time-Out vs. Temperature0255075100-50-25255075100125Temperature P o w e r -U p R e s e t T im e -O u t (m s )(°C)Reset Threshold Deviation vs. Temperature1.002.003.004.005.006.00-50-25255075100125Temperature R e s e t T h r e s h o l d D e v i a t i on (V )(°C)Pch Driver Output Current vs. Input Voltage0510152025123456Input Voltage (V)O u t p u t C u r r e n t(m A )Nch Driver Output Current vs. V DS204060801001201401600123456V DS (V)N c h D r i v e r O u t p u t C ur r e n t (m A )Power-Up Reset Time-Out vs. Temperature0100200300400500-50-25255075100125Temperature P o w e r -U p R e s e t T i me -O u t (m s )(°C)8DS9817-13 April 2022 Nch Driver Output Current vs. Input Voltage1020304050600123456Input Voltage (V)N c h D r i v e r O u t p u t C u r r e n t (m A )Output Voltage vs. Input Voltage01234567123456Input Voltage (V)O u t p u tV o l t a g e (V )Power-Down Reset Time-Out vs. Temperature051015202530-50-25255075100125Temperature P ow e r -D o w n R e s e t T i m e -O u t (u s )(°C)Power Down Reset Time-Out vs. Temperature0100200300400500-50-25255075100125Temperature P o w e r D o w n R e s e t T i m e -O u t (m s )(°C)9DS9817-13 April 2022Application InformationBenefits of Highly Accurate Reset ThresholdMost μP supervisor ICs have reset threshold voltages between 1% and 1.5% below the value of nominal supply voltages.This ensures a reset will not occur within 1% of the nominal supply, but will occur when the supply is 1.5% below nom inal.10DS9817-13 April 2022SOT-143 Surface Mount Package11DS9817-13 April Richtek Technology CorporationHeadquarter5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789 Fax: (8863)5526611Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design,specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.Richtek Technology Corporation Taipei Office (Marketing)5F, No. 95, Minchiuan Road, Hsintien City Taipei County, Taiwan, R.O.C.Tel: (8862)86672399 Fax: (8862)86672377Email:*********************SC -82 Surface Mount Package。
trimAl Phylogenetics Alignment Trimming Tool说明书
trimAl: a tool for automated alignment trimming in large-scale phylogenetics analyses Salvador Capella-Gutiérrez, Jose M. Silla-Martínez and Toni GabaldónTutorialVersion 1.2trimAl tutorialtrimAl is a tool for the automated trimming of Multiple Sequence Alignments. A format inter-conversion tool, called readAl, is included in the package. You can use the program either in the command line or webserver versions. The command line version is faster and has more possibilities,so it is recommended if you are going to use trimAl extensively.The trimAl webserver included in Phylemon 2.0 provides a friendly user interface and the opportunity to perform many different downstream phylogenetic analyses on your trimmed alignment. This document is a short tutorial that will guide you through the different possibilities of the program.Additional information can be obtained from where a more comprehensive documentation is available.If you use trimAl or readAl please cite our paper:trimAl: a tool for automated alignment trimming in large-scale phylogenetic analyses.Salvador Capella-Gutierrez;Jose M.Silla-Martinez;Toni Gabaldon.Bioinformatics 2009 25: 1972-1973.If you use the online webserver phylemon or phylemon2, please cite also this reference:Phylemon:a suite of web tools for molecular evolution,phylogenetics and phylogenomics.Tárraga J, Medina I, Arbiza L, Huerta-Cepas J, Gabaldón T, Dopazo J, Dopazo H. Nucleic Acids Res. 2007 Jul;35 (Web Server issue):W38-42.1. Program Installation.If you have chosen the trimAl command line version you can download the source code from the Download Section in trimAl's wikipage.For Windows OS users, we have prepared a pre-compiled trimAl version to use in this OS. Once the user has uncompressed the package, the user can find a directory,called trimAl/bin, where trimAl and readAl pre-compiled version can be found.Meanwhile for the OS based on Unix platform, e.g. GNU/Linux or MAC OS X, the user should compile the source code before to use these programs. To compile the source code, you have to change your current directory to trimAl/source and just execute "make".Once you have the trimAl and readAl binaries program, you should check if trimAl is running in appropriate way executing trimal program before starting this tutorial.2. trimAl. Multiple Sequence Alignment dataset.In order to follow this tutorial, we have prepared some examples. These examples have been taken from and you can use the codes from these files to get more information about it in this database.You can find three different directories called Api0000038, Api0000040 and Api0000080 with different files. The directory contains these files:A file .seqs with all the unaligned sequences.A file .tce with the Multiple Sequence Alignment produced by T-Coffee1.A file .msl with the Multiple Sequence Alignment produced by Muscle2.A file .mft with the Multiple Sequence Alignment produced by Mafft3.A file .clw with the Multiple Sequence Alignment produced by Clustalw4.A file .cmp with the different names of the MSAs in the directory. This file would be used by trimAl to get the most consistent MSA among the different alignments.You can use any directory to follow the present tutorial.3. Useful trimAl's features.Among the different trimAl parameters, there are some features that can be useful to interpret your alignment results:-htmlout filename. Use this parameter to have the trimAl output in an html file. In this way you can see the columns/sequences that trimAl maintains in the new alignment in grey color while the columns/sequences that have been deleted from the original alignment are in white color.-colnumbering. This parameter will provide you the relationship between the column numbers in the trimmed and the original alignment.-complementary. This parameter lets the user get the complementary alignment, in other words,when the user uses this parameter trimAl will render the columns/sequences that would be deleted from the original alignment.-w number. The user can change the windows size, by default 1, to take into account the surrounding columns in the trimAl's manual methods. When this parameter is fixed, trimAl take into account number columns to the right and to the left from the current position to compute any value, e.g. gap score, similarity score, etc. If the user wants to change a specific windows size value should use the correspond parameter-gw to change window size applied only a gap score assessments, -sc to change window size applied only to similiraty score calculations or -cw to change window size applied only to consistency part.4. Useful trimAl's/readAl's features.Both programs, trimAl and readAl, share common features related to the MSA conversion. It is possible to change the output format for a given alignment, by default the output format is the same than the input one, you can produce an output in different format with these options: -clustal. Output in CLUSTAL format.-fasta. Output in FASTA format.-nbrf. Output in PIR/NBRF format.-nexus. Output in NEXUS format.-mega. Output in MEGA format.-phylip3.2. Output in Phylip NonInterleaved format.-phylip. Output in Phylip Interleaved format.5. Getting Information from Multiple Sequence Alignment.trimAl computes different scores, such as gap score or similarity score distribution, from a given MSA. In order to obtain this information, we can use different parameters through the command line version.To do this part,we are going to use the MSA called Api0000038.msl.This file is in the Api0000038 directory.$ cd Api0000038$ trimal -in Api0000038.msl -sgt$ trimal -in Api0000038.msl -sgc$ trimal -in Api0000038.msl -sct$ trimal -in Api0000038.msl -scc$ trimal -in Api0000038.msl -sidentYou can redirect the trimAl output to a file. This file can be used in subsequent steps as input of other programs, e.g.gnuplot,,microsoft excel,etc,to do plots of this information.$ trimal -in Api0000038.msl -scc > SimilarityColumnsFor instance, in the lines below you can see how to plot the information generated by trimAl using the GNUPLOT program.$ gnuplotplot 'SimilarityColumns' u 1:2 w lp notitleset yrange [-0.05:1.05]set xrange [-1:1210]set xlabel 'Columns'set ylabel 'Residue Similarity Score'plot 'SimilarityColumns' u 1:2 w lp notitleexitIn this other example you can see the gaps distribution from the alignment. This plot also was generated using GNUPLOT$ trimal -in Api0000038.msl -sgt > gapsDistribution$ gnuplotset xlabel '% Alignment'set ylabel 'Gaps Score'plot 'gapsDistribution' u 7:4 w lp notitleexit6. Using user-defined thresholds.If you do not want to use any of the automated procedures included in trimAl (see sections 7 and 8) you can set your own thresholds to trim your alignment. We will use the parameter -htmlout filename for each example so differences can be visualized. In this example, we will use the Api0000038.msl file from the Api0000038 directory.Firstly, we are going to trim the alignment only using the -gt value which is defined in the [0 - 1] range. In this specific example, those columns that do not achieve a gap score, at least, equal to 0.190, meaning that the fraction of gaps on these columns are smaller than this value, will be deleted from the input alignment.$ trimal -in Api0000038.msl -gt 0.190 -htmlout ex01.htmlYou can see different parts of the alignment in the image below.This figure has been generated from the trimAl's HTML file for the previous example.In this other example, we can see the effect to be more strict with our threshold. An usual consequence of higher stringency is that the trimmed MSA has fewer columns. Be careful so you do not remove too much signal$ trimal -in Api0000038.msl -gt 0.8 -htmlout ex02.htmlTo be on the safe side, you can set a minimal fraction of your alignment to be conserved. In this example,we have reproduced the previous example with the difference that here we required to the program that, at least, conserve the 80% of the columns from the original alignment. This will remove the most gappy 20% of the columns or stop at the gap threshold set.$ trimal -in Api0000038.msl -gt 0.8 -cons 80 -htmlout ex03.htmlSecondly,we are going to introduce other manual threshold-st value.In this case,this threshold,also defined in the[0-1]range,is related to the similarity score.This score measures the similarity value for each column from the alignment using the Mean Distance method, by default we use Blosum62 similarity matrix but you can introduce any other matrix (see the manual). In the example below, we have used a smaller threshold to know its effect over the example.$ trimal -in Api0000038.msl -st 0.003 -htmlout ex04.htmlIn this example, similar to the previous example, we have required to conserve a minimum percentage of the original alignment in a independent way to fixed by the similarity threshold.A given threshold maintains a larger number of columns than the cons threshold, trimAl selects this first one.$ trimal -in Api0000038.msl -st 0.003 -cons 30 -htmlout ex05.htmlThirdly, we are going to see the effect of combining two different thresholds. In this case, trimAl only maintains those columns that achieve or pass both thresholds.$ trimal -in Api0000038.msl -st 0.003 -gt 0.19 -htmlout ex06.htmlFinally, we are going to see the effect of combining two different thresholds with the cons parameter. In this case, if the number of columns that achieve or pass both thresholds is equal or greater than the percentage fixed by cons parameter, trimAl chose these columns. However, if the number of columns that achieve or pass both thresholds is less than the number of columns fixed by cons parameter, trimAl relaxes both to thresholds in order to retrieve those columns that lets to achieve this minimum percentage.$ trimal -in Api0000038.msl -st 0.003 -gt 0.19 -cons 60 -htmlout ex07.html7. Selection of the most consistent alignment.trimAl can select the most consistent alignment when more than one alignment is provided for the same sequences (and in the same order) using the -compareset filename parameter. To do this part, we are going to move to Api0000040 directory, we can find there a file calledApi0000040.cmp listing the alignment paths. Using this file, we execute the instruction below to select the most consistent alignment among the alignment provided$ trimal -compareset Api0000040.cmpAs in previous section, once trimAl has selected the most consistent alignment, we can get information about the alignment selected using the appropriate parameters. For example, we can use the follow instructions to know the consistency value for each column in the alignment or its consistency values distribution$ trimal -compareset Api0000040.cmp -sct$ trimal -compareset Api0000040.cmp -sccAlso, we can trim the selected alignment using a specific threshold related to the consistency value. To do that, we should use the -ct value where the value is a number defined in the [0 - 1] range. This number refers to the average conservation of residue pars in that column with respect to the other alignments.$ trimal -compareset Api0000040.cmp -ct 0.6 -htmlout ex08.htmlOn the same way than the previous section, we can define a minimum percentage of columns that should be conserve in the new alignment. For this purpose, we have to use the cons parameter as we explained before.$ trimal -compareset Api0000040.cmp -ct 0.6 -cons 50 -htmlout ex09.htmlFinally, we can combine different thresholds, in fact, we can use all of them as well as we can define a minimum percentage of columns that should be conserve in the output alignment. In the line below, you can see an example of this situation.$ trimal -compareset Api0000040.cmp -ct 0.6 -cons 50 -gt 0.8 -st 0.01-htmlout ex10.html8. Applying automated methods.One of the most powerful aspects of trimAl is that it provides you with several automated options.This option will automatically select the most appropriate thresholds for your alignment after examining the distribution of various parameters along your alignment. Among the alignment features that trimAl takes into account to compute these optimal cut-off are the gap distribution, the similarity distribution, the identity score, etc.You can find a complete explanation about all of these methods in the trimAl's Publications Section.Here,we provide some examples on how to use these methods.The automated methods, gappyout, strict and strictpus, can be used independently if you are working with one or more than one alignment, in the last case, for the same sequences.In the lines below, you can see how to use the gappyout method in both ways. This method will eliminate the most gappy fraction of the columns from your alignment. For this, we are going to continue using the same directory than the previous section.$ trimal -compareset Api0000040.cmp -gappyout -htmlout ex11.html$ trimal -in Api0000040.mft -gappyout -htmlout ex12.htmlIn this case, we are going to use the same files than in the example before but we have changed the method to trim the alignmnet. Now, we are using strict and strictplus methods. These two methods combine the information on the fraction of gaps in a column and their similarity scores, being strictplus for more stringent than strict method.$ trimal -compareset Api0000040.cmp -strict -htmlout ex13.html$ trimal -in Api0000040.clw -strictplus -htmlout ex14.htmling an heuristic method to decide which is the best automated method for a given MSA.Finally, we implemented an heuristic method to decide which is the best automated method to trim a given alignment. The heuristic method takes into account alignment features such as the number of sequences in the alignment as well as some measures about the identity score among the sequences in the alignment or among the best pairwise sequences in that MSA. According to these characteristics trimAl will decide upon one of the two automated methods (gappyout or strictplus).To illustrate how to use this method, we provide a couple of example using the same directory than the section before. First, we used trimAl to selecte the most consistent alignment and then we trimmed that alignmnet using our heuristic method.$ trimal -compareset Api0000040.cmp -automated1 -htmlout ex15.htmlThen, we trim a single MSA using the previously mentioned method.$ trimal -in Api0000040.msl -automated1 -htmlout ex16.html10. Getting more information.We hope that this short introduction to trimAl's features has been useful to you.We advise you to visit periodically the trimAl's wikipage()where you could get the latest news about the program as well as more information, examples, etc, about trimAl's package. You can also subscribe to the mailing list if you want to be updated in new trimAl developing.11. References.1.T-Coffee: A novel method for fast and accurate multiple sequence alignment.Notredame C, Higgins DG, Heringa J. J Mol Biol. 2000 Sep 8;302(1):205-17.2.MUSCLE:multiple sequence alignment with high accuracy and highthroughput. Edgar RC.Nucleic Acids Res. 2004 Mar 19;32(5):1792-7.3.MAFFT: a novel method for rapid multiple sequence alignment based on fastFourier transform. Katoh K, Misawa K, Kuma K, Miyata T. Nucleic Acids Res. 2002 Jul 15;30(14):3059-66.4.CLUSTAL W:improving the sensitivity of progressive multiple sequencealignment through sequence weighting,position-specific gap penalties and weight matrix choice. Thompson JD, Higgins DG, Gibson TJ. Nucleic Acids Res. 1994 Nov 11;22(22):4673-80.。
INTERNORMEN-electronics Bottle Sampling System BSS
Instruction manualVersion 1.8Serial-No.: .................. Version-/Rev.-Date : 12.06.2012Contents1. General (3)2. Safety Instructions (4)3. Extent of Delivery (5)4. Switch Panel (6)5. Bottle Sampling (7)5.1. Reservoir (7)5.2. Sampling (7)6. Commissioning (8)6.1. Power supply (8)6.2. Compressed Air Supply (9)6.2.1. Operation with the Compressor from INTERNORMEN-electronics (10)6.2.2. Operation with Existing Compressed Air Supply (11)6.3. Connection to CCS 1 / CCS 2 (12)7. Before the Analysis (13)7.1. Conditioning of the Sample (14)8. Analysis of sample (14)8.1. Degassing (14)8.2. Sample Feed (17)9. Cleaning and Maintenance (19)10. Technical Data (20)10.1. Connections (20)10.1.1. Electrical (20)10.1.2. Pneumatic (20)1. GeneralDear CustomerWe congratulate you on buying the INTERNORMEN-electronics Bottle Sampling System BSS 2. Before commissioning please read this manual carefully to prevent damages to the BSS 2.You have purchased a product which is technically up-to-date and which enables you to perform a particle count in lab quality, at any points of your plant where an online-analysis is not possible.The sampling and the output of results only take a few minutes.In general an online-measurement is to be preferred rather than a bottle sample analysis. The process from sampling to particle counting involves many possibilities of mistakes. Therefore this kind of analysis should be carried out only by trained per-sonal.2. Safety Instructions☝To prevent accidents it is important to keep strictly to the manual during the oper-ation of the BSS 2.☝Never try to open the pressure chamber, when the system pressure varies from the ambient air pressure.☝Never try to pressurise the chamber before being sure that it is tightly closed (see the lighting diode!)☝ Never use damaged or defective components (threaded joints, hoses, connect-ors etc.)!☝ A damaged pressure vessel (scratches in the glass, bent housing etc.) must not be used.☝Never open the BSS 2 housing !3. Components of BSS 2The BSS 2 includes :- Case [1]- Instrument base with integrated service unit [2] - Pressure vessel [3] - Power supply unit [4] - Connector for pneumatics [5]- High pressure hose with mini-measuring connection M 16x2 [6] - Compressor [7] (optional) -Spiral hose [8] (optional)Illustration 1178235464. Switch PanelIllustration 2B1 – Vacuum + pressure gauge B2 – Regulator (pressure + vacuum) B3 – Switch VENT / WORKB4 – Switch PRESSURE / VACUUM B5 – Switch OPEN / CLOSEB6 – Green light emitting diode OPEN B7 – Yellow light emitting diode CLOSEB1B5 B3B2B6 B4B75. Bottle Sampling5.1. ReservoirBefore sampling make sure that the reservoir to be used can be put into the pressure chamber of the BSS 2.To guarantee reliable results of measurement you should only use reservoirs whose cleanliness according to ISO 3722 is proved. You can buy them directly from INTERNORMEN Technology GmbH (two sample bottle set, Best. Nr. 313427). These glasses should be used only once.5.2. SamplingThe bottle sampling requires a very careful handling. First flush the sampling point for a few seconds. Open the sample reservoir just directly before taking the sample, and close it immediately afterwards. Only this way the ambient influences do not impact your measuring results.Label your samples carefully. Note:Sampling pointDate and time of samplingSampler (name, first name)Special notes, if applicableThis is important for samplings at different plants, respectively different points of the plant to help prevent any unclearness.6. Commissioning6.1. Power supplyFor the operation of the BSS 2 you should only use the plug-in power supply supplied by INTERNORMEN-electronics, which is included in the system. Make sure that this power supply unit is set to the required output voltage of 12 V DC. (Illustration 3).Illustration 3Put the plug of the power supply unit into the current outlet (230 V~ 50 Hz) and the connection cable into the socket of the BSS 2 (Illustration 4) on the backside of the device. The actual unit might vary depending on the respective country's voltage.Illustration 4When correctly connected, one of the light emittingdiodes OPEN respectively CLOSE should light upafter a few seconds.Turn the switch VENT / WORK to the directionVENT, if it is in WORK.6.2. Compressed Air SupplyIn addition to the electric connection, the BSS 2 of INTERNORMEN-electronics also requires an external compressed air supply. This is provided either by an existing compressed air piping or the compressor optionally available.6.2.1. Operation with the Compressor from INTERNORMEN-electronics Instructions for the handling of the compressor are given in the enclosed manual.Connect the BSS 2 with the com-pressor. For this use the spiral hose(Pos. 8, Illustration 1) which is op-tionally available. Put the hose pluginto the coupler of the compressor.(Illustration 5).Illustration 5Now put the other end (coupler) into the quick con-nect plug at the backside of the BSS 2 (Illustration6). The coupler is locked, when you hear a clickingnoise while putting into one another.To release the plug connectors, pull back the lock-ing ring of the closing coupler.Before releasing make sure that the system is notunder pressure.Illustration 6Integrated service unitThe serialize inserted service unit prevents the entryof dirt and humidity into the BSS 2.To empty the container over knurled screw duringaccumulation of liquid.6.2.2. Operating with Existing Compressed Air SupplyConnect the BSS 2 to the pressure air supply. For this please use the optional attached plug-in connection to be connected with the device. This plug-in connection has an internal screw thread G 1/4 for the hose. Please make sure a firm seat and sealing between the hose and connector.Now slip the connection cap over the plug at thebackside of the BSS 2 (Illustration 7).To release the plug connectors, pull back thelocking ring of the closing coupler.Before releasing make sure that the system isnot under pressure.Illustration 7Integrated service unitThe serialize inserted service unit prevents the entryof dirt and humidity into the BSS 2.To empty the container over knurled screw duringaccumulation of liquid.6.3. Connection to CCS 1 / CCS 2Connect the BSS 2 to the contamination control system by means of the pressure hose (6, Illustration 1) included in the BSS 2. First remove the screw cap of the mini-measuring connection at the top of the pressure vessel (Illustration 8). Now you can mount the hose. The same way of connection applies to the CCS 1 as well as the CCS 2.Illustration 87. Before the AnalysisAfter following the instructions you are ready to operate the BSS 2. Make sure that you have sufficient air supply and pressure (max. 10 bar).Turn the compressor on (if operated by compressor), respectively open thefeeding main to the BSS 2 (existing compressed air supply). Set the pressure control valve to a rate between 6,0 and 6,5 bar. A different pressure rate might cause malfunctions or damages to the BSS 2.Turn the switch OPEN / CLOSE to the position OPEN. When the diodeOPEN (green) lights up, the pressure chamber lock is released. Now youcan remove the pressure vessel.Make sure that an O-ring (90x2,5) is inside the locking device (Illustration 9).Illustration 97.1. Conditioning of the SampleBefore putting the bottle into the BSS 2 for examination, homogenize thoroughly and ½ - 1 minute in the ultrasonic bath place. For exact measuring results an equal distribution of the particles is important. The following shakingprocedure should take about two minutes, dependent on the fluid viscosity, contamination and time interval between sampling and analysis.The vibration time depends directly on the fluid viscosity.< ISO-VG-32 2 minISO-VG-46 ... 100 3 ... 4 min> ISO-VG-100 5 ... 10 min (additional warming-up is indicated)8. Analysis of sampleInstructions for the operation of the CCS1, respectively the CCS2 can be taken from their manuals.Immediately after termination of the sample conditioning the analysis should be done.8.1. DegassingPlace the sample on the cover plate of the pressure chamber at the topside of the device. Please make sure once again that the O-ring is in proper position. Place the pressure vessel over the sample. Be aware of the correct position, i.e. it has to have slipped completely downwards. Now you can turn the switch OPEN / CLOSE to the position CLOSE (Illustration 12, 1). Wait until after a few seconds the diode CLOSE (yellow) lightens. Close the ball valve at the topside of the pressure vessel (Illustra-tion 10).Illustration 10Turn the switch VENT / WORK to the position WORK (Illustration 11, 2). Turn the switch PRESSURE / VACUUM to the position VACUUM (Illustration 11, 3).Illustration 11Pull out the handle of the pressure regulator.Illustration 12closeopen123Now turn the handle clockwise (Illustration 13) until – 1,0 bar. This will produce a vacuum in the pressure chamber. The more you turn, the lower the pressure in the chamber. You can observe this on the vacuum / pressure gauge (Illustration 13).Illustration 13Keep the vacuum in the chamber until there are no gas bub-bles in the fluid anymore.Illustration 14Turn the handle (illustration 15) anticlockwise until 0,0.Illustration 158.2. Sample FeedTurn the switch PRESSURE / VACUUM to the position PRESSURE (Illustration 16, 1).Now turn the handle (Illustration 16, 2) slowly clockwise. This will increase the pres-sure in the chamber. Continue turning until the gauge (Illustration 16) indicates a pressure of about approximate 3,0 bar. When you hear a hissing noise, the pressure in the chamber is too high. In this case turn the handle anticlockwise until this noise stops.Illustration 1612Open the ball valve at the top of the pressure vessel (Illustration 15). Turn the switch PRESSURE / VACUUM to the position PRESSURE (Illustration 16, 1).Illustration 15Now you can start the measurement at your particle counter. Please observe the in-st ructions for …Bottle Sampling“ in the manual of your contamination co ntroller.Illustration 17closeopenAfter finishing the measurements turn the switch VENT / WORK to the position VENT. You will then hear a hissing noise produced by the air escaping from the pressure chamber. Wait until this is ended, and then turn the switch OPEN / CLOSE to the position OPEN. When the green diode OPEN lights up, the vessel is unlocked and you can remove it by lifting upwards. Remove the sample glass.9. Cleaning and MaintenancePlease keep the device and the feeding tubes absolutely clean. After every use the device has to be flushed. For the flushing please use fine filtered low viscosity oil (e.g. ISOVG22 / ISOVG32). Before operating the BSS2 after a long time of not using it (about 2 weeks), the particle counting device should be flushed properly.For the cleaning of the pressure dome and the device housing please use a soft, fuzz-free cloth.Take care that the ascending tube is not bent while cleaning the pressure cham-ber. A contamination especially of this component would have negative affects on correct counting results, as it is in direct contact with the sample.Wipe the oil remains away from the plate of the pressure chamber lock and from the sealing area. For the cleaning do not use any aggressive chemical or rubbing agents.10. Technical DataDimensions: 220 x 240 x 390Weight: 6,5 kgInitial pressure: 0...4 barVacuum: 0...-0,95 bar10.1. Connections10.1.1. ElectricalPower supply / mains: 230V ~ 50 Hz or 110 V ~ 60 HzPower supply / device: 12 V DC10.1.2. PneumaticPressure range: 5...7 barFlow rate: min. 40 l/min airConnections: Rapid action coupling NW 7,2 with internal thread G ¼Mini-measuring connection with screw coupling M16 x 2 Subject to technical alterations!North America — HQ70 Wood Ave., South, 2nd Floor Iselin, NJ 08830Toll Free: (800) 656-3344 (North America Only)Voice: (732) 767-4200ChinaNo. 3, Lane 280, Linhong Road Changning District, 200335 Shanghai, P.R. ChinaVoice: +86-21-5200-0099 Singapore4 Loyang Lane #04-01/02 Singapore 508914Voice: +65-6825-1668Europe/Africa/Middle EastFriedensstraße 41D-68804 Altlussheim, GermanyVoice: +49-6205-2094-0Auf der Heide 253947 Nettersheim, GermanyVoice: +49-2486-809-0An den Nahewiesen 2455450 Langenlonsheim, GermanyVoice: +49 6704 204-0BrazilAv. Julia Gaioli, 474 –Bonsucesso07251-500 – Guarulhos, BrazilVoice: +55 (11) 2465-8822For more information, please e-mail us at filtra-******************Visit us online /filtration for a completelist of Eaton´s filtration products.©2012 Eaton Corporation. All Rights Reserved.All trademarks and registered trademarks are the property of their respectiveowners. Litho USA.All information and recommendations appearing in this brochure concerning theuse of products described herein are based on tests believed to be reliable.However, it is the user’s responsibility to determine the suitability for his own useof such products. Since the actual use by others is beyond our control, no guaran-tee, expressed or implied, is made by Eaton as to the effects of such use or theresults to be obtained. Eaton assumes no liability arising out of the use by othersof such products. Nor is the information herein to be construed as absolutelycomplete, since additional information may be necessary or desirable whenparticular or exceptional conditions or circumstances exist or because of applica-ble laws or government regulations.。
AutoDock4.2.6_UserGuide
User Guide AutoDock Version 4.2Updated for version 4.2.6Automated Docking of Flexible Ligands to Flexible Receptors Garrett M. Morris, David S. Goodsell, Michael E. Pique, William “Lindy” Lindstrom, Ruth Huey, Stefano Forli, William E. Hart, Scott Halliday, Rik Belew and Arthur J. OlsonModification date: July 28, 2014 15:30 D7/P7AutoDock, AutoGrid, AutoDockTools, Copyright © 1991-2009ContentsAutomated DockingIntroduction (3)Getting Started with AutoDock (3)Whatʼs New? (5)Support (7)TheoryOverview of the Free Energy Scoring Function (8)Using AutoDockSTEP 1: Preparing Coordinates (12)Creating PDBQT files with AutoDockTools (13)STEP 2: Running AutoGrid (18)Creating grid parameter files with AutoDockTools (19)STEP 3: Running AutoDock (20)Choosing a protocol for your application (21)Creating docking parameter files with AutoDockTools (23)STEP 4: Evaluating the Results of a Docking (24)Information in the docking log file (24)Analyzing docking results with AutoDockTools (24)Appendix I: AutoDock File FormatsPDBQT format for coordinate files (27)PDBQT format for flexible receptor sidechains (29)AutoGrid Grid Parameter File: GPF (30)Atomic Parameter File (33)Grid Map File (35)Grid Map Field File (36)AutoDock Docking Parameter File: DPF (37)Appendix II: Customizing the Docking ProtocolIntroduction (51)Docking parameter file examples (56)Appendix III: Docking Flexible Rings with AutoDock Introduction (61)Flexible RIngs (62)Reference (65)Appendix IV: AutoDock ReferencesAutomated DockingIntroductionAutoDock is an automated procedure for predicting the interaction of ligands with biomacromolecular targets. The motivation for this work arises from problems in the design of bioactive compounds, and in particular the field of computer-aided drug design. Progress in biomolecular x-ray crystallography continues to provide important protein and nucleic acid structures. These structures could be targets for bioactive agents in the control of animal and plant diseases, or simply key to the understanding of fundamental aspects of biology. The precise interaction of such agents or candidate molecules with their targets is important in the development process. Our goal has been to provide a computational tool to assist researchers in the determination of biomolecular complexes.In any docking scheme, two conflicting requirements must be balanced: the desire for a robust and accurate procedure, and the desire to keep the computational demands at a reasonable level. The ideal procedure would find the global minimum in the interaction energy between the substrate and the target protein, exploring all available degrees of freedom (DOF) for the system. However, it must also run on a laboratory workstation within an amount of time comparable to other computations that a structural researcher may undertake, such as a crystallographic refinement. In order to meet these demands a number of docking techniques simplify the docking procedure. AutoDock combines two methods to achieve these goals: rapid grid-based energy evaluation and efficient search of torsional freedom.The current version of AutoDock, using the Lamarckian Genetic Algorithm and empirical free energy scoring function, typically will provide reproducible docking results for ligands with approximately 10 flexible bonds. Our related software, AutoDock Vina (), uses a simpler scoring function that allows a faster search method, and provides reproducible results for larger systems with upwards of 20 flexible bonds. A more complete discussion of options is included below in the section "Choosing a Protocol for Your Application."This guide includes information on the methods and files used by AutoDock and information on use of AutoDockTools to generate these files and to analyze results.Getting Started with AutoDockAutoDock and AutoDockTools, the graphical user interface for AutoDock are available on the WWW at:/The WWW site also includes many resources for use of AutoDock, including detailed Tutorials that guide users through basic AutoDock usage, docking with flexible rings, and virtual screening with AutoDock. Tutorials may be found at:/faqs-help/tutorialAutoDock calculations are performed in several steps: 1) preparation of coordinate files using AutoDockTools, 2) precalculation of atomic affinities using AutoGrid, 3) docking of ligands using AutoDock, and 4) analysis of results using AutoDockTools.Step 1—Coordinate File Preparation. AutoDock4.2 is parameterized to use a model of the protein and ligand that includes polar hydrogen atoms, but not hydrogen atoms bonded to carbon atoms. An extended PDB format, termed PDBQT, is used for coordinate files, which includes atomic partial charges and atom types. The current AutoDock force field uses several atom types for the most common atoms, including separate types for aliphatic and aromatic carbon atoms, and separate types for polar atoms that form hydrogen bonds and those that do not. PDBQT files also include information on the torsional degrees of freedom. In cases where specific sidechains in the protein are treated as flexible, a separate PDBQT file is also created for the sidechain coordinates. AutoDockTools, the Graphical User Interface for AutoDock, may be used for creating PDBQT files from traditional PDB files.Step2—AutoGrid Calculation. Rapid energy evaluation is achieved by precalculating atomic affinity potentials for each atom type in the ligand molecule being docked.In the AutoGrid procedure the protein is embedded in a three-dimensional grid and a probe atom is placed at each grid point. The energy of interaction of this single atom with the protein is assigned to the grid point. AutoGrid affinity grids are calculated for each type of atom in the ligand, typically carbon, oxygen, nitrogen and hydrogen, as well as grids of electrostatic and desolvation potentials. Then, during the AutoDock calculation, the energetics of a particular ligand configuration is evaluated using the values from the grids.Step 3—Docking using AutoDock. Docking is carried out using one of several search methods. The most efficient method is a Lamarckian genetic algorithm (LGA), but traditional genetic algorithms and simulated annealing are also available. For typical systems, AutoDock is run several times to give several docked conformations, and analysis of the predicted energy and the consistency of results is combined to identify the best solution.Step 4—Analysis using AutoDockTools. AutoDockTools includes a number of methods for analyzing the results of docking simulations, including tools for clustering results by conformational similarity, visualizing conformations, visualizing interactions between ligands and proteins, and visualizing the affinity potentials created by AutoGrid.Whatʼs New?AutoDock 4.2 includes several enhancements over the methods available in AutoDock 3.0.Sidechain Flexibility. AutoDock 4.2 allows incorporation of limited sidechain flexibility into the receptor. This is achieved by separating the receptor into two files, and treating the rigid portion with the AutoGrid energy evaluation and treating the flexible portion with the same methods as the flexible ligand.Force Field. The AutoDock 4.2 force field is designed to estimate the free energy of binding of ligands to receptors. It includes an updated charge-based desolvation term, improvements in the directionality of hydrogen bonds, and several improved models of the unbound state. Expanded Atom Types. Parameters have been generated for an expanded set of atom types including halogens and common metal ions.Desolvation Model. The desolvation model is now parameterized for all supported atom types instead of just carbon. Because of this, the constant function in AutoGrid is no longer used, since desolvation of polar atoms is treated explicitly. The new model requires calculation of a new map in AutoGrid that holds the charge-based desolvation information.Unbound State. Several models are available for estimating the energetics of the unbound state, including an extended model and a model where the unbound state is assumed to be identical with the protein-bound state.For users of AutoDock 4.0, there are several changes in AutoDock 4.2:Default Unbound State. The default model for the unbound state has been changed from “extended” to “bound=unbound”. This is in response to persistent problems when docking sterically-crowded ligands. The “extended” unbound state model is available in AutoDock 4.2 through use of the “unbound extended” keyword.Backwards Compatibility. We have made every attempt to ensure that docking parameter files generated for use in AutoDock 4.0 should be correctly run by AutoDock 4.2.For users of AutoDock 4.2.3 or 4.2.4, there are several changes in AutoDock 4.2.5:Finer Control of Output. In response to the widespread use of AutoDock in virtual screening, we have modified the “outlev” command to allow more control over the level of output. The default of “1” will now output primarily information on the docked conformations and analysis, and higher levels will provide diagnostic information.Program will Halt with Critical Errors. Several error conditions that previously gave warnings will now cause AutoDock to halt. This is a response to use of AutoDock in virtual screening,where the user may not examine each individual docking experiment, and critical errors may not be noticed.Ligand Internal Electrostatics are now ‘on’ by Default. The electrostatic interactions between non-bonded atoms in flexible ligands are now considered ‘on’ by default. Previous releases of AutoDock required the “intelec” command to turn this on. If you wish to ignore these interactions and restore the previous default behavior, use “intelec off” in your DPF.Force Field Consistency. Smoothing of potentials has been added to internal energy potentials, to make them consistent with intermolecular energy potentials. This will have a small effect on conformations when docking with rigid receptors, and possibly a significant effect on conformations and predicted free energies when docking with flexible receptors. In addition, an error in output of energies with flexible receptors has been corrected, and AutoDock’s intra-ligand desolvation potential cutoff distance has been increased to match AutoGrid’s.For users of AutoDock 4.2.5, there are several changes in AutoDock 4.2.6:Platforms. More computer platforms are supported:•Linux2 on Intel i86 (32-bit) and on Intel x86_64 (64-bit)•Linux3 on Intel x86_64 (64-bit)•Macintosh OS X 10.5 (Leopard) on PowerPC (32- and 64-bit), OS X 10.5-10.9 (Leopard, Snow Leopard, Lion, Mountain Lion, and Mavericks) on Intel i86 (32-bit) and Intelx86_64 (64-bit)•Solaris 8 (SunOS 5.8) on SPARC•Windows 5 (XP), 6 (Vista), 7, 8.1 on Intel i86.Now, both AutoDock and AutoGrid are compiled using double-precision arithmetic. There is also better cross-platform compatibility of the internal random number generator.Improved Error Checking. There is improved error checking of command-line arguments. AutoDock now checks the atom numbers that define internal and “flexres” torsions.Job and Run Provenance and Reproducibility. Each docking log file (dlg) always contains the host name, run date, working directory, and names of input PDBQT files. Each docking run always contains its initial random number seeds, its ending total energy, and its final state in a uniform format suitable for automated analysis. Invoking “autodock4 (or autogrid4) –version” reports compile-time configuration options.Clustering of Multiple Search Algorithms. Now, multiple search methods can be used in a single AutoDock job: for example, 50 runs of Lamarckian Genetic Algorithm followed by 50 runs of Simulated Annealing. The runs are done serially: no results carry over from one algorithm to the next. All results are ranked and clustered together in the analysis step at the end of the entire job.Visualization of Simulated Annealing and Local-Search-Only Runs. You can now use ADT (AutoDock Tools) to visualize results from AutoDock jobs that use simulated annealing or local-search-only. You must download the latest build of ADT from/downloads/latest4.2.6 Release Limitation. The “do_local_only” command runs the pseudo-solis-wets algorithm, even if the solis-wets has been specified using “set_local sw1”. This applies only to“do_local_only”: the “ga_run” command will use whichever local search has been specified. (We recommend the pseudo-solis-wets for all local searches: “set psw1”).For more information about this release, see the Release 4.2.6 Notes on the AutoDock 4.2 download web page.SupportAutoDock is distributed, with full source code, free of charge. There are some caveats, however. Firstly, since we receive limited funding to support the academic community of users, we cannot guarantee response to queries on installation and use. While there is documentation, it may require at least some basic Unix abilities to install. If you still need help:(1) Ask your local system administrator or programming guru for help about compiling, using Unix/Linux, etc.(2) Consult the AutoDock web site, where you will find a wealth of information and a FAQ (Frequently Asked Questions) page with answers on AutoDock:/faqs-help(3) If you can’t find the answer to your problem, send your question to the AutoDock List (ADL) or the AutoDock Forum. There are many seasoned users of computational chemistry software and some AutoDock users who may already know the answer to your question. You can find out more about the ADL on the WWW at:/mailman/listinfo/autodockThe Forum is available on the WWW at:/forum(4) If you have tried (1), (2) and (3), and you still cannot find an answer, send email to goodsell@ for questions about AutoGrid or AutoDock; or to rhuey@ for questions about AutoDockTools.Thanks for your understanding!E-mail addressesArthur J. Olson, Ph.D. olson@David S. Goodsell, Ph.D. goodsell@Ruth Huey, Ph.D. rhuey@Fax: +1 (858) 784-2860The Scripps Research InstituteMolecular Graphics LaboratoryDepartment of Molecular Biology, Mail Drop MB-510550 North Torrey Pines RoadLa Jolla, CA 92037-1000, U.S.A.TheoryOverview of the Free Energy Scoring FunctionAutoDock 4.2 uses a semi-empirical free energy force field to evaluate conformations during docking simulations. The force field was parameterized using a large number of protein-inhibitor complexes for which both structure and inhibition constants, or K i , are known.The force field evaluates binding in two steps. The ligand and protein start in an unbound conformation. In the first step, the intramolecular energetics are estimated for the transition from these unbound states to the conformation of the ligand and protein in the bound state. The second step then evaluates the intermolecular energetics of combining the ligand and protein in their bound conformation.The force field includes six pair-wise evaluations (V) and an estimate of the conformational entropy lost upon binding (ΔS conf ):"G =(V bound L #L #V unbound L #L )+(V bound P #P #V unbound P #P )+(V bound P #L #V unbound P #L +"S conf )where L refers to the “ligand” and P refers to the “protein” in a ligand-protein docking calculation.Each of the pair-wise energetic terms includes evaluations for dispersion/repulsion, hydrogen bonding, electrostatics, and desolvation:The weighting constants W have been optimized to calibrate the empirical free energy based on a set of experimentally determined binding constants. The first term is a typical 6/12 potential for dispersion/repulsion interactions. The parameters are based on the Amber force field. The second term is a directional H-bond term based on a 10/12 potential. The parameters C and D are assigned to give a maximal well depth of 5 kcal/mol at 1.9Å for hydrogen bonds with oxygen and nitrogen, and a well depth of 1 kcal/mol at 2.5Å for hydrogen bonds with sulfur. The function E(t) provides directionality based on the angle t from ideal H-bonding geometry. The third term is a screened Coulomb potential for electrostatics. The final term is a desolvation potential based on the volume of atoms (V) that surround a given atom and shelter it from solvent, weighted by a solvation parameter (S) and an exponential term with distance-weighting factor σ=3.5Å. For a detailed presentation of these functions, please see our published reports, included in Appendix IV.By default, AutoGrid and AutoDock use a standard set of parameters and weights for the force field. The parameter_file keyword may be used, however, to use custom parameter files. The format of the parameter file is described in Appendix I.Several methods for estimating the contribution of the unbound state are implemented in AutoDock. In Autodock 3.0 and earlier versions, an assumption is made that the unbound formof the ligand (V L-Lbound in the equation above) is the same as the final docked conformation of theligand (V L-Lunbound ), yielding a final contribution V L-Lbound-V L-Lunbound= 0. AutoDock 4.1introduced a method of generating an extended form of the ligand to model the unbound state. Reports from users, however, revealed that the method caused significant problems with sterically-crowded molecules, and the default method was changed to the bound=unbound assumption in AutoDock 4.2 and later. In addition, there is an option for a user-defined unbound state.Viewing Grids in AutoDockTools. The protein is shown on the left in white bonds, and the grid box is shown on the right side. The blue contours surround areas in the box that are most favorable for binding of carbon atoms, and the red contours show areas that favor oxygen atoms. A ligand is shown inside the box at upper right.AutoDock Potentials. Examples of the four contributions to the AutoDock force field are shown in this graph. The dispersion/repulsion potential is for interaction between two carbon atoms. The hydrogen bond potential, which extends down to a minimum of about –2 kcal/mol, is shown for an oxygen-hydrogen interaction. The electrostatic potential is shown for interaction of two oppositely-charged atoms with a full atomic charge. The desolvation potential is shown for acarbon atom, with approximately 10 atoms displacing water at each distance.Using AutoDockSTEP 1: Preparing CoordinatesThe first step is to prepare the ligand and receptor coordinate files to include the information needed by AutoGrid and AutoDock. These coordinate files are created in an AutoDock-specific coordinate file format, termed PDBQT, which includes:1) Polar hydrogen atoms;2) Partial charges;3) Atom types;4) Information on the articulation of flexible molecules.For a typical docking calculation, you will create a file of coordinates for the receptor, and a separate file of coordinates for the ligand. In dockings where selected amino acids in the receptor are treated as flexible, you will create a third file that includes the coordinates of the atoms in the flexible portions of the receptor.In a typical study, the user prepares coordinate files in several steps using AutoDockTools. A detailed tutorial is available on the AutoDock WWW site to guide you through this process. The first two steps may be performed using the tools in the Edit menu of AutoDockTools, or with other molecular modeling programs:1) Add hydrogen atoms to the molecule.2) Add partial charges.Then, read the molecule into AutoDockTools using the Ligand (for the ligand) or Grid (for the receptor) menus, and create the PDBQT file:3) Delete non-polar hydrogens and merge their charges with the carbon atoms.4) Assign atom types, defining hydrogen bond acceptors and donors and aromatic and aliphatic carbon atoms.5) Choose a root atom that will act as the root for the torsion tree description of flexibility.6) Define rotatable bonds and build the torsion tree.There are a few things to keep in mind during this process:Be Critical. AutoDockTools and PMV currently use a modified version of Babel to add hydrogen atoms and assign charges. Unfortunately the method has trouble with some molecules. In those cases, hydrogen positions and charges may be assigned by the user’s preferred method, e.g. using Reduce, InsightII, Quanta, Sybyl, AMBER or CHARMm.Check Your Hydrogen Positions. In addition, most modeling systems add polar hydrogens in a default orientation, typically assuming each new torsion angle is 0° or 180°. Without some formof refinement, this can lead to spurious locations for hydrogen bonds. One option is to relax the hydrogens and perform a molecular mechanics minimization on the structure. Another is to use a program like “pol_h” which takes as input the default-added polar hydrogen structure, samples favorable locations for each movable proton, and selects the best position for each. This “intelligent” placement of movable polar hydrogens can be particularly important for tyrosines, serines and threonines.Watch for Disordered Residues. Care should be taken when the PDB file contains disordered residues, where alternate location indicators (column 17) have been assigned. For each such atom, the user must select only one of the possible alternate locations, making sure that a locally consistent set is chosen.Randomize Starting Coordinates When Redocking.In redocking experiments, where coordinates from a known protein-ligand complex are separated and docked, it is important to randomize the conformation of the ligand before it is docked. The techniques used to implement rotation of the ligand may be biased to prefer values of zero rotation, so to obtain an unbiased result, create a pdbqt file with the randomized ligand coordinates using the "Randomize" command in the ADT Ligand menu, then use this randomized coordinate file for docking experiments.Please note: coordinate preparation is the most important step in the docking simulation. The quality and accuracy of the docked results will only be as good as the quality of the starting coordinates. Be critical and carefully examine hydrogen positions, atom type assignments, partial charges, and articulation of the molecules to ensure that they make sense chemically. If you are using the Babel method within AutoDockTools to add charges and hydrogens, carefully check the results and make corrections if necessary—it often has trouble with molecules such as nucleotides.Creating PDBQT files in AutoDockToolsOverview of AutoDockToolsAutoDockTools is a set of commands implemented within the Python Molecular Viewer (PMV), providing a Graphical User Interface for AutoGrid and AutoDock. It is available at: /resources/adt.The AutoDockTools window has several parts:1) at the top are menus that access the general methods available in PMV. These include tools for reading and writing coordinates and images, for modifying coordinates, for selection, and for visualization.2) a row of buttons at the top allows quick access to the most popular tools of PMV3) below the buttons, there are a series of menus that access the AutoDock-specific tools of AutoDockTools.4) the 3-D molecular viewer is at center right.5) the Dashboard, located to the left of the viewer, allows quick selection, visualization, and coloring of molecules currently displayed in the viewer.Hydrogen Atoms and ChargesThe tools available in PMV are used to read coordinates in PDB and other formats, to add hydrogens, to select portions of the molecule, and to add partial charges. These functions are all accessed through menus at the top of the PMV window. A few useful commands will be described here—for more information on the many other functions of PMV, please see the PMV documentation.File>ReadMolecule: opens a browser that allows reading of PDB coordinate files.Edit>Delete:several options for deleting entire molecules, selected sets of atoms, or hydrogen atoms.Edit>Hydrogens>Add: options for adding all hydrogens or polar hydrogens using Babel. Edit>Charges: options for computing Gasteiger charges for arbitrary molecules using Babel. Ligand PDBQT Files – the “Ligand” MenuOnce ligand coordinates are created with hydrogen atoms and charges, they can be processed in the “Ligand” menu to create the ligand PDBQT file.Ligand>Input>QuickSetup:uses defaults to create the PDBQT file. PDB files can be read from the PMV viewer or from a file, and written directly to a new PDBQT file. Please note that hydrogen atoms will not be added.Ligand>Input>Open: reads coordinates from a file.Ligand>Input>Choose: chooses a molecule already read into PMV.Ligand>Input>OpenAsRigid: reads an existing PDBQT file and writes a new file with NO active torsions.Ligand>TorsionTree>ChooseRoot: manual selection of the root atom.Ligand>TorsionTree>DetectRoot:automatic detection of the root that provides the smallest largest subtree.Ligand>TorsionTree>ShowRootExpansion: for molecules with several atoms in the root, displays small spheres to show all atoms in the root, including atoms connected to each root atom by rigid bonds.Ligand>TorsionTree>ShowRootMarker: displays a sphere on the root atom.Ligand>TorsionTree>ChooseTorsions: launches an interactive browser for choosing rotatable bonds. Rotatable bonds are shown in green, and non-rotatable bonds are shown in red. Bonds that are potentially rotatable but treated as rigid, such as amide bonds and bonds that are made rigid by the user, are shown in magenta. Rotation of rotatable bonds may be switched on and off by clicking on the bonds.Ligand>TorsionTree>SetNumberOfTorsions: sets the number of rotatable bonds in the ligand by leaving the specified number of bonds as rotatable. The two options will choose the torsions that rotate either the fewest atoms in the ligand or the most atoms in the ligand. Ligand>AromaticCarbon>SetNames:clicking on atom positions will switch carbon atoms between aromatic and aliphatic. Aromatic carbons are shown in green. Click on the “Stop” button when finished.Ligand>AromaticCarbon>AromaticityCriterion: Sets the angular deviation from planarity that AutoDockTools uses to identify aromatic rings.Ligand>Output>RandomizethenSaveasPDBQT:randomizes the conformation of the ligand and writes the formatted PDBQT file.Ligand>Output:opens a browser to write the formatted PDBQT file.Rigid Receptor PDBQT Files – the “Grid” MenuFor docking calculations using rigid receptor coordinates, add the hydrogen atoms and charges in PMV, then read the coordinates into AutoDockTools using the “Grid” menu.Grid>Macromolecule>Open: launches a browser to open an existing PDBQT file.Grid>Macromolecule>Choose:chooses a molecule that has been previously read into PMV. It will merge non-polar hydrogen atoms and charges, assign aromatic carbons, and prompt the user to write a PDBQT file.Flexible Receptor PDBQT Files – the “FlexibleResidues” MenuFor docking calculations with selected flexibility in the receptor, add the hydrogen atoms and charges in PMV, then create two PDBQT files in AutoDockTools, one for the rigid portion of the receptor and one for the flexible atoms.FlexibleResidues>Input>OpenMacromolecule:launches a browser to open an existing PDBQT file.。
Altair Basic 3.X和4.X 88-PIO 引导加载器说明书
Loading Basic with the 88-PIO BoardIncluding support for the Oliver Audio Engineering OP-80 Paper Tape ReaderMartin Eberhard 6 June 2013Corrected 12 Jul 2013. Corrected and enhanced 15 Dec 2019.Standard 88-PIO Bootstrap LoaderBelow is the standard Altair Basic 3.X and 4.X 88-PIO bootstrap loader, to be toggled in via the front panel. Important 88-PIO Bootstrap Loader notes:1.The 88-PIO bootstrap loader in the Basic 4.0 manual is incorrect. The correction is noted below.2.This loader will fail if the reader generates any strobe pulses on the parallel port interface before the dataload. For example, it is common for a paper tape reader to generate strobe pulses while loading paper tape into the reader. (See the next section for an improved bootstrap loader.)3.MITS changed the standard address of the 88-PIO between Basic 3.X and Basic4.X. For Basic 3.X, the 88-PIObase address is 000. For Basic 4.X and later, the 88-PIO base address is 004. You must set up the 88-PIO hardware correctly for the version of Basic that you plan to load.4.The bytes at bootstrap loader addresses 001, 004, and 014 all change with the version of Basic.5.The byte at bootstrap loader address 002 changes for different sizes of Basic.6.Basic 3.X uses the same port for loading Basic as it does for the Basic console. This makes loading Basic 3.Xfrom a stand-alone paper tape reader tricky.7.The “leader” portion of the paper tape should be positioned in the reader before running the bootstraploader. The leader is octal 256 for Basic 3.X, and octal 302 for Basic 4.X and later. (Paper tapes often have several inches of nulls before the leader. Nulls have only the sprocket holes punched.)8.The sense switches are set differently depending on the version of Basic. See below.Octal Address Octal Data Mnemonic Comment000 041 LXI H,LADDR Checksum Loader last address001 302 (256 for Basic 3.X, 302 for Basic 4.X and later)002 037 (017 for 4K, 037 for 8K, 077 for Extended Basic)003 061 LXI SP,STACK Used for the following return instructions004 023005 000006 333 IN PSTAT Get 88-PIO status007 004 (000 for Basic 3.X, 004 for Basic 4.X and later)010 346 ANI PDAVAIL Any received data available?011 002 <---Altair Basic 4.0 manual had incorrect 001 here012 310 RZ No: loop back to address 003013 333 IN PDATA Get 88-PIO data014 005 (001 for Basic 3.X, 005 for Basic 4.X and later)015 275 CMP L Is this a leader byte?016 310 RZ Yes: loop back to address 003017 055 DCR L Next address, set Z flag if done020 167 MOV M,A Write data to memory021 300 RNZ Loop back to address 003 unless done022 351 PCHL Jump to loaded checksum loader023 003 Local stack address for above returns024 000Improved 88-PIO Bootstrap LoaderThe 88-PIO will latch and hold its input-port data until the input port is read by software. It is common for the 88-PIO’s data latch to contain a garbage data byte that was generated, for example, by loading paper tape into the reader. (It is nearly impossible not to create a garbage byte while setting up an OP-80 paper tape reader.)If the 88-PIO input port does contain a garbage byte at the beginning of the load, then the load will fail – since the MITS bootstrap loader will interpret the garbage byte as the first byte of the paper tape data.The simple solution (implemented in the following bootstrap loader) is for the bootstrap loader to perform one read of the 88-PIO data port during its initialization phase, to clear out any potential garbage data. This improvement should work for any device that is attached to the 88-PIO.Important notes for this modified 88-PIO Bootstrap Loader1.MITS changed the standard address of the 88-PIO between Basic 3.X and Basic 4.X. For Basic 3.X, the 88-PIObase address is 000. For Basic 4.X and later, the 88-PIO base address is 004. You must set up the 88-PIO hardware correctly for the version of Basic that you plan to load.2.The bytes at bootstrap loader addresses 001, 004, 011 and 016 all change with the version of Basic.3.The byte at bootstrap loader address 002 changes for different sizes of Basic.4.Basic 3.X uses the same port for loading Basic as it does for the Basic console. This makes loading Basic 3.Xfrom a stand-alone paper tape reader tricky.5.The “leader” portion of the paper tape should be positioned in the reader before running the bootstraploader. The leader is octal 256 for Basic 3.X, and octal 302 for Basic 4.X and later. (Paper tapes often have several inches of nulls before the leader. Nulls have only the sprocket holes punched.) For an OP-80 reader, position the tape such that the optical sensors are blocked by paper tape (between holes in the leader) before running the bootstrap loader.6.Set the sense switches for loading from the 88-PIO, before running the bootstrap loader. See below.Octal Address Octal Data Mnemonic Comment000 041 LXI H,LADDR Checksum Loader last address001 302 (256 for Basic 3.X, 302 for Basic 4.X and later)002 037 (017 for 4K, 037 for 8K, 077 for Extended Basic)003 333 IN PDATA Read 88-PIO data to clear OP-80004 005 (001 for Basic 3.X, 005 for Basic 4.X and later)005 061 LXI SP,STACK Used for the following return instructions006 025007 000010 333 IN PSTAT Get 88-PIO status011 004 (000 for Basic 3.X, 004 for Basic 4.X and later)012 346 ANI PDAVAIL Any received data available?013 002014 310 RZ No: loop back to address 003015 333 IN PDATA Get 88-PIO data016 005 (001 for Basic 3.X, 005 for Basic 4.X and later)017 275 CMP L Is this a leader byte?020 310 RZ Yes: loop back to address 003021 055 DCR L Next address, set Z flag if done022 167 MOV M,A Write data to memory023 300 RNZ Loop back to address 003 unless done024 351 PCHL Jump to loaded checksum loader025 003 Local stack address for above returns026 000Basic 3.X Sense Switch SettingsThe Basic 3.X loader uses the same port for loading Basic and for the Console.Load & Console A15 A14 A13 A12 A11 A10 A9 A888-SIOA,B,C (not rev 0) 0 0 0 0 0 0 0 088-SIOA,B,C (rev 0) 0 1 0 0 0 0 0 088-PIO 0 0 1 0 0 0 0 088-4PIO 0 0 0 1 0 0 0 088-2SIO-0 (1 stop bit) 0 0 0 0 1 1 0 088-2SIO-0(2 stop bits) 0 0 0 0 1 0 0 0Basic 4.X Sense Switch SettingsThe Basic 4.X loader makes a distinction between the Load Source and the Console Device, allowing you to load from one device, and use another for the Basic console.Load Source A11 A10 A9 A8 Console Device A15 A14 A13 A12 88-2SIO-0 (2 stop bits) 0 0 0 0 88-2SIO-0 (2 stop bits) 0 0 0 0 88-2SIO-0 (1 stop bit) 0 0 0 1 88-2SIO-0 (1 stop bit) 0 0 0 1 88-SIO 0 0 1 0 88-SIO 0 0 1 0 88-ACR 0 0 1 1 (not allowed) 0 0 1 1 88-4PIO 0 1 0 0 88-4PIO 0 1 0 0 88-PIO 0 1 0 1 88-PIO 0 1 0 1 HSR 0 1 1 0 (not allowed) 0 1 1 0Basic 4.X Loader Error MessagesError Code MeaningC Checksum error. Bad tape data.M Memory error. Data won’t store properly.O Overlay error. Attempt to overwrite checksum loader.I Invalid Load source. Illegal sense -switch setting.Basic 4.X Initialization Dialog4K BasicMEMORY SIZE? (<RETURN> to use all memory. Basic uses 3.4K.)TERMINAL WIDTH? (<RETURN> for 72 columns)SIN? (Y saves SIN, SQR and RND. N deletes SIN and brings next question.)SQR? (Y saves SQR and RND. N deletes SQR and brings next question.)RND? (Y saves RND, N deletes RND.)8K BasicMEMORY SIZE? (<RETURN> to use all memory. Basic uses 6.2K.)TERMINAL WIDTH? (<RETURN> for 72 columns)WANT SIN-COS-TAN-ATN? (Y or N)Extended BasicMEMORY SIZE? (<RETURN> to use all memory. Basic uses 14.6K.)LINEPRINTER? (O for 80LP, C for C700, Q for Q70)WANT SIN-COS-TAN-ATN? (Y or N)Connecting the OP-80 to the 88-PIOThe OP-80 has just one configuration jumper, that selects either active-high or active-low acknowledge. This jumper should be set for Active low acknowledge, since the BIN output from the 88-PIO is active low.Connect the OP-80 to the 88-PIO via a DB25 connector set on the back of the Altair, as follows. The wire colors for the 88-PIO are just suggestions. The DB25 pinout is compatible with the Altair 88-4PIO. The wire colors for the OP-80 are those found on its rainbow ribbon cable.88-PIO DB25 OP-80 Function 8212 function Pin Wire color Pin Wire Color Pin Function N/C 1 Orange 7 RDASBI H STB 19 Orange/black 2 Brown 6 /RDABIN H /INT 20 White 3 White 5 /ACKDI0 H DI0 11 Brown 4 Brown 1 D0DI1 H DI1 12 Red 5 Red 16 D1Ground Note 1Green/black 6 Green 8 GroundVcc Note 1 Blue/black 7 Blue 9 +5V89DO6 G DO6 7 Grey/black 10DO7 G DO7 8 Pink 11SBO G STB 9 Light Blue 12BO G /INT 10 Light Green 13DI2 H DI2 13 Orange 14 Orange 2 D2DI3 H DI3 14 Yellow 15 Yellow 15 D3DI4 H DI4 15 Green 16 Green 3 D4DI5 H DI5 16 Blue 17 Blue 14 D5DI6 H DI6 17 Violet 18 Violet 4 D6DI7 H DI7 18 Grey 19 Grey 13 D7DO0 G DO0 1 Yellow/black 20 Yellow 10 S1DO1 G DO1 2 Red/black 21 Red 11 S2DO2 G DO2 3 Black 22 Black 12 SPAREDO3 G DO3 4 Brown/black 23DO4 G DO4 5 Violet/black 24DO5 G DO5 6 White/black 25Note 1: The 88-PIO (amazingly) has no ground pin on its interface. (See page 12 of the 88-PIO manual.) Because the OP-80 is powered by the interface, it is necessary to provide both ground and regulated +5V tothe DB25, from the 88-PIO. You can do this (without damaging the 88-PIO board) by tack-soldering a 3-pin connector onto the back of the 88-PIO board, at the top, where the +5V trace is parallel to the groundtrace. (Use a 3-pin connector so that you can key it, to prevent connecting it the wrong way.) Then put a mating connector on the wires from DB25 pins 06 and 08, and plug this connector into the one that you installed on the 88-PIO.•Since Basic 3.X uses the same port for loading Basic as it does for the console, the OP-80 (or any stand-alone paper tape reader) is not practical for loading Basic 3.X. However, the OP-80 works great for loading Basic 4.X. •Pull the paper tape through the OP-80 at about 2 feet per second. A crank-driven paper tape winder is an excellent addition to the OP-80.。
Flex System x440 Compute Node(7917)产品指南(已撤销产品)说明书
Flex System x440 Compute Node (7917)Product Guide (withdrawn product)The Lenovo Flex System x440 Compute Node is a four-socket Intel Xeon processor-based server that is optimized for high-end virtualization, mainstream database deployments, and memory-intensive, high-performance environments.Based on the Intel Xeon E5-4600 processors, it is price-performance optimized with a selection of processors, memory, and I/O options to help you match system capabilities and cost to workloads without compromise. The Flex System x440 Compute Node can help reduce floor space that is used and lower data center power and cooling costs.Suggested usage: Database, virtualization, and enterprise applications.Figure 1 shows the Flex System x440 Compute Node.Figure 1. The Flex System x440 Compute NodeDid you know?Flex System is a new category of computing that integrates multiple server architectures, networking, storage, and system management capability into a single system that is easy to deploy and manage. Flex System has full, built-in virtualization support of servers, storage, and networking to speed provisioning and increased resiliency. In addition, it supports open industry standards, such as operating systems, networking and storage fabrics, virtualization, and system management protocols, to easily fit within existing and future data center environments. Flex System is scalable and extendable with multi-generation upgrades to protect and maximize IT investments.Click here to check for updatesLocations of key components and connectors Figure 2 shows the front of the server.Figure 2. Front view of the Flex System x440 Compute Node Figure 3 shows the locations of key components inside the server.Figure 3. Inside view of the Flex System x440 Compute NodeStandard modelsThe following table lists the standard models. Table 2. Standard modelsModel Intel Xeon processor(4 maximum)**Memory DiskadapterDisk bays(used/max)†Disks10 GbEEmbeddedVirtualFabric‡I/O slots(used/max)7917-A2x Xeon E5-4603 4C 2.0 GHz10 MB 1066 MHz 95W 1x 8 GB1066 MHz*SAS/SATARAID2.5” hot-swap(0 / 2)Open No0 / 47917-A4x Xeon E5-4603 4C 2.0 GHz10 MB 1066 MHz 95W 1x 8 GB1066 MHz*SAS/SATARAID2.5” hot-swap(0 / 2)Open Standard 2 / 4‡7917-B2x Xeon E5-4607 6C 2.2 GHz12 MB 1066 MHz 95W 1x 8 GB1066 MHz*SAS/SATARAID2.5” hot-swap(0 / 2)Open No0 / 47917-B4x Xeon E5-4607 6C 2.2 GHz12 MB 1066 MHz 95W 1x 8 GB1066 MHz*SAS/SATARAID2.5” hot-swap(0 / 2)Open Standard 2 / 4‡7917-C2x Xeon E5-4610 6C 2.4 GHz15 MB 1333 MHz 95W 1x 8 GB1333 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open No0 / 47917-C4x Xeon E5-4610 6C 2.4 GHz15 MB 1333 MHz 95W 1x 8 GB1333 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open Standard 2 / 4‡7917-D2x Xeon E5-4620 8C 2.2 GHz16 MB 1333 MHz 95W 1x 8 GB1333 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open No0 / 47917-D4x Xeon E5-4620 8C 2.2 GHz16 MB 1333 MHz 95W 1x 8 GB1333 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open Standard 2 / 4‡7917-F2x Xeon E5-4650 8C 2.7 GHz20 MB 1600 MHz 130W 1x 8 GB1600 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open No0 / 47917-F4x Xeon E5-4650 8C 2.7 GHz20 MB 1600 MHz 130W 1x 8 GB1600 MHzSAS/SATARAID2.5” hot-swap(0 / 2)Open Standard 2 / 4‡** Processor detail: Processor quantity and model, cores, core speed, L3 cache, memory speed, and power consumption.* For models Axx and Bxx, the standard DIMM is rated at 1333 MHz, but operates at up to 1066 MHz to match the processor memory speed.† The 2.5-inch drive bays can be replaced and expanded with additional internal bays to support up to eight 1.8-inch solid-state drives (SSDs). See the "Internal disk storage options" section.‡ The x4x models include two Embedded 10Gb Virtual Fabric Ethernet controllers. Connections are routed using a Fabric Connector. The Fabric Connectors preclude the use of an I/O adapter in I/O connectors 1 and 3, except the ServeRAID M5115 controller, which can be installed in slot 1.Chassis supportIf memory mirroring is used, then DIMMs must be installed in pairs (minimum of one pair per processor), and both DIMMs in a pair must be identical in type and size.If memory rank sparing is used, then a minimum of one quad-rank DIMM or two single-rank or dual-rank DIMMs must be installed per populated channel (the DIMMs do not need being identical). In rank sparing mode, one rank of a DIMM in each populated channel is reserved as spare memory. The size of a rank varies depending on the DIMMs installed.The following table lists the memory options that are available for the x440 Compute Node.Table 6. Memory optionsPart number FeaturecodeDescription MaximumsupportedWhereusedUDIMMs49Y140486484GB (1x4GB, 2Rx8, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP UDIMM 32 (8 per processor)-RDIMMs - 1333 MHz49Y140689414GB (1x4GB, 1Rx4, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP RDIMM 48 (12 per processor)-49Y140789424GB (1x4GB, 2Rx8, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP RDIMM 48 (12 per processor)-49Y139789238GB (1x8GB, 2Rx4, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP RDIMM 48 (12 perprocessor)All othermodels49Y1563A1QT16GB (1x16GB, 2Rx4, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP RDIMM 48 (12 per processor)-RDIMMs - 1600 MHz49Y1559A28Z4GB (1x4GB, 1Rx4, 1.5V) PC3-12800 CL11 ECC DDR31600MHz LP RDIMM 48 (12 per processor)-90Y3109A2928GB (1x8GB, 2Rx4, 1.5V) PC3-12800 CL11 ECC DDR31600MHz LP RDIMM 48 (12 perprocessor)F2x andF4x46W0672A3QM16GB (1x16GB, 2Rx4, 1.35V) PC3L-12800 CL11 ECC DDR31600MHz LP RDIMM 48 (12 per processor)-00D4968A2U516GB (1x16GB, 2Rx4, 1.5V) PC3-12800 CL11 ECC DDR31600MHz LP RDIMM 48 (12 per processor)-LRDIMMs90Y3105A29132GB (1x32GB, 4Rx4, 1.35V) PC3L-10600 CL9 ECC DDR31333MHz LP LRDIMM 48 (12 per processor)-Internal storageattachment locations and flex cables for attachment to up to four 1.8-inch SSDs.Note: The above kits are specific for the x440 and cannot be used with the x240 or x220.The following table shows the kits required for each combination of drives. For example, if you plan to install eight 1.8-inch SSDs, then you need the M5115 controller, the Flash Kit, and the SSD Expansion kit.Table 8. ServeRAID M5115 hardware kitsDesired drive support Components requiredMaximum number of 2.5-inch drives Maximumnumber of1.8-inchSSDsServeRAIDM511590Y4390Enablement Kit46C9030Flash Kit47C8809SSDExpansion Kit46C903220=>Required Required0 4 (front)=>Required Required2 4 (internal)=>Required Required Required08 (both)=>Required Required RequiredThe following figure shows how the ServeRAID M5115 and the Enablement Kit are installed in the server tosupport two 2.5-inch drives with MegaRAID CacheVault flash cache protection (row 1 of previous table).Figure 4. The ServeRAID M5115 and the Enablement Kit installedThe following figure shows how the ServeRAID M5115 and Flash and SSD Expansion Kits are installed in the server to support eight 1.8-inch solid-state drives (row 4 of the previous table).Figure 5. ServeRAID M5115 with Flash and SSD Expansion Kits installedPart number Feature code Description Maximumsupported90Y8944A2ZK146GB 15K 6Gbps SAS 2.5" SFF G2HS SED290Y8913A2XF300GB 10K 6Gbps SAS 2.5" SFF G2HS SED244W22645413300GB 10K 6Gbps SAS 2.5" SFF Slim-HS SED290Y8908A3EF600GB 10K 6Gbps SAS 2.5" SFF G2HS SED281Y9662A3EG900GB 10K 6Gbps SAS 2.5" SFF G2HS SED200AD085A48T 1.2TB 10K 6Gbps SAS 2.5'' G2HS SED215K SAS hard disk drives90Y8926A2XB146GB 15K 6Gbps SAS 2.5" SFF G2HS HDD281Y9670A283300GB 15K 6Gbps SAS 2.5" SFF HS HDD200AJ300A4VB600GB 15K 6Gbps SAS 2.5'' G2HS HDD2NL SATA drives81Y9722A1NX250GB 7.2K 6Gbps NL SATA 2.5" SFF HS HDD281Y9726A1NZ500GB 7.2K 6Gbps NL SATA 2.5" SFF HS HDD281Y9730A1AV1TB 7.2K 6Gbps NL SATA 2.5" SFF HS HDD2NL SAS drives90Y8953A2XE500GB 7.2K 6Gbps NL SAS 2.5" SFF G2HS HDD281Y9690A1P31TB 7.2K 6Gbps NL SAS 2.5" SFF HS HDD2SAS-SSD Hybrid drive00AD102A4G7600GB 10K 6Gbps SAS 2.5'' G2HS Hybrid2Enterprise SSDs49Y6129A3EW200GB SAS 2.5" MLC HS Enterprise SSD249Y6134A3EY400GB SAS 2.5" MLC HS Enterprise SSD249Y6139A3F0800GB SAS 2.5" MLC HS Enterprise SSD249Y6195A4GH 1.6TB SAS 2.5" MLC HS Enterprise SSD241Y8331A4FL S3700 200GB SATA 2.5" MLC HS Enterprise SSD241Y8336A4FN S3700 400GB SATA 2.5" MLC HS Enterprise SSD241Y8341A4FQ S3700 800GB SATA 2.5" MLC HS Enterprise SSD200W1125A3HR100GB SATA 2.5" MLC HS Enterprise SSD243W7718A2FN200GB SATA 2.5" MLC HS SSD2Enterprise Value SSDs90Y8648A2U4128GB SATA 2.5" MLC HS Enterprise Value SSD290Y8643A2U3256GB SATA 2.5" MLC HS Enterprise Value SSD200AJ000A4KM S3500 120GB SATA 2.5" MLC HS Enterprise Value SSD200AJ005A4KN S3500 240GB SATA 2.5" MLC HS Enterprise Value SSD200AJ010A4KP S3500 480GB SATA 2.5" MLC HS Enterprise Value SSD200AJ015A4KQ S3500 800GB SATA 2.5" MLC HS Enterprise Value SSD200FN268A5U4S3500 1.6TB SATA 2.5" MLC HS Enterprise Value SSD800AJ355A56Z120GB SATA 2.5" MLC HS Enterprise Value SSD200AJ360A570240GB SATA 2.5" MLC HS Enterprise Value SSD200AJ365A571480GB SATA 2.5" MLC HS Enterprise Value SSD200AJ370A572800GB SATA 2.5" MLC HS Enterprise Value SSD2* Supports self-encrypting drive (SED) technology. For more information, see Self-Encrypting Drives for System x at /tips0761.The 1.8-inch solid state drives supported are listed in the following table. The use of 1.8-inch drives requires the ServeRAID M5115 SAS/SATA controller.Table 11. Supported 1.8-inch solid state drivesPart number FeaturecodeDescription MaxsupportEnterprise SSDs00W1120A3HQ100GB SATA 1.8" MLC Enterprise SSD849Y6119A3AN200GB SATA 1.8" MLC Enterprise SSD849Y6124A3AP400GB SATA 1.8" MLC Enterprise SSD841Y8366A4FS S3700 200GB SATA 1.8" MLC Enterprise SSD841Y8371A4FT S3700 400GB SATA 1.8" MLC Enterprise SSD8Enterprise Value SSDs00AJ335A56V120GB SATA 1.8" MLC Enterprise Value SSD800AJ340A56W240GB SATA 1.8" MLC Enterprise Value SSD800AJ345A56X480GB SATA 1.8" MLC Enterprise Value SSD800AJ350A56Y800GB SATA 1.8" MLC Enterprise Value SSD800AJ040A4KV S3500 80GB SATA 1.8" MLC Enterprise Value SSD800AJ045A4KW S3500 240GB SATA 1.8" MLC Enterprise Value SSD800AJ050A4KX S3500 400GB SATA 1.8" MLC Enterprise Value SSD800AJ455A58U S3500 800GB SATA 1.8" MLC Enterprise Value SSD8Internal tape drivesThe server does not support an internal tape drive. However, it can be attached to external tape drives using Fibre Channel connectivity.Optical drivesThe server does not support an internal optical drive option, however, you can connect an external USB optical drive. See /en/documents/pd011281 for information about available external optical drives from Lenovo.Note: The USB port on the compute nodes supply up to 0.5 A at 5 V. For devices that require more power, an additional power source will be required.Embedded 10Gb Virtual FabricFigure 6. Location of the I/O adapter slots in the Flex System x440 Compute NodeAll I/O adapters are the same shape and can be used in any available slot. A compatible switch or pass-through module must be installed in the corresponding I/O bays in the chassis, as indicated in the following table. Installing two switches means that all ports of the adapter are enabled, which improves performance and network availability.Table 13. Adapter to I/O bay correspondenceI/O adapter slot in the server Port on the adapter Corresponding I/O module bay in the chassis Slot 1Port 1Module bay 1Port 2Module bay 2Port 3 (for 4-port cards)Module bay 1Port 4 (for 4-port cards)Module bay 2Slot 2Port 1Module bay 3Port 2Module bay 4Port 3 (for 4-port cards)Module bay 3Port 4 (for 4-port cards)Module bay 4Slot 3Port 1Module bay 1Port 2Module bay 2Port 3 (for 4-port cards)Module bay 1Port 4 (for 4-port cards)Module bay 2Slot 4Port 1Module bay 3Port 2Module bay 4Port 3 (for 4-port cards)Module bay 3Port 4 (for 4-port cards)Module bay 4For a list of supported switches, see the Flex System Interoperability Guide, available from:/fsigFigure 7 shows the location of the switch bays in the Flex System Enterprise Chassis.Figure 7. Location of the switch bays in the Flex System Enterprise ChassisFigure 8 shows how 2-port adapters are connected to switches installed in the chassis.Figure 8. Logical layout of the interconnects between I/O adapters and I/O modules Network adaptersNetwork adaptersAs described in the Embedded 10Gb Virtual Fabric section, certain models (those with a model number of the form x4x) have two 10 Gb Ethernet controllers on the system board, and its ports are routed to the midplane and switches installed in the chassis through two Compute Note Fabric Connectors that takes the place of adapters in I/O slots 1 and 3.Models without the Embedded 10Gb Virtual Fabric controller (those with a model number of the form x2x) do not include any other Ethernet connections to the Enterprise Chassis midplane as standard. Therefore, for those models, an I/O adapter must be installed to provide network connectivity between the server and the chassis midplane and ultimately to the network switches.The following table lists the supported network adapters and upgrades. Adapters can be installed in any slot. However, compatible switches must be installed in the corresponding bays of the chassis.Table 14. Network adaptersPart number Featurecode Description Numberof portsMaximumsupported*40 Gb Ethernet90Y3482A3HK Flex System EN6132 2-port 40Gb Ethernet Adapter4410 Gb Ethernet88Y5920A4K3Flex System CN4022 2-port 10Gb Converged Adapter2490Y3554A1R1Flex System CN4054 10Gb Virtual Fabric Adapter4400Y3306A4K2Flex System CN4054R 10Gb Virtual Fabric Adapter4490Y3558A1R0Flex System CN4054 Virtual Fabric Adapter (SW Upgrade)(Feature on Demand to provide FCoE and iSCSI support)License490Y3466A1QY Flex System EN4132 2-port 10Gb Ethernet Adapter241 Gb Ethernet49Y7900A10Y Flex System EN2024 4-port 1Gb Ethernet Adapter44 InfiniBand90Y3454A1QZ Flex System IB6132 2-port FDR InfiniBand Adapter22* For x4x models with two Embedded 10Gb Virtual Fabric controllers standard, the Compute Node Fabric Connectors occupy the same space as the I/O adapters in I/O slots 1 and 3, so you have to remove the Fabric Connectors if you plan to install adapters in those I/O slots. To use slots 3 and 4 requires the second processor. For adapter-to-switch compatibility, see the Flex System Interoperability Guide: /fsigStorage host bus adaptersStorage host bus adaptersThe following table lists storage HBAs supported by the x440 server. Table 15. Storage adaptersPart number Featurecode Description Numberof portsFibre Channel88Y6370A1BP Flex System FC5022 2-port 16Gb FC Adapter269Y1938A1BM Flex System FC3172 2-port 8Gb FC Adapter295Y2375A2N5Flex System FC3052 2-port 8Gb FC Adapter295Y2386A45R Flex System FC5052 2-port 16Gb FC Adapter295Y2391A45S Flex System FC5054 4-port 16Gb FC Adapter469Y1942A1BQ Flex System FC5172 2-port 16Gb FC Adapter2For x4x models with two Embedded 10Gb Virtual Fabric controllers standard, the Compute Node Fabric Connectors occupy the same space as the I/O adapters in I/O slots 1 and 3, so you have to remove the Fabric Connectors if you plan to install adapters in those I/O slots. To use slots 3 and 4 requires the second processor. Power suppliesServer power is derived from the power supplies installed in the chassis. There are no server options regarding power supplies.Integrated virtualizationLight path diagnostics panelFor quick problem determination when located physically at the server, the x440 offers a 3-step guided path:1. The Fault LED on the front panel2. The light path diagnostics panel3. LEDs next to key components on the system boardThe x440 light path diagnostics panel is visible when you remove the server from the chassis. The panel is located at the upper right side of the compute node, as shown in Figure 9.Figure 9. Location of x440 light path diagnostics panelTo illuminate the light path diagnostics LEDs, power off the compute node, slide it out of the chassis, and press the power button. The power button doubles as the light path diagnostics remind button when the server is removed from the chassis. The meanings of the LEDs are listed in the following table.Table 17. Light path diagnostic panel LEDsLED MeaningLP The light path diagnostics panel is operational.S BRD A system board error is detected.MIS A mismatch has occurred between the processors, DIMMs, or HDDs.NMI A non-maskable interrupt (NMI) has occurred.TEMP An over-temperature condition occurred that was critical enough to shut down the server.MEM A memory fault has occurred. The corresponding DIMM error LEDs on the system board are also lit.ADJ A fault is detected in the adjacent expansion unit (if installed).Remote managementTrademarksLenovo and the Lenovo logo are trademarks or registered trademarks of Lenovo in the United States, other countries, or both. A current list of Lenovo trademarks is available on the Web athttps:///us/en/legal/copytrade/.The following terms are trademarks of Lenovo in the United States, other countries, or both:Lenovo®Flex SystemServeRAIDServerGuideServerProven®System x®ThinkSystem®The following terms are trademarks of other companies:Intel® and Xeon® are trademarks of Intel Corporation or its subsidiaries.Linux® is the trademark of Linus Torvalds in the U.S. and other countries.Microsoft®, Windows Server®, and Windows® are trademarks of Microsoft Corporation in the United States, other countries, or both.Other company, product, or service names may be trademarks or service marks of others.。
XDS560常见问题
XDS560 Emulator版本说明;2.1版下面的说明适用于XDS560 仿真器目标处理器和所有支持德州仪器的处理器。
你的处理器可能不涵盖说明书中的所有功能。
对操作系统的要求 (1)安装说明 (1)固件升级 (2)对C64x 1.0X版本用户的特殊说明 (2)高速RTDX数据链接 (3)发现故障并维修 (4)勘误 (6)对操作系统的要求XDS560仿真器可以在如下的操作系统中运行:Windows 98Windows 98SEWindows NT 4 with SP4 或更新版本Windows 2000 with SP1或更新版本Windows XPWindows Me不能在其它操作系统下运行。
安装说明请看仿真器外包装上的仿真器快速入门指南。
那里有对安装过程的详细说明。
在安装本仿真器之前,希望Code Composer Studio version 2.0或更高版本已经安装在了您的机器上。
推荐2.1版本。
已经安装了2.0的可以用CCS升级顾问工具升级,这个工具集成在CCS的产品中,可以通过CCS环境下的Help -> CCS on the Web -> Update Advisor来访问。
卸载说明:卸载XDS560文件和快捷方式,请使用操作系统提供的安装和卸载功能。
在卸载之后XDS560 驱动在CC Setup功能下不可用,请手动卸载。
固件升级XDS560产品包含一个pci板卡,和串口及eeprom的升级,这个升级只适用于参加XDS560测试计划的用户,以保证和未来的XDS560或CCS新版本软件的兼容性。
这个升级只适用于XDS560测试版的用户,XDS560新用户已经有了正确的设置,不需要升级。
升级会减少XDS560PCI板卡所需的内存,且只有在XDS560 v2.1软件安装了之后,才可以升级。
升级功能和说明书在您的CD中,目录如下<cd root>\Drivers\Update请按照XDS560_Update_ReadMe.txt文件的说明执行。
Atmel ARM GNU Toolchain 发布说明书
RELEASE NOTES GNU Toolchain for Atmel ARM EmbeddedProcessorsIntroductionThe Atmel ARM GNU Toolchain (5.3.1.487) supports Atmel ARM® devices.The ARM toolchain is based on the free and open-source GCC. This toolchainis built from sources published by ARM's "GNU Tools for ARM Embedded Processors" project at (https:///gcc-arm-embedded). The toolchain includes compiler, assembler, linker, binutils (GCC and binutils), GNU Debugger (GDB with builtin simulator) and Standard C library (newlib, newlib nano).Table of ContentsIntroduction (1)1.Supported Configuration (3)1.1.Supported Hosts (3)1.2.Supported Targets (3)2.Downloading, Installing, and Upgrading (4)2.1.Downloading/Installing on Windows (4)2.2.Downloading/Installing on Linux (4)2.3.Downloading/Installing on Mac OS (4)2.4.Upgrading (4)yout and Components (5)yout (5)ponents (5)4.Toolset Background (6)piler (6)4.2.Assembler, Linker, Librarian (6)4.3. C Library (7)4.4.Debugging (7)4.5.Source Code (7)5.New and Noteworthy (8)5.1.Supported Architectures (8)6.Contact Information and Disclaimer (9)6.1.Contact (9)6.2.Disclaimer (9)1.Supported Configuration1.1Supported HostsThis release includes the following:●Bare metal EABI pre-built binaries for running on a Windows host●Bare metal EABI pre-built binaries for running on a Linux host●Bare metal EABI pre-built binaries for running on a Mac OS X host1.2Supported Targets●Bare metal ARM EABI only (Use rdimon specs for semi-hosting enviroment)2.Downloading, Installing, and UpgradingThe ARM GNU toolchain provided by Atmel is available for download. Use one of the following ways forinstallation.2.1Downloading/Installing on Windows●to try the Atmel ARM GNU toolchain alone, you can download it from here1●If you want to try the Atmel ARM GNU Toolchain along with Atmel studio, you can download and installAtmel Studio version 6.0 or later which will also install the Atmel ARM GNU toolchain. See Atmel studiorelease notes for more details.2.2Downloading/Installing on LinuxFor Linux, the Atmel ARM GNU Toolchain is available as tar.gz archive which can be extracted using the tarutility. In order to install, simply extract to the location, from where you want to execute. The Linux builds areavailable here2.Note64-bit version of libncurses and libc are required to run the tools.2.3Downloading/Installing on Mac OSFor Mac, the Atmel ARM GNU Toolchain is available as tar.gz archive which can be extracted using the tarutility. To install, extract to the location, from where you want to execute. MAC builds are available here3 2.4UpgradingIf the Atmel ARM GNU Toolchain is installed by Atmel Studio installation, refer Atmel Studio documentation for more details.If the toolchain is installed separately using one of the (Windows, Linux, Mac) installers, upgrading is notsupported. You can install the new package side-by-side of the old package and use it.1 /tools/atmel-arm-toolchain.aspx2 /tools/atmel-arm-toolchain.aspx3 /tools/atmel-arm-toolchain.aspxyout and ComponentsListed below are some of the directories that you might want to look, to have a high level understanding of what is packaged inside the Atmel ARM GNU Toolchain. The layout is identical in Windows, Linux and Mac OS X.3.1LayoutThe layout of the installation is as follows.●INSTALLDIRThe directory where the ARM GNU Toolchain is installed in the target machine.●INSTALLDIR\binThe ARM software development programs. This directory should be in your PATH environemntvariable. (Note : If you are using this toolchain from within Atmel Studio, please configure Atmel studioappropriately). This includes●GNU Binutils●GCC●GDB●INSTALLDIR\arm-none-eabi\libThe directory which have the ARM newlib libraries, startup files and linker scripts.●INSTALLDIR\arm-none-eabi\includeARM-newlib header files. This is where the system include files will be searched for by the toolchain.●INSTALLDIR\libGCC libraries, other libraries and headers.●INSTALLDIR\libexecGCC program components.3.2ComponentsThe components used to build this toolchain along with their version number can be found here1.1 http://distribute.atmel.no/tools/opensource/Atmel-ARM-GNU-Toolchain/5.3.14.Toolset BackgroundARM GNU toolchain is a collection of executable software development tools for the Atmel ARM processors.These software development tools include:piler2.Assembler3.Linker4.Archiver5.File converter6.Other file utilities7. C Library8.Debugger4.1CompilerThe compiler is the GNU compiler collection, or GCC. This compiler is incredibly flexible and can be hosted on many platforms, it can target many different processors/operating systems(backends), and can be configuredfor multiple different languages (frontends).The GCC included is targeted for the ARM processor, and is configured to compile C, and C++.Because this GCC is targeted for the ARM, the main executable that is created is prefixed with the targetname: `arm-none-eabi-gcc`. It is also referred to as ARM GCC.`arm-none-eabi-gcc` is just a driver program. The compiler itself is called cc1.exe for C, or cc1plus.exe for C++. Also the preprocessor cpp.exe will usually automatically be prefixed with the target name arm-none-eabi-cpp.exe. The actual set of component programs called is usually derived from the suffix of each soruce codefile being processed.GCC compiles a high-level computer lanugage into assembly, and that is all. It cannot work alone. GCC iscoupled with another project, GNU Binutils, which provides the assembler, linker, librarian and more. SinceGCC is just a driver program, it can automatically call the assembler and linker directly to build the finalprogram.4.2Assembler, Linker, LibrarianGNU Binutils is a collection of binary utilities. This also includes the assembler,as. Sometimes you will see itreferenced as GNU as or gas. Binutils includes the linker, ld; the librarian or archiver, ar. There are many other programs included that provide various functionality.Binutils is configured for the ARM target and each of the programs is prefixed with the target name. So youhave programs such as:●arm-none-eabi-as: The GNU Assembler●arm-none-eabi-ld: The GNU Linker●arm-none-eabi-ar: The GNU Archiver, Create, modify, and extract from archives (libraries)●arm-none-eabi-ranlib:Generate index of archive (library) contents●arm-none-eabi-objcopy:Copy and translate object files●arm-none-eabi-objdump:Display information from object files including disassembly●arm-none-eabi-size:List section size, total size●arm-none-eabi-nm:List symbol from object files.●arm-none-eabi-strings:List printable strings from files●arm-none-eabi-strip:Discard symbols●arm-none-eabi-readelf:Display the contents of ELF file formats●arm-none-eabi-addr2line:Convert addresses to file and line●arm-none-eabi-c++filt:Filter to demangle encoded C++ symbols●arm-none-eabi-gdb:Debugger to debug the targetSee the binutils user manual for more information on what each program can do.4.3 C LibraryNewlib is the Standard C Library for ARM GCC. Newlib is the C library intended for use on embedded systems.It is a conglomeration of sevaral library parts. The library is ported to support ARM processor.In addition to standard C library, newlib-nano also added to the toolchain package. Newlib-nano is newlibbranch optimized for code size by ARM (https:///gcc-arm-embedded). To use newlib-nano, users should provide additional gcc link option "--specs=nano.specs". For more details, refer to the readme fromhere1.4.4Debugging●The toolchain distribution ships the `arm-none-eabi-gdb` which can be used for debugging purposes.●Atmel Studio provides faclities to debug the executable produced by this toolchain. Note that `AtmelStudio` is currently free to the public, but it is not Open Source.4.5Source CodeThis toolchain is built using the source from ARM's gcc-arm-embedded project 5-2016-q1-update2 release. For Atmel's modification on source and build scripts, refer SOURCES.README from here3.1 http://distribute.atmel.no/tools/opensource/Atmel-ARM-GNU-Toolchain/5.3.12 https:///gcc-arm-embedded/5.0/5-2016-q1-update3 http://distribute.atmel.no/tools/opensource/Atmel-ARM-GNU-Toolchain/5.3.15.New and NoteworthyRead ARM's gcc-arm-embedded project 5-2016-q1-update1 release for updates and fixes. This section listsAtmel's modifications to that release.●Default debug information is set to DWARF-2, which is supported by Atmel software debugger tools.●Added object file wise memory usage details to map file. This shall be enabled using '--detailed-mem-usage' linker option.●Multilib for armv7-a architecture with float variants Neon-vfpv4 and vfpv4-d16 FPUs.Please read section "Architecture options usage" of gcc-arm-embedded project's readme (also available here)2 for more information about multilib selections. Please refer below table for Atmel's modification to armv7-amultilibs.Table 5-1.5.1Supported Architecturesarmv2armv5e armv6z armv8-a+crcarmv2a armv5t armv6zk armv8-m.basearmv2armv5te armv7armv8-m.mainarmv2a armv6armv7-a armv8-m.main+dsparmv3armv6-m armv7-m iwmmxtarmv3m armv6j armv7-r iwmmxt2armv4armv6k armv7e-m nativearmv4t armv6s-m armv7vearmv5armv6t2armv8-aRefer ARM-Options3 for more details about ARM architecture and processorsPlease refer Atmel Studio documentation for the supported Atmel ARM devices.1 https:///gcc-arm-embedded/5.0/5-2016-q1-update2 http://distribute.atmel.no/tools/opensource/Atmel-ARM-GNU-Toolchain/5.3.1/readme.txt3 https:///onlinedocs/gcc/ARM-Options.html6.Contact Information and Disclaimer6.1ContactFor support on Atmel ARM GNU Toolchain, visit design support1.Users of ARM GNU Toolchain are also welcome to discuss on the AT91SAM Community website2 forum.6.2DisclaimerAtmel ARM GNU toolchain is distributed free of charge for the purpose of developing applications for Atmel SAM devices. Atmel ARM GNU Toolchain comes without any warranty.1 /design-support/2 /Atmel Corporation1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311F: (+1)(408) 436.4200| © 2016 Atmel Corporation. / Rev.: 42368A-MCU-06/2016Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, AVR®, tinyAVR®, XMEGA®, megaAVR® SAM®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. Windows®, and others, are registered trademarks of Microsoft Corporation in U.S. and or other countries. ARM®, Cortex® are registered trademark of ARM Holdings in U.K. Other terms and product names may be trademarks of others.DISCLAIMER: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. SAFETY-CRITICAL, MILITARY, AND AUTOMOTIVE APPLICATIONS DISCLAIMER: Atmel products are not designed for and will not be used in connection with any applications where the failure of such products would reasonably be expected to result in significant personal injury or death (“Safety-Critical Applications”) without an Atmel officer's specific written consent. Safety-Critical。
IFC300说明书
100-230 V AC (允许范围 -15% / +10%)
• 注意仪表铭牌上的数据, 电源电压和频率范围 (50 - 60 Hz)。
• 供电的保护接地 PE 必须连接到信号转换器壳体中 U 型端子上。
• 连接图 I - II 电源和传感器与信号转换器之间的电气连接见第 1.3.6 节。
12 - 24 V DC (允许范围 -25% / +30%) • 注意仪表铭牌上的数据 ! • 在测量过程中, 功能接地 FE 须连接到信号转换器壳体中 U 型端子上。
说明书!
修,确保在危险区域安全操作。
警告! 小心!
信息
注意! 假如不注意安全容易造成人身伤害,误操作会引起损坏仪表。
小心! 谨防人身伤害和仪表的误操作。 信息和处理
信号转换器型号和铭牌
提供的流量计根据合同要求配置,操作数据根据你的订单设置,信号转换器标准配置带显示、操作键和 HART® 接口。
IFC 300 C IFC 300 F
CE / EMC / 标准 / 认证
KROHNE 电磁流量计都能满足下列安全要求:
• EMC Directive 89 / 336 / EEC 和 93 / 68 / EEC 相当于 EN 61326-1 (1997) 和 A1 (1998), A2 (2001)
• Low-Voltage Directives 73 / 23 / EEC 和 93 / 68 / EEC 相当于 EN 61010-1: 2001
流量计供电,系统就可运行。
• 信号转换器操作 (第 4 节) • IFC 300 技术数据 (第 5 节)
第
6- 8页
第
9 - 15 页
第 16 – 28 页
simufact.forming中文手册教程
SuperForge2005使用手册内容:参数设置,试验分析,结果分析编制:王 毅部门:工程部时间:2005.7.28~2005.8.10目录一、计算机配置及相关参数设置和结果简介-----------------------------11.计算机配置情况:-----------------------------------------------12.软件主要参数设置说明-------------------------------------------13.软件运行结果的说明---------------------------------------------2二、SUPERFORGE2005操作步骤详解------------------------------------31.生成STL模型文件------------------------------------------------32.在S UPER F ORGE环境下设置各参数-------------------------------------53.参数调入设计树-------------------------------------------------84.运行-----------------------------------------------------------95.结果显示-------------------------------------------------------9三、关键参数设置试验及分析----------------------------------------101.STL文件精度的设置--------------------------------------------102.模具类型的设置------------------------------------------------123.网格长度的设置------------------------------------------------144.摩擦系数的设置------------------------------------------------165.水压机速度设置------------------------------------------------186.材料的定义----------------------------------------------------20四、结果显示与分析------------------------------------------------221.接触应力(C ONTACT P RESSURE)-------------------------------------222.其他结果说明--------------------------------------------------25 结论--------------------------------------------------------------27一、计算机配置及相关参数设置和结果简介SuperForge2005试用过程是在2004使用的一定经验之上进行的,对于我司的产品的一些参数,大体上已经有一定的积累,记录如下:1. 计算机配置情况:CPU:奔腾D520(64位2.66主频)内存:2G显卡:ATI X700主板:Intel 915G硬盘:120G(SATA)2. 软件主要参数设置说明按照我司产品的整个制作过程,对软件运行的整体参数按步骤作如下设置:①模具的类型选择:Backward Extrusion (或者closed die)②输入模具及锻件文件为STL格式(具体制作过程见附录)Model->From fileSTL文件在制作时会因为误差和角度的不同,在本文中,若不作特殊说明则:“粗”是指误差为0.0557mm,角度为30°的STL文件;“良”是指误差为0.0215mm,角度为10°的STL文件;“精”是指误差为0.0023mm,角度为0.5°的STL文件。
W9812G2GB-6资料
1M × 4 BANKS × 32BITS SDRAM Table of Contents-1.GENERAL DESCRIPTION (3)2.FEATURES (3)3.AVAILABLE PART NUMBER (3)4.BALL CONFIGURATION (4)5.PIN DESCRIPTION (5)6.BLOCK DIAGRAM (6)7.FUNCTIONAL DESCRIPTION (7)7.1.Power Up and Initialization (7)7.2.Programming Mode Register (7)7.3.Bank Activate Command (7)7.4.Read and Write Access Modes (7)7.5.Burst Read Command (8)7.6.Burst Write Command (8)7.7.Read Interrupted by a Read (8)7.8.Read Interrupted by a Write (8)7.9.Write Interrupted by a Write (8)7.10.Write Interrupted by a Read (8)7.11.Burst Stop Command (9)7.12.Addressing Sequence of Sequential Mode (9)7.13.Addressing Sequence of Interleave Mode (9)7.14.Auto-precharge Command (10)7.15.Precharge Command (10)7.16.Self Refresh Command (10)7.17.Power Down Mode (11)7.18.No Operation Command (11)7.19.Deselect Command (11)7.20.Clock Suspend Mode (11)8.OPERATION MODE (12)9.ELECTRICAL CHARACTERISTICS (13)9.1.Absolute Maximum Ratings (13)9.2.Recommended DC Operating Conditions (13)9.3.Capacitance (13)9.4.DC Characteristics (14)9.5.AC Characteristics and Operating Condition (15)10.TIMING WAVEFORMS (17)mand Input Timing (17)10.2.Read Timing (18)10.3.Control Timing of Input/Output Data (19)10.4.Mode Register Set Cycle (20)11.OPERATING TIMING EXAMPLE (21)11.1.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3) (21)11.2.Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge) (22)11.3.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3) (23)11.4.Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge) (24)11.5.Interleaved Bank Write (Burst Length = 8) (25)11.6.Interleaved Bank Write (Burst Length = 8, Auto-precharge) (26)11.7.Page Mode Read (Burst Length = 4, CAS Latency = 3) (27)11.8.Page Mode Read / Write (Burst Length = 8, CAS Latency = 3) (28)11.9.Auto-precharge Read (Burst Length = 4, CAS Latency = 3) (29)11.10.Auto-precharge Write (Burst Length = 4) (30)11.11.Auto Refresh Cycle (31)11.12.Self Refresh Cycle (32)11.13.Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) (33)11.14.Power Down Mode (34)11.15.Auto-precharge Timing (Read Cycle) (35)11.16.Auto-precharge Timing (Write Cycle) (36)11.17.Timing Chart of Read to Write Cycle (37)11.18.Timing Chart of Write to Read Cycle (37)11.19.Timing Chart of Burst Stop Cycle (Burst Stop Command) (38)11.20.Timing Chart of Burst Stop Cycle (Precharge Command) (38)11.21.CKE/DQM Input Timing (Write Cycle) (39)11.22.CKE/DQM Input Timing (Read Cycle) (40)12.PACKAGE SPECIFICATION (41)12.1.TFBGA 90 Balls pitch=0.8mm (41)13.REVISION HISTORY (42)1. GENERAL DESCRIPTIONW9812G2GB is a high-speed synchronous dynamic random access memory (SDRAM), organized as 1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.11 µm process technology, W9812G2GB delivers a data bandwidth of up to 166MHz words per second (-6). For different application, W9812G2GB is sorted into two speed grades: -6/-6I and -75. The –6 is compliant to the 166MHz/CL3 specification (the -6I grade which is guaranteed to support -40°C ~ 85°C). The -75 is compliant to the 133MHz/CL3 specification.Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst to maximize its performance. W9812G2GB is ideal for main memory in high performance applications.2. FEATURES• 3.3V ± 0.3V Power Supply•Up to 166 MHz Clock Frequency• 1,048,576 Words × 4 banks × 32 bits organization• Self Refresh Mode•CAS Latency: 2 and 3•Burst Length: 1, 2, 4, 8 and full page•Burst Read, Single Writes Mode•Byte Data Controlled by DQM•Auto-precharge and Controlled Precharge•4K Refresh cycles / 64 mS• Interface: LVTTL•Packaged in TFBGA 90 Ball•W9812G2GB is using lead free materials with RoHS compliant3. AVAILABLE PART NUMBERPART NUMBER SPEEDMAXIMUM SELFREFRESH CURRENTOPERATINGTEMPERATUREW9812G2GB-6 166MHz/CL3 2mA 0°C ~ 70°C W9812G2GB-6I 166MHz/CL3 2mA -40°C ~ 85°C W9812G2GB-75 133MHZ/CL3 2mA 0°C ~ 70°C4. BALL CONFIGURATION5. PIN DESCRIPTION6. BLOCK DIAGRAM7. FUNCTIONAL DESCRIPTION7.1. Power Up and InitializationThe default power up state of the mode register is unspecified. The following power up and initialization sequence need to be followed to guarantee the device being preconditioned to each user specific needs.During power up, all V DD and V DDQ pins must be ramp up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power up voltage must not exceed V DD +0.3V on any of the input pins or V DD supplies. After power up, an initial pause of 200 µS is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles (CBR) are also required before or after programming the Mode Register to ensure proper subsequent operation.7.2. Programming Mode RegisterAfter initial power up, the Mode Register Set Command must be issued for proper device operation. All banks must be in a precharged state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. The Mode Register Set Command is activated by the low signals of RA,S CAS, CS and WE at the positive edge of the clock. The address input data during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A new command may be issued following the mode register set command once a delay equal to t RSC has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.7.3. Bank Activate CommandThe Bank Activate command must be applied before any Read or Write operation can be executed. The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate command is applied to when the first read or write operation can begin must not be less than the RAS to CAS delay time (t RCD). Once a bank has been activated it must be precharged before another Bank Activate command can be issued to the same bank. The minimum time interval between successive Bank Activate commands to the same bank is determined by the RAS cycle time of the device (t RC). The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank delay time (t RRD). The maximum time that each bank can be held active is specified as t RAS (max).7.4. Read and Write Access ModesAfter a bank has been activated, a read or write cycle can be followed. This is accomplished by setting S RCD delay. WE pin voltage level RAS high and CA low at the clock rising edge after minimum of tdefines whether the access cycle is a read operation (WE high), or a write operation (WE low). The address inputs determine the starting column address.Reading or writing to a different row within an activated bank requires the bank be precharged and a new Bank Activate command be issued. When more than one bank is activated, interleaved bank Read or Write operations are possible. By using the programmed burst length and alternating the access and precharge operations between multiple banks, seamless data access operation amongmany different pages can be realized. Read or Write Commands can also be issued to the same bank or between active banks on every clock cycle.7.5. Burst Read CommandThe Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page explain the address sequence of interleave mode and sequential mode.7.6. Burst Write CommandThe Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be ignored.7.7. Read Interrupted by a ReadA Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on the outputs until the CAS Latency from the interrupting Read Command the is satisfied.7.8. Read Interrupted by a WriteTo interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM masking is no longer needed.7.9. Write Interrupted by a WriteA burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the programmed burst length is satisfied.7.10. Write Interrupted by a ReadA Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention. When the Read Command is activated, any residual data from the burst write cycle will be ignored.7.11. Burst Stop CommandA Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read cycle interrupted by Burst Stop.7.12. Addressing Sequence of Sequential ModeA column access is performed by increasing the address from the column address which is input to the device. The disturb address is varied by the Burst Length as shown in Table 2.Table 2 Address Sequence of Sequential Mode7.13. Addressing Sequence of Interleave ModeA column access is started in the input column address and is performed by inverting the address bit in the sequence shown in Table 3.Table 3 Address Sequence of Interleave Mode7.14. Auto-precharge CommandIf A10 is set to high when the Read or Write Command is issued, then the auto-precharge function is entered. During auto-precharge, a Read Command will execute as normal with the exception that the active bank will begin to precharge automatically before all burst read cycles have been completed. Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled burst cycle. The number of clocks is determined by CAS Latency.A Read or Write Command with auto-precharge can not be interrupted before the entire burst operation is completed. Therefore, use of a Read, Write or Precharge Command is prohibited during a read or write cycle with auto-precharge. Once the precharge operation has started, the bank cannot be reactivated until the Precharge time (t RP) has been satisfied. Issue of Auto-precharge command is illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation two clocks delay from the last burst write cycle. This delay is referred to as Write t WR. The bank undergoing auto-precharge can not be reactivated until t WR and t RP are satisfied. This is referred to as t DAL, Data-in to Active delay (t DAL = t WR + t RP). When using the Auto-precharge Command, the interval between the Bank Activate Command and the beginning of the internal precharge operation must satisfy t RAS (min).7.15. Precharge CommandThe Precharge Command is used to precharge or close a bank that has been activated. The Precharge Command is entered when CS, RAS and WE are low and CAS is high at the rising edge of the clock. The Precharge Command can be used to precharge each bank separately or all banks simultaneously. Three address bits, A10, BS0, and BS1, are used to define which bank(s) is to be precharged when the command is issued. After the Precharge Command is issued, the precharged bank must be reactivated before a new read or write access can be executed. The delay between the Precharge Command and the Activate Command must be greater than or equal to the Precharge time (t RP).7.16. Self Refresh CommandThe Self Refresh Command is defined by having CS, RAS, CAS and CKE held low with WE high at the rising edge of the clock. All banks must be idle prior to issuing the Self Refresh Command. Once the command is registered, CKE must be held low to keep the device in Self Refresh mode. When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are disabled. The clock is internally disabled during Self Refresh Operation to save power. The device will exit Self Refresh operation after CKE is returned high. A minimum delay time is required when the device exits Self Refresh Operation and before the next command can be issued. This delay is equal to the t AC cycle time plus the Self Refresh exit time.If, during normal operation, AUTO REFRESH cycles are issued in bursts (as opposed to being evenly distributed), a burst of 4,096 AUTO REFRESH cycles should be completed just prior to entering and just after exiting the self refresh mode. The period between the Auto Refresh command and the next command is specified by t RC.7.17. Power Down ModeThe Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are gated off to reduce the power. The Power Down mode does not perform any refresh operations, therefore the device can not remain in Power Down mode longer than the Refresh period (t REF) of the device.The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation Command is required on the next rising clock edge, depending on t CK. The input buffers need to be enabled with CKE held high for a period equal to t CKS (min) + t CK (min).7.18. No Operation CommandThe No Operation Command should be used in cases when the SDRAM is in a idle or a wait state to prevent the SDRAM from registering any unwanted commands between operations. A No Operation Command is registered when CS is low with RAS, CAS, and WE held high at the rising edge of the clock. A No Operation Command will not terminate a previous operation that is still executing, such as a burst read or write cycle.7.19. Deselect CommandThe Deselect Command performs the same function as a No Operation Command. Deselect Command occurs when CS is brought high, the RAS, CAS, and WE signals become don’t cares.7.20. Clock Suspend ModeDuring normal access mode, CKE must be held high enabling the clock. When CKE is registered low while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode deactivates the internal clock and suspends any clocked operation that was currently being executed. There is a one clock delay between the registration of CKE low and the time at which the SDRAM operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are issued. The Clock Suspend mode is exited by bringing CKE high. There is a one clock cycle delay from when CKE returns high to when Clock Suspend mode is exited.8. OPERATION MODEFully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 1 shows the truth table for the operation commands.Table 1 Truth Table (Note (1), (2))Notes:(1) v =valid x =Don’t care L =Low Level H =High Level(2) CKEn signal is input level when commands are provided.CKEn-1 signal is the input level one clock cycle before the command is issued.(3) These are state of bank designated by BS0, BS1 signals.(4) Device state is full page burst operation.(5) Power Down Mode can not be entered in the burst cycle.When this command asserts in the burst cycle, device state is clock suspend mode.9. ELECTRICAL CHARACTERISTICS9.1. Absolute Maximum RatingsRATINGUNIT PARAMETER SYMBOLInput/Output Voltage V IN, V OUT -0.3 ~ V DD +0.3 VPower Supply Voltage V DD, V DDQ-0.3 ~ 4.6 VOperating Temperature (-6/-75) T OPR0 ~ 70 °C°C85Operating Temperature (-6I) T OPR -40~°C150Storage Temperature T STG -55~Soldering Temperature (10s) T SOLDER 260 °CW Power Dissipation P D 1mA Short Circuit Output Current I OUT 50Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.9.2. Recommended DC Operating Conditions(Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I)UNIT PARAMETER SYMBOL MIN.MAX.TYP.Power Supply Voltage V DD 3.0 3.3 3.6 VPower Supply VoltageV DDQ 3.0 3.3 3.6 V(for I/O Buffer)V DD +0.3 VInput High Voltage V IH 2.0 -Input Low Voltage V IL -0.3 - 0.8 VNote: V IH(max) = V DD/ V DDQ+1.2V for pulse width < 5 nSV IL(min) = V SS/ V SSQ-1.2V for pulse width < 5 nS9.3. Capacitance(V DD= 3.3V, f = 1 MHz, Ta 25°C)Note: These parameters are periodically sampled and not 100% tested.9.4. DC Characteristics(VDD =3.3V± 0.3V, Ta = 0 to 70°C for-6/-75, Ta= -40 to 85°C for -6I)NOTESUNIT PARAMETER SYMBOL MIN.MAX.Input Leakage CurrentI I(L) -5 5 µA (0V ≤V IN≤ V DD, all other pins not under test = 0V)Output Leakage CurrentI O(L) -5 5 µA (Output disable , 0V ≤ V OUT≤ V DDQ)LVTTL Output ″H″ Level VoltageV OH 2.4 - V(I OUT = -2 mA )LVTTL Output ″L″ Level VoltageV OL - 0.4 V(I OUT = 2 mA )9.5. AC Characteristics and Operating Condition(VDD =3.3V ± 0.3V, Ta = 0 to 70°C for -6/-75, Ta= -40 to 85°C for -6I, Notes: 5, 6, 7, 8, 9, 10)-6/-6I -75PARAMETER SYM.MIN. MAX. MIN. MAX.UNIT NOTESRef/Active to Ref/Active Command Period t RC 60 65 Active to precharge Command Period t RAS 42 10000045 100000 nSActive to Read/Write Command Delay Timet RCD 18 20 Read/Write(a) to Read/Write(b) Command Periodt CCD 1 1 t CKPrecharge to Active Command Period t RP 18 20 Active(a) to Active(b) Command Period t RRD 12 15 nS CL* = 2 22 t CKWrite Recovery Time CL* = 3 t WR 22CL* = 2 101000101000CLK Cycle TimeCL* = 3t CK6 1000 7.5 1000CLK High Level widtht CH 2 2.5 9 CLK Low Level widtht CL 2 2.59CL* = 2 6 6 Access Time from CLKCL* = 3t AC 5 5.4 10 Output Data Hold Timet OH 3 3 10 Output Data High Impedance Time t HZ 3 6 3 7.5 8 Output Data Low Impedance Time t LZ 0 0 10 Power Down Mode Entry Time t SB 0 6 0 7.5Transition Time of CLK (Rise and Fall) t T 0.1 1 0.1 1 7 Data-in Set-up Time t DS 1.5 1.5 9 Data-in Hold Time t DH 1.0 1.0 9 Address Set-up Time t AS 1.5 1.5 9 Address Hold Time t AH 1.0 1.0 9 CKE Set-up Time t CKS 1.5 1.5 9 CKE Hold Time t CKH 1.0 1.0 9 Command Set-up Time t CMS 1.5 1.5 9 Command Hold Time t CMH 1.0 1.0nS9Refresh Timet REF 64 64 mS Mode register Set Cycle Time t RSC 12 15 nS Exit self refresh to ACTIVE commandt XSR72 75 nS*CL = CAS LatencyNotes:1. Operation exceeds “Absolute Maximum Ratings” may cause permanent damage to the devices.2. All voltages are referenced to V SS3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the minimum values of t CK and t RC .4. These parameters depend on the output loading conditions. Specified values are obtained with output open.5. Power up sequence is further described in the “Functional Description” section.6. AC Testing ConditionsPARAMETER CONDITIONSOutput Reference Level1.4VOutput LoadSee diagram belowInput Signal Levels (V IH /V IL ) 2.4V/0.4VTransition Time (t T : tr/tf) of Input Signal 1/1 nS Input Reference Level 1.4V7. Transition times are measured between V IH and V IL .8. t HZ defines the time at which the outputs achieve the open circuit condition and is not referenced to output level.9. Assumed input transition Time (t T ) = 1nS.If tr & tf is longer than 1nS, transient time compensation should be considered, i.e., [(tr + tf)/2-1]nS should be added to the parameter(The t T maximum can’t be more than 10nS for low frequency application.)10. If clock rising time (t T ) is longer than 1nS, (t T /2-0.5)nS should be added to the parameter.10. TIMING WAVEFORMS 10.1. Command Input Timing10.2. Read Timing10.3. Control Timing of Input/Output Data10.4. Mode Register Set Cycle11. OPERATING TIMING EXAMPLE11.1. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)11.2. Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)11.3. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)11.4. Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)11.5. Interleaved Bank Write (Burst Length = 8)11.6. Interleaved Bank Write (Burst Length = 8, Auto-precharge)11.7. Page Mode Read (Burst Length = 4, CAS Latency = 3)11.8. Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)11.9. Auto-precharge Read (Burst Length = 4, CAS Latency = 3)11.10. Auto-precharge Write (Burst Length = 4)11.11. Auto Refresh Cycle11.12. Self Refresh Cycle11.13. Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)11.14. Power Down Mode11.15. Auto-precharge Timing (Read Cycle)11.17. Timing Chart of Read to Write Cycle11.18. Timing Chart of Write to Read Cycle11.19. Timing Chart of Burst Stop Cycle (Burst Stop Command)11.20. Timing Chart of Burst Stop Cycle (Precharge Command)11.21. CKE/DQM Input Timing (Write Cycle)11.22. CKE/DQM Input Timing (Read Cycle)12. PACKAGE SPECIFICATION12.1. TFBGA 90 Balls pitch=0.8mmPublication Release Date:Aug. 13,2007- 41 - Revision A07Publication Release Date: Aug. 13,2007- 42 - Revision A0713. REVISION HISTORYVERSION DATEPAGEDESCRIPTIONA01 Mar. 24, 2006 All Create new datasheet A02 Jul. 05, 2006 8 Burst Stop commandA03 Sep. 08, 2006 10 Exit Auto refresh to next command is specified by t RC A04 Sep. 27, 200615,16Modify Characteristics Notes 9 and add Notes 10 (t T ) A05 Apr. 12, 2007 15,32,34,41Add t XSR timing specification and package dimension ball openingA06 Jun. 21, 2007 3,13,14,15Add -6I gradeA07 Aug. 13, 200716Revise transient time t T AC test condition and calculate formula for compensation consideration in Notes 6, 9 of AC Characteristics and Operating ConditionImportant NoticeWinbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur.Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.。
ArmorBlock LP2 4输入4输出模块(分类号:1792D-4BT4LP)说明书
Installation InstructionsArmorBlock LP24 Sinking Input / 4 Output Module(Cat. No. 1792D-4BT4LP)This ArmorBlock LP2™ I/O module (Cat. No. 1792D-4BT4LP) is a stand-alone 24V dc I/O product which communicates via a DeviceNet network. The sealed housing of this module requires no enclosure.This module has 4 sinking inputs and 4 sourcing outputs accessed through Y splitter cables. Four self-protected 24V dc outputs can provide up to 300mA each.Package ContentsYour package contains:• 1 ArmorBlock LP2 Module •Installation Instructions416222 4 Sinking Input / 4 Output ModuleEuropean Union Directive ComplianceIf this product has the CE mark it is approved for installation within the European Union and EEA regions. It has been designed and tested to meet the following directives.EMC DirectiveThis product is tested to meet Council Directive 89/336/EEC Electromagnetic Compatibility (EMC) and the following standards, in whole or in part, documented in a technical construction file:•EN 50081-2 EMC - Generic Emission Standard, Part 2 - Industrial Environment•EN 50082-2 EMC - Generic Immunity Standard, Part 2 - Industrial EnvironmentThis product is intended for use in an industrial environment.Low Voltage DirectiveThis product is tested to meet Council Directive 73/23/EEC Low V oltage, by applying the safety requirements of EN 61131-2 Programmable Controllers, Part 2 - Equipment Requirements and Tests.For specific information required by EN 61131-2, see the appropriate sections in this publication, as well as the following Allen-Bradley publications:•Industrial Automation Wiring and Grounding Guidelines For Noise Immunity, publication 1770-4.1•Automation Systems Catalog, publication B111Install Your ArmorBlock LP2 I/O ModuleTo install the module:•Set the node address and baud rate.•Mount the module.•Connect the unit to the DeviceNet trunk and the auxilary power source.•Connect the cord sets.Set the Node AddressSet the node address using RSNetworx for DeviceNet software, DeviceNetManager™ software, or another software configuration tool. The module is equipped with AutoBaud detect. AutoBaud lets the module read the settings already in use on your DeviceNet network and automatically adjusts to follow those settings.4 Sinking Input / 4 Output Module3Install the Module1.Attach the module using the dimensions shown below.2.Connect the grey DeviceNet cable to the DeviceNet trunk. Use the1485P-P1R5-MN5R1 T-Part tap to connect to round media. Use the 1485P-P1E4-R5 to connect to the Kwik Link flat media system. Connect the Input / Output Cord Sets to the LP2 ModuleThis module uses 5 pin micro (12mm) style PCB mounted connectors. Four micro caps cover the connectors on your module. Remove the caps and connect your cord sets to the appropriate ports. This product has two inputs or outputs per I/O connector. Use a “Y” splitter cable for access to all I/O connections. For more information on these cables, see the Product Data guide publication 1792-2.1.Use the micro caps to cover and seal unused ports. Pinout diagrams for the connectors are shown next.Input Micro-Connector(View into Sockets)Pin 1 Sensor Source VoltagePin 2 Input BPin 3 Return Logic Ground1Pin 4 Input APin 5 Not UsedOutput Micro-Connector(View into Sockets)Pin 1 Not UsedPin 2 Output BPin 3 Auxilary Power GroundPin 4 Output APin 5 Not UsedLogic Ground is approximately 0.4V above DeviceNet V-measured at the module.414524 4 Sinking Input / 4 Output ModuleOutput Power and DeviceNet CablesRefer to the DeviceNet Cable Planning and Installation Manual for more information on output power and DeviceNet cables for your application.!ATTENTION:•Make sure to connect the proper color coded cables together. DeviceNet cable should connect to DeviceNet cables and auxillary outputs should match auxillary outputs.•Make sure all connectors and caps are securely tightened to properly seal the connections against leaks and maintain IP67 requirements•For maximum noise immunity, input and output cable return wires must be properly terminated. When inputs and outputs are connected in loopback, return wires should be connected together.•I/O cable length should be less than 30 meters.Input 030706-MInput 1Input 2Input 34 Sinking Input / 4 Output Module 5Communicate With Your ArmorBlock LP2 I/O ModuleThis ArmorBlock module’s I/O is exchanged with the master through a polled, change of state, or cyclic connection.The module consumes and produces I/O data as follows:Cyclic - allows configuration of the block as an I/O client. The block will produce and consume its I/O cyclically at the rate configured.Polled - a master initiates communication by sending its polled I/O message to the module. The 4 input / 4 output module consumes themessage, updates outputs, and produces a response. The response has input data, and the status of the Auxiliary power.Change of state - productions occur when an input changes. If no input change occurs within the expected packet rate, a heartbeat production occurs. This heartbeat production tells the scanner module that the I/O module is alive and ready to communicate. Consumption occurs when data changes and the master produces new output data to the I/O module. Refer to the table below for the word/bit definitions.Type of I/O Connections Consumes Produces Cyclic 1 Byte 1 Byte Polled 1 Byte 1 Byte Change of State1 Byte1 ByteBit 0706050403020100Produces 0RSVD OPWR RSVD RSVD I3I2I1I0Consumes 0RSVDRSVDRSVDRSVDO3O2O1O0Where:RSVD= Reserved I = InputO = OutputOPWR= Output Power (Auxiliary Power)6 4 Sinking Input / 4 Output ModuleThe DeviceNet Network uses advanced network technology, producer/consumer communication, to increase network functionality andthroughput. Visit our web site at /networks for producer/consumer technology information and updates.Byte Bit DescriptionProduces 000-0304050607Input status bits: When the bit is set (1), the input is on. Bit 00 corresponds to input 0, bit 01 corresponds to input 1, bit 02 corresponds to input 2, bit 03 corresponds to input 3.Reserved ReservedOutput Powr Fault (OPWR): When the bit is set (1) auxilary power is not present.ReservedConsumes 000-0304-07Output bits: When the bit is set (1), the output will be turned on. Bit 00 corresponds to output 0, bit 01 corresponds to output 1, bit 02 to output 2, bit 03 to output 3.Reserved4 Sinking Input / 4 Output Module7Troubleshoot with the IndicatorsThis module has the following indicators:•Network status indicator•Module status indicator•Auxiliary Power indicator•Individual point status indicators for inputs 0, 1, 2, and 3 and outputs 0,Module Status IndicatorIndication StatusNone No PowerGreenBlinking Solid Needs Commissioning Operating NormalRedBlinking Solid Recoverable Fault Unrecoverable Faultand 130706-M 38 4 Sinking Input / 4 Output ModuleFor more information on indications see the Product Data publication 1792-2.1.Network Status Indicator Indication Status None Not On-lineGreen Blinking Solid On-line/No Connections On-line/ConnectedRed Blink SolidConnection Timed OutFailed Communication: A duplicate node address exists or module is at the wrong baud rate.Auxiliary Power Indication StatusNone No Auxiliary Power Green SolidAuxiliary Power PresentI/O Status Indicators Function Module Status Indicator Point Indicator Condition Outputs Green Green None Yellow Output not energized Output energized InputsGreen GreenNone YellowNo valid input Valid input4 Sinking Input / 4 Output Module9 Specifications4 Input / 4 Output Module - Cat. No. 1792D-4BT4LPSinking Input Specifications Max MinInputs per block 4 - 3 wire or dry contact PNP devices or 2 - 4 wirePNP devicesSensor Source Current (per input)50mA-On-state Voltage 25V dc10V dcOn-state Current10mA2mAOff-state Voltage5V dcOff-state Current 1.5mA Sourcing Output Specifications Max MinOutputs per block 4 sourcing outputs labeled O0, O1, O2, and O3 Output Auxiliary Voltage30V10VOn-state Voltage Drop1V-On-state Current0.3A-Off-state Leakage 1.5mA-Module Current (all outputs) 1.2A-Surge Current - for 10ms,repeatable every 2s0.6A-No Load Sense Current (On-state)0.18A-General SpecificationsIndicators Network Status - red/greenModule Status - red/greenAuxiliary Power - greenPoint LED - yellowCommunication Rate•125Kbps @ 500 meters(1600 feet) for thickcable, flat media length 375 meters•250Kbps @ 200 meters(600 feet) for thick cable,flat media length 150 meters• 500Kbps @ 100 meters (330 feet) for thickcable, flat media length 75 metersDeviceNet Power Voltage Current25V dc125mA (no sensors)300mA (full load)11V dcAuxiliary Power Voltage Current30V dc1.2A max10V dc1.2A maxDimensions (assembled to base) inches - (Millimeters)1.023H x 2.7w x 4.72D (26)H x (68.5)W x (120)D10 4 Sinking Input / 4 Output ModuleThis product has been tested at an Open DeviceNet V endor Association, Inc. (ODV A) authorized independent test laboratory and found to comply with ODV A Conformance Test Software Composite Test Version 11.ArmorBlock, ArmorBlock LP2 and DeviceNetManager are trademarks of Rockwell Automation.4 Input / 4 Output Module - Cat. No. 1792D-4BT4LP General Specifications Cont.MaxMinEnvironmental Conditions Operational Temperature Storage Temperature Relative Humidity Shock Operating Non-operating Vibration -25 to 60o (-13 to 140o F)-25 to 80o C (-13 to 176O F)Up to 100%30g peak acceleration, 11 (+1) ms pulse width 50g peak acceleration, 11(+1)ms pulse width Tested 10g @ 10-500Hz per IEC 68-2-6Conductors Publication DN-6.7.2EnclosureMeets or exceeds IP67Agency Certification(when product is marked)•CE marked for all applicable directives4 Sinking Input / 4 Output Module11Publication 1792D-5.26 - January 199912 4 Sinking Input / 4 Output ModulePublication 1792D-5.26 - January 1999PN 955134-80© 1999 Rockwell International. All Rights Reserved. Printed in USA。
惠威Dx46 FIR-DRIVE数字音响处理器说明书
Dx46FIR-DRIVESound System ProcessorKey Features:• 116 dB dynamic range• 2 analog inputs, 6 analog outputs • 2 digital AES/EBU inputs • FIR-DRIVE • TEMP limiter• Configuration via IRIS-NetGeneral Description:The Electro-Voice Dx46 is a digital sound system processor with 2 analog inputs, 2 digital AES/EBU inputs and 6 analog outputs. With high resolution FIR filters, sophisticated speaker protection and a multi level delay concept the Dx46 sets new standards for digital loudspaker processors. FIR-DRIVE provides highly detailed optimization of loudspeaker performance through the use of complex-phase FIR filters and advanced DSP settings. The con-figuration and operation of the device can be done via the front panel or the IRIS-Net software. For remote configuration and control the Dx46 can be connected via Ethernet or USB. The integrated 2 port ethernet switch allows daisy chain connection of devices. Direct-access buttons for editing DSP pa-rameters are available on the front panel. Up to 90 presets (60 factory pre-sets and 30 programmable user presets) can be used. The integrated FLASH memory allows software or preset update via Ethernet or USB. Five control inputs on the rear panel can be used for recall of presets using external switches or contacts. On the front panel level meters for input and output signals, output gain reduction, limit and clip LEDs, dedicated Mute buttons,output channel function indicators (SUB, LO, MID, HI) and a LCD display (192x32 pixesl) with blue backlight are available. There are 6 preconfigured configurations plus one free configurable full edit (2 in 6 out) configuration available. Three dedicated processing groups (user, array, speakers) are available. For each output 512-tap FIR filters can be used, the PEQ and GEQ use 48 Bit filter algorithms. A look-ahead Peak limiter and TEMP limiter (Thermal Energy Management and Protection) are available. The integrated Signal Generator allows internal generation of pink noise, white noise or sine signal. Every DSP parameter can be locked and / or hidden. The configura-tion of the ethernet port can be done via IRIS-Net device scan. Using 24 Bit AD/DA converters a dynamic range of 116 dB is reached. A switchable input PAD (-6 dB) can be activated. Configuration is done via IRIS-Net software,the visualization of the system transfer function is possible using Electro-Voice Speaker Settings. Please refer to the Dx46 owner‘s manual and IRIS-Net documentation for more details.T echnical Specifications:Mains Voltage 100 to 240 V AC, 50 to 60 Hz Power Consumption 25 WAnalog Audio Inputs2 XLR IN, electronically balanced 2 x XLR THRU OUT, electronically balancedDigital Audio Inputs 1 x XLR AES/EBU IN1 x XLR AES/EBU THRU OUT Digital Audio Format AES3, 32 kHz to 192 kHz sample rate Nominal Input Voltage 1.55 V / +6 dBu Maximum Input Voltage (with -6dB PAD engaged)17.3 V / +27 dBu Input Impedance10 kOhmCommon Mode Rejection-85 dB @ 1 kHz (typical)A/D Conversion 24-Bit Sigma-DeltaAnalog Audio Outputs 6 x XLR OUT, electronically balanced Nominal Output Voltage 1.55 V / +6 dBu Maximum Output Voltage8.7 V / +21 dBu Output Impedance 50 OhmD/A Conversion 24-Bit Sigma-DeltaFrequency Response20 Hz to 22 kHz (+/-0.5 dB)THD+N< 0.002% (band limited 22 Hz to 22 kHz)Dynamic Range116 dB (A-weighted)USB USB Type B on front panel (PC Inter-face)Ethernet 2 x RJ-45 ports, 100 MB, Integrated SwitchControl Port1 x 6-pole Euro blockSoftware Configurable for Preset Recall Sample Rate 48 kHz Data Format24-BitInternal Processing 48-Bit Double PrecisionSignal ProcessingParametric EQs, 31 band Graphic EQs, Delays, Routing, X-Over, 512 Taps FIR filters, PA limiter, TEMP limi-ter, Level, Polarity, Signal generator Operating Temperature Range0 °C to 40 °CDimensions (WxHxD)19 x 13.9 x 1.72 inch (483 x 356.1 x 43.6 mm)Weight (Net)4.8 kgDx46FIR-DRIVESound System Processor Block Diagram:Dx46FIR-DRIVESound System Processor DSP Signal Flow Chart:12000 Portland Avenue South, Burnsville, MN 55337Phone: 952/884-4051, Fax: 952/884-0043© Bosch Communications Systems 03/2010Part Number F01U126854 Vs 01U.S.A. and Canada only. For customer orders, contact Customer Service at :800/392-3497 Fax: 800/955-6831Europe, Africa, and Middle East only. For customer orders, contact Customer Service at:+ 49 9421-706 0 Fax: + 49 9421-706 265Other International locations. For customer orders, Contact Customer Service at:+ 1 952 884-4051 Fax: + 1 952 887-9212For warranty repair or service information, contact the Service Repair department at:800/685-2606For technical assistance, contact Technical Support at: 866/78AUDIOSpecifications subject to change without notice.Dimensions Drawings:Rear View:Dx46 Part Number:Agency ApprovalsDx46, 120 V -- F01U126855CE Dx46, 230 V -- F01U126854FCC, ICCB。
HP SmartStream Print Module服务器与控制器说明书
HP SmartStreamPrint Module workflow solutionsVariable data where you want it, when you want itThe HP SmartStream Print Module Server and the HP SmartStream Print Module Controller offer an intelligent, high-performance,reliable, scalable, and easy-to-use solution for managing large and complex variable data print jobs. Together, they enable you to increase productivity and job efficiencies.HP SmartStream Print Module ServerOptimize color quality with advanced color-managementcapabilities. Utilize site-specific International Color Consortium (ICC) profiles for specific color characterizations and workflows, promoting consistent color quality.Minimize manual tasks, reduce operator intervention, simplify management, and save valuable time. Simplify management by providing a single interface to view your job statuses and manage print job processing. Production managers can set up job tickets for specific workflows, to streamline work processes. Load-balancing algorithms allow you to stream jobs automatically across RIPprocessors. Hot folders submit the files to initiate and streamline high-volume job processing.Achieve greater flexibility. Combined with industry-leading partner solutions and integrated with the broad and deep HP Print Module Solution family, the HP SmartStream Print Module Server optimizes digital imprinting and simplifies the integration of your digital workflows.Scale your processing capacity by adding additional server capabilities. Start with a base configuration and add processing capabilities as your workload and job complexity increases.HP SmartStream Print Module ControllerSimplify color and monochrome print module management. The HP SmartStream Print Module Controller provides an easy-to-use interface for managing print modules and data streams for multiple print module configurations. This management interface can be used in single- and double-sided imprinting applications for web, envelope, and cut-sheet equipment – at speeds from 500 feet (152 meters) per minute to up to 800 feet (244 meters) per minute – providing you with greater flexibility.Easily scalable so you can increase your capabilities. Base configurations are scalable for growing business requirements, supporting up to five HP color print modules or up to 10 HP monochrome print modules per side. It can also be expanded to support multiple print modules in single- and double-sided imprinting applications, and you can add more print modules as needed.Simplify your web printing setup. The HP SmartStream Print Module Controller comes with an auto-alignment feature for web lineintegrations. This automates the printhead alignment between CMYK print heads within each HP Color Print Module and module to module when stitched. As a result, you achieve consistent, high quality no matter how print modules are configured. The controller supports read and print capabilities for dynamic data requirements. Print job configurations can be stored and reused, which simplifies job print management for operators.For more information visit: /go/printmodulesolutions© Copyright 2012 Hewlett-Packard Development Company, L.P . The information contained herein is subject to change without notice. The only warranties for HP products and services are set forth in the express warranty statements accompanying suchproducts and services. Nothing herein should be construed as constituting an additional warranty. HP shall not be liable for technical or editorial errors or omissions contained herein.4AA3-9852ENW, April 2012.Technical specificationsHP SmartStream Print Module Server H2P59A HP Print Module PS050 Print Server Tower H2P60A HP Print Module PS100 Server Rack System H3A35A HP Print Module PSRIPEXP Rack ServerHP Print Module Solutions Supported HP SmartStream Print Module Controller, HP Color Print Module, HP Monochrome Print ModuleInput file formatsPostscript 1,2,3, PDF 1.7, PDF/x-1a: 2001, PDF (Including optimized PDF)/X-1a:2003, PDF /x-3:2002, PDF/X-3:2003, PDF/ X-4, PPML, 2.2, PPML-T, EPS, GIF , JPEG, TIFF 6, Microsoft XPS 1.0 including HD photo assets, DCS, DCS 2Operating SystemMicrosoft Windows 2008 server R2Client OS versions Windows ® XP , Vista, 2003, and 2000. MacOS ® 10.4 and 10.5UI Language English, French, Italian, German, Spanish, Japanese, Simplified Chinese RIP core Global Graphics Harlequin 8.0Color & Quality ICC version 4.0Switching hubsHP ProCurve - some items depend on the specific product configuration HP SmartStream Print Module ControllerH2P54A HP Print Module PC25T Tower Controller H2P55A HP Print Module PC510C Rack Controller H2P27A HP Print Module PC510WS Rack Controller H2P28A HP Print Module PC510WD Rack ControllerHP Print Module Solutions Supported HP Color Print Module, HP Monochrome Print Module, HP Intelligent Ink Supply Station, HP Color Print Module Ink Supply Station, and HP Remote Ink Transfer Station Number of modules supported 5 color print modules per side (10 total)10 mono print modules per side (20 total)Print Module Stitching Disjoined and stitched configurations. Stitching can be staggered or nose-to-nose Control input Read and print, cue marksMin Input Image Size Width (y dir.) is 4.25 inchesLength (x dir.) is distance between TOF sensor and furthest nozzle of furthest print module divided by 32Max Input Image Size 900 Square inches (e.g. 20” swath, 45” long)Operating System Microsoft Windows Server 2008 R2 64-bit and Windows Server 2003 R2 SP2 32-bit UI Language EnglishNetwork switchHP ProCurve - some items depend on the specific product configuration。
FASM
FASM 是一个 x86 体系处理器下的汇编语言编译器,它可以通过多遍扫描来优化生成的机 器码。 这篇文档还描述了用于 windows 系统的 IDE 版本,这个版本带有界面,并且有一个集成 的编辑器。但从编译的角度,它和命令行版本是一样的。IDE 版本的可执行文件为 fasmw.exe,命令行的为 fasm.exe
运行命令也调用执行编译器,并且在编译成功后如果此格式能在 Windows 环境下执行的 话执行编译的程序;否则将弹出消息提示此类型文件不能执行。如果发生错误,编译器显 示和编译命令相同的提示。
如果编译器运行超出内存,你可以在【选项】菜单中的【编译器设置】对话框中增加内存 分配。你可以设置编译器应当使用多少 KB 字节,以及编译线程的优先级。
保存优化 - 如果允许此选项,当保持文件的时候,空白区域将被优化的 tab 和空格填充来 减少文件的大小。如果关闭此选项,空白区域将填充为空格(不保存最后一行的空格)。 Revive dead keys - left to do.
1.1.4 在命令行下执行编译器 在命令行下执行编译需要运行 fasm.exe。fasm 接受两个参数 - 第一个提供源码文件,第 二个提供目标文件。如果没有给定第二个文件,输出文件名称将自动猜测一个。当显示简 短的程序名称和版本后,编译器从源码文件中读取数据并且编译它。当编译成功,编译器 将写入生成的文件到目标文件,并且显示编译过程总结;否则将显示发生的错误信息 源码文件必须是文本格式的,行结束符接受 DOS(CR+LF)和 Unix(LF)两种格式, tab 将被当做空格处理。 在命令行中你可以指定-m 选项用来指定 fasm 汇编器最大使用的内存(KB)。在 DOS 版 本中,这个选项仅用来限定扩展内存的使用。-p 选项后面用来指定汇编器要执行的遍数。 如果代码不能再指定的遍后生成,汇编器将结束并给出错误信息。最大值为 65536,默认 值为 100。这个参数可以用来限制汇编器最多执行的遍数,-p 参数跟随一指定的最大遍数 即可。 没有命令行参数来影响输出,flat 汇编器仅需要源码文件来包含真正需要的信息。例如, 为了制定输出格式你可以在源码文件开头使用 format 指令。
Matrox Solios eA 和 eCL 计算机兼容性测试规格说明书
Intel 5520
x16, x4 PCIe / 5V PCI
Single Intel Xeon E5540 0.17
3 GB of DDR3 1333 MHz SDRAM
Windows XP 32‐bit (SP3) / Windows 7 64‐bit / MIL 9 RC2 (b1950)
Comments
Test configurations
None.
Matrox Solios eA/eCL/eCL‐B tested in slot 1 with Matrox P650.
Requires PLX bridge update.
Matrox Solios eA/eCL/eCL‐B/ eCL‐F tested in slots 1 and 4 with Matrox G550 (eA, eCL) and P650 (eCL, eCL‐B, eCL‐F). Matrox Solios eCL‐B also tested in slot 5.
Matrox Solios eA and eCL PC Compatibility Test Specifications September 2, 2011
This list provides additional details about the platforms (desktop systems, motherboards and industrial computers) certified by Matrox Imaging to be compatible with the Matrox Solios eA and eCL frame grabber board. Compatibility is defined as the general ability of the Matrox Solios eA and eCL to function properly on the specified platform. It does not necessarily take into account interaction with other expansion peripherals. Therefore, customers should perform testing based on their applications’ specific needs. Compatibility is not limited to the platforms listed below. Other platforms with similar characteristics may also be compatible. Please contact Matrox Imaging Technical Support for more information. Blue shaded text indicates a recently added listing.
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Automatic Processor Lower Bound Formulas for Array ComputationsPeter CappelloDepartment of Computer Science University of California at Santa Barbara Santa Barbara,CA93106,USAcappello@¨Omer E˘g ecio˘g luDepartment of Computer Science University of California at Santa Barbara Santa Barbara,CA93106,USAomer@AbstractIn the directed acyclic graph(dag)model of algorithms, consider the following problem for precedence-constrained multiprocessor schedules for array computations:Given a sequence of dags and linear schedules parameterized by, compute a lower bound on the number of processors re-quired by the schedule as a function of.This problem is formulated so that the number of tasks that are scheduled for execution during anyfixed time step is the number of non-negative integer solutions to a set of parametric lin-ear Diophantine equations.Generating function methods are then used for constructing a formula for the numbers .We implemented this algorithm as a Mathematica pro-gram.This paper is an overview of the techniques involved and their applications to well-known schedules for Matrix-Vector Product,Triangular Matrix Product,and Gaussian Elimination dags.Some example runs and automatically produced symbolic formulas for processor lower bounds by the algorithm are given.1IntroductionParallel execution of array computations(uniform recur-rence equations)[17]has been studied extensively[18,14, 15,19,20,16]).In such computations,the computational tasks are viewed as the nodes of a dag;arcs represent data dependencies.Given a dag,a multiprocessor schedule assigns node for processing during step on processor.A valid multiprocessor schedule is subject to the constraints:Causality:A node is computed only after its children have been computed:Non-conflict:A processor cannot compute2different nodes during the same time step:In what follows,we refer to valid schedules simply as schedules.A schedule is good,if it uses time efficiently; an implementation of a schedule is good,if it uses few processors.This view prompted several researchers to in-vestigate processor-time-minimal schedules for families of dags.These are time-minimal schedules that in addition use as few processors as possible.Processor-time-minimal schedules for various fundamental problems have been pro-posed in the literature:Scheiman and Cappello[3,11,9] examine the dag family for matrix product;Louka and Tchuente[8]examine the dag family for Gauss-Jordan elimination;Scheiman and Cappello[10]examine the dag family for transitive closure;Benaini and Robert[2,1]ex-amine the dag families for the algebraic path problem and Gaussian elimination.Clauss,Mongenet,and Perrin[4]de-veloped a set of mathematical tools to helpfind a processor-time-minimal multiprocessor array for a given dag.Another approach to a general solution has been reported by Wong and Delosme[13],and Shang and Fortes[12].They present methods for obtaining optimal linear schedules.That is, their processor arrays may be suboptimal,but they get the best linear schedule possible.Darte,Khachiyan,and Robert[16]show that such schedules are close to optimal, even when the constraint of linearity is relaxed.In[9],a lower bound on the number of processors needed to satisfy a schedule for a particular time step was formulated as the number of solutions to a linear Diophan-tine equation,subject to the linear inequalities of the con-vex polyhedron that defines the dag’s computational do-main.Such a geometric/combinatorial formulation for the study of a dag’s task domain has been used in various other contexts in parallel algorithm design as well(e.g., [17,18,19,7,6,20,4,12,13];see Fortes,Fu,and Wah [5]for a survey of systolic/array algorithm formulations.) The maximum such bound for a given linear schedule,taken over all time steps,is a lower bound for the number of pro-cessors needed to satisfy the schedule for the dag family. [23,22]present a more general and uniform technique for deriving such lower bounds:Given a parameterized dagfamily and a correspondingly parameterized linear sched-ule,a formula for a lower bound on the number of proces-sors required by the schedule is computed.This is much more general than the analysis of an optimal schedule for a given specific dag.The lower bounds obtained are good; we know of no dag treatable by this method for which the lower bounds are not also upper bounds.The nodes of the dag typically can be viewed as lattice points in a convex polyhedron.Adding to these constraints the linear constraint imposed by the schedule itself results in a linear Diophantine system of the formwhere the matrix and the vectors and are integral, but not necessarily non-negative.The number of solu-tions in non-negative integers to this linear system is a lower bound for the number of processors required when the dag corresponds to parameter.Our algorithm produces(symbolically)the generating function for the sequence,and from the generating function,a formula for the numbers.We do not make use of any special properties of the system that reflects the fact that it comes from a dag.Thus in the linear system above, can be taken to be an arbitrary integral matrix,and and arbitrary-dimensional integral vectors.As such,we solve a more general combinatorial problem of constructing the generating function,and a formula for given a matrix and vectors and,for which the lower bound computation is a special case.2Examples from Array Computations2.1Matrix-Vector ProductAn algorithm for matrix-vector product is given in the following procedure.is the input matrix,is the input vector,and is the output vec-tor.We index the entries of an-dimensional vector by.for to do:;for to do:;endfor;endfor;Computation is“located”at certain index pairs defined by the for loop limits,namely all pairs satisfying:(1)These pairs are the lattice points inside the2-dimensional convex polyhedron whose four faces are de-fined by the four inequalities above.The faces of the poly-hedron are,in turn,constructed from the for loop limits.We henceforth are concerned with only non-negative inte-gral solutions to Diophantine equations.In this way,the inequalities,and are implied,and need not be specified.In order to transform the set of inequalities in(1) to a set of equations(which turn out to be easier to work with),we introduce integral slack variables: The standard array computation for matrix-vector product is given by,where.and,and or,and.i + j + 1 = 2Figure1.The matrix-vector product dag for .The standard,time-minimal linear multiprocessor sched-ule for is to execute node at time. For the case,the computation begins in time step 1with the computation of,and ends in time step with the computation of.At time step,all nodes,where are scheduled for parallel execution(see Figure1).At time step,there are nodes scheduled for execution:.If we include the linear schedule in the set of Diophantine equations describing the loop index ranges,then number of non-negative solutions to the augmented system of linear Diophantine equations is the number of tasks scheduled for execution during time step.Thus for any particular with,the number of solutions to the resulting linear Diophantine system is a lower bound on the number of processors necessary for the schedule.As an example, for,the augmented system obtained from(1)is(2)The number of non-negative integral solutions to(2)is a processor lower bound for the Matrix-Vector Product problem.2.2Triangular Matrix ProductAn algorithm for the computation of the matrix product ,where and are given upper triangular matrices is given below.for to do:for to do:for to do:;endfor;endfor;endfor;The computational nodes are defined by non-negative inte-gral triplets satisfyingIn fact,the whole polyhedron is defined by the inequalitiesNote that as before we assume from the outset that the variables are non-negative.Introducing inte-gral slack variables,we obtain the equivalent linear Diophantine systemA linear schedule for the corresponding dag is given by.Since ranges from to ,we can augment the system by adding the constraintfor any rational number between 0and1.In particular the halfway point in this schedule is time step.Again,we only present the case of even because of space considerations.For,we can take to be.Adding the schedule constraint to system we already have,we obtain the augmented Dio-phantine systemHere and. Therefore,a lower bound for the number of processors needed to implement the schedule of the algorithm for Gaussian elimination without pivoting of an matrix with is the number of solutions of the above sys-tem.In the examples above,thefinal problem to be solved is the determination of the number of non-negative integralsolutions to a linear parametric(parametrized by)Dio-phantine system of the form where is someintegral matrix,and are-dimensional integralvectors.3The General FormulationNext,we describe how to use a Mathematica program toto automatically construct a formula for the number of lat-tice points inside a linearly parameterized family of convexpolyhedra.The algorithm for doing this and its implemen-tation have been reported in detail in[our paper].First of all,the general setting exemplified by the prob-lems in the preceding section is as follows:Suppose(alsodenoted by)is an integral matrix,and and are-dimensional integral vectors.Suppose further that,for ev-ery,the linear Diophantine system,i.e.in the non-negative integral variables hasafinite number of solutions.Let denote the number ofsolutions for.The generating function of the sequenceis.For a linear Diophantine systemof the above form is always a rational function,andcan be computed symbolically[23,22].The Mathematicaprogram DiophantineGF.m we have written for thiscomputation1implementing the algorithm also constructs aformula for the numbers from this generating function.Given a nested for loop,the procedure to follow is infor-mally as follows:1.Write down the node space as a system of linear in-equalities.The loop bounds must be affine functionsof the loop indices.The domain of computation is rep-resented by the set of lattice points inside the convexpolyhedron,described by this system of linear inequal-ities.2.Eliminate unnecessary constraints by translating theloop indices(so that as opposed to,for example).The reason for this is that theinequality is implicit in our formulation,whereasintroduces an additional constraint.3.Transform the system of inequalities to a system ofequalities by introducing non-negative slack variables,one for each inequality.4.Augment the system with a linear schedule for theassociated dag,“frozen”in some intermediate timevalue:;5.Run the program DiophantineGF.m on the re-sulting data.The program calculates the rational gen-erating function,where is the num-when is a non-negative integer,and zerootherwise.4.2Triangular Matrix Product()For the Triangular Matrix Product problem theDiophantine system is whereand for.In this case,In[1]:=<<DiophantineGF.mIn[2]:=a={{1,1,1,0,0,0},{0,1,0,1,0,0},{0,-1,1,0,1,0},{1,0,-1,0,0,1}};In[3]:=b={3,2,0,0};c={-2,-1,0,0}; In[4]:=DiophantineGF[a,b,c]tOut[4]=--------3(1-t)In[5]:=formulaBinomial Formula:C[1+n,2]n(1+n)Power Formula:---------2Since the in this formula is our,substituting,wefind that a lower bound for the number of processors needed to satisfy the linear schedule forthe Triangular Matrix Product is where .Considering the case as well,wefind that a lower bound for the number of processors needed tosatisfy a the linear schedule for the Triangular Matrix Product is4.3Gaussian EliminationFor Gaussian Elimination without pivoting of an matrix the Diophantine system is whereHere and,for .The generating function computed isfor.This also happens to be the formula produced bining the results,for Gaussian elimination without pivoting for arbitrary,we obtain the processor lower boundIn bounding the number of processors needed to satisfy a linear multiprocessor schedule for a nested loop program, we actually derived a solution to a more general linear Dio-phantine problem.This leaves open some interesting com-binatorial questions of rationality and associated algorithm design:e.g.how to compute the associated generating func-tion of the number of solutions when the right hand side of the main system consists of higher degree polynomials in, and not just linear.For details of this presentation,please refer to[23,22]. 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