ApplicationNote-Negative Spike In Buck Converters_6 值得学习

合集下载

Buck电源设计

* (Rx, Cy) 显示驱动极点及零点的组成部分。详尽的公式登载在注释的一页内。
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电压模式 ─ 误差信号放大器
VC ZF =− VOUT ZI
我们可以因应误差信号放大器的四周环境变化而调整所需补偿，我们可以因应误差信号放大器的四周环境变化而调整所需补偿，这是最容易为整个环路提供补偿的地方。此外，也有几个其他方法可以采用。容易为整个环路提供补偿的地方。此外，也有几个其他方法可以采用。
R C2 = 1 ω P2C C3
CC3 =
1 ωZ2RFB2
C C2 =
C C1 =
ω Z2 R FB2 Cc 3 ω Z1R C1
RC1 = kRFB2
1 ω P1R C1
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简单易用的电源产品
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如何利用第 5 代 SIMPLE SWITCHER® 解决这个问题?
完全无需考虑外部补偿的问题
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电压模式 ─ 第 3 类 (Type III) 补偿
VOUT
ZF
CC2 CC3 CC1 RC1 RC2 VFB VREF
ZI
dB
60 40
(RFB2, Cc3)
RFB2
20 0
k
~ = Rc /RFB2
ωz 2 ~ = Rc1 /Rc2
ωP1
ωP 2
Hz
100,000 1,000,000
(Rc2, Cc3)
Buck电源设计
2011年8月
1-1
内容
直流/直流转换器的基本原理简单易用的电源产品
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直流/直流转换器的基本原理
1-3
降压稳压器
控制开关输入电容器
电感器开关节点电压输出电容器

Kingbright 蓝色LED灯的数据手册说明书

Part NumberEmitting Color (Material)Lens TypeIv (mcd) @ 20mA [2] Viewing Angle [1]Min. Typ. 2θ1/2L-7104PBC-A■ Blue (InGaN)Water Clear 400 30°900DESCRIPTIONSzThe Blue source color devices are made with InGaN on SiC Light Emitting Diodez Electrostatic discharge and power surge could damage the LEDsz It is recommended to use a wrist band oranti-electrostatic glove when handling the LEDs z All devices, equipments and machineries must be electrically groundedFEATURESzLow power consumptionz Popular T-1 diameter package z General purpose leads z Reliable and ruggedz Long life - solid state reliability z Available on tape and reel z RoHS compliantAPPLICATIONSz Status indicator z Illuminatorz Signage applicationsz Decorative and entertainment lightingzCommercial and residential architectural lightingATTENTIONObserve precautions for handlingelectrostatic discharge sensitive devicesPACKAGE DIMENSIONSL-7104PBC-AT-1 (3mm) Solid State LampSELECTION GUIDENotes:1. θ1/2 is the angle from optical centerline where the luminous intensity is 1/2 of the optical peak value.2. Luminous intensity / luminous flux: +/-15%.3. Luminous intensity value is traceable to CIE127-2007 standards.Notes:1. All dimensions are in millimeters (inches).2. Tolerance is ±0.25(0.01") unless otherwise noted.3. Lead spacing is measured where the leads emerge from the package.4. The specifications, characteristics and technical data described in the datasheet are subject to change without prior notice.ABSOLUTE MAXIMUM RATINGS at T A =25°CELECTRICAL / OPTICAL CHARACTERISTICS at T A =25°CNotes:1. 1/10 Duty Cycle, 0.1ms Pulse Width.2. 2mm below package base.3. 5mm below package base.4. Relative humidity levels maintained between 40% and 60% in production area are recommended to avoid the build-up of static electricity – Ref JEDEC/JESD625-A and JEDEC/J-STD-033.Notes:1. The dominant wavelength (λd) above is the setup value of the sorting machine. (Tolerance λd : ±1nm. )2. Forward voltage: ±0.1V.3. Wavelength value is traceable to CIE127-2007 standards.4. Excess driving current and / or operating temperature higher than recommended conditions may result in severe light degradation or premature failure.ParameterSymbol Value Unit Power Dissipation P D 120 mW Reverse Voltage V R 5 V Junction Temperature T j 125 °C Operating Temperature T op -40 to +85 °C Storage Temperature T stg -40 to +85°C DC Forward Current I F 30 mA Peak Forward CurrentI FM [1]100 mA Electrostatic Discharge Threshold (HBM) -1000VLead Solder Temperature [2] 260°C For 3 Seconds Lead Solder Temperature [3]260°C For 5 SecondsParameterSymbol Emitting ColorValue Unit Typ. Max. Wavelength at Peak Emission I F = 20mA λpeak Blue 468 - nm Dominant Wavelength I F = 20mA λdom [1] Blue 465 - nm Spectral Bandwidth at 50% Φ REL MAX I F = 20mA Δλ Blue 21 - nm CapacitanceC Blue 100 - pF Forward Voltage I F = 20mA V F [2] Blue 3.2 4 V Reverse Current (V R = 5V)I RBlue-10uATECHNICAL DATABLUERECOMMENDED WAVE SOLDERING PROFILENotes:1. Recommend pre-heat temperature of 105°C or less (as measured with a thermocoupleattached to the LED pins) prior to immersion in the solder wave with a maximum solder bath temperature of 260°C2. Peak wave soldering temperature between 245°C ~ 255°C for 3 sec (5 sec max).3. Do not apply stress to the epoxy resin while the temperature is above 85°C.4. Fixtures should not incur stress on the component when mounting and during soldering process.5. SAC 305 solder alloy is recommended.6. No more than one wave soldering pass.PACKING & LABEL SPECIFICATIONSPRECAUTIONSStorage conditions1. Avoid continued exposure to the condensing moisture environment and keep the product away from rapid transitions in ambient temperature.2. LEDs should be stored with temperature ≤ 30°C and relative humidity < 60%.3. Product in the original sealed package is recommended to be assembled within 72 hours of opening. Product in opened package for more than a week should be baked for 30 (+10/-0) hours at 85 ~ 100°C.2. When soldering wires to the LED, each wire joint should be separately insulated with heat-shrink tube to prevent short-circuit contact. Do not bundle both wires in one heat shrink tube to avoid pinching the LED leads. Pinching stress on the LED leads may damage the internal structures and cause failure.3. Use stand-offs (Fig.1) or spacers (Fig.2) to securely position the LED above the PCB.4. Maintain a minimum of 3mm clearance between the base of the LED lens and the first lead bend (Fig. 3 ,Fig. 4).5. During lead forming, use tools or jigs to hold the leads securely so that the bending force will not be transmitted to the LED lens and its internal structures. Do not perform lead forming once the component has been mounted onto the PCB. (Fig. 5 )LED Mounting Method1. The lead pitch of the LED must match the pitch of the mounting holes on the PCB during component placement.Lead-forming may be required to insure the lead pitch matches the hole pitch.Refer to the figure below for proper lead forming procedures.Note 1-3: Do not route PCB trace in the contact area between the leadframe and the PCB to prevent short-circuits." ○" Correct mounting method " x " Incorrect mounting methodLead Forming Procedures1. Do not bend the leads more than twice. (Fig. 6 )2. During soldering, component covers and holders should leaveclearance to avoid placing damaging stress on the LED duringsoldering.(Fig. 7)3. The tip of the soldering iron should never touch the lens epoxy.4. Through-hole LEDs are incompatible with reflow soldering.5. If the LED will undergo multiple soldering passes or face otherprocesses where the part may be subjected to intense heat,please check with Kingbright for compatibility.PRECAUTIONARY NOTES1. The information included in this document reflects representative usage scenarios and is intended for technical reference only.2. The part number, type, and specifications mentioned in this document are subject to future change and improvement without notice. Before production usage customer should refer tothe latest datasheet for the updated specifications.3. When using the products referenced in this document, please make sure the product is being operated within the environmental and electrical limits specified in the datasheet. Ifcustomer usage exceeds the specified limits, Kingbright will not be responsible for any subsequent issues.4. The information in this document applies to typical usage in consumer electronics applications. If customer's application has special reliability requirements or have life-threateningliabilities, such as automotive or medical usage, please consult with Kingbright representative for further assistance.5. The contents and information of this document may not be reproduced or re-transmitted without permission by Kingbright.6. All design applications should refer to Kingbright application notes available at /application_notes。

Agilent 7700x 7800 ICP-MS application note说明书

Analysis of flue gas desulfurization wastewaters with the Agilent 7700x/7800 ICP-MS Application noteAuthorsRichard Burrows TestAmerica Laboratories, Inc. USASteve WilburAgilent TechnologiesUSAEnvironmentalIntroductionThe U.S. Environmental Protection Agency (US EPA) is in the processof revising effluent guidelines for the steam electric power generating industry, due to increases in wastewater discharges as a result of Phase 2 of the Clean Air Act amendments. These regulations require SO2scrubbing for most coal-fired plants resulting in ‘flue gas desulfurization’ (FGD) wastewaters. The revised effluent guidelines will apply to plants ‘primarily engaged in the generation of electricity for distribution and sale which results primarily from a process utilizing fossil-type fuel (coal, oil or gas) or nuclear fuel in conjunction with a thermal cycle employing the steam water system as the thermodynamic medium’[1]. This includes most large-scale power plants in the United States. Effluents from these plants, especially coal-fired plants, can contain several hundred to several thousand ppmof calcium, magnesium, manganese, sodium, boron, chloride, nitrate and sulfate. Measurement of low ppb levels of toxic metals (including As, Cd,Cr, Cu, Pb, Se, Tl, V and Zn) in this matrix presents a challenge for ICP-MS,Sample preparationThe samples were collected in HDPE containers and acidified with trace metal grade nitric acid to pH <2. Sample preparation was performed according to EPA 1638, Section 12.2 for total recoverable analytes by digestion with nitric and hydrochloric acid in a covered Griffin beaker on a hot plate. All calibrations wereprepared in 2% HNO 3/0.5% HCl v/v as described in the method.Analytical methodA standard Agilent 7700x ICP-MS with Micromist nebulizer and optional ISIS-DS was used. HMI aerosol dilution was set to medium, using the MassHunter ICP-MS software to automatically optimize the plasma parameters and robustness (CeO +/Ce + ratio ~0.2%). MassHunter uses HMI optimization algorithms that take into account the type of nebulizer used, to ensure reproducible conditions from run to run and from instrument to instrument. Operating parameters are shown in Table 1.Table 1. Instrument parameters used, illustrating simple, consistentHMI modeRobust plasma, medium aerosol dilutionForward RF power (W)1550Carrier gas flow (L/min)0.56Dilution gas flow (L/min)0.33Extraction lens 1 (V)0Kinetic energy discrimination (V)4Cell gas flow (mL/min) 4 (He)4 (H 2)Acquisition conditions Number of isotopes (including ISTDs)253Number of replicates 3Total acquisition time (s)80 (total for both ORS modes)ISIS parameters Sample loop volume (μL)600Online dilution factor1:2due to the very high dissolved solids levels and potential interferences from matrix-based polyatomic ions. Furthermore, FGD wastewater can vary significantly from plant to plant depending on the type and capacity of the boiler and scrubber, the type of FGD process used, and the composition of the coal, limestone and make-up water used. As a result, FGD wastewater represents the most challenging of samples for ICP-MS; it is very high in elements known to cause matrix interferences, and also highly variable. To address this difficult analytical challenge, in 2009 the EPA commissioned the development of a new ICP-MS method specifically for FGD wastewaters. This method was developed and validated at TestAmerica Laboratories, Inc. using an Agilent 7700x ICP-MS equipped with an Agilent ISIS-DS discrete sampling system.Methods and materialsInstrumentationThe Agilent 7700x ICP-MS with ISIS-DS is uniquely suited to the challenge of developing a simple, robust analytical method for the analysis of regulated metals in uncharacterized high-matrix FGD wastewaters. Three attributes of the 7700x system are particularly critical and work together to enable reliable, routine analysis of large batches of variable high-matrix samples:•Agilent’s unique High Matrix Introduction (HMI) system enables controlled, reproducible aerosol dilution, which increases plasma robustness and significantly reduces exposure of the interface and ion lenses to undissociated sample matrix.•The Octopole Reaction System (ORS 3) operating in helium collision mode eliminates matrix-based polyatomic interferences regardless of sample composition, without the need for time consuming sample-specific or analyte-specific optimization.•The optional ISIS-DS discrete sampling system significantly reduces run time, while further reducing both matrix exposure and carryover.The ORS 3 was operated in two modes: helium collision mode (He mode) for all analytes except selenium, which was measured in hydrogen reaction mode (H 2 mode). Twenty-five masses including internal standards were acquired, with typical integration times of 50 ms per replicate and three replicates per sample. Instrument detection limits (IDLs) were automatically calculated by the MassHunter software, based on the precision of the calibration blank measurement and the slope of the calibration plots (Table 2). Method detection limits (MDLs) (3σ) were calculated from 7 replicate analyses of a low-level spike of the synthetic FGD matrix solution.Cr 520.05He Sc 0.17-Mn 550.05He Sc 0.440.68Ni 600.05He Sc 0.170.45Cu 630.05He Sc 0.150.48Zn 660.05He Ge 0.94 2.04As 750.1He Ge 0.490.61Se 780.05H 2Ge 0.080.31Ag 1070.05He In 0.020.29Cd 1110.05He In 0.190.59Sb 1210.05He In 0.050.36Tl 2050.05He Ho 0.020.23Pb2080.05HeHo0.030.36* MDL calculated as 3σ of low-level spike into synthetic FGD matrix sample (n=7). MDL not calculated for chromium due to significant contamination in the synthetic FGD matrix solution. Additional isotopes were acquired for internal confirmation, but not reported.Quality controlThe quality control used for the new FGD wastewater method was based on the typical protocols used in other EPA methods. Prior to commissioning for routine operation, initial method validation requires determination of method detection limits, linear ranges, and analysis of multiple, single-element interference check solutions, to assess the effectiveness ofpolyatomic interference removal under the collision/reaction cell conditions used in the method. In routine use, daily quality control in a typical analytical sequence includes the analyses outlined in Table 3.The FGD wastewater method requires the analysis of two new QC samples: a synthetic FGD matrix sample and a fortified FGD matrix sample.Prior to preparing the synthetic FGD matrix samples, each potential matrix component was analyzed as a separate single-element standard, in order to determine the source and magnitude of any potential contaminants and the effectiveness of He mode atremoving matrix-based interferences. Results are shown in Table 4. Nearly all contaminants and interferences were sub-ppb. The most significant contaminants were Cr, Ni and Zn in the 10,000 ppm Ca solution, confirmed by measuring secondary or qualifier isotopes for the analytes. Approximately 2 ppb of V was detected in the 10% HCl solution. This was either due to contamination, a small residual interference from 35Cl 16O, or acombination of the two, but at less than 2 ppb it did not present a problem for this analysis.After each matrix component was characterized individually, a mixed synthetic FGD solution was prepared with the composition shown in Table 5, together with a second solution with the same matrix components but additionally spiked with all the analyte elements at 40 ppb. These new FGD matrix samples are analogous to the interference check solutionsICS-A and ICS-AB required by EPA method 6020, except the synthetic FGD samples are much higher in total dissolved solids (TDS) than the ICS-A and AB solutions, and contain those matrix elements that are commonly high in actual FGD samples. The detailed composition of the FGD matrix samples, which contain a total of >1% (10,000 ppm) TDS, is listed in Table 5, and results from the analysis of the synthetic FGD matrix blank and synthetic FGD matrix spike are shown in Table 6.Table 3. Typical FGD analytical sequence including all required quality control. ICV: Initial Calibration Verification, ICB: Initial Calibration Blank,CCV: Continuing Calibration Verification, CCB: Continuing Calibration Blank, LCS: Laboratory Control Sample, MS/MSD: Matrix Spike/Matrix Spike DuplicateTable 4. Initial demonstration of interference removal in single-element matrix solutions. Analyte concentrations (ppb) for each matrix (sum of analyte52 Cr0.7710.0000.17155 Mn0.0190.1370.64760 Ni 1.1150.7400.07863 Cu-0.0950.1870.17866 Zn 2.7060.160-0.12675 As0.689-0.1540.27178 Se0.0290.2130.320107 Ag0.0120.0400.002111 Cd-0.005-0.031-0.044121 Sb0.6560.0280.542205 Tl0.0620.013-0.003208 Pb0.0580.1350.037Table 5. Composition of synthetic FGD matrix sample. Laboratory fortified synthetic FGD sample is spiked with 40 ppb of each of the target elementsCalcium2000 mg/LMagnesium1000 mg/LSulfate2000 mg/LSodium1000 mg/LButanol 2 mL/LTable 6. Analysis of mixed matrix FGD interference check sample and spiked52 Cr12.699*96.6%0.01548.8510.11755 Mn-0.10194.3%-0.32848.4350.10060 Ni0.24788.4%-0.00948.5350.15463 Cu0.09491.6%0.09647.3160.11566 Zn 3.18186.1%-0.30249.8040.10075 As0.107110.0%-0.04348.2050.00978 Se0.538120.2%-0.14449.6050.186 107 Ag0.14594.3%0.01047.6320.003 111 Cd0.03998.9%-0.01748.6950.017 121 Sb0.18198.4%0.01550.8060.031 205 Tl0.02190.3%0.00048.1080.008 208 Pb0.43692.1%0.00348.3810.008* Cr contamination verified by secondary isotope.ResultsInitial performance verification indicated that the 7700x with HMI was able to analyze the very high matrix samples, and He mode successfully eliminated matrix-based spectroscopic interferences, while the use of ISIS-DS helped to minimize memory effects (Table 6). Accuracy, both in terms of calibration stability (CCV) and for spike recoveries in the matrix (spiked FGD solution), were well within the standard operating procedure (SOP) requirements (CCV ± 15%, matrix spike recoveries ± 30%).When running real FGD samples in a long sequence, continuing instrument performance must be monitored according to typical EPA criteria. Each group of 10 samples must include one laboratory control sample (LCS) of known concentration, and one matrix spike/ matrix spike duplicate (MS/MSD) pair in addition to 7 unknown samples.After each block of 10 samples, calibration and blank levels were verified through the analysis of a CCV and CCB standard (Figure 1). Additionally, internal standards were monitored for all samples and easily met the requirement to fall within 60 to 125% of the intensity measured in the calibration blank (Figure 2). Internal standard recoveries provide information on sample-specific matrix effects as well as longterm instrument drift.Figure 1. CCV recoveries over a sequence of 88 analyses including real FGD samples, all required QC samples and synthetic FGD matrix samples. Control limits (85–115%) are indicated in red.Internal standard recoveries for the 88 sample validation sequence are shown in Figure 2. All samples met the ISTD QC requirements of 60 to 125% recovery and total instrument drift over the course of the sequence was less than 10% as indicated by the ISTD response for the final CCV sample.In the complete sequence, a total of six MS/MSD pairs were analyzed and the relative percent difference (RPD) calculated for each pair is shown in Table 7. The method limit for RPD is < 20% which includes both measurement and sample preparation errors. Only silver proved to be problematic late in the sequence, most likely due to chemical stability/solubility problems in samples containing high and variable levels of chloride.Figure 2. Internal standard recoveries for entire 88 sample sequence. Control limits (60–125%) are indicated by red dashed lines.Table 7. Matrix spike (MS) and matrix spike duplicate (MSD) results and relative percent differences (RPD) for the sequence of 88 analyses. Spike concentrationwas 20 ppb except silver, which was 5 ppb.51 V21.4321.99 2.6%22.2021.85-1.6%21.3122.08 3.6%52 Cr20.0820.190.5%20.9519.55-6.7%20.4420.15-1.4%55 Mn5093.085097.500.1%5060.455121.08 1.2%5444.415340.90-1.9%60 Ni25.1720.08-20.2%19.0023.0721.4%20.5319.39-5.5%63 Cu19.2619.53 1.4%19.4518.73-3.7%19.2219.230.1%66 Zn21.4421.27-0.8%20.4721.73 6.1%21.0218.23-13.3%75 As25.7122.84-11.2%24.0724.080.0%24.1822.80-5.7%107 Ag 6.02 2.87-52.3% 5.758.3044.3% 5.22 6.0215.2%111 Cd17.6920.0613.4%17.4818.19 4.0%19.0018.71-1.5%121 Sb21.4222.69 5.9%21.6121.650.2%22.3821.82-2.5%205 Tl20.7920.45-1.7%20.4420.540.5%21.0820.53-2.6%208 Pb19.4019.62 1.1%19.4719.73 1.3%19.3019.27-0.2%ConclusionsFlue gas desulfurization (FGD) wastewater samples are extremely challenging due to their high and variable matrix composition and the fact that most of the required analytes can suffer from overlap from matrix-based polyatomic interferences. However, the new EPA method development and validation has demonstrated that these difficult sample matrices can be routinely analyzed for trace metal contaminants using the Agilent 7700x ICP-MS with optional ISIS-DS discrete sampling accessory.Based on extensive initial validation and strict ongoing EPA mandated quality control, the new method has been shown to be simple, robust, and reliable. Using the combined advantages of a highly robust plasma, HMI aerosol dilution, helium collision mode to eliminate interferences, and discrete sampling, this method has achieved performance comparable to that normally expected when analyzing much simpler samples such as waters and soil digests.References1. Technical Support Document for the Preliminary 2010 Effluent Guidelines Program Plan, 40 CFR Part 423.10, NoteResults presented in this document were obtained using the 7700x ICP-MS, but performance is also validated for the 7800 ICP-MS.Agilent shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance or use of this material.Information, descriptions, and specifications in this publication are subject to change without notice.© Agilent Technologies, Inc. 2015Published June 1, 2015Publication number: 5990-8114EN。

一种无源无损吸收的交错并联Buck电路

摘要：针对传统单相高压大功率 B uck 变换器中由于线路寄生参数和器件非理想特性的影响，在功率开关管两
端会产生过高电压尖峰的缺点，提出一种无源无损吸收的交错并联 B u c k 电路。详细分析了该变换器的工作原
分析工作原理前假设滤波电感电流是线性的，功率开关管处于理想状态。此处以连续导通模式下，占空比大于0 . 5 的工作状态为例，一个开关周期内变换器存在4 个工作模态。
工作模态 V , 驱动信号到来，V ,导通，此时％还未关断，二极管丫 0,和 V D 2截止。Ln 和电流上升，同时储存能量。在时刻，乂2 关断，k 达到最大值。
电力电子技术 Power Electronics
Vol.55, No.6 June 2021
继续上升，此时 v 2 驱动信号到来，v 2 导通,L 储存能量的同时电流上升。
工作模态 4(t3~f4) V , 关断，电感电流。通过 V D ,传输给负载，Ln 放电，电流下降，％仍导通，
由图 3a 可以看出，当变换器不加吸收电路
时，关断瞬间功率开关管承受一个极大的电压尖峰，达到 667.4 V ,在实际工作中极有可能损坏开关管，因此在设计过程中必须考虑增加吸收电路。
S G 3 5 2 5 输出的驱动信号经过延时模块后，占空比相等，与原驱动信号交错 180°，如图 3b 所示。图 3c 为其中一个 M 0 S F E T 漏源电压与驱动信号

Richtek RT4801A 双输出LCD偏置电源说明书

RT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 2015Dual Output LCD Bias for Smartphones and TabletsGeneral DescriptionThe RT4801A is a highly integrated Boost and LDO and inverting charge pump to generate positive and negative output voltage. The output voltages can be adjusted from ±4V to ±6V with 100mV steps by I 2C interface protocols. With its input voltage range of 2.5V to 5.5V, RT4801A is optimized for products powered by single-cell batteries and symmetrical output currents up to 80mA. The RT4801A is available in the WL-CSP -15B 1.31x2.07 (BSC) package.Ordering Information50 : 5V 60 : 6V±±Note :Richtek products are :④ RoHScompliant and compatible with the currentrequirements of IPC/JEDEC J-STD-020.④ Suitable for use in SnPb or Pb-free soldering processes.Features● 2.5V to 5.5V Supply Voltage Range● Up to 90% Efficiency with Small Magnetics ● Support Up to 80mA Output Current ● Low 1μA Shutdown Current ● Internal Soft-start Function● Short Circuit Protection Function ● Over-Voltage Protection Function ● Over-Current Protection Function● Over-Temperature Protection Function●Elastic Positive and Negative Voltage On/Off Control by ENP/ENN● Voltage Output from 4V to 6V per 0.1V● Low Input Noise and EMI●Output with Programmable Fast Discharge when IC Shutdown●Adjustable Output Voltage by I 2C Compatible Interface●Available in the 15-Ball WL-CSP PackageApplications● TFT-LCD Smartphones● TFT-LCD Tablets●General Dual Power Supply ApplicationsSimplified Application CircuitOP ONRT4801APin Configurations(TOP VIEW)VIN PGNDCF1BST VOPLXP VONGNDBSTENN CF2PGND ENPSCLSDAC1C2C3D3D1E1E2E3D2A1A2A3B3B1B2WL-SP-15B 1.31x2.07 (BSC)Marking Information3B : Product Code W : Date Code.Functional Pin DescriptionRT4801AFunction Block DiagramVOPCF2GNDVONCF1OperationThe RT4801A is a highly integrated Boost, LDO and inverting charge pump to generate positive and negative output voltages for LCD panel bias or consumer products. It can support input voltage range from 2.5V to 5.5V and the output current up to 80mA. Both positive and negative voltages can be programmed by a MCU through the dedicated I 2C interface. The RT4801A provides Over-Temperature Protection (OTP) and Short Circuit Protection (SCP) mechanisms to prevent the device from damage with abnormal operations. When the EN voltage is logic low for more than 375μs, the IC will be shut down with low input supply current less than 1μA.RT4801AAbsolute Maximum Ratings (Note 1)•Supply Input Voltage V IN Pin --------------------------------------------------------------------------------------- -0.3V to 6V●Output Voltage VOP Pins -------------------------------------------------------------------------------------------- -0.3V to 7V●Output Voltage VON Pins ------------------------------------------------------------------------------------------- -7V to 0.3V●Others Pin to GND ---------------------------------------------------------------------------------------------------- -0.3V to 6V●Power Dissipation, P D @ T A = 25°CWL-CSP-15B 1.31x2.07 (BSC) ----------------------------------------------------------------------------------- 2W●Package Thermal Resistance (Note 2)WL-CSP-15B 1.31x2.07 (BSC), θJA----------------------------------------------------------------------------- 49.8°C/W●Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260︒C●Junction Temperature ----------------------------------------------------------------------------------------------- 150︒C●Storage Temperature Range -------------------------------------------------------------------------------------- -65︒C to 150︒C ●ESD Susceptibility (Note 3)HBM (Human Body Model) ---------------------------------------------------------------------------------------- 2kVMM (Machine Model) ----------------------------------------------------------------------------------------------- 200V Recommended Operating Conditions (Note 4)●Supply Input Voltage ------------------------------------------------------------------------------------------------- 2.5V to 5.5V●Ambient Temperature Range--------------------------------------------------------------------------------------- -40︒C to 85︒C ●Junction Temperature Range -------------------------------------------------------------------------------------- -40︒C to 125︒C Electrical Characteristics(V IN = 3.7V, C IN= C OP = C F1 = 4.7μF, C BST = C ON = 10μF, L1 = 2.2μH, T A = 25°C, unless otherwise specified.)Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 2015RT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These arestress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at T A = 25︒C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. Note 3. Devices are ESD sensitive. Handling precaution recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. T OTP , T OTP_HYST are guaranteed by design.RT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 2015Typical Application CircuitL1V OPV ONTable 1. Component List of Evaluation BoardRT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.I 2C InterfaceSDASCL VV V VRT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 2015I 2C CommandSlave AddressWrite Command(a) Write single byte of data to Register11111Slave ACK Slave AddressRegister AddressR7R6R3R5R4R2R1R0Slave ACKData From MasterStartSlave ACK StopD7D6D5D4D3D2D1D0(b) Write multiple bytes of data to Registers111110Slave ACK Slave AddressRegister Address n thSlave ACK n th Data From MasterStartD7D6D5D4D3D2D1D0SlaveACKSlave ACKStop(n + 1)th Data From MasterLast Data From MasterR7R6R3R5R4R2R1R0D7D6D5D4D3D2D1D0Slave ACK D7D6D5D4D3D2D1D0Read Command(a) Read single byte of data from Register111110Slave ACK Slave AddressRegister Address111111Slave ACK Slave AddressData From MasterRe-startStartSlaveACKD7D6D5D4D3D2D1D0Master NACKStop D7D6D5D4D3D2D1D0(b) Read multiple bytes of data from Registers11111Slave ACK 0111111Slave ACK Slave Addressn th Data From MasterMaster ACKRe-startStart Slave AddressRegister AddressMaster NACKStopLast Data From MasterD7D6D5D4D3D2D1D0Slave ACKD7D6D5D4D3D2D1D0D7D6D5D4D3D2D1D0Start : Start command R7 to R0 : Register Address. VOP : Register address = 0X00h VON : Register address = 0X01h DISP : Register address = 0x03h DISN : Register address = 0x03hR/W : Read active (R/W = H) or Write active (R/W = L)ACK : Acknowledge = L activeD7 to D0 : Write data when WRITE command or read data when READ command Stop : Stop commandRT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.Registers MapTable 3. VON Voltage SelectionCopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201511The Reserved bits are ignored when written and return either 0 or 1 when read.The Reserved bits are ignored when written and return either 0 or 1 when read.Factory Default Register ValueRT4801A-50WSC default VOP/VON DATA is 0Ah/0Ah. RT4801A-60WSC default VOPN/VON DATA is 14h/14h.Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS4801A-00 December 201512Typical Operating CharacteristicsEfficiency vs. Output Current010203040506070809010000.020.040.060.08Output Current (A)E f f i c i e n c y (%)V OP vs. Output Current4.974.984.995.005.015.020.010.020.030.040.050.060.070.08Output Current (A)V O P(V )V ON vs. Output Current-5.02-5.01-5.00-4.99-4.98-4.970.010.020.030.040.050.060.070.08Output Current (A)V O N (V )V OP vs. Input Voltage4.974.984.995.005.015.02V O P (V )V ON vs. Input Voltage-5.02-5.01-5.00-4.99-4.98-4.972.533.544.555.5Input Voltage (V)V O N (V )0.000.020.040.060.080.100.120.140.160.180.20-40-2020406080100Temperature (°C)S h u t d o w n C u r r e n t (μA )Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201513Quiescent Current vs. Temperature0.40.50.60.70.80.91.01.11.2-40-2020406080100Temperature (°C)Q u i e s c e n t C u r r e n t (m A )Input Voltage vs. Temperature2.102.122.142.162.182.202.222.242.262.282.30-40-2020406080100Temperature (°C)I n p u t V o l t a g e (V )V IN = 3.7V, V OP = 5V, I OP = 0mA V OP (10mV/Div)Time (1ms/Div)V OP Ripple Voltage V OP(10mV/Div)Time (1ms/Div)V OP Ripple VoltageV IN = 3.7V, V OP = 5V, I OP = 20mAV OP(10mV/Div)Time (1ms/Div)V OP Ripple Voltage V IN = 3.7V, V OP = 5V, I OP = 40mA V OP (10mV/Div)Time (1ms/Div)V OP Ripple VoltageV IN = 3.7V, V OP = 5V, I OP = 80mACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS4801A-00 December 201514V ON (20mV/Div)Time (1ms/Div)V ON Ripple VoltageV IN = 3.7V, V ON = 5V, I ON = 0mA V ON (20mV/Div)Time (10μs/Div)V ON Ripple VoltageV IN = 3.7V, V ON = 5V, I ON = 20mAV ON (20mV/Div)Time (10μs/Div)V ON Ripple Voltage V IN = 3.7V, V ON = 5V, I ON = 40mA V ON (20mV/Div)Time (10μs/Div)V ON Ripple VoltageV IN = 3.7V, V ON = 5V, I ON = 80mAV IN = 2.9V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 5m to 35mAV OP (50mV/Div)V ON (50mV/Div)I OP(20mA/Div)Time (100μs/Div)Load TransientV IN = 2.9V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 10m to 70mAV OP (50mV/Div)V ON (50mV/Div)I OP(50mA/Div)Time (100μs/Div)Load TransientCopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201515V IN = 3.7V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 5m to 35mAV OP (50mV/Div)V ON (50mV/Div)I OP(20mA/Div)Time (100μs/Div)Load TransientV IN = 3.7V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 10m to 70mAV OP (50mV/Div)V ON (50mV/Div)I OP(50mA/Div)Time (100μs/Div)Load TransientV IN = 4.5V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 5m to 35mAV OP (50mV/Div)V ON (50mV/Div)I OP(20mA/Div)Time (100μs/Div)Load TransientV IN = 4.5V, V OP = 5V, V ON = -5V, T R = T F = 10μs, I OPN = 10m to 70mAV OP (50mV/Div)V ON (50mV/Div)I OP(50mA/Div)Time (100μs/Div)Load TransientV IN = 2.9V to 3.4V, V OP = 5V,V ON = -5V, I OPN = 5mAV IN (1V/Div)V OP (50mV/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INV IN = 3.7V to 4.2V, V OP = 5V,V ON = -5V, I OPN = 5mAV OP (50mV/Div)V IN (1V/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INCopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS4801A-00 December 201516V IN = 2.9V to 3.4V, V OP = 5V,V ON = -5V, I OPN = 40mAV OP (50mV/Div)V IN (1V/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INV IN = 3.7V to 4.2V, V OP = 5V,V ON = -5V, I OPN = 40mAV OP (50mV/Div)V IN (1V/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INV IN = 2.9V to 3.4V, V OP = 5V,V ON = -5V, I OPN = 80mAV OP (50mV/Div)V IN (1V/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INV IN = 3.7V to 4.2V, V OP = 5V,V ON = -5V, I OPN = 80mAV OP (50mV/Div)V IN (1V/Div)V ON (50mV/Div)Time (500μs/Div)Line TransientV INV IN = 3.7V, V OP = 5V, V ON = -5V, No Load, ENP/ENN On simultaneouslyENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OnV OP V ONV IN = 3.7V, V OP = 5V, V ON = -5V, No Load, ENP/ENN Off simultaneouslyENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OffV OPV ONCopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201517V IN = 3.7V, V OP = 5V, V ON = -5V,No Load, ENP prior ENN OnENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OnV OP V ONV IN = 3.7V, V OP = 5V, V ON = -5V,No Load, ENP prior ENN OffENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OffV OP V ONV IN = 3.7V, V OP = 5V, V ON = -5V,No Load, ENN prior ENP OnENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OnV OPV ONV IN = 3.7V, V OP = 5V, V ON = -5V,No Load, ENN prior ENP OffENP (5V/Div)ENN (5V/Div)(5V/Div)I IN(200mA/Div)Time (1ms/Div)Power OffV OPV ONCopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS4801A-00 December 201518Application InformationThe RT4801A is a highly integrated Boost, LDO and inverting charge pump to generate positive and negative output voltages for LCD panel bias or consumer products. It can support input voltage range from 2.5V to 5.5V and the output current up to 80mA. The V OP positive output voltage is generated from the LDO supplied from a synchronous Boost converter, and V OP is set at a typical value of 6V. The Boost converter output also drives an inverting charge pump controller to generate V ON negative output voltage which is set at a typical value of -6V. Both positive and negative voltages can be programmed by a MCU through the dedicated I 2C interface and the available voltage range is from ±4V to ±6V with 100mV per step. Input Capacitor SelectionInput ceramic capacitor with 4.7μF capacitance is suggested for applications. For better voltage filtering, select ceramic capacitors with low ESR, X5R and X7R types are suitable because of their wider voltage and temperature ranges. Boost Inductor SelectionThe inductance depends on the maximum input current. As a general rule, the inductor ripple current range is 20% to 40% of the maximum input current. If 40% is selected as an example, the inductor ripple current can be calculated according to the following equations :OUT OUT(MAX)IN(MAX)IN RIPPLE IN(MAX)V I I =V I = 0.4I η⨯⨯⨯w here η is the efficiency of the VOP Boost converter, I IN(MAX) is the maximum input current, and ∆I L is the inductor ripple current. The input peak current can then be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : I PEAK = 1.2 x I IN(MAX)Note that the saturated current of the inductor must be greater than I PEAK .The inductance can eventually be determined according to the following equation :()()()22IN OUT IN OUT OUT(MAX)OSCηV V V L 0.4V I f ⨯⨯-=⨯⨯⨯where f OSC is the switching frequency. For better system performance, a shielded inductor is preferred to avoid EMI problems.Boost Output Capacitor SelectionThe output ripple voltage is an important index for estimating IC performance. This portion consists of two parts. One is the product of ripple current with the ESR of the output capacitor, while the other part is formed by the charging and discharging process of the output capacitor. As shown in Figure 1, ∆V OUT1 can be evaluated based on the ideal energy equalization. According to the definition of Q, the ∆V OUT1 value can be calculated as the following equation :OUT OUT OUT1SOC OUT OUT1SOC OUT1Q = I D = CV f I DV =f C ⨯⨯⨯∆⨯∆⨯where f OSC is the switching frequency and D is the duty cycle.Finally, taking ESR into consideration, the overall output ripple voltage can be determined by the following equation :OUT OUT ESR OUT1SER OSC OUTI DV = V + V = V + f C ⨯∆∆∆∆⨯where ∆V ESR = I Crms x R CESRThe output capacitor, C OUT , should be selected accordingly.Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201519Figure 1. The Output Ripple Voltage without theContribution of ESRUnder Voltage LockoutTo prevent abnormal operation of the IC in low voltage condition, an under voltage lockout is included which shuts down IC operation when input voltage is lower than the specified threshold voltage. Soft-StartThe RT4801A employs an internal soft-start feature to avoid high inrush current during start-up. The soft-start function is achieved by clamping the output voltage of the internal error amplifier with another voltage source that is increased slowly from zero to near VIN during the soft-start period. Output Voltage SettingThe output voltage can be programmed by a MCU through the dedicated I 2C interface according to the V OP /V ON Voltage Selection Table. Shutdown Delay and DischargeWhen the EN signal is logic low for more than 375μs, the IC function will be shut down. The output V OP /V ON can be actively discharged to GND via discharge selection bit enabled. In shutdown mode, the input supply current for the IC is less than 1μA.Over Current ProtectionThe RT4801A includes a cycle-by-cycle current limit function which monitors the inductor current during each ON period. The power switch will be forced off to avoid large current damage once the current is over the limit level.Short Circuit ProtectionThe RT4801A has an advanced output short-circuit protection mechanism which prevents the IC from damage by unexpected applications. When the output becomes shorted to ground, and the output voltage is under the limit level with 1ms (typ.) duration, the LCD bias function enters shutdown mode and can only re-start normal operation after triggering the ENP/ENN pin.Over Temperature ProtectionThe RT4801A equips an over temperature protection circuitry to prevent overheating due to excessive power dissipation. The OTP will shut down LCD bias operation when ambient temperature exceeds 140°C. Once the ambient temperature cools down by approximately 15°C, IC will automatically resume normal operation. To maintain continuous operation, the maximum junction temperature should be prevented from rising above 125°C.Thermal ConsiderationsFor continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) - T A ) / θJAwhere T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θJA is the junction to ambient thermal resistance.For recommended operating condition specifications, the maximum junction temperature is 125︒C. The junction to ambient thermal resistance, θJA , is layout dependent. For WL-CSP-15B 1.31x2.07 (BSC) package, the thermal resistance, θJA , is 49.8︒C/W on a standard JEDEC 51-7 four-layer thermal test board.Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. DS4801A-00 December 201520The maximum power dissipation at T A = 25︒C can be calculated by the following formula :P D(MAX) = (125︒C - 25︒C) / (49.8︒C/W) = 2W for WL-CSP-15B 1.31x2.07 (BSC) packageThe maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA . The derating curve in Figure 2 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.Figure 2. Derating Curve of Maximum PowerDissipationLayout ConsiderationsFor the best performance of RT4801A, the followingPCB layout guidelines should be strictly followed. ④ For good regulation, place the power components asclose to the IC as possible. The traces should be wide and short especially for the high current output loop.④ Theinput and output bypass capacitor should beplaced as close to the IC as possible and connected to the ground plane of the PCB.④ The flying capacitor should be placed as close to theCF1/CF2 pin as possible to avoid noise injection.④ Minimizethe size of the LXP node and keep thetraces wide and short. Care should be taken to avoid running traces that carry any noise-sensitive signals near LXP or high-current traces.④ Separate power ground (PGND) and analog ground(GND). Connect the GND and the PGND islands at a single end. Make sure that there are no other connections between these separate ground planes.Figure 3. PCB Layout Guide0.00.40.81.21.62.02.4255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )RT4801ACopyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.DS4801A-00 December 201521Outline DimensionWL-CSP-15B 1.31x2.07 (BSC)Richtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.。

(重点)Emulated Current Mode Control for Buck Regulators Using Sample and Hold Technique

LM3495Emulated Current Mode Control for Buck Regulators Using Sample and Hold TechniqueLiterature Number: SNVA537EMULATED CURRENT MODE CONTROL FOR BUCK REGULATORS USING SAMPLE AND HOLD TECHNIQUE Small Signal Linear Analysis and Comparison to Peak and ValleyMethodsbyRobert SheehanPrincipal Applications EngineerNational Semiconductor CorporationSanta Clara, CAPES02Tuesday, October 24, 20068:30am – 9:30amPower Electronics Technology Exhibition and ConferenceOctober 24-26, 2006Long Beach Convention CenterLong Beach, CAEMULATED CURRENT MODE CONTROL FOR BUCK REGULATORS USINGSAMPLE AND HOLD TECHNIQUESmall Signal Linear Analysis and Comparison to Peak and Valley MethodsbyRobert SheehanPrincipal Applications EngineerNational Semiconductor CorporationSanta Clara, CAAbstract – While naturally sampled peak and valley current mode control methods have been widely used, other control architectures are possible using gated sampling techniques. Theory for an emulated peak current mode control method using a gated sample and hold of the valley current is developed. This gated sampling technique removes the duty cycle dependence of the slope compensating ramp, stabilizing the modulator gain over changes in line voltage. A general solution for current mode buck regulator small signal linear equations is presented. This allows the modulator gain for any control method to be introduced into the equations, including peak, valley, average and gated sampling methods. Comparison to peak and valley is made using switching, linear and LaPlace spice models. Sub-harmonic stability bounds are demonstrated using graphical spreadsheet calculators. Theory is verified with frequency response measurements of an actual circuit.Figure 1: Naturally sampled peak or valley current mode buck regulator.Figure 2: Emulated peak current mode buck regulator using valley sample and hold.1. IntroductionThere are a lot of misconceptions and misinformation about current mode control in the industry. Papers that have been written at the graduate or PhD level are hard to understand. Concepts are difficult to put into practical use. Basically, an ideal current mode converter is only dependent on the dc or average inductor current. The inner current loop turns the inductor into a voltage controlled current source, effectively removing the inductor from the outer voltage control loop at dc and low frequencies. The current loop gain splits the complex conjugate pole of the output filter into two real poles, so that the characteristic of the output filter is set by the capacitor and load resistor. Only when the impedance of the output inductor equals the current loop gain does the inductor pole reappear at higher frequencies.Whether the current mode converter is peak, valley, average, or sample and hold is secondary to the operation of the current loop. As long as the dc current is sampled, current mode operation is maintained. The modulator gain is dependent on the effective slope of the ramp presented to the modulating comparator input. Each operating mode will have a unique characteristic equation for the modulator gain. The requirement for slope compensation is dependent on the relationship of the average current to the value of current at the time when the sample is taken.To understand the theory and follow the derivations presented in this paper, a good working knowledge of the references is needed. For the practical designer, simplified transfer functions along with tabulated general gain parameters provide the basic tools for design analysis.The primary application for emulated current mode is high input voltage to low output voltage operating at a narrow duty cycle. In any practical design, device capacitance may cause a significant leading edge spike on the current sense waveform. By sampling the inductor current at the end of the switching cycle and adding an external ramp, the minimum on time can be significantly reduced, without the need for blanking or filtering which is normally required for peak current mode control.2. Linear ModelingFigure 3: Buck regulator linear models.Averaged ModelReference [1] has been one of the most popular papers covering current mode control. The analysis presented here refers the inductor current to the control voltage as the basis for writing the transfer functions.Starting with , write the transfer function in terms of voltages: O vˆLO OSW O Z Z Z v ˆvˆ+⋅= (1)d ˆV D v ˆv ˆIN IN SW ⋅+⋅= (2))K v ˆK v ˆR i ˆv ˆ(F d ˆO O I IN i L C m⋅+⋅−⋅−⋅= (3)OO L Z v ˆi ˆ= (4)Combining equations 1 through 4 yields:L O O O O I IN O i O C m IN IN O Z Z Z K v ˆK v ˆZ R v ˆv ˆF V D v ˆv ˆ+⋅⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛⋅+⋅−⋅−⋅⋅+⋅= (5)Define K mp as:m IN mp F V K ⋅= (6)Setting to zero allows the control to output gain to be found: IN vˆ)Z K R (K Z Z Z K v ˆvˆO O i mp L O O mp C O ⋅−⋅++⋅=(7)Setting to zero allows the line to output gain to be found: C vˆ)Z K R (K Z Z Z )K K D (v ˆvˆO O i mp L O O I mp IN O ⋅−⋅++⋅⋅−=(8)Define Z O and Z L :)R R (C s 1)R C s 1(R R ||R C s 1Z C O O C O O O C O O +⋅⋅+⋅⋅+⋅=⎟⎟⎠⎞⎜⎜⎝⎛+⋅= (9)S L L R R L s Z ++⋅=(10)Equations 7 and 8 can be plotted without further analysis using MATHCAD, SPICE or other application. Define terms for: K mp Modulator gain coefficient K I Line to modulator gain block K O Output to modulator gain block R i Current sense amplifier gain = G I · R SDC Transfer FunctionsControl to OutputLet Z O =R O , Z L =R L +R S . From equation 7:)R K R (K R R R R K )dc (v ˆvˆO O i mp S L O O mp C O ⋅−⋅+++⋅=(11)By factoring this becomes:imp O mp O i mp SL iO C O R K K K 1R R K R R 11R R )dc (v ˆv ˆ⋅⋅−⋅+⋅++⋅= (12)Define K m as the modulator gain where:Ompm K K 11K −=(13)This allows the control to output gain to be expressed as:im O i mp S L iO C O R K R R K R R 11R R )dc (v ˆv ˆ⋅+⋅++⋅= (14)If R O >>R L +R S the simplified expression is:im O iO C O R K R 11R R )dc (v ˆv ˆ⋅+⋅≈(15)Line to OutputIn similar fashion:)R K R (K R R R R )K K D ()dc (v ˆvˆO O i mp S L O O I mp IN O ⋅−⋅+++⋅⋅−=(16)By factoring this becomes:imp O mp O i mp SL Imp iO IN O R K K K 1R R K R R 1DK K 1R DR )dc (v ˆv ˆ⋅⋅−⋅+⋅++−⋅⋅= (17)Define K n as the audio susceptibility coefficient:DK K 1K I mp n −=(18)This allows the line to output gain to be expressed as:im O i mp S L niO IN O R K R R K R R 1K R D R )dc (v ˆv ˆ⋅+⋅++⋅⋅= (19)If R O >>R L +R S the simplified expression is:im O niO IN O R K R 1K R D R )dc (v ˆv ˆ⋅+⋅⋅≈ (20)Continuous-Time ModelReferences [2] and [3] cover this model. The sampling gain is incorporated into the current loop as H e (s). Derivation of the gain blocks for the on voltage and off voltage requires differentiation of the inductor current with respect to each voltage. Here, a straightforward algebraic method is used to relate the continuous-time model to the averaged model. This provides a simple means to derive the equations for different control modes.Starting with , write the transfer function in terms of voltages: dˆ)K vˆK v ˆ)s (H R i ˆv ˆ(F d ˆr OFF f ON e i L C m ′⋅+′⋅+⋅⋅−⋅′= (21)Combining with equations 1, 2 and 4 for the power stage yields:L O O r OFF f ON O e i O C m IN IN O Z Z Z K v ˆK v ˆZ )s (H R v ˆv ˆF V D v ˆv ˆ+⋅⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛′⋅+′⋅+⋅⋅−⋅′⋅+⋅= (22)Define K ′mp as:m IN mp F V K ′⋅=′ (23)Let , , Z O IN ON v ˆv ˆv ˆ−=O OFF v ˆv ˆ=O =R O , Z L =0, H e (s)=1. Solve for the dc gain equation.⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛′⋅+′⋅−′⋅+⋅−⋅′+⋅≈r O f O f IN O iO C mp IN O K v ˆK v ˆK v ˆR R v ˆv ˆK D v ˆ)dc (v ˆ (24)Setting to zero allows the control to output gain to be found: IN vˆi mp rmp f mp O i O C O R K K K K K 1R 11R R )dc (v ˆv ˆ⋅′′⋅′−′⋅′+⋅+⋅≈(25)Setting to zero allows the line to output gain to be found: C vˆimp rmp f mp O fmp i OIN O R K K K K K 1R 1D K K 1R DR )dc (v ˆv ˆ⋅′′⋅′−′⋅′+⋅+′+′⋅⋅≈ (26)Define K ′m and K ′n where:rf mp m K K K 11K ′−′+′=′ D K K 1K f mp n ′+′=′ (27)Equate K m to K ′m and K n to K ′n . Solve for K ′f and K ′r .I mp mp f K K 1K 1D K −⎟⎟⎠⎞⎜⎜⎝⎛′−⋅=′ O f mpmp r K K K 1K 1K +′+−′=′ (28)Figure 4: Simplified continuous-time model using general gain parameters. This model is valid for control to output transfer functions of all operating modes. The line to output transfer function is valid at dc, but diverges from theactual response over frequency.⎟⎟⎠⎞⎜⎜⎝⎛−′⋅+=m mp i L e K 1K 1R Z )s (H )s (H (29) Where:2n 2z n e ωs Q ωs 1)s (H +⋅+= T πωn = π2Q z−= (30)Unified ModelThe unified model is presented in references [4] and [5]. This uses a single pole in series with the modulator to account for the sampling gain.Starting with , write the transfer function in terms of voltages: dˆ)K v ˆR i ˆv ˆ()s (F d ˆIN i L C m⋅−⋅−⋅= (31)Combining with equations 1, 2 and 4 for the power stage yields:L O O IN O i O C m IN IN O Z Z Z K v ˆZ Rv ˆv ˆ)s (F V D v ˆv ˆ+⋅⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛⋅−⋅−⋅⋅+⋅= (32)Define:)s (H K )s (F V p m m IN ⋅=⋅ (33)Let Z O =R O , Z L =0, H p (s)=1. Solve for the dc gain equation.⎥⎥⎦⎤⎢⎢⎣⎡⎟⎟⎠⎞⎜⎜⎝⎛⋅−⋅−⋅+⋅≈K v ˆR R v ˆv ˆK D v ˆ)dc (v ˆIN O iO C m IN O (34)Setting to zero allows the control to output gain to be found: IN vˆim O iO C O R K R 11R R )dc (v ˆv ˆ⋅+⋅≈(35)Setting to zero allows the line to output gain to be found: C vˆim O m iO IN O R K R 1DK K 1R D R )dc (v ˆv ˆ⋅+−⋅⋅≈ (36)Comparing this to the averaged and continuous-time models:D KK 1K m n −= Therefore: ⎟⎟⎠⎞⎜⎜⎝⎛−⋅=n m K K 1D K (37)Figure 5: Unified model uses the high frequency asymptote for a single pole in series with the modulator. This accurately models the current loop and control to output transfer functions, but is limited to PCM1, VCM1 andVCM3 operating modes.Hpp ωs 11)s (H +=Where:Qωωn Hp = (38)Algebraic manipulation of the closed loop continuous-time expression for H(s) to find a general open loop expression for H p (s) would appear to be straightforward. For peak or valley current mode with a fixed slopecompensating ramp, ⎟⎟⎠⎞⎜⎜⎝⎛−′⋅−≅⋅m mpi L z n K 1K 1R Z Q ωs . H(s) reduces to 2n 2ωs 1+, which leads to the simplification of a single pole for H p (s). This is not the case for other operating modes. Further work is needed to develop a general expression for H p (s). Though the unified model shows the potential to accurately model the line to output transfer function, this has not been validated. Comparisons of line to output bode plots from the linear model to SPICE results from the switched model do not match over frequency.Simplified Transfer FunctionsThe simplified transfer functions assume poles that are well separated by the current loop gain. Expressions for the averaged model do not show the additional phase shift due to the sampling effect. The control to output gain of the continuous-time model accurately represents the circuit’s behavior to half the switching frequency. The line to output expressions for audio susceptibility are accurate at dc, but diverge from the actual response over frequency.Averaged Model:⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅+⋅≈L P Z i m O i O C O ωs 1ωs 1ωs 1R K R 11R R v ˆv ˆ (39) ⎟⎟⎠⎞⎜⎜⎝⎛+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅+⋅⋅≈L P Zim OniO IN O ωs 1ωs 1ωs 1R K R 1K R DR v ˆv ˆ (40)Continuous-Time Model:⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅+⋅≈2n 2n P Zim OiO C O ωs Qωs 1ωs 1ωs 1R K R 11R R v ˆvˆ(41)⎟⎟⎠⎞⎜⎜⎝⎛+⋅+⋅⎟⎟⎠⎞⎜⎜⎝⎛++⋅⋅+⋅⋅≈2n 2n P Z i m O ni O IN O ωs Q ωs 1ωs 1ωs 1R K R 1K R D R vˆv ˆ (42)Where: CO Z R C 1ω⋅=⎟⎟⎠⎞⎜⎜⎝⎛⋅+⋅≈i m O O P R K 1R1C 1ω LR K ωimp L ⋅≈Tπωn =(43)Figure 6: SIMPLIS SPICE schematic - emulated peak current mode synchronous buck.Figure 7: SIMPLIS SPICE results of control to output gain.Figure 8: SIMPLIS SPICE results of line to output gain.Figure 9: SIMPLIS SPICE results of current loop gain.TABLE 5Calculated General Gain ParametersV IN=10 V O=5 D=0.5R O=1 R i=0.1 T=5μ L=5μMODE V SLOPE K SL V SL K m K n m c QPCM1 V SL0.10 0.5020.00 0.025 2.000 0.637PCM2 V O·K SL0.10 --- 10.00 0.025 2.000 0.637VCM1 V SL0.10 0.5020.00 0.075 2.000 0.637VCM2 (V IN-V O)·K SL0.10 --- 10.00 0.175 2.000 0.637EPCM1 V SL0.10 1.0010.00 0.125 1.000 0.637EPCM2 V IN·K SL0.10 --- 10.00 0.025 1.000 0.637EVCM1 V SL0.10 1.0010.00 0.075 1.000 0.637EVCM2 V IN·K SL0.10 --- 10.00 0.175 1.000 0.637VCM3 V IN·K SL0.10 --- 10.00 0.225 3.000 0.318EPCM3 (V IN-V O)·K SL +V SL0.10 0.5020.00 0.025 1.000 0.637EPCM4 V IN·K SL +V SL0.05 0.5010.00 0.075 1.000 0.637PCM2 0.5·V O·K SL0.10 --- 20.00 0.000 1.250 2.546VCM2 0.5·(V IN-V O)·K SL0.10 --- 20.00 0.100 1.250 2.546Table Notation:PCM – Peak Current Mode VCM – Valley Current ModeEPCM – Emulated Peak Current Mode EVCM – Emulated Valley Current Mode1 – Fixed slope compensation V SL2 – Optimal slope compensation proportional to K SL3, 4 – Other fixed or proportional slope compensation implementationsIn the last section of Table 5 for PCM2, peak current mode with a slope compensating ramp equal to one half the down slope of the inductor current represents a special case. K n=0 which corresponds to infinite line rejection. This is difficult to achieve due to finite resistance and parasitic elements in a practical circuit. This is not optimal since sub-harmonic oscillation is possible at D>0.5 with feedback control. See section 4 on general slope compensation requirements.TABLE 6Calculated Values and Measured PSPICE Switching Circuit DataR O=1 R i=0.1 T=5μ L=5μV IN=6 V O=5 D=0.83MeasuredCalculatedMODE V SLOPE K SL V SL V O/V C V O/V IN V O/V C V O/V IN PCM1 V SL0.10 0.50 6.67 0.231 6.66 0.240 PCM2 V O·K SL0.10 --- 4.29 0.149 4.25 0.154 VCM1 V SL0.10 0.10 6.67 0.324 6.55 0.325 VCM2 (V IN-V O)·K SL0.10 --- 6.00 0.392 5.98 0.383 EPCM1 V SL0.10 0.60 4.29 0.506 4.24 0.502 EPCM2 V IN·K SL0.10 --- 4.29 0.149 4.25 0.148 EVCM1 V SL0.10 0.60 6.00 0.292 6.00 0.300 EVCM2 V IN·K SL0.10 --- 6.00 0.392 5.96 0.388 VCM3 V IN·K SL0.10 --- 4.29 0.577 4.23 0.571 EPCM3 (V IN-V O)·K SL +V SL0.10 0.50 6.67 0.231 6.61 0.231 EPCM4 V IN·K SL +V SL0.05 0.50 3.75 0.391 3.71 0.389TABLE 7Calculated Values and Measured PSPICE Switching Circuit DataV IN=10 V O=5 D=0.5R O=1 R i=0.1 T=5μ L=5μMeasuredCalculatedMODE V SLOPE K SL V SL V O/V C V O/V IN V O/V C V O/V INPCM1 V SL0.10 0.50 6.67 0.083 6.65 0.088 PCM2 V O·K SL0.10 --- 5.00 0.063 5.00 0.065 VCM1 V SL0.10 0.50 6.67 0.250 6.57 0.249 VCM2 (V IN-V O)·K SL0.10 --- 5.00 0.438 4.97 0.427 EPCM1 V SL0.10 1.00 5.00 0.313 5.00 0.313 EPCM2 V IN·K SL0.10 --- 5.00 0.063 5.00 0.063 EVCM1 V SL0.10 1.00 5.00 0.188 4.99 0.189 EVCM2 V IN·K SL0.10 --- 5.00 0.438 4.99 0.430 VCM3 V IN·K SL0.10 --- 5.00 0.563 4.98 0.550 EPCM3 (V IN-V O)·K SL +V SL0.10 0.50 6.67 0.083 6.56 0.085 EPCM4 V IN·K SL +V SL0.05 0.50 5.00 0.188 5.00 0.188TABLE 8Calculated Values and Measured PSPICE Switching Circuit DataV IN=50 V O=5 D=0.1R O=1 R i=0.1 T=5μ L=5μMeasuredCalculatedMODE V SLOPE K SL V SL V O/V C V O/V IN V O/V C V O/V INPCM1 V SL0.10 0.50 6.67 0.003 6.56 0.009 PCM2 V O·K SL0.10 --- 6.25 0.003 6.17 0.009 VCM1 V SL0.10 4.50 6.67 0.063 6.52 0.063 VCM2 (V IN-V O)·K SL0.10 --- 4.17 0.415 4.16 0.407 EPCM1 V SL0.10 5.00 6.25 0.066 6.19 0.066 EPCM2 V IN·K SL0.10 --- 6.25 0.003 6.14 0.005 EVCM1 V SL0.10 5.00 4.17 0.040 4.15 0.041 EVCM2 V IN·K SL0.10 --- 4.17 0.415 4.16 0.412 VCM3 V IN·K SL0.10 --- 6.25 0.628 6.21 0.618 EPCM3 (V IN-V O)·K SL +V SL0.10 0.50 6.67 0.003 6.53 0.005 EPCM4 V IN·K SL +V SL0.05 0.50 8.33 0.013 8.09 0.014EMULATED CURRENT MODE CONTROL FOR BUCK REGULATORS by Robert SheehanFigure 10: SIMPLIS SPICE results for EPCM2 with varying Q.3. Discrete Time Analysis for Slope Compensation(a) Peak current mode(b) Valley current modeFigure 11: Slope compensation for peak and valley current mode buck.Peak Current Mode Trailing Edge ModulationFor peak current mode control, the peak current must be accounted for in its relationship to the average current. By perturbing the duty cycle, we can see the effect on V C .Write the equation for the voltage at V C :C SLOPE i O IN i L v d V R LTd )v v (5.0R i =⋅+⋅⋅⋅−⋅+⋅ (44)V IN , V O , and V SLOPE are considered to be fixed with respect to the period T. The duty cycle is perturbed, whichshows the effect on the control voltage with respect to the inductor current. The quantity , and . )T (i ˆI LL=Δ)T (d ˆD =Δ)T (vˆV C C =ΔC SLOPE i O IN i L V D V R LTD )V V (5.0R I Δ=Δ⋅+⋅⋅Δ⋅−⋅+⋅Δ (45)To maintain constant average inductor current, the control voltage must change by ½ the ripple current times the current sense gain:i PK C R I 5.0V ⋅Δ⋅−=Δ (46)LTD V L T )D 1(V I O O PK ⋅Δ⋅−=⋅Δ−⋅=Δ (47)Combine equations and solve for ∆D/∆I L :INSLOPE i INi L V V LT R )D 5.0(1V R I D +⋅⋅−⋅−=ΔΔ (48)The term INSLOPE i V V LTR )D 5.0(1+⋅⋅− is equivalent to the peak current mode modulator gain K m with fixedV SLOPE .By factoring, this becomes:⎥⎥⎦⎤⎢⎢⎣⎡−−⋅⎟⎟⎠⎞⎜⎜⎝⎛⋅−+⋅⋅−=ΔΔ5.0)D 1(L /R )V V (T/V 1L T 1V 1I Di O IN SLOPE IN L (49)This can be expressed as:)5.0D m (LT1V 1I D c IN L −′⋅⋅⋅−=ΔΔ (50) Where:D 1D −=′n e c S S1m += Slope compensating ramp: T /V S SLOPE e =Positive current sense ramp:L /R )V V (S i O IN n ⋅−=Reviewing the equation for ∆D/∆I L , when D>0.5, the T/L term goes negative. V SLOPE must be large enough to compensate, or this will manifest itself in the time domain as a sub-harmonic oscillation of the current loop. If the condition is set such that:iIN SLOPE R V VL T D ⋅=⋅ (51)Then m C ·D ′ = 1, so the current loop will be stable for any duty cycle. To meet this condition, solve for V SLOPE :LTR V V i O SLOPE ⋅⋅= (52)Figure 12: Peak current mode sub-harmonic oscillation. For D<0.5, sub-harmonic oscillation is damped. For D>0.5,sub-harmonic oscillation builds with insufficient slope compensation.Valley Current Mode Leading Edge ModulationFor valley current mode control, the valley current must be accounted for in its relationship to the average current. By perturbing the duty cycle, we can see the effect on V C .Write the equation for the voltage at V C :C SLOPE i O i L v )d 1(V R LT)d 1(v 5.0R i =−⋅−⋅⋅−⋅⋅−⋅ (53)V IN , V O , and V SLOPE are considered to be fixed with respect to the period T. The duty cycle is perturbed, whichshows the effect on the control voltage with respect to the inductor current. The quantity , and . )T (i ˆI LL=Δ)T (d ˆD =Δ)T (vˆV C C =ΔC SLOPE i O i L VD V R LTD V 5.0R I Δ=Δ⋅+⋅⋅Δ⋅⋅+⋅Δ (54)To maintain constant average inductor current, the control voltage must change by ½ the ripple current:i PK C R I 5.0V ⋅Δ⋅=Δ(55)LTD )V V (I O IN PK ⋅Δ⋅−=Δ(56)Combine equations and solve for ∆D/∆I L :INSLOPE i INi L V V LT R )5.0D (1V R I D +⋅⋅−⋅−=ΔΔ (57)The term INSLOPE i V V LTR )5.0D (1+⋅⋅− is equivalent to the valley current mode modulator gain K m with fixedV SLOPE .By factoring, this becomes:⎥⎥⎦⎤⎢⎢⎣⎡−⋅⎟⎟⎠⎞⎜⎜⎝⎛⋅+⋅⋅−=ΔΔ5.0D L /R V T /V 1L T 1V 1I Di O SLOPE IN L (58)This can be expressed as:)5.0D m (LT1V 1I D c IN L −⋅⋅⋅−=ΔΔ (59) Where: ne c S S1m +=Slope compensating ramp:T /V S SLOPE e =Negative current sense ramp: L /R V S i O n ⋅=Reviewing the equation for ∆D/∆I L , when D<0.5, the T/L term goes negative. V SLOPE must be large enough to compensate, or this will manifest itself in the time domain as a sub-harmonic oscillation of the current loop. If the condition is set such that:iIN SLOPE R V VL T )D 1(⋅=⋅− (60)Then m C ·D = 1, so the current loop will be stable for any duty cycle. To meet this condition, solve for V SLOPE .LTR )V V (V i O IN SLOPE ⋅⋅−= (61)Figure 13: Valley current mode sub-harmonic oscillation. For D>0.5, sub-harmonic oscillation is damped. ForD<0.5, sub-harmonic oscillation builds with insufficient slope compensation.Emulated Peak Current Mode Valley Sample and HoldThe valley current is sampled on the down slope of the inductor current. This is used as the DC value of current to start the next cycle. A slope compensating ramp is added to produce V RAMP at the modulator input.Write the equation for the voltage at V C :C SLOPE i O IN i L v d V R LTd )v v (5.0R i =⋅+⋅⋅⋅−⋅−⋅ (62)V IN , V O , and V SLOPE are considered to be fixed with respect to the period T. The duty cycle is perturbed, whichshows the effect on the control voltage with respect to the inductor current. The quantity , and . )T (i ˆI LL=Δ)T (d ˆD =Δ)T (vˆV C C =ΔC SLOPE i O IN i L V D V R LTD )V V (5.0R I Δ=Δ⋅+⋅⋅Δ⋅−⋅−⋅Δ (63)To maintain constant average inductor current, the control voltage must change by ½ the ripple current:i PK C R I 5.0V ⋅Δ⋅−=Δ (64)LTD V L T )D 1(V I O O PK ⋅Δ⋅−=⋅Δ−⋅=Δ (65)Combine equations and solve for ∆D/∆I L :LT R 5.0V V 1V R I D i IN SLOPE INi L ⋅⋅−⋅−=ΔΔ (66)By factoring, this becomes:⎟⎟⎠⎞⎜⎜⎝⎛−⋅⋅⋅−=ΔΔ5.0L /R V T /V L T 1V 1I D i IN SLOPE IN L (67)This can also be written as:()5.0m LT 1V 1I D C IN L−⋅⋅−=ΔΔ (68)Where:ne C S S m = T /V S SLOPE e =L /R V S i IN n ⋅=Reviewing the equation for ∆D/∆I L , when m C <0.5, the T/L term goes negative. V SLOPE must be large enough to compensate, or this will manifest itself in the time domain as a sub-harmonic oscillation of the current loop. If the condition is set such that:LR V T V iIN SLOPE ⋅= (69)Then m C = 1, so the current loop will be unconditionally stable. Unlike peak or valley current mode, slope compensation is independent of duty cycle. To meet this condition, solve for V SLOPE .LTR V V i IN SLOPE ⋅⋅=(70)Figure 14: Emulated peak current mode sub-harmonic oscillation. Tendency for sub-harmonic oscillation isindependent of duty cycle. Even with minimal damping, it will eventually die out.Emulated Valley Current ModePeak Sample and HoldThe peak current is sampled on the positive slope of the inductor current. This is used as the DC value of current to start the next cycle. A slope compensating ramp is added to produce V RAMP at the modulator input.Write the equation for the voltage at V C :C SLOPE i O i L v )d 1(V R LT)d 1(v 5.0R i =−⋅−⋅⋅−⋅⋅+⋅ (71)V IN , V O , and V SLOPE are considered to be fixed with respect to the period T. The duty cycle is perturbed, whichshows the effect on the control voltage with respect to the inductor current. The quantity , and . )T (i ˆI LL=Δ)T (d ˆD =Δ)T (vˆV C C =ΔC SLOPE i O i L V D V R LTD V 5.0R I Δ=Δ⋅+⋅⋅Δ⋅⋅−⋅Δ (72)To maintain constant average inductor current, the control voltage must change by ½ the ripple current:i PK C R I 5.0V ⋅Δ⋅=Δ(73)LTD )V V (I O IN PK ⋅Δ⋅−=Δ(74)Combine equations and solve for ∆D/∆I L :LT R 5.0V V 1V R I Di IN SLOPE IN i L⋅⋅−⋅−=ΔΔ(75)By factoring, this becomes:⎟⎟⎠⎞⎜⎜⎝⎛−⋅⋅⋅−=ΔΔ5.0L /R V T /V L T 1V 1I D i IN SLOPE IN L (76)This can be expressed as:)5.0m (LT 1V 1I D c IN L−⋅⋅−=ΔΔ (77)Where: ne C S S m = T /V S SLOPE e =L /R V S i IN n ⋅=Reviewing the equation for ∆D/∆I L , when m C <0.5, the T/L term goes negative. V SLOPE must be large enough to compensate, or this will manifest itself in the time domain as a sub-harmonic oscillation of the current loop. If the condition is set such that:LR V T V iIN SLOPE ⋅= (78)Then m C = 1, so the current loop will be unconditionally stable. Unlike peak or valley current mode, slope compensation is independent of duty cycle. To meet this condition, solve for V SLOPE .LTR V V i IN SLOPE ⋅⋅= (79)4. General Slope Compensation RequirementsThe graphs in the preceding section were made by entering the discrete time expressions for the inductor current and slope compensating ramp into an Excel spreadsheet. The results are plotted on a cycle by cycle basis. This shows the current loop behavior without any feedback to the control voltage. Reference [6] discusses the voltage loop gain effect on the slope compensation requirement for peak current mode. Peaking of the closed loop gain due to insufficient slope compensation and ripple on the control voltage can cause sub-harmonic oscillation before the calculated limit, i.e. at duty cycles below 0.5 for peak current mode.For any mode of operation, when the sum of the sensed inductor current’s slope (times the current sense gain) plus the slope of the compensation ramp is proportional to V IN , any tendency toward sub-harmonic oscillation will damp in one switching cycle. This condition is represented by equations 52, 61, 70 and 79, which corresponds to a Q of 0.637. Operation is considered to be optimal, in that the effective sampled gain inductor pole is fixed in frequency with respect to changes in line voltage. This allows for the highest closed loop gain without any tendency toward sub-harmonic oscillation. Increasing the external ramp beyond this point will lower the modulator gain, consequently shifting toward a more voltage mode behavior.The effective sampled gain inductor pole frequency (45° phase shift) is given by:⎟⎠⎞⎜⎝⎛−⋅+⋅⋅⋅=1Q 41Q T 41)Q (f 2L(80)5. Correlation of Measured DataThe LM3495 standard reference design was chosen as a platform for correlation. It is an emulated peak current mode controller with MOSFET current sensing and internally generated slope compensation using mode EPCM4. Operating parameters:V IN =12 V O =1.2 T=2μs V SL =0.125 K SL =1/16 L=1μH R L =3m Ω G I =4 R S =3.4m Ω C O =200μF R C =1m Ω R O =1Ω and 0.2ΩMeasurement of control to output gain was made using an AP200 frequency response analyzer.The simplified transfer function using equation 41 was entered into SPICE as LaPlace for the calculated results. Nominal data sheet values were used for the components and operating parameters.Comparison of the results is shown in figure 15.Figure 15: LM3495 control to output gain.6. ConclusionThis analysis has focused on current mode buck regulators with continuous inductor current. Using the methodology outlined here, general expressions for the boost and buck-boost can be developed. Preliminary work has demonstrated good correlation between switching and linear models. Using the gain coefficients from reference [2], general expressions for discontinuous conduction mode can also be developed.Limitations of existing models have been identified, with direction for further work. Regardless of the limitations, the simplified transfer functions and general gain parameters allow accurate modeling of the control to output gain. This is the most important parameter from a design standpoint. Tools like SIMPLIS provide bode plots for any transfer function directly from the switching model.REFERENCES[1] R.D. Middlebrook, “Topics in Multi-Loop Regulators and Current-Mode Programming,” IEEE PESCRecord, pp. 716–732, 1985 (also in IEEE Transactions on Power Electronics, Volume 2, Issue 2, pp. 109–124, 1987).[2] R.B. Ridley, “A New Continuous-Time Model for Current-Mode Control with Constant Frequency,Constant On-Time, and Constant Off-Time, in CCM and DCM,” IEEE PESC Record, pp. 382–389, 1990.[3] R.B. Ridley, “A New, Continuous-Time Model for Current-Mode Control,” IEEE Transactions on PowerElectronics, Volume 6, Issue 2, pp. 271–280, 1991.[4] F.D. Tan, R.D. Middlebrook, “Unified Modeling and Measurement of Current-Programmed Converters,”IEEE PESC Record, pp. 380–387, 1993.[5] F.D. Tan, R.D. Middlebrook, “A Unified Model for Current-Programmed Converters,”IEEE Transactions on Power Electronics, Volume 10, Issue 4, pp. 397–408, 1995.“Modeling, Analysis and Compensation of the Current-Mode Converter,” Powercon 11 Holland,[6] BarneyProceedings, I-2, 1984.。

超特克（Supertex）高压DC DC转换器应用注解说明书

Supertex inc.AN-H59Application NoteApplication CircuitHigh Voltage DC/DC Converter forSupertex Ultrasound Transmitter DemoboardsBy Afshaneh Brown, Applications Engineer,and Jimes Lei, Applications ManagerIntroductionThe Supertex AN-H59DB1 demoboard is a high voltage DC/DC converter. It can provide up to +90V voltage supply for V PP and -90V for V NN . It also provides +8.0 to +10V voltage supply for V DD , floating power supplies of V NN +8.0 to V NN +10V for V NF and V PP -8.0 to V PP -10V for V PF . The input supply voltage is 12V.The AN-H59DB1 circuitry consists of two high voltage PWM Current-Mode controllers, a DC/DC transformer driver, and three low dropout regulators. The Supertex AN-H59DB1 uses a high-voltage, current mode, PWM controller boost topology to generate +15 to +90V and a high-voltage current mode PWM controller buck-boost topology to generate -15 to -90V power supply voltage for Supertex HV738DB1 and HV748DB1 ultrasound transmitter demoboards.Each of the transmitter demoboards has slightly different operating voltages as summarized below.To accommodate all three demoboards, the AN-H59DB1 demoboard has adjustable V PP , V NN , V DD , V PF and V NF . The purpose of the AN-H59DB1 is to aid in the evaluation of the three transmitter demoboards. The intention of this application note is to provide a general circuit description on how each of the output voltages is generated.The VSUB pin on the HV738DB1 and HV748DB1 can either be connected to the most positive supply voltage on the demoboard, or can be left floating.To power up the AN-H59DB1, ensure that the 3.3V power supply will be powered up first, and then the 12V power supply. The sequences on the HV738DB1 and HV748DB1 took into consideration using the protection diodes on each power line.The circuit is shown in Figure 6, the component placement in Figure 5, and the bill of materials is at the end of thisapplication note.PP The circuit in Figure 1 shows U5, the Supertex high volt -age current mode PWM controller, being used to generate the high voltage power supply for V PP . The maximum output power for V PP was set for 10mA at 90V, which is 900mW. With an input voltage of 12V, a converter frequency of 110 kHz with a 100µH inductor was chosen to provide the de -sired output power.The converter frequency is set by an external resistor, R20, across OSC IN and OSC OUT pins of U5. A 154kΩ resistor will set the frequency to about 110 kHz. R24 is the current sense resistor. 2.2Ω was used to set the maximum peak current limit to about 450mA. An RC filter, R23 and C15, is added between the current sense resistor and the current sense terminal pin 3 of U5. This reduces the leading edge spike on R24 from entering the current sense pin.Inductor L1 is being charged from the 12V input by M3. When M3 turns off, the energy in L1 is discharged into C16, which is the V PP output through D8. The V PP voltage is di-vided down by feedback resistors R25, R26, and R27. The wiper of R26 is connected to pin 14 of U5. The overall con -verter will regulate the voltage on pin 14 to 4.0V. Different V PP output voltages can be obtained by adjusting R26.When the wiper for R26 is set to the top, V PP can be calcu-lated as:where V FB is 4.0VWhen the wiper for R26 is set to the bottom, V PP can be calculated as:By adjusting potentiometer R26, V PP meets the adjustable target range of 15 to parator U6 will turn on LED D7 when the V PP output is out of regulation due to excessive load. During initial power up, C16 will be at 0V. D7 is therefore expected to be on until C16 is charged to the desired regulation voltage.Figure 1: Adjustable V PP Power SupplyV PPGNDV PP = 4.0V x ( 232k + 100k + 14.3k )= 12.1V 100k + 14.3k V PP= V FBx ( R25 + R26 + R27 )R26 + R27V PP = 4.0V x ( 232k + 100k + 14.3k )= 96.9V 14.3kV PP = V FBx ( R25 + R26 + R27 )R27NN The circuit in Figure 2 shows U7, the Supertex high voltage current mode PWM controller, being used to generate the high voltage power supply for V NN . The function of U7 is very similar to what was described in the V PP circuit description for U5. However, in this circuit a negative voltage is gener -ated from a positive input voltage source, therefore requir-ing a buck-boost topology. The maximum output power for V NN was set for -10mA at -90V which is 900mW. With an input voltage of 12V, a converter frequency of 110 kHz with a 100µH inductor was chosen to provide the desired output power.Inductor L2 is being charged from the 12V input by the par-allel combination of M6 and M7. When M6 and M7 turn off, the energy in L2 is discharged into C23, which is the V NNoutput through D10. M6 and M7 are high voltage P-channel MOSFETs. U7 is designed to drive a high voltage N-chan -nel MOSFET. The drive output for U7 therefore needs to be inverted. This is accomplished by M4 and M5.The feedback voltage that U7 detects on pin 14 is +4.0V. The V NN that needs to be sensed is a negative voltage. A cir-cuit is needed to make sure the feedback voltage is positive. This is consists of Q4, Q5, R33, R34, R35, R37, and R38. Q4 becomes a constant current sink set by the V NN voltageand R35. The same current will be flowing through R33 and R34.The voltage on the base of Q5 will be V IN minus the voltage drop across the sum of R33 and R34. By varying R34, the base voltage on Q5 will change. Q5 becomes a constant current source with a value set by its base voltage and R37. The current source of Q5 is going into R38, which creates a positive voltage that is now proportional to the magnitude of V NN .where V BE = 0.6V, V FB = 4.0V.When R34 is set to 100k, V NN is calculated to be:= -4.0VWhen R34 is set to 0k, V NN is calculated to be:= -97.4V By adjusting potentiometer R34, V NN meets the adjustable target range of -15 to parator U8 will turn on LED D9 when the V NN output isout of regulation due to excessive load. During initial power up, C23 will be at 0V. D9 is therefore expected to be on until C23 is charged to the desired regulation voltage.Figure 2: Adjustable V NN Power SupplyVNN-15V to -90V GNDV NN = V BE - ( R35 ) x (V BE + V FB x R37 ), R33 + R34 R38V NN = 0.6V - ( 273k) x (0.6V + 4.0V x 14.7k ) 4.99k + 100k 40.2k V NN = 0.6V - ( 273k ) x (0.6V + 4.0V x 14.7k )4.99k + 0k 40.2kVPF and VNF Circuit DescriptionThe three transmitter demoboards require two floating low voltage supplies, V PF and V NF . The floating supplies need to be adjustable to accommodate the different operating re-quirements for the three different boards. The V PF is 8.0 to 10V below the high voltage V PP positive supply. The V NF is 8.0 to 10V above the high voltage V NN negative supply. The two floating supplies are generated by using two isolated transformers, T1 and T2, and an isolated transformer driver, U1, as shown in Figure 4. Both outputs utilize adjustable low dropout linear regulators, U2 and U3, as shown in Figure 3. U2 and U3 are both Linear Technology LT1521, which has a reference voltage of 3.75V on the ADJ pin. For V PF , resistors R6, R7, and R8 set the output V PF voltage. R7 is a potentiom -eter for adjusting V PF . V PF can be calculated with the following equation:When R7 is set to 20kΩ, V PF becomes:When R7 is set to 0Ω, V PF becomes:Please note that the OUT pin on U2 is referenced to V PP , thereby setting V PF to be 8.0 to 10V below V PP . V NF can also be calculated in a similar manner using resistors R12, R13, and R14. Please note that the GND pin on U3 is referenced to V NN thereby setting V NF to be 8.0 to 10V above V NN .LED indicators, D5 and D11, start to turn on when the input current to U2 and U3 reaches an arbitrary value of 40mA. This is set by Q1 and R3 for V PF and Q2 and R9 for V NF . The input current can be calculated with the following equation: Input current = V EB = 0.5V = 41.3mA R 12.1Ω50mA current limits are added to protect against output shorts. The current limiter is consists of a depletion-mode MOSFET and a series source resistor. The resistor sets the current limit and can be estimated with the following equa -tion:R SERIES = V TH x ( √I LIM / I DSS - 1) where, I LIMV TH = pinch-off voltage for M1 and M2: -2.5V I LIM = desired current limit: 50mAI DSS = saturation current for M1 and M2: 1.1A R SERIES = 39.3Ω. A 40.2Ω resistor was used.Figure 3: Adjustable V PF and V NF Power SupplyV VNFVFPV PF = 3.75V x ( 45.3k + 20k + 24.9k )= 7.53V 20k + 24.9kV PF = 3.75V x ( 45.3k + 0k + 24.9k )= 10.6V 0 +24.9kV PF= V ADJx ( R6 + R7 + R8 )R7 + R8V DD Circuit DescriptionThe V DD output voltage utilizes an adjustable low dropout lin -ear regulator, U4 LT1521, as shown in Figure 4. The desiredadjustable output voltage range is 8.0 to 10V to accommo-date the different operating V DD voltages for the three differ-ent transmitter demoboards.The LT1521 has a reference voltage of 3.75V on the adj pin. Resistors R17, R18, and R19 set the output V DD voltage. R18 is a potentiometer for adjusting V DD . V DD can be calcu-lated with the following equation:When R18 is set to 20kΩ, V DD becomes:When R18 is set to 0Ω, V DD becomes:An LED indicator, D6, is included in case of excessive input,I IN, current. D6 is starts to turn on when the input currentreaches an arbitrary value of 20mA. This is set by Q3 and R15. When the emitter-base junction of Q3 is forward biased (0.5V), Q3 will start to turn on, thereby forward biasing D6.The I IN value to turn D6 on can be calculated with the follow -ing equation: I IN = V EB = 0.5V= 20.6mAR1524.3Ω 3.3V Input TerminalThe AN-H59DB1 has a 3.3V input terminal that is directly connected to the output terminal, V CC . There is no circuitry on this board that uses the 3.3V supply. It is only there as a convenient connection to the 8-pin header. V CC is the logic supply voltage for HV738DB1 and HV748DB1 and can oper-ate from 1.2 to 5V. However, most users will operate V CC at either 3.0 or 3.3V.Input and Output PowerThe output voltages from the AH-H59DB1 are all generated from the 12V input line. With no load on the outputs, the measured input current was about 70mA. This input current can vary from board to board due to variations in the isolated transformer.The maximum output power is:P OUT(MAX) = P VPP(MAX) + P VNN(MAX) + P VPF(MAX) + P VNF(MAX) + P VDD(MAX)P OUT(MAX) = 0.9W + 0.9W + 0.4W + 0.4W + 0.2W P OUT(MAX) = 2.8WUnder this condition, the 12V input current was measured to be 340mA. Input power is therefore 4.08W. This gives an approximate overall efficiency of 69% at full load.Figure 4: Adjustable V DD Power SupplyV IN = 12VVDD+8.0 to 10V GNDV DD = 3.75V x ( 45.3k + 20k + 24.9k )= 7.53V20k + 24.9kV DD = 3.75V x ( 45.3k + 0k + 24.9k )= 10.6V 0 + 24.9k V DD = V ADJ x ( R17 + R18 + R19 )R18 + R19VPF and VNF Output CurrentThe AN-H59DB1 can supply more than 40mA of current for the V PF and V NF outputs. The I NF and I PF input currents for the HV738 or the HV748 can be found in their respective datasheet but are summarized below:This is for continuous 5.0 MHz operation. For ultrasound, thehigh voltage transmitter is operating at very low duty cycles; 1% or lower. At a 1% duty cycle, the average current is ex -pected to be a 100 times lower. The 40mA output current ca -pability on the AN-H59DB1 is more than sufficient to power up the HV738 or the HV748.ConclusionThe main purpose of AN-H59DB1 power supply demoboard is to help the evaluation of the Supertex HV738DB1 and HV748DB1 demoboards by reducing the number of power supplies needed. The AN-H59DB1 was designed to operate from a single 12V input which should be commonly available in any engineering laboratory.The five on-board LEDs allow the user to quickly determine whether there is an overload condition on each of the supplylines. The five potentiometers allow the user to easily adjust each supply to meet their particular needs.Figure 5: AN-H59 Component PlacementFigure 6: AN-H59 Circuit SchematicVPPVPFVNFSupertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//)©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited.Supertex inc.1235 Bordeaux Drive, Sunnyvale, CA 94089。

MAP3012_Application Note_Ver1.0_24_Aug 2013

Aug. 2013
MagnaChip Semiconductor Ltd.
Confidential
Version 0.5
MAP3012
Once RSET is selected refer to the drive current table, on page 6 of the datasheet. The maximum total current is 165 mA; if the current through a single layer is 22 mA the number of parallel LED emitters in each layer is 7.
LED Stage #1 VF
Figure 2. Basic Operation
Adjustable Power by RSET
The difference between MAP3011A and MAP3012B is in their power rating. MAP3012B has a higher output power than MAP3011A. The current drawn by the LED stages is programmed by the . Figure 1. Typical Application Circuit
X7R (-55℃ to 125℃)
Voltage rating
PKG Size
Dielectric
Function Reduces Input Noise Reduces EMI
Confidential
Version 3012B
Application Note
Introduction

BTS3000双温度电子温度开关 PT100 类A DIN IEC 60751 温度传感器说明书

TemperatureElectronic Dual Temperature SwitchBTS3000Sensor element:PT100 Class A DIN/IEC 60751Materials:Wetted parts:Enclosure: Seals:304 Stainless steel304 Stainless steel / PBT, PA6.6 GF30FKM ﬂuoroelastomer (standard) EPDM (optional)Operating elements: 3 easy-response push-buttons Enclosure rating: Type 4X (IP65) / Type 6 (IP67)Protection class:IIIElectrical connection:Plug M12 x 1, 4-pin / 5-pin / 8-pinProcess connection:1/4” NPT Male, 1/2” NPT Male, 7/16-20 UNF (SAE-4) Male, G1/4” MaleDimensions Enclosure: 1.6 Ø x 4.4 inches (without plug connector and sensor)Weight:Approx. 0.4 lb (200 g)Measuring ranges: -22°F to +284°F (-30°C to +140°C)Max. pressure:2,900 psi (200 bar)A/D-Converter:Resolution:Scanning rate:12 bit (4,096 steps per measure span)1000/s Time Constant:Approx. 40 sAccuracy:< ±0.5 % f. s. at +25 °C Repeatability:±0.1% f. s.Temperature range:Electronics:Storage:14°F to 140°F (-10°C to +60°C)-22°F to 176°F (-30°C to +80°C)Power supply:15 to 28 V DC, reversed polarity protected (SELV , PELV)Class 2Digital display:Display rate:4-digit 14-segment LED red display,digit height .35 inches (9 mm)20/sError display:LED RED and alphanumeric display Power consumption:Approx. 50 mA (without load)Approx. 80 mA (Output Code 6)Relay output (option 6):Relay 1 NC Relay 2 NOLoad: max. 1A, max. 60V , max. 30VAFeaturesMeasuring range: -22° to +284°F (-30° to +140°C) One or two switch points Analog output 4 - 20 mADisplay & electronic connection: rotatable by 320° Simple navigation menu Superior EMI protection 0.50% accuracyIO-Link communication interfaceEnclosure Rating: Type 4X (IP65) / Type 6 (IP67)ApplicationsMachine tool industryHydraulic & pneumatic systems Injection molding machines Cooling monitoring / circuits Lubrication systemsConstruction machineryAutomobile industryGeneral Specifications** See product conﬁgurator for additional options.** At probe length over 100mm shock & vibration resistance can be inﬂuenced by the application Analog output:Current output:Scanning rate:Adjustment range:4-20 mA 2 ms25% to 100% f. s.Transistor switching outputs:Switching function:Normally open / normally closed,standard /window mode and diagnosis function adjustableSwitching output: Adjustment range for switching point and hysteresis:PNP / (NPN field-selectable on IO-Link units)0% to 125% f. s.Switching frequency:Max. 100 HzLoad:Max. 500mA, short-circuit-proof IO-Link: Max. 250mA Delay:0.0 s to 50.0 s adjustable Status display(s):LED(s) redIO-Link Communication Interface:Transmission type: COM2 (38.4 kBaud)IO-Link revision: 1.1SDCI standard: IEC 61131-9Profiles: Smart Sensor, Process Data Variable, Device Identiﬁcation, Device Diagnosis SIO modules:Yes Required master port type: ASIO output:1 analog /2 binary (switch points) [see product configurator]Min. process cycle time [ms]: 2.5Device ID: 0x011...Approvals:EMIShock resistance **Vibration resistance **cULus *** - E302981 EN 61000-4-2 ESD 4 kV CD / 8 kV AD EN 61000-4-3 HF radiated 10 V/m EN 61000-4-4 Burst 2 kV EN 61000-4-5-Surge 1/2 kV EN 61000-4-6 HF conducted10 V DIN EN 60028-2-2750 g (11 ms)DIN EN 60028-2-2620 g (10 to 2000 Hz)*** 1 - 5 output options only1Technical DrawingsElectronic Dual Temperature SwitchBTS3000Product ConfiguratorExample BTS3 E VM 11Dual switch point2Single switch point plus 4-20mA (0-10V ﬁeld selectable) 3Single switch point plus 0-10V (4-20mA ﬁeld selectable)4Dual switch point plus 4-20mA (0-10V ﬁeld selectable)5Dual switch point plus 0-10V (4-20mA ﬁeld selectable)6Dual switch points (1 x NO SPST / 1 x NC SPST), not UL approved 7IO-Link / Dual switch point, no UL IO-Link / Dual switch point plus 4-20mA (0-10V ﬁeld selectable), no ULOutput:Series BTS3000, electronic dual temperature switchSeries:N 91/4” NPT male thread31,91/2” NPT male thread (Consult factory)E 7/16-20 UNF (SAE 4)G1/4" male thread2G1/2” male thread (Consult factory)Process Connections:Sensor Length :0017M 517 mm probe 0025M 525 mm probe 0050M 550 mm probe 0100M 5100 mm probe 0300M 300 mm probe 0650M 5,6650 mm probe 0.70Z 1,70.7” probe 2.00Z 1,72” probe 4.00Z 1,74” probe 6.00Z 1,76” probe12.0Z 6,712” probeSealing:V FKM ﬂuoroelastomer (standard)E 2EPDM (EPR) (optional)X No seal (Required for units with NPT thread) FFFKM (optional) (Consult factory)Electrical Connection:M12AccessoriesOrder Number Description239535-1M-R-S84 Pin M12 Female Right Angle Plug Molded Cable, 3.28 Feet (1 Meter), Shielded 239535-1M-S 8 4 Pin M12 Female Straight Plug Molded Cable, 3.28 Feet (1 Meter), Shielded 239537 4 Pin M12 Female Straight Connector 2392364 Pin M12 Female Right Angle Connector239546-1M-R-S 8 5 Pin M12 Female Right Angle Molded Cable, 3.28 Feet (1 Meter), Shielded 239546-1M-S 8 5 Pin M12, Female Straight Plug Molded Cable, 3.28 Feet (1 Meter), Shielded 239548-S 5 Pin M12 Female Straight Connector 239548-R 5 Pin M12 Female Right Angle Connector 20877912” Probe - Brass Thermowell208779-SS 12” Probe - 316 Stainless Steel Thermowell 20878014” Probe - Brass Thermowell208780-SS14” Probe - 316 Stainless Steel Thermowell 20878116” Probe - Brass Thermowell208781-SS 16” Probe - 316 Stainless Steel ThermowellNote:1. Thermowell option available for 1/2” NPTF only with 2”, 4” and 6” probes only; consult factory for details.2. Available only for G and UNF thread.3. Mating connector not included with unit; mating connectors are available and can be ordered as an accessory.4. Custom probe length available; minimum quantities may apply.5. Available only for G1/4” or G1/2” thread.6. At probe length over 11.8” (300 mm), the probe must be kept out of the direct path of the flowing media.7. Available only for NPT and UNF thread.8. See Cable Connectors & Accessories for more options.9. Requires sealing code XTemperature Ranges:0 to 100°C 2-30 to 140°C 332 to 210°F 4-22 to 280°FElectrical Connection ChartMating connectornot included; see accessories for options*L2 is theeffective length for NPT fitting.Dimensions inches [mm]Length.7” [17.78 mm] 0.67” [17 mm] 2” [50.8 mm]0.98” [25 mm]4” [101.6 mm] 1.97” [50 mm]6” [152.4 mm]3.94” [100 mm]12” [304.8 mm]11.80” [300 mm]25.59” [650 mm](/(&75,&$/ &211(&7,21,2 /,1. 21/< )25 6,*1$/ 287387 &2'(6$%&'&RQQHFWLRQ GLDJUDPIO-LINK ONLY FOR SIGNAL OUTPUT CODES 7 & 82BTS38G 2M351。

DFTMAX_and_OCC

Adaptive Scan with On-Chip ClockingApplication NoteY-2006.06OverviewThis application note describes a workaround for the automated flow for Adaptive Scan (DFT MAX) with On-Chip Clocking (OCC) Support. The flow which is described here is currently the only way to get two independent test mode controls, one for compression vs. normal-scan modes and the other for PLL test mode. This flow also avoids top-level logic, which the automated flow adds.This application note covers the insertion of Adaptive Scan and OCC, the generation and manual modifications of test-protocols for various test-modes and the automatic pattern generation (ATPG) on a hierarchical example design. BackgroundThe example design in this application note has two top level blocks, one core and a clock-generator block. Adaptive Scan should be inserted to the core block and the DesignWare IP clock controller and clock chain should be synthesized into the clock-generator block. There should be no glue-logic on the top level.To simplify the process, we will do the Adaptive Scan- and OCC-insertion in a hierarchical flow in separate steps. Adaptive Scan will be inserted on the core level and the OCC-controller and clock-chain will be inserted in the clock-generator block. The top-level connections will have to be made by the user, see Figure 1: Design Block Diagram.In this example we want to have three test modes:1. Pure scan without OCC support(using the test clock for scan shifting and capture)2. Adaptive Scan compression without OCC support(using the test clock for scan shifting and capture)3. Adaptive Scan compression with OCC support(using the test clock for shifting and the PLL clocks for launch & capture)Figure 1: Design Block DiagramTest Ports ConsiderationsBefore inserting Adaptive Scan and OCC we should consider the required test ports, so that we can already create them in our RTL code together with the top-level connections to the two sub-blocks.For Adaptive Scan we need Scan-In and Scan-Out ports to feed the scan-compression logic and the reconfigured scan-chains. We also need a test-mode signal to switch between the scan-compression mode and the reconfigured scan mode (pure scan). In this example we are using 5 Scan-In/Scan-Out pairs (test_si[0..4], test_so[0..4]), a Scan-Enable (test_se) and the test-mode port (test_mode_compr).For the OCC controller we need a separate test-mode signal (test_mode_occ) to activate the OCC controller in test mode. Beside the reference-clock (ref_clk), which feeds the PLLs, we need one test-clock (ate_clk) for scan-shifting. A PLL-bypass signal is used to bypass the PLLs and feed through the test-clock to the scan-cells (test_pll_bypass). The OCC controller requires the Scan-Enable (test_se) and a PLL-reset to reset the controller. In this example the PLL-reset isshared with the active high chip reset (rst).Because the Clock-Chain cannot be included to the Adaptive Scan chains, we need separate Scan-In and Scan-Out ports. In this design we only want a single Clock-Chain (test_clk_chain_in, test_clk_chain_out).Table 1: Test Access Portstest_si[0..4] Scan Data Intest_so[0..4] Scan Data Outtest_clk_chain_in Clock-Chain Intest_clk_chain_out Clock-Chain Outtest_se Scan-Enabletest_mode_compr Test-Mode Scancompressiontest_mode_occ Test-Mode On-Chip-Clockingtest_pll_bypass PLL-Bypassref_clk Reference Clockate_clk Test Clockrst ResetOCC Controller and Clock-Chain InsertionThis section describes the insertion of the OCC controller and the Clock-Chain. We are starting with a test-ready netlist, all flip-flops in the design have been replaced by scan-flops. The clock-generator block in this example contains a PLL-module, which generates three PLL clocks (clka, clkb and clkc). The PLL itself is triggered by one reference clock (ref_clk). The designer has already created the ports for the OCC controller and Clock-Chain (ate_clk, test_mode_occ, pll_reset, test_pll_bypass, test-se, test_clk_chain_in, test_clk_chain_out).Figure 2 : clock-generator block before OCC controller insertionIn this design we want to insert a single OCC controller and one Clock-Chain for all three PLL-clocks with two capture cycles per clock. We are following the instructions from the DFT Compiler User Guide Vol.1: Scan (XG Mode), section On-Chip Clocking Support:current_design clock_genset_dft_configuration -clock_controller enableset_dft_signal -view existing -type Oscillator -hookup_pin pll_module/clkaset_dft_signal -view existing -type Oscillator -hookup_pin pll_module/clkbset_dft_signal -view existing -type Oscillator -hookup_pin pll_module/clkcset_dft_signal -view existing -type Oscillator -port ref_clkset_dft_signal -view existing -type Oscillator -port ate_clkset_dft_signal -view existing -type ScanClock -port ate_clk -timing { 45 55 } set_dft_signal -view spec -type pll_bypass -port test_pll_bypassset_dft_signal -view spec -type pll_reset -port pll_resetset_dft_clock_controller -cell_name pll_controller1 -design snps_clk_mux \-pllclocks { pll_module/clka pll_module/clkb pll_module/clkc } \-ateclocks { ate_clk } -cycles_per_clock 2 -chain_count 1set_dft_signal -view spec -type TestMode -port test_mode_occset_dft_signal -view spec -type ScanEnable -port test_seset_dft_signal -view spec -type ScanDataIn -port test_clk_chain_inset_dft_signal -view spec -type ScanDataOut -port test_clk_chain_outcreate_test_protocoldft_drcpreview_dftinsert_dftchange_names -rule verilogwrite -f verilog -h -o ./netlist/occ.vwrite_test_protocol -test_mode Internal_scan -o ./atpg/clock_gen_occ.spfwrite_test_protocol -test_mode Internal_scan -o ./atpg/clock_gen_pll_bypass.spf -pll_bypassScan Compression InsertionThis section describes the scan compression insertion on the core-level. The core-level contains the core logic and the designer has already created the test access ports (test_se, test_si[0..4], test_so[0..4], test_mode_compr). We are following the standard Adaptive Scan flow, which is described in the Design Compiler User Guide Vol.2: Adaptive Scan (XG Mode). We want 5 Scan-In/Scan-Out pairs with the default compression factor of 10x.Figure 3: core block before insertioncurrent_design coreset scan_chains 5set_dft_configuration -scan_compression enableset_scan_configuration -chain_count $scan_chainsset_dft_signal -view existing -type ScanClock -port clk1 -timing { 45 55 }set_dft_signal -view existing -type ScanClock -port clk2 -timing { 45 55 }set_dft_signal -view existing -type ScanClock -port clk3 -timing { 45 55 }set_dft_signal -view existing -type Reset -port rst -active 1for {set i 0} {$i<$scan_chains} {incr i} {set_dft_signal -view spec -type ScanDataIn -port test_si[$i]set_dft_signal -view spec -type ScanDataout -port test_so[$i]}set_dft_signal -view spec -type ScanEnable -port test_seset_dft_signal -view spec -type TestMode -port test_mode_comprcreate_test_protocoldft_drcpreview_dftinsert_dftchange_names -rule verilogwrite -f ddc -h -o ./netlist/core_dftmax.ddcwrite_test_model -o ./netlist/core_dftmax.ctldbwrite_test_protocol -o ./atpg/core_scan.spf \-test_mode Internal_scanwrite_test_protocol -o ./atpg/core_scancompression.spf \-test_mode ScanCompression_modeTest DRC on Top-LevelThis section describes the top level test DRC for the reconfigured scan mode and PLL bypassed. After the Adaptive Scan- and OCC controller insertion we will now go to the top level and use the ‘existing scan’ flow to perform a test DRC. For this purpose we will constrain the design to the reconfigured scan mode (scan compression disabled) and bypass the PLL (ate_clk used for scan-shift and capture).To bring the design into the reconfigured scan mode we have to set the scan compression test mode signal to ‘0’ (test_mode_compr = ‘0’). To bypass the PLL we have to set the OCC test mode signal (test_mode_occ = ‘1’) and the PLL bypass signal (test_pll_bypass = ‘1’).If the DRC passes successfully, we can write out our first top level test protocol for pure scan without OCC support.set scan_chains 5current_design toplinkset_scan_state scan_existingset_dft_signal -view existing -type ScanClock -port ate_clk -timing { 45 55 } set_dft_signal -view existing -type Constant -port rst -active 0 set_dft_signal -view existing -type Constant -port test_mode_occ -active 1 set_dft_signal -view existing -type Constant -port test_pll_bypass -active 1 set_dft_signal -view existing -type Constant -port test_mode_compr -active 0 set_dft_signal -view existing -type ScanEnable -port test_sefor {set i 0} {$i<$scan_chains} {incr i} {set_scan_path chain$i -view existing -scan_data_in test_si[$i] \-scan_data_out test_so[$i] -infer_dft_signals}set_scan_path clock_chain -view existing -scan_data_in test_clk_chain_in \-scan_data_out test_clk_chain_out -infer_dft_signalscreate_test_protocoldft_drcchange_names -rule verilogwrite -f verilog -h -o ./netlist/final_netlist.vwrite -f ddc -h -o ./netlist/final_netlist.ddcwrite_test_protocol -o ./atpg/top_pure_scan_without_occ.spfGenerating the Test Protocols for ATPGThis section describes the manual steps which are necessary to create the test protocols for the scan compression ATPG with and without the OCC support. The insertion of Adaptive Scan and the OCC controller and Clock-Chain above was quite simple. It was also not a big effort to generate the top level test protocol for pure scan without OCC, see last section. Unfortunately the creation of the top level test protocols for the scan compression with OCC is a little bit complex because we have to merge the block level protocols for OCC and Adaptive Scan and map them to the top-level. This process is not that automated yet and requires some hand editing.Test Protocol for Adaptive Scan without OCCWe have already written out a test protocol for Adaptive Scan on the core level. Or task now is to map the scan structure information from this file to the top levelprotocol. In this design we have used the same test port names at the core block and at the top level so no renaming is necessary. Beside the Adaptive Scan structures, the new protocol should also contain the Clock-Chain. In this mode the Clock-Chain behaves like a normal scan chain. To create the protocol we follow these steps:1. Copy ./atpg/top_pure_scan_without_occ.spfto ./atpg/top_scancompression_without_occ.spf2. Delete the ScanStructures block3. Replace it with copies of these blocks (complete)from ./atpg/core_scancompression.spfScanStructures {[...]}UserKeywords CompressorStructures;CompressorStructures {[...]}4. Add the Clock-Chain to the ScanStructures block:[...]ScanStructures {ScanChain "clock_chain" {ScanIn "test_clk_chain_in";ScanOut "test_clk_chain_out";}[...]5. Change every instance of "test_mode_compr"=0; to"test_mode_compr"=1;6. Add the line “ActiveScanChains core_group;” to the top of the"load_unload" Procedure:[...]Procedures {"load_unload" {ActiveScanChains core_group;W "_default_WFT_";[...]Test Protocol for Adaptive Scan with OCCThis is the most complex task in our flow. The first step is to create a top level test protocol for OCC and pure scan. We are using the TetraMAX Quick-STIL feature to generate a template, which has to be modified by hand. The following TetraMAX commands are used to generate the template:read netlist ./library/lib.vread netlist ./library/pll.vread netlist ./netlist/final_netlist.vrun build topset drc -num_pll_cycles 2set atpg -min_refclock_cycles 5add clock 0 ate_clk -shift -refclock -timing 100 45 55 20add clock 0 ref_clk -refclock -shift -timing 100 45 55 20add clock 0 U_clock_gen/pll_module/clka -pllclockadd clock 0 "U_clock_gen/pll_controller1/U2/Z" -intclock \-pll_source U_clock_gen/pll_module/clka \-cycle 0 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_4/Q" 1 \-cycle 1 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_5/Q" 1add clock 0 U_clock_gen/pll_module/clkb -pllclockadd clock 0 "U_clock_gen/pll_controller1/U4/Z" -intclock \-pll_source U_clock_gen/pll_module/clkb \-cycle 0 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_2/Q" 1 \-cycle 1 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_3/Q" 1add clock 0 U_clock_gen/pll_module/clkc -pllclockadd clock 0 "U_clock_gen/pll_controller1/U6/Z" -intclock \-pll_source U_clock_gen/pll_module/clkc \-cycle 0 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_0/Q" 1 \-cycle 1 "U_clock_gen/snps_clk_chain_0/U_ctr_i_0/FF_1/Q" 1add scan enable 1 test_seadd pi constraints 1 test_mode_occadd pi constraints 0 test_pll_bypassadd pi constraints 0 rstadd pi constraints 0 test_seadd pi constraints 0 test_mode_compradd scan chain scan_chain_0 test_si[0] test_so[0]add scan chain scan_chain_1 test_si[1] test_so[1]add scan chain scan_chain_2 test_si[2] test_so[2]add scan chain scan_chain_3 test_si[3] test_so[3]add scan chain scan_chain_4 test_si[4] test_so[4]add scan chain clk_chain test_clk_chain_in test_clk_chain_outrun drcwrite drc ./atpg/template_top_pure_scan_with_occ.spf -replacequitThe information about the -intclock, -pll-source and –cycle for the clock controller is taken from the “PLLStructures” in the core level OCC protocol (./atpg/clock_gen_occ.spf). Please note that we have to apply the complete top level paths to the the -intclock, -pll-source and –cycle, see Figure 4: converting protocol to TetraMAX commands. The ‘run drc‘ will fail because of a missing preamble clock pulse in the load_unload procedure and a missing reset execution in the test_setup. Despite the failing ‘run drc‘ we save the protocol as a template (./atpg/template_top_pure_scan_with_occ.spf).Figure 4: converting protocol to TetraMAX commandsThe second step is to edit the template and add the missing preamble clock pulse in the load_unload procedure and execute the reset in the test_setup procedure:[...]Procedures {"load_unload" {W "_default_WFT_";C { "test_si[1]"=0; "test_so[4]"=X; "test_si[0]"=0; "test_so[3]"=X;"test_clk_chain_out"=X;"test_so[2]"=X; "test_si[4]"=0; "test_so[1]"=X; "test_si[3]"=0;"test_so[0]"=X; "test_si[2]"=0; "test_clk_chain_in"=0; "ate_clk"=0;"ref_clk"=0; "test_se"=1; }V { "ate_clk"=P; "ref_clk"=P; }Shift { W "_default_WFT_";V { "_si"=######; "_so"=######; "ate_clk"=P; "ref_clk"=P; }}}[...]MacroDefs {"test_setup" {W "_default_WFT_";V { "test_mode_occ"=1; "test_mode_compr"=0; "test_se"=0;"test_pll_bypass"=0; "rst"=1; "ate_clk"=P; "ref_clk"=P; }V { "test_mode_occ"=1; "test_mode_compr"=0; "test_se"=0;"test_pll_bypass"=0; "rst"=0; "ate_clk"=0; "ref_clk"=0; }}}We now have a top level test protocol file for pure scan with On-Chip Clocking (./atpg/top_pure_scan_with_occ.spf). The third step is to get the top level test protocol for OCC and Adaptive Scan. For this purpose we just have to add the Scancompression information to it.1. Copy ./atpg/top_pure_scan_with_occ.spfto ./atpg/top_scancompression_with_occ.spf2. Delete the ScanStructures block3. Replace it with copies of these blocks (complete)from ./atpg/top_scancompression_without_occ.spfScanStructures {[...]}UserKeywords CompressorStructures;CompressorStructures {[...]}4. Change every instance (there are 5 in this file) of"test_mode_compr"=0; to"test_mode_compr"=1;5. Add the line “ActiveScanChains core_group;” to the top of the"load_unload" Procedure:[...]Procedures {"load_unload" {ActiveScanChains core_group;W "_default_WFT_";[...]We now have prepared all test protocols for the various ATPG runs. Performing ATPGThis section describes the ATPG runs for pure scan without OCC, Adaptive Scan without OCC and Adaptive Scan with OCC. With the three top level test protocols we created previously we can follow the standard TetraMAX flows.Pure Scan ATPG without On-Chip ClockingIn this mode the test clock (ate_clk) is used for scan shifting and capture. The ATPG is performed on the reconfigured scan-chains.set message log logfiles/atpg_pure_scan_without_occ.log -replaceread netlist ./library/lib.vread netlist ./library/pll.vread netlist ./netlist/final_netlist.vrun build toprun drc ./atpg/top_pure_scan_without_occ.spfadd faults -allrun atpg –autowrite patterns ...Adaptive Scan ATPG without On-Chip ClockingIn this mode the Scancompression is enabled. For scan shifting and capture the test clock (ate_clk) is used.set message log logfiles/atpg_scancompression_without_occ.log -replaceread netlist ./library/lib.vread netlist ./library/pll.vread netlist ./netlist/final_netlist.vrun build toprun drc ./atpg/top_scancompression_without_occ.spfadd faults -allrun atpg -autowrite patterns ...Adaptive Scan ATPG with On-Chip ClockingIn this mode a transition delay ATPG is performed with Scancompression enabled. The test clock (ate_clk) is used for scan shifting and the internal PLL clocks are used for launch and capture.set message log logfiles/atpg_scancompression_with_occ.log -replaceread netlist ./library/lib.vread netlist ./library/pll.vread netlist ./netlist/final_netlist.vrun build topset drc -num_pll_cycles 2set atpg -min_refclock_cycles 5run drc ./atpg/top_scancompression_with_occ.spfset faults -model transitionset delay -launch system_clockadd faults -allrun atpg -autowrite patterns ...SummaryThis application note described a workaround for Adaptive Scan (DFT MAX) and On-Chip Clocking (OCC) Support to get two independent test mode controls, one for compression vs. normal-scan modes and the other for PLL test mode.On a hierarchical example design we considered the required test access ports and discussed all scripts for DFT-Compiler and TetraMAX. This application note also contains step by step instructions to create the top level test protocols for the three modes of operation (pure scan without OCC support, Adaptive Scan compression without OCC support and Adaptive Scan compression with OCC). 11/20/2006 Adaptive Scan with On-Chip Clocking Page 11。

GRE大写乱序词汇背诵

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EQUINE TRIBUTARY RESUSCITATE SECEDE COAXZONEHARRY WILLOW EQUIVALENT CALIBRE MISTRAL ANTAGONIZECOMPATRIOT SLAG CAPTION MINNOW COMPONENT FILTER PANDER QUASH STRATIFY URCHIN FURTIVE TRAIT DISCERNIBLE DOUR COMPOST CRUMB DIVERSITY MAMMOTH MOLEST DESIGNATION LIBERALITY BILINGUAL MASSACRE SOPPING AMITY FRATERNITY FORTIFY GLADE LATENT PACIFIST STANCE INDIFFERENTHECKLE UNFLAPPABLE CAPITALIZE PHENOMENAL SUPERFLUITY BOMBASTIC SOLVENT METALLURGY HUSBAND ELONGATESOAKCONVINCECLEFTCYPRESS PLETHORA FERVIDLEDGER PROPITIATE STEALTH HURRICANE EQUESTRIAN INTERLOCUTOR YAWNATONALJOGWISTFUL VESTIGEAMASS GENERATOR INDISPENSABILITY GLOSS ASKANCECUBSOJOURN INTRIGUE SWARM SEDITION EXTERNALIZE PROBOSCIS TEMERITYBIN HIEROGLYPH INFEST TESTATOR PARIAHWILY CARDIOLOGIST AFFLUENT CONTENTIOUS GARBLE HALCYONBIDCYTOLOGY DEFORESTATION EMBOSS EFFIGY SHIPSHAPE BRACKET GRATITUDE OBNOXIOUS IMPERTURBABLE BRIBE PROVINCIAL EPITOMEPLEBEIAN REPUTE PROGENY IGNITE ESPOUSAL ANTIQUE FACTOTUM ANNEXATION SERVICEABLE MIGHTY PERSONABLE DWELLING BELITTLE NONRADIOACTIVE SINECURE OCCIDENTAL BRAGLUMPGAINSAYHIVEVIRTUAL INEBRIATE COLLOQUIAL TERMINATION LINEAR MAINTENANCE DISCIPLINE CONSECRATE PECKTELLING POSTERIOR ASTHMAVAPORIZE SEEP BROCHURE YEAST QUADRUPED THRALL MUSCULAR LUMBERJACK RELEASE MUTINEER SCRIPT INTENSIFY TREACHEROUS EMBOLDEN LIQUIDRIGOR VOTARY DECENTRALIZE DELECTABLE GAUCHERIE DIM PENETRATE EXTREMIST ATONESLATE RETAINER ENTRÉE DISEMBODY SMART WARDROBE CONCILIATORYQUAINT TALLY ABSENTEEISM HITHERTO ANVIL INIMITABLE SIMPLETON INTRICATE ASPERSION RACKETEER PULLEY GUILELESS PETULANT NASCENT SATURATED MAGNIFICENT NICOTINE PESTICIDE PREDICAMENT OLIGARCH NEOLITHIC TORQUE SPONTANEITY SUFFICIENT EWE LAPIDARY GRENADE RAPT SINCERE PECAN INFERNALLUNATIC CRUMPLE QUAGMIRE PODIATRIST DIPSOMANIA SCAR VIRTUOSO NIGHTMARE JOVIAL GANGWAY ADMIRE INVESTIGATE CONUNDRUM BARRIER SOLEMN COMPOSURE WARRANTY ENERVATE IMPRESSIONABLE ROSTRUM ARROYOSTAID BEWILDER LOGJAM DISCOMPOSE UNSTINTING HISTRIONIC BOREDOMLUCID TREACHERY PURLIEU GASTRONOMYBENEVOLENT INKLING INSPECTION FOOTHOLD PROTUBERANT CAMEO EXCORIATE PRIG FAINTHEARTED YEARN WINDBAG TESTY PRETEXT GRANT APOCRYPHAL DISILLUSION INCINERATE BRUSQUE AUGER WAYLAY BRAID EVASIVE GENERIC LOCALE ENTRENCH PYRE ANNIHILATE CAVALRY RAPSCALLION SCION ABSOLUTE STRATUMAGGLOMERATE CONSTRAIN CACHE GLIMMER SABOTEUR RAFTER ABSURD DISFRANCHISE IMPUTATION MARSHALSIPILLEGALGILD PROVERBIALLY WHISTLE SCALDPRÉCIS TAMPER GROOVE DISTENSION OBSOLETE ANTAGONISM CODA IMPOSING SUBMISSION SALUBRIOUS PORE LEGISLATURE FELON EARSPLITTING SEDATE FREQUENT。

Infineon TLI4971高精度无核电流传感器说明书

TLI4971 high precision coreless current sensor for industrial applications in 8x8mm SMD packageFeatures & Benefits∙ Integrated current rail with typical 220µΩ insertion resistance enables ultra-low power loss∙ Smallest form factor, 8x8mm SMD, for easy integration and board area saving∙ High accurate, scalable, DC & AC current sensing ∙ Bandwidth typical 240kHz enables wide range of applications∙ Very low sensitivity error over temperature (< 2.5%) ∙ Galvanic functional isolation up to 1150V peak V IORM ∙ V ISO 3500V RMS agency type-tested for 60 seconds per UL1577∙ Differential sensor principle ensures superior magnetic stray field suppression∙ Two independent fast Over-Current Detection (OCD)outputssCoreless current sensor in PG-TISON-8 packageDescriptionTLI4971 is a high precision miniature coreless magnetic current sensor for AC and DC measurements with analog interface and two fast over-current detection outputs.Infineon's well-established and robust monolithic Hall technology enables accurate and highly linear measurement of currents with a full scale up to ±120A. All negative effects (saturation, hysteresis) commonly known from open loop sensors using flux concentration techniques are avoided. The sensor is equipped with internal self-diagnostic feature.Typical applications are electrical drives and general purpose inverters.The differential measurement principle allows great stray field suppression for operation in harsh environments.Two separate interface pins (OCD) provide a fast output signal in case a current exceeds a pre-set threshold.The sensor is shipped as a fully calibrated product without requiring any customer end-of-line calibration.All user-programmable parameters such as OCD thresholds, blanking times and output configuration modes are stored in an embedded EEPROM memory.2) Semi-differential mode, non-ratiometric output sensitivityPin ConfigurationFigure 1 Pin layout PG-TISON-8-5The current I PN is measured as a positive value when it flows from pin 8 (+) to pin 7 (-) through the integrated current rail.Pin configurationTarget ApplicationsThe TLI4971 is suitable for AC as well as DC current measurement applications: ∙ Electrical drives∙ General purpose inverters ∙ Chargers∙ Current monitoring∙ Overload and over-current detection ∙ etc.Due to its implemented magnetic interference suppression, it is extremely robust when exposed to external magnetic fields. The device is suitable for fast over-current detection with a configurable threshold level. This allows the control unit to switch off and protect the affected system from damage, independently from the main measurement path.1 2 3 456 78+- I PNGeneral DescriptionThe current flowing through the current rail on the primary side induces a magnetic field that is differentially measured by two Hall probes. The differential measurement principle of the magnetic field combined with the current rail design provides superior suppression of any ambient magnetic stray fields. A high performance amplifier combines the signal resulting from the differential field and the internal compensation information provided by the temperature and stress compensation unit. Finally the amplifier output signal is fed into a differential output amplifier which is able to drive the analog output of the sensor.Depending on the selected programming option, the analog output signal can be provided either as: ∙Single-ended∙Fully-differential∙Semi-differentialIn single-ended mode, the pin VREF is used as a reference voltage input. The analog output signal is provided on pin AOUT. In fully-differential mode, both AOUT (positive polarity) and VREF (negative polarity) are used as signal outputs whereas VDD is used as reference voltage input. Compared to the single-ended mode, the fully-differential mode enables doubling of the output voltage swing.In semi-differential mode a chip-internal reference voltage is used and provided on VREF (output). The current sensing information is provided in a single-ended way on AOUT.For fast over-current detection, the raw analog signal provided by the Hall probes is fed into comparators with programmable switching thresholds.A user-programmable deglitch filter is implemented to enable the suppression of fast switching transients. The open-drain outputs of the OCD pins are active “low” and they can be directly combined into a wired-AND configuration on board level to have a general over-current detection signal.All user-programmable parameters such as OCD thresholds, deglitching filter settings and output configuration mode are stored in an embedded EEPROM memory.Programming of the memory can be performed in the application through a Serial Inspection and Configuration Interface (SICI). The interface is descripded in detail in the programming guide which can be found on the Infineon webside. Please contact your local Infineon sales office for further documentation. Standard Product Configuration∙The pre-configured full scale range is either set to ±120A, ±75A, ±50A or ±25A depending on the choosen product variant.∙The pre-configured output mode is set to semi-differential mode.∙The quiescent voltage is set to 1.65V.∙The OCD threshold of channel 1 is set to the factor 1.25 of the full scale range.∙The OCD threshold of channel 2 is set to the factor 0.82 of the full scale range.∙The pre-defined setting of the OCD deglitching filter time is set to 0µs.∙The sensor is pre-configured to work in the non-ratiometric mode.∙The sensitivity and the derived measurement range (full scale) can be reprogrammed by user according to the sensitivity ranges listed in Table 4.∙The sensor can be reprogrammed into single-ended operating mode or fully-differential mode by user without any recalibration of the device.∙The OCD thresholds and filter settings can be reprogrammed by the user according to the values listed in Table 6 and Table 7.∙For semi-differential uni-directional mode or ratiometric output sensitivity, please contact your local Infineon sales office.Block DiagramThe current flowing through the current rail on the primary side induces a magnetic field, which is measured by two Hall probes differentially. The differential measurement principle provides superior suppression of any ambient magnetic stray fields. A high performance amplifier combines the signal resulting from the differential field and the compensation information, provided by the temperature and stress compensation unit. Finally the amplifier output signal is fed into a differential output amplifier, which is able to drive the analog output of the sensor.Absolute Maximum RatingsTable 1 Absolute Maximum RatingsThermal equilibrium reached after 2 min.2)Tested with primary nominal rated current of 70A rms on Infineon reference PCB at High Frequency (HF).Thermal equilibrium reached after 2 min.3)Human Body Model (HBM), according to standard AEC-Q 100-0024)Accor ding to standard IEC 61000−4−2 e lectrostatic discharge immunity testStress above the limit values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings. Exceeding only one of these values may cause irreversible damage to the integrated circuit.Product Characteristics Table 2 Operating RangesTable 3 Operating ParametersFunctional Output DescriptionThe analog output signal depends on the selected output mode:∙Single-ended∙Fully-differential∙Semi-differentialSingle-Ended Output ModeIn single-ended mode VREF is used as an input pin to provide the analog reference voltage, V REF. The voltage on AOUT, V AOUT, is proportional to the measured current I PN at the current rail:V AOUT(I PN)=V OQ+S∙I PNThe quiescent voltage V OQ is the value of V AOUT when I PN=0. V OQ tracks the voltage on VREFV OQ(V REF)=V REFThe reference voltage can be set to different values which allow either bidirectional or uniderictional current sensing. The possible values of V REFNOM are indicated in Table 2.The sensitivity is by default non ratiometric to V REF. If ratiometricity is activated the sensitivity becomes as follows:S(V REF)=S(V REFNOM)∙V REF V REFNOMFully-Differential Output ModeIn fully-differential output mode, both VREF and AOUT are analog outputs to achieve double voltage swing: AOUT is the non-inverting output, while VREF is the inverting output:V AOUT(I PN)=V QAOUT+S∙I PNV REF(I PN)=V QREF−S∙I PNThe quiescent voltage is derived from the supply pins VDD and GND and has the same value on both AOUT and VREF:V QAOUT(V DD)=V QREF(V DD)=V DD2The sensitivity in the fully-differential mode can begenerally expressed as:S(V DD)diff=S(3.3V)diff∙V DD3.3VIn this mode, the quiescent voltages and thesensitivity are both ratiometric with respect to V DDif ratiometricity is enabled.Semi-Differential Output ModeIn semi-differential output mode, the sensor isusing a chip-internal reference voltage to generatethe quiescent voltage that is available on pin VREF(used as output).The analog measurement result is available assingle-ended output signal on AOUT. Thedependence of sensitivity and output offset onreference voltage is the same as described in single-ended output mode.The quiescent voltage is programmable at 3different values, V OQbid_1and V OQbid_2forbidirectional current and V OQuni for unidirectionalcurrent (see Table 4).Total error distributionFigure 3 shows the total output error at 0h (E TOTT)and over lifetime (E TOTL) over the full scale range forsensitivity range S1 (10mV/A).Table 4 Analog Output Characteristics2) Can be programmed by user.3) Values refer to semi-differential mode or single-ended mode, with VREF =1.65 V. In fully-differential mode the sensitivity value is doubled.4) Not subject to production test. Verified by design and characterization.5) Typical value in fully-differential mode, sensitivity range S66) Noise Density=RMS√ π2 ∗ BW[Hz]1Sensitivity[VA]Table 4 Analog Output Characteristics (cont’d)Fast Over-Current Detection (OCD)The Over-Current Detection (OCD) function allows fast detection of over-current events. The raw analog output of the Hall probes is fed directly into comparators with programmable switching thresholds. A user programmable deglitch filter is implemented to enable the suppression of fast switching transients. The two different open-drain OCD pins are active low and can be directly combined into a wired-AND configuration on board level to have a general over-current detection signal. TLI4971 supports two independent programmable OCD outputs, suited for different application needs.The OCD pins are providing a very fast response, thanks to independence from the main signal path. They can be used as a trap functionality to quickly shut down the current source as well as for precise detection of soft overload conditions.OCD pins external connectionThe OCD pins can be connected to a logic input pin of the microcontroller and/or the gate-driver to quickly react to over-current events. They are designed as open-drain outputs to easily setup a wired-AND configuration and allow monitoring of several current sensors outputs via only one microcontroller pin. OCD thresholdsThe symmetric threshold level of the OCD outputs is adjustable and triggers an over-current event in case of a positive or negative over-current. The possible threshold levels are listed in Table 6 and Table 7. The instruction for the settings is documented in the TLI4971 programming guide. OCD outputs timing behaviorBoth output pins feature a deglitch filter to avoid false triggers by noise spikes on the current rail. Deglitch filter settings can be programmed according to application needs. Available options are listed in Table 6 and Table 7.Figure 4 shows the OCD output pin typical behavior during an over-current event.Over-current Pulse 1: duration exceeds the over-current response time t D_OCDx + response time jitter Δt D_OCDx + deglitch filter time t deglitch. The OCD output voltage is set low until the current value drops below the OCD threshold.Over-current Pulse 2: duration does not exceed the over-current response time t D_OCDx and therefore no OCD event is generated.Over-current Pulse 3: duration exceeds the response time t D_OCDx + response time jitter Δt D_OCDx, but does not exceed the glitch filter time t deglitch and no OCD event is generated.Fast Over-Current Detection (OCD) Output ParametersTable 5 Common OCD Parameters2) Can be programmed by user.3) Pre-configured threshold level4) Time between primary current exceeding current threshold and falling edge of OCD1-pin at 50%.5) Not subject to production test. Verified by design and characterization.6) The specified deglitching timing is valid when input current step overtakes the threshold of at least 10%.2) Can be programmed by user.3) Pre-configured threshold level.4) Time between primary current exceeding current threshold and falling edge of OCD2-pin at 50%.5) Not subject to production test. Verified by design and characterization.6) The specified deglitching timing is valid when input current step overtakes the threshold of at least 10%.Undervoltage / Overvoltage detectionTLI4971 is able to detect undervoltage or overvoltage condition of its own power supply (V DD). When an undervoltage (V DD<U VLOH) or overvoltage (V DD>O VLOH) condition is detected both OCD pins are pulled down in order to signal such a condition to the user.The undervoltage detection on OCD pins is performed only if V DD > V DD,OCD.Both OCD pins are pulled down at start up. When V DD exceeds the undervoltage threshold U VLOH_R and the power on delay time t POR has been reached, the sensor indicates the correct functionality and high accuracy by releasing the OCD pins.Isolation CharacteristicsTLI4971 conforms functional isolation.2) After stress test according to qualification plan.3) Not subject to production test. Verified by design and characterization.4) Agency type tested for 60 seconds by UL according to UL 1577 standard.System integrationFor bandwidth limitation an external filter is recommended as shown in the above application circuits.Typical Performance CharacteristicsFigure 8 Typical error in sensitivity over temperature Figure 9 Typical offset drift over temperaturePackageThe TLI4971 is packaged in a RoHS compliant, halogen-free leadless package (QFN-like). PG-TISON-8 Package OutlineRevision HistoryMajor changes since the last revisionPublished byInfineon Technologies AG 81726 München, Germany © 2021 Infineon Technologies AG. All Rights Reserved.Do you have a question about this document?Email: ********************Document reference IMPORTANT NOTICEThe information given in this document shall in no event be regarded as a guarantee of conditions or chara cteristics (“Beschaffenheitsgarantie”) .With respect to any examples, hints or any typical values stated herein and/or any information regarding the application of the product, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party.In addition, any information given in this document is subject to customer’s compliance with its obligations stated in this document and any applicable legal requirements, norms and standards concerning customer’s products and any use of the product of Infineon Technologies in customer’s applications.The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document withFor further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( ).WARNINGSDue to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office.Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.Edition 12-02-2021----Trademarks of Infineon Technologies AGµHVIC™, µIPM™, µPFC™, AU -ConvertIR™, AURIX™, C166™, CanPAK™, CIPOS™, CIPURSE™, CoolDP™, CoolGaN™, COOLiR™, CoolMOS™, CoolSET™, CoolSiC™, DAVE™, DI -POL™, DirectFET™, DrBlade™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPACK™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, GaNpowIR™, HEXFET™, HITFET™, HybridPACK™, iMOTION™, IRAM™, ISOFACE™, IsoPACK™, LEDrivIR™, LITIX™, MIPAQ™, ModSTACK™, my -d ™, NovalithIC™, OPTIGA™, OptiMOS™, ORIGA™, PowIRaudio™, PowIRStage™, PrimePACK™, PrimeSTACK™, PROFET™, PRO -SIL™, RASIC™, REAL3™, SmartLEWIS™, SOLID FLASH™, SPOC™, StrongIRFET™, SupIRBuck™, TEMPFET™, TRENCHSTOP™, TriCore™, UHVIC™, XHP™, XMC™ Trademarks updated November 2015 Other Trademarks All referenced product or service names and trademarks are the property of their respective owners.。

Evaluation Board Manual for i7x Non-Isolated DC-DC

i7CxxC03-EVK-S1; i7AxxC01-EVK-S1 Evaluation Kit Manual for i7x Non-Isolated DC-DC SeriesContents1.Introduction (2)2.Ordering Information (2)3.General Features (3)4.Turn-on / Turn-off module by switch (4)5.Change Output Voltage (4)6.When use external clock (SYNC function) (4)7.Capture output ripple/noise waveform (4)8.Mechanical Outline (5)9.Schematic (6)10.PCB Layout (7)11.Parts List (9)1. IntroductionThis evaluation kit has been designed to provide an easy way to characterize the product performance and its features. It is intended to aid customers and determine the product suitability for the target application. The evaluation board incorporates the required external components to demonstrate the complete product functionality. It also includes other components (e.g. test points, etc…) to facilitate a successful end user experience. Not all these external components are required if the product features are not needed. Details of the external components, schematics, and PCB layout are provided in this documentation for reference only. Final design and qualification needs to be verified at customer’s end system level.2. Ordering InformationTDK-Lambda offers a wide variety of non-isolated dc-dc power modules in the i7X series. Not every product is currently available in an evaluation kit. The table below includes description and ratings which should help in selecting the most applicable evaluation kit.Evaluation Kit PartNumberNon-Isolated DC-DC Module(Included and Mounted on the Evaluation Board)DC-DC Module PartNumberType I/P Range O/P RangeO/P Current(max)O/P Power(Max)i7C08A-C03-EVK-S1 i7C4W008A120V-003-R Buck-Boost 9 – 53 V 9.6 – 48 V 8 A 300 Wi7C12A-C03-EVK-S1 i7C4W012A050V-003-R Buck-Boost 9 – 53 V 5.0 – 28 V 12.5 A 300 Wi7C20A-C03-EVK-S1 i7C2W020A120V-003-R Buck-Boost 9 – 36 V 8.0 – 24 V 20 A 300 Wi7A33A-C01-EVK-S1 i7A4W033A033V-001-R Buck 18 – 60 V 3.3 – 24 V 33 A 500 Wi7A45A-C01-EVK-S1 i7A24045A033V-001-R Buck 18 – 32 V 3.3 – 18 V 45 A 750 WIMPORTANT INFORMATION∙Observe proper safety and laboratory procedures when testing electronic products. This list serves as general guide only and not a substitute for common sense and best practices.∙Before applying power, double check and ensure all connections to the evaluation board interface are correct (e.g.Input source polarity connections, etc…).∙This evaluation board is not populated with an input fuse. An input fuse can be populated in pcb location F1. Check the product specifications for the input fuse ratings and the evaluation board schematics included this manual.Make sure the existing jumper connections, BB4 and BB5, are removed when adding the fuse.∙Although highly efficient, these high power density modules can dissipate significant amounts of power, especially at heavy load. Care should be taken to ensure adequate cooling is provided and the modules are operated within the thermal specifications outlined in the product data sheets. Heat sink and base plated versions of the i7X family are available for use in demanding environments.∙This evaluation kit is designed for general laboratory use. It is not intended for installation in end customer product or equipment.∙Please check the pertinent product (DC-DC Module) datasheets and specifications for complete information.3. General Features∙ Screw Terminals for secured input and output connections ∙ Toggle switch for Remote ON/OFF∙ Test points / Scope probe hook-ups for ease of measurement ∙ Trim Potentiometer for adjusting the output voltage setting∙Component PCB pad provisions for: Input fuse, input inductor, additional input and output capacitance*, Output header connector for optional features and signals.* Note the output capacitor value may need to be adjusted to meet transient response or ripple requirements of the final application. Refer to product data sheet for a range of acceptable values.Test Point DescriptionTest PointDescriptionTP1 Vin (+) TP8 SENSE + TP2 Vin (-) / GND TP9 PG (Power Good) TP3 Not Populated TP10 Vout (+) TP4 ON / OFF TP11 Vout (-) / GNDTP5 SYNC (Frequency Synchronization)TP12 Vout (+) - for Output Ripple MeasurementTP6I_MON (Output Current Monitor)TP13Vout (-) / GND – for Output Ripple MeasurementScrew Terminal DescriptionScrew Terminal DescriptionJ1 Vin (+) J3 Vout (+) J2Vin (-) / GNDJ4Vout (-) / GNDOUTPUT (+)INPUT (+)OUTPUT (-)INPUT (-)TP11VR1 (Vout Adjust)S1: On/Off SwitchTP4 TP5TP6TP2TP1TP9TP8TP10 J1J2J3J4TP12TP134. Turn-on / Turn-off module by switchChange position of toggle switch”S1” to “CLOSE” turns-on the powersupply unit.5. Change Output VoltageTurn screw on trimmer pot “VR1” to change the output voltage.Turn clockwise to decrease output voltage.Turn counter clockwise to increase output voltage.C.C.W.C.W.6. When using external clock (SYNC function)SYNC function default setting is disabled. Please removeresister ”R14” on bottom side of the board to enable theSYNC function.Remove R14When using sync7. Capture output ripple/noise waveformPlease use TP12, TP13 to measure output ripple/spike.Wired GND clip may pick up higher spike noise.To use bare probe minimize spike noise.Please pay attention for connect right polarity.TP12 is Vout(+) / TP13 is GND.recommend8. Mechanical Outline9. SchematicG e n e r a l S c h e m a t i c : C h e c k t h e a c c o m p a n y i n g p a r t s l i s t t h a t p e r t a i n s t o t h e a c t u a l E v a l u a t i o n K i t p a r t n u m b e r t o s e e w h i c h c i r c u i t c o d e s /c o m p o n e n t s a r e u s e d .10. PCB LayoutTop LayerLayer 2PCB Layout (continued) Layer 3Bottom11. Parts ListSchematic Circuit Code Part TypeManufacturer (Mfr)Mfr Part No.Manufacturer (Mfr)Mfr Part No.i7A_i7C DC-DC Module TDK Lambda i7C4W008A120V-003-R TDK Lambda i7C4W012A050V-003-R Q1OMIT OMIT OMIT C1Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C2Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C3Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C4-C18OMIT OMIT OMIT C19Capacitor NI-CHEMI EMHB630ARA361MLH0S NI-CHEMI EMHB630ARA361MLH0S C20-C22OMIT OMIT OMIT C23Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C24Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C25Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C26Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C27Capacitor MURATA GRM32ER71J106MA12L MURATA GRM32ER71J106MA12L C28-C34OMIT OMITOMITC35Capacitor NI-CHEMI EMHB630ARA361MLH0S NI-CHEMI EMHB630ARA361MLH0S C36Capacitor TDK C1608X7S2A104KT TDK C1608X7S2A104KT C37-C38OMIT OMITOMITC39Capacitor TDK C1608X7S2A104KT TDK C1608X7S2A104KT C40Capacitor TDK C1608X7S2A104KT TDK C1608X7S2A104KT F1OMITOMITOMITBB1Copper Pin ROWLEY SPRING ZP00185_01ROWLEY SPRING ZP00185_01BB2Copper Pin ROWLEY SPRING ZP00185_01ROWLEY SPRING ZP00185_01BB3OMITOMITOMITBB4Copper Pin ROWLEY SPRING ZP00185_01ROWLEY SPRING ZP00185_01BB5Copper Pin ROWLEY SPRING ZP00185_01ROWLEY SPRING ZP00185_01IC1OMIT OMIT OMIT VR1Resistor BOURNS 3266W-1-204LFBOURNS 3266W-1-503LFL1OMIT OMIT OMIT R1-R6OMIT OMIT OMIT R7Resistor KOA RK73Z1JTTDKOA RK73Z1JTTDR8Resistor KOA RK73H1JTTD21R5F KOA RK73H1JTTD3010F R9OMIT OMITOMITR10Resistor KOA RK73Z2ATTD KOA RK73Z2ATTDR11OMIT OMIT OMIT R12Resistor KOA RK73H1JTTD3323F OMIT R13OMIT OMIT OMIT R14Resistor KOA RK73Z1JTTDKOA RK73Z1JTTDR15Resistor KOA RK73H1JTTD1002D KOA RK73H1JTTD1002D CN1OMIT OMITOMITS1SwitchLIGHT COUNTRY 2US1T1A1M2RES LIGHT COUNTRY 2US1T1A1M2RES J1, J2, J3, J4Screw Terminal KEYSTONE 8196KEYSTONE 8196TP1Test Point: Vin(+)MAC8WT-2-2MAC8WT-2-2TP2Test Point: Vin(-)MAC8WT-2-2MAC8WT-2-2TP3OMITOMIT OMIT TP4Test Point: On/Off MAC8WT-2-2MAC8WT-2-2TP5Test Point: SYNC MAC8WT-2-2MAC8WT-2-2TP6Test Point: I_Mon MAC8WT-2-2MAC8WT-2-2TP8Test Point: SENSE+MAC8WT-2-2MAC8WT-2-2TP9Test Point: PG MAC8WT-2-2MAC8WT-2-2TP10Test Point: Vout(+)MAC8WT-2-2MAC8WT-2-2TP11Test Point: Vout(-)MAC8WT-2-2MAC8WT-2-2TP12Test Point: Vout(+)MAC8WT-2-2MAC8WT-2-2TP13Test Point: Vout(-)MAC8WT-2-2MAC8WT-2-2SCR1, SCR2, SCR3, SCR4Screw for J1, J2, J3, J4KEYSTONE 9427KEYSTONE 9427SO1, SO2, SO3, SO4StandoffKEYSTONE1902CKEYSTONE1902Ci7C08A-C03-EVK-S1i7C12A-C03-EVK-S1Evaluation Kit Part Number。

Richtek RT7296C 3A 同步步进下降电源说明书

RT7296C 3A, 17V Current Mode Synchronous Step-Down ConverterGeneral DescriptionThe RT7296C is a high-efficiency, 3A current mode synchronous step-down DC/DC converter with a wide input voltage range from 4.5V to 17V. The device integrates 80mΩhigh-side and 30mΩlow-side MOSFETs to achieve high efficiency conversion. The current mode control architecture supports fast transient response and internal compensation. A cycle-by-cycle current limit function provides protection against shorted output. The RT7296C provides complete protection functions such as input under-voltage lockout, output under-voltage protection, over-current protection, and thermal shutdown. The PWM frequency is adjustable by the EN/SYNC pin. The RT7296C is available in the TSOT-23-8 (FC) package. Ordering InformationG : Green (Halogen Free and Pb Free) RT7296CNote :Richtek products are :④RoHS compliant and compatible with the currentrequirements of IPC/JEDEC J-STD-020.④Suitable for use in SnPb or Pb-free soldering processes. Features● 4.5V to 17V Input Voltage Range●3A Output Current●Internal N-Channel MOSFETs●Current Mode Control●Fixed Switching Frequency : 1.4MHz●Synchronous to External Clock : 300kHz to 3MHz ●Cycle-by-Cycle Current Limit●External Soft-Start Function●Input Under-Voltage Lockout●Output Under-Voltage Protection●Thermal ShutdownApplications●Industrial and Commercial Low Power Systems●Computer Peripherals●LCD Monitors and TVs●Set-top BoxesMarking Information00= : Product CodeDNN : Date CodeSimplified Application CircuitEnableOUTV INRT7296CPin ConfigurationsS SS WG N D F BE N /S Y N CB O O TV I NP V C C(TOP VIEW)TSOT-23-8 (FC)Functional Pin DescriptionRT7296CFunction Block DiagramBOOTGNDSWFBOperationUnder Voltage Lockout ThresholdThe IC includes an input Under Voltage Lockout Protection (UVLO). If the input voltage exceeds the UVLO rising threshold voltage (3.9V), the converter resets and prepares the PWM for operation. If the input voltage falls below the UVLO falling threshold voltage (3.25V) during normal operation, the device stops switching. The UVLO rising and falling threshold voltage includes a hysteresis to prevent noise caused reset. Chip EnableThe EN pin is the chip enable input. Pulling the EN pin low (<1.1V) will shutdown the device. During shutdown mode, the RT7296C’s quiescent current drops to lower than 1μA. Driving the EN pin high (>1.6V) will turn on the device.Operating Frequency and SynchronizationThe internal oscillator runs at 1400kHz (typ.) when the EN/SYNC pin is at logic-high level (>1.6V). If the EN pin is pulled to low-level over 8μs, the IC will shut down. The RT7296C can be synchronized with an external clock ranging from 300kHz to 3MHz applied to the EN/SYNC pin. The external clock duty cycle must be from 20% to 80% with logic-high level = 2V and logic-low level = 0.8V. Internal RegulatorThe internal regulator generates 5V power and drive internal circuit. When VIN is below 5V, PVCC will drop with VIN. A capacitor (>0.1μF) between PVCC and GND is required. Soft-Start FunctionThe RT7296C provides external soft-start function. The soft-start function is used to prevent large inrush current while converter is being powered-up. TheRT7296Csoft-start timing can be programmed by the external capacitor between SS pin and GND. The Chip provides a 11μA charge current for the external capacitor. Over Current ProtectionRT7296C provides cycle-by-cycle over current limit protection. When the inductor current peak value reaches current limit, IC will turn off High Side MOS to avoid over current.Under Voltage Protection (Hiccup Mode)RT7296C provides Hiccup Mode of Under Voltage Protection (UVP). When the FB voltage drops below half of the feedback reference voltage, V FB , the UVP function will be triggered and the IC will shut down for a period of time and then recover automatically. The Hiccup Mode of UVP can reduce input current in short-circuit conditions. Thermal ShutdownThermal shutdown is implemented to prevent the chip from operating at excessively high temperatures. When the junction temperature is higher than 150︒C, the chip will shutdown the switching operation. The chip is automaticallyre-enabledwhenthejunctiontemperature cools down by approximately 20︒C.RT7296C Absolute Maximum Ratings(Note 1)●Supply Input Voltage, VIN ----------------------------------------------------------------------------------- -0.3V to 20V●Switch Voltage, SW-------------------------------------------------------------------------------------------- -0.3V to V IN + 0.3V<20ns--------------------------------------------------------------------------------------------------------------- -5V●BOOT to SW, V BOOT – SW ----------------------------------------------------------------------------------- -0.3V to 6V (7V for < 10μs) ●Bias Supply Output, PVCC---------------------------------------------------------------------------------- -0.3V to 6V (7V for < 10μs) ●Other Pins--------------------------------------------------------------------------------------------------------- -0.3V to 6V●Power Dissipation, P D @ T A = 25︒CTSOT-23-8 (FC) ------------------------------------------------------------------------------------------------ 1.428W●Package Thermal Resistance (Note 2)TSOT-23-8 (FC), θJA ----------------------------------------------------------------------------------------- 70︒C/WTSOT-23-8 (FC), θJC ----------------------------------------------------------------------------------------- 15︒C/W●Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------- 260︒C●Junction Temperature ----------------------------------------------------------------------------------------- -40︒C to 150︒C●Storage Temperature Range ------------------------------------------------------------------------------- -65︒C to 150︒C●ESD Susceptibility (Note 3)HBM (Human Body Model) --------------------------------------------------------------------------------- 2kV Recommended Operating Conditions(Note 4)●Supply Input Voltage, VIN --------------------------------------------------------------------------------------- 4.5V to 17V●Junction Temperature Range ---------------------------------------------------------------------------------------- -40︒C to 125︒C●Ambient Temperature Range ---------------------------------------------------------------------------------------- -40︒C to 85︒C Electrical Characteristics(V = 12V, T = 25︒C, unless otherwise specified)RT7296Cstress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability.Note 2. θJA is measured at T A= 25︒C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package.Note 3. Devices are ESD sensitive. Handling precaution recommended.Note 4. The device is not guaranteed to function outside its operating conditions.RT7296CTypical Application CircuitOUT 3.3VVNote : All input and output capacitance in the suggested parameter mean the effective capacitance. The effective capacitance needs to consider any De-rating Effect like DC Bias.Table 1. Suggested Component ValuesRT7296CTypical Operating CharacteristicsEfficiency vs. Output Current010203040506070809010000.51 1.52 2.53Output Current (A)E f f i c i e n c y (%)Output Voltage vs. Input Voltage3.143.183.223.263.303.343.383.423.46567891011121314151617Input Voltage (V)O u t p u t V ol t a g e (V )Reference Voltage vs. Temperature0.760.770.780.790.800.810.820.830.84-50-25255075100125Temperature (°C)R e f e r e n c e V ol t a g e (V )Output Voltage vs. Output Current3.143.183.223.263.303.343.383.423.4600.511.522.53Output Current (A)O u t p u t Vo l t a g e (V )UVLO Voltage vs. Temperature3.003.203.403.603.804.004.204.40-50-25255075100125Temperature (°C)U V L O V o l t a ge (V )EN Threshold vs. Temperature1.151.201.251.301.351.401.451.50-50-25255075100125Temperature (°C)E N T h r e s h o ld (V )RT7296CV IN = 12V, V OUT = 3.3V, L = 1.5μH,I OUT = 1.5A to 3A to 1.5AV OUT (50mV/Div)I OUT (1A/Div)Time (200μs/Div)Load Transient ResponseV IN = 12V, V OUT = 3.3V,L = 1.5μH,I OUT = 3AV OUT (20mV/Div)V LX (5V/Div)Time (1μs/Div)Output Ripple VoltageV IN = 12V, V OUT = 3.3V, I OUT = 3AV OUT (2V/Div)V EN (2V/Div)V LX (10V/Div)I LX (3A/Div)Time (2ms/Div)Power On from ENV IN = 12V, V OUT = 3.3V, I OUT = 3AV OUT (2V/Div)V EN (2V/Div)V LX (10V/Div)I LX (3A/Div)Time (2ms/Div)Power Off from ENV IN = 12V, V OUT = 3.3V, I OUT = 3AV OUT (2V/Div)V IN (10V/Div)V LX (10V/Div)I LX (3A/Div)Time (5ms/Div)Power On from VINV IN = 12V, V OUT = 3.3V, I OUT = 3AV OUT (2V/Div)V IN (10V/Div)V LX (10V/Div)I LX (3A/Div)Time (5ms/Div)Power Off from VINRT7296CApplication InformationThe RT7296C is a high voltage buck converter that can support the input voltage range from 4.5V to 17V and the input voltage range from 4.5V to 17V and the output current can be up to 3A. Output Voltage SelectionThe resistive voltage divider allows the FB pin to sense a fraction of the output voltage as shown in Figure 1.OUTFigure 1. Output Voltage SettingFor adjustable voltage mode, the output voltage is set by an external resistive voltage divider according to the following equation :OUT FB R1V V 1R2=+⎛⎫⎪⎝⎭Where V FB is the feedback reference voltage (0.807V typ.). Table 2 lists the recommended resistors value for common output voltages.External Bootstrap DiodeConnect a 100nF low ESR ceramic capacitor between the BOOT pin and SW pin. This capacitor provides the gate driver voltage for the high side MOSFET. It is recommended to add an external bootstrap diode between an external 5V and BOOT pin, as shown as Figure 2, for efficiency improvement when input voltage is lower than 5.5V or duty ratio is higher than 65% .The bootstrap diode can be a low cost one such as IN4148 or BAT54. The external 5V can be a 5V fixed input from system or a 5V output (PVCC) of the RT7296C.Figure 2. External Bootstrap DiodeExternal Soft-Start CapacitorRT7296C provides external soft-start function. The soft-start function is used to prevent large inrushcurrent while converter is being powered-up. The soft-start timing can be programmed by the external capacitor (C SS ) between SS pin and GND. The Chip provides a 11μA charge current (I SS ) for the external capacitor. The soft-start time (t SS , V REF is from 0V to 0.8V) can be calculated by the following formula :SS SS SS C (nF) 1.3t (ms) = I (A)μ⨯Inductor SelectionThe inductor value and operating frequency determine the ripple current according to a specific input and output voltage. The ripple current ∆I L increases with higher VIN and decreases with higher inductance.OUT OUT L IN V VI 1f L V ⎛⎫⎛⎫∆=⨯- ⎪ ⎪⨯⎝⎭⎝⎭Having a lower ripple current reduces not only the ESR losses in the output capacitors but also the outputvoltage ripple. High frequency with small ripple current can achieve highest efficiency operation. However, it requires a large inductor to achieve this goal.For the ripple current selection, the value of ∆I L = 0.3(I MAX ) will be a reasonable starting point. The largest ripple current occurs at the highest V IN . To guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation :OUT OUT L(MAX)IN(MAX)V V L 1f I V ⎛⎫⎛⎫=⨯- ⎪ ⎪ ⎪ ⎪⨯∆⎝⎭⎝⎭RT7296CThe inductor's current rating (caused a 40︒C temperature rising from 25︒C ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. C IN and C OUT SelectionThe input capacitance, C IN , is needed to filter the trapezoidal current at the source of the top MOSFET. To prevent large ripple current, a low ESR input capacitor sized for the maximum RMS current shouldbe used. The RMS current is given by :RMS OUT(MAX)I I 1= This formula has a maximum at V IN = 2V OUT , where I RMS = I OUT /2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief.Choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet size or height requirements in the design. The selection of C OUT is determined by the required Effective Series Resistance (ESR) to minimize voltage ripple. Moreover, the amount of bulk capacitance is also a key for C OUT selection to ensure that the control loop is stable. Loop stability can be checked by viewing the load transient response as described in a later section. The output ripple, ∆∆V OUT , is determined by :OUT L OUT 1V I ESR 8fC ⎛⎫∆≤∆⨯+⎪⎝⎭The output ripple will be highest at the maximum input voltage since ∆I L increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR and RMS current handling requirement. Dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. Special polymer capacitors offer very low ESR value. However, it provides lower capacitance density than other types. Although Tantalum capacitors have the highest capacitance density, it is important to only use types that pass the surge test for use in switching power supplies. Aluminum electrolytic capacitors have significantly higher ESR. However, it can be used in cost-sensitive applications for ripplecurrent rating and long term reliability considerations. Ceramic capacitors have excellent low ESR characteristics but can have a high voltage coefficient and audible piezoelectric effects. The high Q of ceramic capacitors with trace inductance can also lead to significant ringing. Thermal ConsiderationsFor continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : P D(MAX) = (T J(MAX) - T A ) / θJAwhere T J(MAX) is the maximum junction temperature, T A is the ambient temperature, and θJA is the junction to ambient thermal resistance.For recommended operating condition specifications, the maximum junction temperature is 125︒C. The junction to ambient thermal resistance, θJA , is layout dependent. For TSOT-23-8 (FC) package, the thermal resistance, θJA , is 70︒C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at T A = 25︒C can be calculated by the following formula :P D(MAX) = (125︒C - 25︒C) / (70︒C/W) = 1.428W for TSOT-23-8 (FC) packageThe maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA . The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation.RT7296CFigure 3. Derating Curve of Maximum PowerDissipationLayout ConsiderationsFor best performance of the RT7296C, the following layout guidelines must be strictly followed.Input capacitor must be placed as close to the IC as possible.SW should be connected to inductor by wide and short trace. Keep sensitive components away from this trace.Keep every trace connected to pin as wide as possible for improving thermal dissipation.SW should be connected to inductor by Wide andVia can help to reduce power trace and improve thermal dissipation.trace wider for thermal.Figure 4. PCB Layout Guide0.00.20.40.60.81.01.21.41.6255075100125Ambient Temperature (°C)M a x i m u m P o w e r D i s s i p a t i o n (W )RT7296C Outline DimensionTSOT-23-8 (FC) Surface Mount PackageRichtek Technology Corporation14F, No. 8, Tai Yuen 1st Street, Chupei CityHsinchu, Taiwan, R.O.C.Tel: (8863)5526789Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.。

LM3406HV评估板2线调节版说明书

User's GuideSNVA407B–August2009–Revised May2013 AN-1993LM3406HV Evaluation Board with2WireDimming1IntroductionThe LM3406HV is a buck regulator controlled current source designed to drive a series string of highpower,high brightness LEDs(HBLEDs)such as the Luxeon™K2Emitter at forward currents of up to1.5A.The converter's output voltage adjusts as needed to maintain a constant current through the LEDarray.plete Circuit SchematicAll trademarks are the property of their respective owners.Circuit Performance 2Circuit PerformanceThe LM3406HV circuit and BOM that come pre-installed on the evaluation board are optimized to run froman input voltage of24V,but the circuit can operate from a wide input voltage range of6.0V to75V.The current output ranges from0.35A to1.5A.Figure2shows the program jumper settings used to program currents of0.35A,0.7A,1A,and1.5A.Figure2.Setting Output Current,J2The LM3406HV is a step-down regulator with an output voltage range extending from a VO-MINof200mV(the reference voltage)to a VO-MAXdetermined by the ratio of the minimum off time(typically230ns)to the switching frequency.The regulator can maintain the output current through any number of LEDs as longas the combined forward voltage of the array does not exceed VO-MAX.VO-MAXcan be calculated with the following formula:VO-MAX=VIN-MINx(1-fSWx tOFF-MIN)(1)For example,if VINis24V±10%,then VIN-MINis21.6V.For a switching frequency of500kHz the maximum output voltage for the converter is21.6x[1-(5x105)x(230x10-9)=19.1V.Output voltage is calculated with the following formula:VO=n x VF+0.2Vwhere•n is the number of series-connected LEDs•VFis the forward voltage of each LED•0.2V represents the voltage across the current sense resistor(2)For InGaN LEDs(white,blue,blue-green)VFis typically3.5V,and with a limit of(19.1-0.2)=18.9V theLM3406HV could drive as many as five in series.For AlInGaP LEDs(red,orange,amber)VFis typically2.5V,so a VO-MAXof18.9V would allow as many as seven to be driven in series.3Connecting the LED ArrayThe LM3406HV Evaluation Board includes test posts for connecting the LED/LED Array.Connect theopen anode of the array to LED+and the cathode of the array to CS/LED-.Keep the leads from the board to the LED(s)as short as possible to minimize inductance.4Setting the LED CurrentThe default forward current IFdelivered to the LED array when no program jumper is installed on J2is0.35A,set by resistor R6.The higher LED currents are set when the program jumper puts resistors R4,R5or R7in parallel with R6.For users that wish to program a current other than one of the four default levels,or for users who want the best accuracy at a given current,the program jumper J2should beremoved,and R6changed according to the following equation:DIMI FTt+t =D SUD MIN 1=T PWMf T=t T - SDD MAX Pulse Width Modulation (PWM)DimmingR.35=0.2/I F(3)This resistor should be rated to handle the power dissipation of the LED current.For example,the closest 5%tolerance resistor to set an LED current of 0.35A is 0.56Ω.In steady state this resistor will dissipate (0.352x 0.56)=69mW,indicating that a resistor with a 1/8W rating is more than capable of dissipating the power.5Pulse Width Modulation (PWM)DimmingThe DIM1terminal on the PCB provides an input for a logic-level pulse width modulation signal for dimming of the LED array.In order to fully enable and disable the LM3406HV the PWM signal shouldhave a maximum logic low level of 0.8V and a minimum logic high level of 2.2V.Graphical representations of minimum and maximum PWM duty cycle are illustrated in Figure 3.The interval t D represents the delay from a logic high at the DIM pin to the rise in output current.The quantities t SU and t SD represent the time needed for the output current to slew up to steady state and slew down to zero,respectively.It isimportant to note that t D is a property of the LM3406HV and remains fixed in all applications.The slew rates t SU and t SD are a function of the external circuit parameters V IN ,V O ,I F ,inductance (L)and theLM3406HV parameter t OFF-MIN .Response times for a circuit driving three white LEDs at 1A from 24V are shown in the Typical Performance Characteristics section,but the user should test every new circuit to determine the actual PWM dimming response.Figure 3.PWM Dimming LimitsThe logic of DIM1is active low,hence the LM3406HV will deliver regulated output current when thevoltage at DIM1is high,and the current output is disabled when the voltage at DIM1is low.Connecting a constant logic low will disable the output.Note that an internal pullup esnures that the LM3406HV isenabled if the DIM pin is open-circuited.The DIM1function disables only the power MOSFET,leaving all other circuit blocks functioning to minimize the converter response time,t D .The DIM2terminal provides a second method for PWM dimming by connecting to the gate of MOSFET Q1through the driver U5.Q1provides a parallel path for the LED current.Shunting the output current through a parallel MOSFET reduces the PWM dimming delays because the inductor current remains continuous,providing faster response time for higher frequency and/or greater resolution in the PWM dimming signal.The trade-off in this method is that the full current flows through Q1while the LED is off,resulting in lower efficiency.The LM3406HV evaluation board includes an output capacitor to reduce output current ripple which is not initially populated,but the drawback of this output capacitor if used is that it causes significant delays when using parallel MOSFET dimming.The output capacitor should be removed to take full advantage of parallel MOSFET dimming.D2O2Wire Input Dimming The logic of DIM2is active low,hence the regulated output current flows through the LED array when the voltage at DIM2is high,and the current flows through the shunt FET when the voltage at DIM2is low.Connecting a constant logic low to the DIM2will turn off the LED but will not shut down the LM3406HV.A voltage of up to 30V must be applied to the DPWR pin to operate U5.62Wire Input DimmingThe LM3406HV evaluation board has been designed for 2wire dimming for systems that present a square wave input voltage for dimming purposes.A diode,D2,separates the VIN pins from the VINS pin.When the input voltage at VINS falls to 70%or less of the voltage at VIN the device stops switching and enters dim mode.The capacitors C1and C2hold up the voltage at the VIN pins during this time so that theLM3406HV is enabled and responds quickly when the voltage at VINS again exceeds 70%of the voltage at VIN.7Low Power ShutdownThe LM3406HV can be placed into a low power shutdown (typically 240µA)by grounding the OFF*terminal.During normal operation this terminal should be left open-circuit.8Output Open CircuitThe LM3406HV will begin to operate as soon as VIN is greater than 6V and the DIM and RON pins are not grounded.If the regulator is powered and enabled but no LED array is connected,the output voltage will rise to V IN .The output of the circuit is rated to 50V (beyond the maximum input voltage)and will not suffer damage,however care should be taken not to connect an LED array if the output voltage is higher than the target forward voltage of the LED array in steady state.If the LEDs are disconnected or one of the LEDs fails open-circuit while the LM3406HV is operating,the output voltage will experience a surge as the current in the output inductor seeks a discharge path.The output capacitor (if present)can absorb some of this energy,however circuits with little or no output capacitance can experience a voltage spike that exceeds the rating of the VOUT pin.The evaluationboard uses a 10k Ωresistor in series with the VOUT pin to limit current flowing into the pin.Alternatively,a diode connected from V IN to V O as shown in Figure 4will clamp the spike to V IN plus a diode drop and is included on the evaluation board.Figure 4.Schottky Diode Protection for Open-Circuit Bill of Materials 9Bill of MaterialsID Part Number Type Size Parameters Qty VendorU1LM3406HV Buck LED TSSOP-1475V,1.5A1NSCDriverU5FDC6333C MOSFET N-SSOT-630V,2.5A1FairchildCH/P-CH Semiconductor D1B1100-13-F Schottky Diode SMA100V,1A1Diodes Inc.D2,D3MBRS3100T3G Schottky Diode SMC100V,3A2ONSemiconductor Q1SI4464DY-E3MOSFET SOIC-8200V,1.7A1VishayC1C2C5750X7R2A475M Capacitor2220 4.7µF,100V2TDKC3GRM188R71C223K01D Capacitor06030.022µF,16V1MurataC4,C5,GRM188R71C104K01D Capacitor06030.1µF,16V3MurataC7C6Capacitor1812OPENL1MSS1038–333MLB Inductor MSS103833μH,1.8A1CoilcraftR1CRCW0805143kFKA Resistor0805143kΩ1%1VishayR2CRCW06031K00JNEA Resistor06031kΩ5%1VishayR3CRCW060310k0FKA Resistor060310kΩ1%1VishayR4ERJ-6RQFR30V Resistor08050.3Ω1%1PanasonicR5ERJ-6RQFR16V Resistor08050.16Ω1%1PanasonicR6ERJ-6RQFR56V Resistor08050.56Ω1%1PanasonicR7ERJ-6RQFR62V Resistor08050.62Ω1%1Panasonic R8,R9CRCW06031R00FNEA Resistor06031Ω1%2VishayCS/LED-1502–2Terminal Keystone1598–28Keystone ,DIM1,DIM2,DPWR,GND2,LED+,OFF*,SWVIN,575–8Terminal575–82KeystoneGNDINPUT VOLTAGE (V)O U T P U T C U R R E N T (A )Typical Performance Characteristics 10Typical Performance CharacteristicsV IN =24V,I F =1A,T A =25°C,and the load consists of three InGaN LEDs in series unless otherwise noted.Efficiency vs.Efficiency vs Number of InGaN LEDs in SeriesOutput CurrentI F vs I F vs V INT A2 és/DIV F0.5A/DIV20V/DIV5V/DIV2 és/DIVDIM1SWI F0.5A/DIV20V/DIV5V/DIV1 és/DIVSWF0.5A/DIV10V/DIV1 és/DIVF20 mA/DIV INPUT VOLTAGE (V)S W I T C H I N G F R E Q U E N C Y (k H z )Typical Performance CharacteristicsSwitching Frequency vs Switching Frequency vsNumber of InGaN LEDs in SeriesV INSwitch Node and Output Current (DC Coupled)Output Current (AC Coupled)DIM1Response (Rising)DIM1Response (Falling)2 ms/DIV OFFSWF0.5A/DIV20V/DIV2V/DIV2 és/DIVF0.5A/DIV20V/DIV2V/DIVTypical Performance CharacteristicsStart Up using OFF TerminalShutdown using OFF Terminal Layout 11LayoutFigure5.Top Layer and Top OverlayLayout Figure6.Bottom Layer and Bottom OverlayIMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46,latest issue,and to discontinue any product or service per JESD48,latest issue.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its components to the specifications applicable at the time of sale,in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by applicable law,testing of all parameters of each component is not necessarily performed.TI assumes no liability for applications assistance or the design of Buyers’products.Buyers are responsible for their products and applications using TI components.To minimize the risks associated with Buyers’products and applications,Buyers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any patent right,copyright,mask work right,or other intellectual property right relating to any combination,machine,or process in which TI components or services are rmation published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of significant 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ROHM BD71847AMWV应用说明书

12 BUCK Could BUCK6 act as a switch? Could it BUCK6 supports 100% max duty but there is the limitation for input
work in 100% duty cycle?
range described as "headroom" in the datasheet.
2. Terminologies
Term DCR DDR I2C LDO PFM PMIC PWM RTC PWM SoC UVLO VR
Definition DC Resistance Double Data Rate Inter-Integrated Circuit Low Dropout Pulse-Frequency Modulation Power Management Integrate Circuit Pulse-Width Modulation Real-Time Clock Pulse-Width Modulation System-on-Chip Under Voltage Lock Out Voltage Regulator
response are acceptable, 0.47uH can be an option.
2
I2C
What is the I2C device/slave address of The device address is 0x4B.
PMIC?
Please refer to Figure4-3 of I2C Device Addressing of the datasheet.
4 Product What is the difference between

ANALOG DEVICES AN-1149 数据手册

AN-1149APPLICATION NOTEOne Technology Way • P .O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • How to Apply DC-to-DC Step-Down/Step-Up (Buck/Boost) Regulatorsby Ken MarascoINTRODUCTIONDC-to-DC switching converters are used to change one dc voltage to another efficiently. High efficiency dc-to-dcconverters come in three basic topologies: step-down (buck), step-up (boost), and step-down/step-up (buck/boost). The buck converter is used to generate a lower dc output voltage, the boost converter is used to generate a higher dcoutput voltage, and the buck/boost converter is used to generate an output voltage less than, greater than, or equal to the input voltage.This application note focuses on how to successfully apply buck/boost dc-to-dc converters. Buck and boost converters are described individually in the AN-1125 Application Note , How to Apply DC-to-DC Step-Down (Buck) Regulators , and the AN-1132 Application Note , How to Apply DC-to-DC Step-Up (Boost) Regulators . Figure 1 shows a typical low power system powered from a single-cell lithium ion (Li-Ion) battery. The battery’s usable output varies from about 3.0 V when discharged to 4.2 V when fully charged. The system ICs require 1.8 V , 3.3 V , and 3.6 V for optimum operation. Whereas the lithium ion battery starts at 4.2 V and ends at 3.0 V , a buck/boost regulator can supply a constant 3.3 V , and a buck regulator or low dropout (LDO) regulator can supply 1.8 V , as the battery discharges. A buck regulator or LDO can conceivably be used for the 3.3 V while the battery voltage is above 3.5 V , but the system would cease to operate when the battery voltage drops below 3.5 V . Allowing the system to be turned off prematurely reduces the system’s operating time before the battery must be recharged.Figure 1. Typical Low Power Portable System10542-001AN-1149 Application Note TABLE OF CONTENTSIntroduction (1)Revision History (2)Buck/Boost Regulators (3)Buck/Boost Regulators Improve System Efficiency (5)Buck/Boost Regulator Key Specifications and Definitions (6)Output Voltage Range Options (6)Ground or Quiescent Current (6)Shutdown Current (6)Soft Start (6)Switching Frequency (6)Thermal Shutdown (TSD) (6)Buck/Boost DC-to-DC Switching Converters Operate atMHz (7)Conclusion (8)References (8)REVISION HISTORY4/12—Revision 0: Initial VersionApplication NoteAN-1149BUCK/BOOST REGULATORSBuck/boost regulators contain four switches, two capacitors, and an inductor, as shown in Figure 2. Current low power, high efficiency buck/boost regulators reduce losses and improve efficiency by actively operating only two of the four switches when operating in buck or boost mode.When V IN is greater than V OUT , Switch C is open and Switch D is closed. Switch A and Switch B operate as in a standard buck regulator, as shown in Figure 3.When V IN is less than V OUT , Switch B is open and Switch A is closed. Switch C and Switch D operate as in a boost regulator, as shown in Figure 4. The most difficult operating mode is when V IN is in the range of V OUT ± 10% and the regulator enters the buck/boost mode. In buck/boost mode, the two operations, buck and boost, take place during a switching cycle. Care must be taken to reduce losses, optimize efficiency, and eliminate instability due to mode switching. The objective is to maintain voltage regulation with minimal current ripple in the inductor to guarantee good transient performance.At high load currents, the buck/boost uses voltage or current-mode, fixed frequency pulse-width modulation (PWM) control for optimal stability and transient response. To ensure thelongest battery life in portable applications, a power save mode reduces the switching frequency under light load conditions. For wireless and other low noise applications where variable-frequency power save mode may cause interference, theaddition of a logic control input to force fixed frequency PWM operation under all load conditions is included.Figure 2. Buck/Boost Converter TopologyFigure 3. Buck Mode When V IN > V OUTV IN 10542-002V INV OUTV INI I I LOADt V IN IN BUCK MODE SWITCH C IS OPEN AND SWITCH D IS CLOSED.10542-003AN-1149Application NoteFigure 4. Boost Mode When V IN < V OUTV INV INOUT V INI I I V ININ BOOST MODE SWITCH B IS OPENAND SWITCH A IS CLOSED.10542-004LOADApplication Note AN-1149 BUCK/BOOST REGULATORS IMPROVE SYSTEM EFFICIENCYA large number of the portable systems in use today are pow-ered by a single-cell rechargeable Li-Ion battery. The battery starts from a fully charged 4.2 V and slowly discharges down to 3.0 V. When the battery output drops below 3.0 V, the system turns off to protect the battery from damage due to extreme discharging. When a low dropout regulator is used to generate a 3.3 V rail, the system shuts down atV IN MIN = V OUT + V DROPOUT = 3.3 V + 0.2 V = 3.5 Vusing only 70% of the battery’s stored energy. However, using a buck/boost regulator such as the ADP2503 or ADP2504 enables the system to continue operating down to the minimum practi-cal battery voltage. The ADP2503 and ADP2504 (see the Buck/Boost DC-to-DC Switching Converters Operate at 2.5 MHz section) are high efficiency, low quiescent current, 600 mA and 1000 mA, step-down/step-up (buck/boost) dc-to-dc converters that operate with input voltages greater than, less than, or equal to the regulated output voltage. The power switches are internal, minimizing the number of external components and thus reducing printed circuit board (PCB) area. This approach allows the system to operate all the way down to 3.0 V, using most of the battery’s stored energy and increasing the system’s operating time before a battery recharge is required.To save energy in portable systems, various subsystems, such as the microprocessor, display backlighting, and power amplifiers, when not in use, are frequently switched between full power-on and sleep mode, which can induce large voltage transients on the battery supply line. These transients can cause the battery’s output voltage to briefly drop below 3.0 V and trigger the low battery warning, causing the system to turn off before the bat-tery is completely discharged. The buck/boost solution tolerates voltage swings as low as 2.3 V, helping to maintain the system’s potential operating time.AN-1149 Application Note BUCK/BOOST REGULATOR KEY SPECIFICATIONS AND DEFINITIONSOUTPUT VOLTAGE RANGE OPTIONSBuck/boost regulators are available with specified fixed output voltages or in an option that allows the output voltage to be programmed via an external resistance divider. GROUND OR QUIESCENT CURRENTGround current is the dc bias current not available for the load (I Q). The lower the I Q is, the better the efficiency, but I Q can be specified under many conditions, including switched off, zero load, pulse frequency modulation (PFM), and pulse-width modulation (PWM) operation. It is, therefore, best to examine operating efficiency at specific operating voltages and load currents when determining the best boost regulator for the application.SHUTDOWN CURRENTShutdown current is the input current consumed when the enable pin has been set to off. Low I Q is important for long standby times when a battery-powered device is in sleep mode. During logic controlled shutdown, the input is disconnected from the output and draws less than 1 μA from the input source. SOFT STARTIt is important to have a soft start function that ramps the output voltage in a controlled manner to prevent excessive output voltage overshoot at startup.SWITCHING FREQUENCYLow power buck/boost converters generally operate between 500 kHz and 3 MHz. Higher switching frequencies allow the use of smaller inductors and reduce the required PCB area, but efficiency is decreased by approximately 2% for every doubling of the switching frequency.THERMAL SHUTDOWN (TSD)If the junction temperature rises above the specified limit, the thermal shutdown circuit turns the regulator off. Consist-ently high junction temperatures can be the result of high current operation, poor circuit board cooling, and/or high ambient temperature. The protection circuit includes hysteresis so that, after thermal shutdown, the device does not return to normal operation until the on-chip temperature drops below the preset limit.Application Note AN-1149 BUCK/BOOST DC-TO-DC SWITCHING CONVERTERS OPERATE AT 2.5 MHZThe ADP2503 and ADP2504 are high efficiency, low quiescent current step-up/step-down dc-to-dc converters that can operate at input voltages greater than, less than, or equal to the regu-lated output voltage. The power switches and synchronous rectifiers are internal to minimize external part count. At high load currents, they use a current-mode, fixed frequency pulse-width modulation (PWM) control scheme for optimal stability and transient response. To ensure the longest battery life in portable applications, the devices have an optional power save mode that reduces the switching frequency under light load conditions. For wireless and other low noise applications where a variable frequency power save mode may cause interference, the logic control input sync forces fixed frequency PWM operation under all load conditions.The ADP2503 and ADP2504 can run from input voltages between 2.3 V and 5.5 V, allowing a single lithium or lithium polymer cell, multiple alkaline or NiMH cells, PCMCIA, USB, and other standard power sources. Various fixed output options are available, or, using the adjustable model, the output voltage can be programmed through an external resistor divider. Compensation is internal to minimize the number of external components.AN-1149 Application Note CONCLUSIONLow power buck/boost regulators with proven performance and in-depth support take the worry out of designs using switching dc-to-dc converters. In addition to a comprehensive ADP2503/ ADP2504 data sheet with design calculations available, the ADIsimPower™ design tool simplifies the task for the end user. Regulator selection guides, data sheets, and application notes can be found at /power-management.For help, visit EngineerZone™ at , or phone or email an application engineer at Analog Devices. REFERENCESMarasco, Ken. AN-1125 Application Note. How to Apply DC-to-DC Step-Down (Buck) Regulators. Analog Devices, Inc., 2011.Marasco, Ken. AN-1132 Application Note. How to Apply DC-to-DC Step-Up (Boost) Regulators. Analog Devices, Inc., 2011.Marasco, Ken. AN-1072 Application Note. How to Successfully Apply Low-Dropout Regulators. Analog Devices, Inc., 2010. /ADIsimPower/power-management/switching_controllers/switching-regulators©2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.AN10542-0-4/12(0)。

AP22615 AP22815-EVM Application Note AP22615 AP228

Application NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability is DescriptionThe AP22815/615 is a 3A single channel current-limited high-side power switch with output OVP optimized for USB and other hot-swap applications which need to have over voltage protection from output to protection the system. The AP22815/615 complies with USB standards and is available with both polarities of Enable input. AP22815 supports fixed current-limited feature, while AP22615 equips adjustable current-limited feature optimized for applications that require precision current limiting support. It supports USB PD3.0 fast role swap function. The output voltage could recovery to USB valid voltage range within 110us during USB PD fast role swap event.The device has fast short-circuit and output over-voltage response time for improved overall system robustness. Both TSOT25 and TSOT26 packages integrate discharge circuitry inside OUT pin. They provide a complete protection solution for applications subject to heavy capacitive loads and the prospect of short circuit, and offer output over-voltage protection, reverse current blocking, over-current, over-temperature and short-circuit protection, as well as controlled rise time and under-voltage lockout functionality. A 7ms deglitch capability on the open-drain Flag output prevents false over-current/over-voltage/over-temperature reporting and does not require any external components.The AP22815 is available in a standard Green TSOT25 packages with RoHS compliant. TheAP22615 is available in a standard Green TSOT26 packages with RoHS compliant.Applications∙Integrated Load Switches in Ultrabook PC ∙ Power Up/Down Sequencing in Ultrabook PC ∙ Notebook, Netbook, Tablet PC, Set-Top Box ∙ SSD (Solid State Drives) ∙ Consumer Electronics ∙USB Charger∙ Telecom SystemsFeatures∙ Input Voltage Range: 3.0V ~ 5.5V ∙ 40mΩ on -resistance∙ Built-in soft-start with 2.1 ms typical rise time ∙ Fault report (FLG) with blanking time (7ms typ) ∙ Accurate Adjustable Current Limit, 0.4A~4.0A (AP22615 only)∙ ESD protection: 2KV HBM, 200V MM ∙ Active low or active high enable∙Protection▪ Output Over-Voltage with Auto Recovery ▪ Over Current with Auto Recovery ▪ Short Circuit with Auto Recovery▪ Over temperature with Auto Recovery ∙ Output Reverse Voltage Protection ∙ Fast Role Swap function∙ Thermally Efficient Low Profile Package ∙ Totally Lead-Free & Fully RoHS compliant (Notes 1 & 2)∙ Halogen and Antimony Free. “Green” Device (Note 3)∙ UL Recognized, File Number E322375 ∙ IEC60950-1 CB Scheme CertifiedNotes: 1. No purposely added lead. Fully EU Directive2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant. 2. See /quality/lead_free.html formore information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green" and Lead-free. 3. Halogen- and Antimony-free "Green” products aredefined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and <1000ppm antimony compounds.Application NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability isTypical Applications CircuitFor AP228153.0V to 5.5VFor AP226153.0V to 5.5VNote: If applying 1µF input capacitor will lead to large V IN spike, it’s recommended to use 10µF capacitor instead.Application NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability isEvaluation BoardAP22615AWU, R LIM =6.8k Ω AP22615BWU, R LIM =6.8k ΩAP22815AWT AP22815BWTApplication NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability is Quick Start GuideThe AP22615/AP22815(Power Switch) evaluation modules (EVM) provide a means for the user to evaluate quickly the functionality and electrical performance of the AP22615/AP22815 device. All inputs and outputs are brought out to test points for control and monitoring. All passive components are included on the EVM for device operation. The input pin should be connected to an external supply; the output should be connected to a load.1. Connect a +5V power supply between IN and GND terminals.2. Connect an adjustable current or resistive load to OUT1 and GND terminals.3. Turn on the power supply.4. Increase the load current of OUT and observe that the load current will stop increasing after reaching certain level. That is an indication that the device is limiting the load current.5.Use an oscilloscope or a voltage meter to check that FLAG pin become low when the current limit is reached.Evaluation Board SchematicFor AP22615AWUFor AP22615BWUApplication NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability is Evaluation Board SchematicFor AP22815AWTFor AP22815BWT(T)SOT25/26(T)SOT25/26Application NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability is Bill of MaterialsFor AP22615AWUFor AP22615BWUApplication NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability is Bill of MaterialsFor AP22815AWTApplication NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability isVendors of peripheral componentsSuggested Capacitors ：Suggested Resistor ：Application NoteAP22615/AP22815 Application Information and Demo Board User GuideThis application note contains new product information. Diodes, Inc. reserves the right to modify the product specification without notice. No liability isIMPORTANT NOTICEDIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on Diodes Incorporated website, harmless against all damages.Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales channel.Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and markings noted herein may also be covered by one or more United States, international or foreign trademarks.This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is the final and determinative format released by Diodes Incorporated.LIFE SUPPORTDiodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:A. Life support devices or systems are devices or systems which: 1. are intended to implant into the body, or2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in significant injury to the user.B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause thefailure of the life support device or to affect its safety or effectiveness.Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems, and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices- or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life support devices or systems.Copyright © 2020, Diodes Incorporated。

PWM 等电源管理 PCB Layout Guidelines

SIMPLE SWITCHER ®PCB Layout GuidelinesIntroductionOne problem with writing an Application Note on PCB layout is that the people who read it are usually not the ones who are going to use it.Even if the designer has struggled through electromagnetic fields,EMC,EMI,board parasitics,transmission line effects,grounding,etc.,he will in all prob-ability then go on with his primary design task,leaving the layout to the CAD/layout person.Unfortunately,especially when it comes to switching regulators,it is not enough to be concerned with just basic routing/connectivity and mechani-cal issues.Both the designer and the CAD person need to be aware that the design of a switching power con-verter is only as good as its layout.Which probably ex-plains why a great many of customer calls received,con-cerning switcher applications,are ultimately traced to poor layout practices.Sadly,these could and should have been avoided on the very first prototype board,saving time and money on all sides.The overall subject of PCB design is an extremely wide one,embracing several test/mechanical/production issues and also in some cases compliance/regulatory issues.There is also a certain amount of physics/electromagnetics involved,if a clearer understanding is sought.But the purpose of this Application Note is to reach the audience most likely to use it.Though there is enough design information for the moreexperienced designer/CAD person,the Application Note in-cludes a quick-set of clear and concise basic rules that should be scrupulously followed to avoid a majority of prob-lems.In particular,we have provided recommended start-ing points for layout when using the popular LM267x,LM259x and LM257x families (Figure 2)The focus is on the step-down (Buck)Simple Switcher ICs from National,but the same principles hold for any topology and switching power application.Most of the issues discussed in this Note revolve around simply assuring the desired performance in terms of basic electrical functionality.Though luckily,as the beleaguered switcher designer will be happy to know,in general all the electrical aspects involved are related and point in the same general ‘direction’.So for example,an ‘ideal’layout,i.e.one which helps the IC function properly,also leads to reduced electromagnetic emissions,and vice-versa.For example,reducing the area of loops with switching currents will help in terms of EMI and performance.However the designer is cautioned that there are some exceptions to this general ’trend’.One which is brought out in some detail here is the practice of ’copper-filling’,which may help reduce parasitic inductances and reduce noise-induced IC problems,but can also increase EMI.Quick-Set of Rules for SIMPLE SWITCHER PCB Layout (Buck)a)Place the catch diode and input capacitor as shown in Figure 2.b)For high-speed devices (e.g.LM267x)do not omit placing input decoupling/bypass ceramic capacitor (0.1µF–0.47µF)as in Figure 2.c)Connect vias to a Ground plane if available (optional,marked ‘X’in Figure 2)d)If vias fall under tab of SMT power device,these are considered ‘thermal vias’.Use correct dimensions as discussed to avoid production issues.Or place the vias close to but not directly under the tab.e)Route feedback trace correctly as discussed,away from noise sources such as the inductor and the diode.f)Do not increase width of copper on switching node injudiciously.g)If very large heatsink area is required for catch diode (having estimated the heatsink requirement correctly)use isolation as discussed.h)For higher power SMT applications,use 2oz board for better thermal management with less copper area.SIMPLE SWITCHER is a Registered Trademark of National Semiconductor.National Semiconductor Application Note 1229Sanjaya Maniktala July 2002SIMPLE SWITCHER PCB Layout GuidelinesAN-1229©2002National Semiconductor Corporation Introduction(Continued)The AC and DC Current PathsReferring to Figure 1a ,the bold lines represents the main (power)current flow in the converter during the time the switch is ON.As the switch turns ON,the edge of the of the current waveform is provided largely by CBYPASS,the re-mainder coming mainly from CIN.Some slower current com-ponents come from the input DC power supply (not shown)and also refresh these input caps.Figure 1b represents the situation when the switch is OFF.We can therefore see that in certain trace sections,current has to start flowing sud-denly during the instant of switch turn-off and in some sec-tions it needs to stop flowing equally suddenly.Figure 1c represents the ‘difference’,i.e.traces shown bold in this Figure are those where the current flow changes suddenly .During the turn-on transition the picture reverses,but the ’difference’trace sections are the same.Therefore during either switch transition,’step changes’of current take place in these difference sections.These traces encounter the harmonic-rich rising or trailing edges of the current pedestal waveform.The difference traces are considered ’critical’and deserve utmost attention during PCB layout.It is often stated colloquially,that ‘AC current’flows in these trace sections,and ’DC current’in the others.The reason is that the basic switching PWM frequency forms only a fraction of the total harmonic (Fourier)content of the current waveform in the ’AC’traces.In comparison,where ‘DC current’flows,the current does not change in a stepped fashion and so the harmonic content is lower.It is also no surprise that the DC20042601FIGURE 1.A N -12292The AC and DC Current Paths (Continued)sections are those in series with the main inductor,because it is known that inductors have the property of preventing sudden changes in current(this is analogous to a capacitor which‘resists’sudden changes in voltage).Summing up:In switching regulator layout,it is the AC paths that are considered critical,whereas the DC paths are not.That is the only basic rule to be kept in mind, and from which all the others follow.This is also true for any topology.Perform an analysis of the current flow for any topology in the same manner as we did for the Buck,to find the’difference traces’:and these traces are by defintion the’critical’ones for layout.What is the problem with step current changes anyway?In a resistor for example,this causes no unexpected/ unidentifiable problem.The voltage is given by V=IR,and so for a given change of current,the voltage will change pro-portionally.For example,a0.5cm wide Cu trace of thick-ness1.4mil has a resistance of1milliohm per cm length (at20degC).So it seems that a1inch long trace with a current changeover of1A,would produce a change in volt-age of only2.5millivolts across the trace,which is insignifi-cant enough to cause the control sections of most ICs to misbehave.But in fact the induced voltage is much larger. The important thing to realize is that traces of copper on a PCB,though barely resistive,are also inductive.Now,the oft-repeated thumb-rule is that‘every inch of trace length has an inductance of about20nH’.Like the trace resis-tance,that too doesn’t seem much at first sight.But it is this rather minute inductance which is in fact responsible for a great many customer calls in SIMPLE SWITCHER applica-tions!The equation for voltage across an inductance is V=L*dl/dt, and so the voltage does not depend on the current but on the rate of change of the current.This fact makes all the differ-ence when the1A change we spoke about occurs within a very short time.The induced voltage can be very high,even for small inductances and currents,if the dl/dt is high.A high dl/dt event occurs during transition from Figure1a to Figure 1b(and back)in all the AC trace sections(shown bold in Figure1c).The induced voltage spike appears across each affected trace,lasting for the duration of the crossover.To get a better feel for the numbers here:the change in current in the AC sections of a typical buck converter is about 1.2times the load current during the switch turn-off transition and is about0.8times the load current during the switch turn-on transition(for an’optimally’designed Buck inductor,as per inductor design guidelines in the relevant Datasheets/Selection Software).The transition time is about30ns for high speed Fet switchers like the LM267x,and is about75ns for the slower bipolar switchers like the LM259x series.This also incidentally means that the voltage spikes in the high-speed families can be more than twice that in the slower families,for a comparable layout and load.Therefore layout becomes all the more critical in high-speed switchers.So,one inch of trace switching say1A of instantaneous current in a transition time of30ns gives0.7V,as compared to 2.5mV(that we estimated on the basis of resistance alone).For3A,and two inches of trace,the induced voltage ’tries’to be4V!In Figure1c,the small triangles along the sections indicate the direction of the momentary induced voltage,as the converter changes from the situation in Fig-ure1a to that in Figure1b(switch turn-off).We can see thatassuming that the ground pin of the IC is the reference point,the switching node(marked‘SW’)tries to go negative(all itsseries trace sections adding up).Similarly the input pin(marked‘VIN’goes high through series contributions in all itsrelated sections.Figure1c represents the picture during theturn-off transition.During the turn-on transition all the in-duced voltage polarities shown are simply reversed.In thatcase,the VIN pin is dragged low,and the switching node pinis dragged high momentarily.The astute designer will recognize that this was to be ex-pected since any inductance,even if it is parasitic,demandsto be‘reset’,which means that the volt-seconds during theon-time must equal and be opposite in sign to thevolt-seconds during the off-time.The designer will also real-ize that till these parasitic trace inductances reset,they donot’allow’the crossover to occur.So for example,traceswhich were carrying current prior to switch turn-off will’insist’on carrying current till the voltage spikes force them to dootherwise.Similarly,the traces which need to start carryingcurrent will’refuse’to do so till the spikes across them forcethem to do likewise.Since switching losses are proportionalto crossover time,even if these voltage spikes do not causeanomalous behavior,they can degrade efficiency.For ex-ample,in transformer-based flyback regulators,when the theprimary number of turns is much larger than the secondaryturns,designers may be surprised to learn how much thesecondary side trace inductances alone can degrade effi-ciency.This is because any secondary side uncoupled(trace/transformer leakage)inductances reflect into theprimary side as an equivalent parasitic inductance inseries with the switch.This adds an additional term tothe effective leakage as seen by the switch that equalsthe secondary inductance multiplied by square of theturns ratio(turns ratio being Np/Ns).Therefore the dissipa-tion in the flyback clamp(zener/RCD)can increase dramati-cally,lowering efficiency.One lesson here is that though’leakage inductance’(from traces or the transformer)is con-sidered’uncoupled’,in reality it can make its presence se-verely felt from one side of the transformer to the other.So itis not totally’uncoupled’at all!In fact this happens to be themain reason why flybacks with low output voltages(highturns ratio)show poorer efficiency as compared to higheroutput flybacks.Therefore,reducing critical trace induc-tances is important for several reasons:efficiency,EMI,be-sides basic functionality.The momentary voltage spikes which last for the duration ofthe transition can be very hard to capture on an oscilloscope.But they may be presumed to be present if the IC is seen tobe misbehaving for no’obvious reason’.These spikes,ifpresent with sufficiently high amplitude,can propagate intothe control sections of the IC causing what we call here acontroller’upset’.This leads to the observed performanceanomalies,and in rare cases this can even cause devicefailure.Since none of these spike-related problems can beeasily corrected,or band-aided,once the layout is initiallybad,the important thing is to get the layout‘right’to startwith.The designer may well ask,why is it that these step currentchanges are a problem with the parasitic trace inductances,and not with the main inductor of the Buck converter?That isbecause all inductors try to resist any sudden currentchange.But since the main inductor has a much largerinductance(and energy storage)as compared to the para-sitic trace inductances,it therefore ends up‘dominating’.From V*dt=L*dl we can also see that if L is large,a muchhigher voltseconds(V*dt)is required to cause a givenAN-12293The AC and DC Current Paths(Continued)change in current.The trace inductances therefore simply ’give in’first before the main inductor does.But they certainly don’t go down without a fight...and the voltage spikes bear testimony to this!Notice that the currents in the signal traces in the schematic are not shown.For example those connected to the com-pensation node (marked ‘COMP’)or bootstrap (marked ‘BOOST’)carry relatively minute currents and therefore are not likely to cause upsets.They are therefore not critical and can be routed relatively ‘carelessly’.The feedback trace is an exception,and will be discussed later.The Ground pin of the IC is another potential entry point of noise pickup.Inex-perienced designers often grossly under estimate the needs of this pin,particulary for Buck converters.They assume that since the main power flow in a Buck converter does not pass through the ground pin,the ‘current through the ground pin is very low’,and therefore the trace length leading up to this pin is not critical.In fact,though the average current through this pin is very low,the peak current or its dl/dt is not.Consider the switch driver as shown schematically in Figure 1.Clearly it needs to supply current to drive the switch.In any Fet operated as a switch,large peak to peak instantaneous current spikes are needed to charge and discharge the gate capacitance.This is essential so as to cause the Fet to switch fast,and this reduces the switching/crossover losses inside the switch and improves the overall efficiency of the converter.(Actually,in a practical IC,the ‘spike’of current comes from the bootstrap capacitor,and then the bootstrap capacitor is quickly refreshed by the internal circuitry of the IC ----it is the refresh current that passes through the ground pin).Further,as in any high-speed digital IC,parts of the internal circuitry,clocks,gates,comparators etc.,can turn on and off suddenly,leading to small but abrupt changes in the current through the ground pin.This can cause ’ground bounce’which in turn can lead to controller upsets.There-fore the length of the trace to the Ground pin also needs to be kept as small as possible.This also implies that the input capacitors,especially the bypass capacitor ‘CBYPASS’should be placed very close to the IC ,even for a Buck IC.Placing Components ‘acap’(as Close as Possible)One has heard this before:“component X needs to be ‘acap’”.Soon we are told the “component Y too needs to be ‘acap’”.Then “Z too”.And so on.Which would be physically impossible because matter cannot occupy the same place at the same time!So which one comes first?This is the million-dollar predicament always facing switcher layout.The troubling trace lengths are those indicated Figure 1c .To keep them small,clearly two components need to be acap.These are the input bypass capacitor and also the catch diode.Consider the input capacitor section first.In the schematic there are in two input capacitors shown.These are marked ‘CIN’and ‘CBYPASS’respectively.The purpose of the total input capacitance is to reduce the volt-age variations at the input pin.The variations are mainly due to the pulsed input current waveshape,as demanded by a Buck topology.Note that for this particular topology,the output capacitor current is smooth (because the inductor is in series with it).In a Boost topology the situation is re-versed:i.e.the input capacitor current is smooth and the current into the output capacitor is pulsed.This makes thedemand for input decoupling less stringent than in a Buck (or Buck-Boost).In a Buck-Boost or ’flyback’,both the input and the output capacitor currents are pulsed,and input decou-pling is required not only for the control-section/drivers of the IC but for the input current step waveform of the power stage.Designers familiar with a Cuk topology know that in this case both input and output currents are smooth.The Cuk converter is therefore often called the ’ideal DC to DC’converter,and expectedly its parasitic inductances can be largely ignored ----because there are no AC trace sections in the sense we described.Now if the input power to a Buck converter was coming through long leads from a distant voltage source,the induc-tance of the incoming leads would seriously inhibit their ability to provide the fast changing pulsed current shape.So an on-board source of power is required right next to the converter,and this is provided by the input capacitor.It provides the pulsed current,and then is itself refreshed at a slower rate (DC current)from the distant voltage source.However,since the input capacitor is fairly large in size,it may not be physically possible to place it as close as de-sired.Especially for very high speed switchers such as the LM267x series (note that a ‘high speed’switcher as de-fined here,is one with a very small crossover/transition time,and it does not necessarily have to be one with a high switching frequency ).In addition,the Equivalent Se-ries Resistance (‘esr’)and Equivalent Series Inductance (‘esl’)of the main input capacitor may be too high,and this can cause high frequency input voltage ripple on the VIN pin.For the Buck converter schematic as shown in Figure 1,the input pin connects not only to the Drain of the Fet switch,but also provides a low internally regulated supply rail to the control sections of the IC.But no real series pass regulator can ’hold off’very fast changes in the applied input voltage.Some noise will feed through into the control section and then much will depend on the internal sensitivity of the IC to noise (related to its design,internal layout,process/logic family).It is therefore best to try to keep voltage on the VIN pin fairly clean --—from a high frequency point of view.Note that it is not being suggested here that one responds to this statement by increasing the input capacitance indiscrimi-nately,because we are not talking about the natural input voltage ripple which occurs at the rate of the switching frequency (e.g.100kHz–260kHz).Our concern here is the noise occurring at the moment of the transitions,and this noise spectrum peaks at around 10MHz–30MHz,as deter-mined by the transition/crossover time of the switch.The crossover time has nothing to do with the basic PWM switch-ing frequency,but does ofcourse depend on the type of switch used i.e.bipolar or Fet.Therefore a high frequency ‘bypass’or ‘decoupling’capacitor with small or no leads,shown as ‘CBYPASS’in Figure 1,is to be placed very close to the VIN and GND pins of the IC.This is usually a 0.1µF–0.47µF (monolithic)multilayer ceramic (typically X7R type,size 1206or the more recent ’inverted’termination version of this popular size,the ’0612’----also note that smaller sized ceramic caps generally have higher esr/esl,but check before use).Since now this com-ponent provides the main pulsed current waveshape,the bulk capacitor shown as ‘CIN’,may be moved slightly further up (about an inch)without any deleterious effect.For lighter loads,and if it is possible to place the input bulk capacitor very close to the IC,the high frequency bypass capacitor may sometimes be omitted.But for high-speed switchers like the LM267x,the input ceramic bypass capacitor is considered almost mandatory for any application.A N -12294Placing Components‘acap’(as Close as Possible)(Continued)The position of the catch diode is also critical.It too needs to be acap.Now,every topology has a node called the’switch-ing node’.This is the’hot’or’swinging’end of the switch.For integrated switchers,this node can also be an easy entry point for noise feed-through into the control sections.Note that the problem is not caused by the simple fact that the voltage at this node swings,for it is designed for exactly that situation in mind.The problem is with the additional noise spikes riding on top of the basic square voltage waveform, arising from the trace inductances as explained earlier. Therefore,it is essential to place the catch diode very close to the IC and connect it directly to the SW pin and GND pins of the IC,with traces that are very short and fairly wide.In some erroneous layouts,where the catch diode was not appropriately placed to start with,the con-verter could be‘bandaided’by a small series RC snubber. This consists typically of a resistor(low inductive type preferred)of value10Ω–100Ωand a capacitor,which should be ceramic of value470pF–rger capaci-tance than this would lead to unacceptably higher dissipation (=1/2*C*V2*f),chiefly in the resistor,and would serve no additional purpose.However,note that this RC snubber needs to be placed very close to and across the Switch-ing pin and Gnd pin of the IC,with short leads/traces. Sometimes designers think that this is’across the diode’, because on the schematic there is no way to tell the differ-ence.However,particularly when the diode is a Schottky,theprimary purpose of such a snubber is to absorb the voltagespikes of the trace inductances.Therefore its position mustbe such that it provides bypassing of the critical or AC tracesections of the output side as shown in Figure1c(right handside of the switcher)----which means it must be close to theIC.Of course,as mentioned previously,it is best to get thelayout right to start with,rather than adding such extracomponents.Remaining component placements can be taken up onlyafter the input bypass capacitor and the catch diode arefirmly in place and are both acap.The traces to either ofthese two components should be short,fairy wide,andshould not go pass through any vias on the way to the IC.For SMT boards this implies that the input capacitor andcatch diode are on the same layer as the IC.In Figure2suggested PCB starting points are provided for severalswitchers.All of them focus on placing these two criticalcomponents correctly.These layouts are strongly recom-mended for most applications.The’X’marks suggest therecommended location where vias can be used to con-nect to a Ground Plane(if present).The remaining compo-nents can be placed relatively carelessly(though in doing so,there may be slight impact,for example on the accuracy ofthe output voltage rail and its ripple,but nothing compared towhat can happen if the input decoupling cap and catch diodeare incorrectly placed).Trace routing is now discussed inmore detail.AN-12295Placing Components ‘acap’(as Close as Possible)(Continued)Routing the TracesAs mentioned above,it is not advisable to route any of the critical traces through ‘vias’.Vias are considered useful from a purely CAD perspective for ‘layer jumping’,but are often used indiscriminately as they seem an easy solution to con-nectivity problems.But they also add impedance,and that is exactly what we are trying to avoid.The inductance of a via is given bywhere ‘h’is the height of the via in mm (equal to the thick-ness of the board,commonly 1.6mm),and ‘d’is the diam-eter in mm.Therefore a single via of diameter 0.4mm on a standard 1.6mm board gives an inductance of 1.2nH.It may not sound much,but it is almost twice that of a wire of the same length and diameter.It has been seen empirically that for the high speed LM267x series,if the bypass capacitor is connected through vias to the IC,occa-sional field problems do arise.So if vias have to be usedfor some reason,several vias in parallel will yield better results than a single via.And larger via diameters would help further (unless they are being used as ’thermal vias’---discussed later).It is also said that “the traces also need to be ‘wide’and ‘short’”.The necessity of short traces is clearly understood,usually intuitively,by most engineers.In fact the thumbrule of ‘20nH per inch’also implies that trace inductance is almost proportional to length.However,a common ‘intuitive’mis-take is to assume that inductance is inversely propor-tional to the width of the trace .So some engineers mis-takenly ‘add copper’lavishly to critical traces (though there are some other reasons why this may be being done,and these will be discussed later).A first approximation for the inductance of a conductor having length ‘l’and diameter ‘d’iswhere l and d are in centimeters.Note that the equation for a PCB trace is not much different from that of a wire.20042602FIGURE 2.Recommended Layout Starting PointsA N -1229 6Routing the Traces(Continued)where ‘w’is the width of the trace.For PCB traces,L hardly depends on the thickness of the copper (1oz or 2oz board).Both the above equations are plotted in Figure 3.It will be seen that for a given length,a PCB trace of width ‘x’has higher inductance than a wire of diameter ‘x’.In fact the width of a PCB trace has to be about 1.78times the diameter of a wire for the same inductance .A wire of AWG 20has a diameter of 32mils (or 0.081cm).So for a length of one inch (1000mils or 2.54cm)L equals 21nH (which is the usual thumbrule).We can see that L is almost proportional to length.But if we double the diameter to 0.16cm,L equals 17nH,which is not much different from 21nH.This indicates a non-linear relationship.Referring to Figure 3,where the above function is plotted out (dotted lines are for a PCB trace),we can see that the diameter/width of a wire/trace has to typically increase by a factor of 10for the inductance to halve .The rela-tionship of L to d is therefore logarithmic in nature.The reason for this is the effects of mutual inductance between parallel sections/strips of the conductor.‘Beefing up’traces to reduce the effects of parasitic induc-tances should be a last resort.Decreasing the length of the trace should be the first step.Increasing the width of certain traces can in fact become counterproductive.In particular,the trace from the switch node to the diode is ‘hot’from an EMI point of view.This is not only because of the AC (high frequency)current it carries,but because of its voltage,which is a switched waveform.Any conductor with a varying voltage,irrespective of the current,becomes an antenna if its dimensions are large enough.Radiated emissions from this antenna can cause undesirable common-mode interfer-ence in its vicinity.Therefore this calls for the area of the copper around the switching node to be reduced,not rge planes of switched voltage also cause ca-pacitive noise coupling into nearby traces.On a typical SMT board,if the opposite side happens to be a ’ground plane’,noise from the switching node can couple through the FR4dielectric of the PCB into the Ground plane.No Groundplane is ’perfect’,and therefore this injected high frequency noise can also cause the ground plane to not only radiate,but to pass noise onto the IC through ’ground bounce’.Some people suggest that a copper island,exactly the same size/shape as the switching-node island be created on the oppo-site side of the PCB,connected through several vias.This is supposed to prevent ’capacitive cross-talk’to other traces and to enhance thermal dissipation.But this obviously also leads to the breaking-up/partioning of the Ground plane.This defeats the very purpose of Ground plane as it can cause strange effects arising due to the odd current flow patterns in the now divided Ground plane.In general,the Ground plane should be kept continuous/unbroken as far as possible,or it could behave like a slot antenna.For the switching node therefore,the best option is to keep the amount of copper around it to the actual minimum re-quirement.Some basic physics to be reminded of here:electric fields are caused by electric charge,and magnetic fields by cur-rents.But if an electric field varies with time,it produces a corresponding magnetic field.However magnetic fields are associated with currents.Therefore AC voltages (varying electric fields)on opposite planes of copper on a PCB cause a ’displacement current’(capacitive coupling current)through the FR4dielectric.Similarly,a varying magnetic field causes an electric field.So for example in a transformer,when we pass AC current (varying magnetic field)in a wind-ing,we get Faraday induced voltages (electric field).When-ever voltage or current is switched,an electromagnetic field is generated,which produces EMI.And this EMI is inadvert-ently ’helped’by antenna structures.Therefore,on a PCB layout,the area enclosed by all current loops carrying ’AC (switched)current’must be kept small.Similarly the area of copper planes with ’AC (switched)voltage’must be kept small.Both can behave as antennae.In addition,traces carrying switching currents/voltages must also be kept away from ’quieter’traces to avoid cross-coupling.Further,since ’sharp edges’are known to cause an increase in field strengths,two 45degree bends in a trace are preferred to a single 90degree bend.Copper Filling:when to StopAdding copper lavishly to traces serves some purpose oc-casionally,sometimes none at all,and sometimes it even works against the design in an unintended manner.There may be no simple hard and fast rules here.Judiciousness needs to be applied.But first it is instructive to consider some of the ‘reasons’why copper is lavished,and to the degree it is really required.Most often the requirements are actually much less than predictions based on ’gut instinct’:We will take each of these separately:A)CURRENT HANDLING CAPABILITYIf we multiply the width of a trace with its thickness we get the ‘cross sectional area’of the conductor.This determines the resistance (per unit length)of the conductor and the consequent self-heating.This leads to an estimable tem-perature rise.It is important to note that the ‘current handling capability’is therefore not a ‘stake in the ground’as some people think,but is related to a permissible temperature rise.20042606FIGURE 3.Inductance of Wire of Length ‘1’AN-12297。

ST AN2063 Application note 数据手册

GENERAL FEATURESs ULTRA LOW STANDBY POWER DISSIPATIONs BURST MODE OPERATION IN STAND-BY s 72% TYPICAL EFFICIENCY s CURRENT MODE CONTROLLER s OUTPUT SHORT CIRCUIT PROTECTION s THERMAL SHUT DOWN PROTECTION1. INTRODUCTIONThe new regulations on the power supply stand-by consumption for the battery charger are becoming more stringent. Thanks to VIPerX2A family low power consumption, it is possible to build a battery charger with a power consumption in stand-by mode with no-load of 100mW. In table 1 this charger solution with VIPer12A is presented.Table 1: Operation conditions2. VIPer12A DESCRIPTIONVIPer12A is a high voltage integrated circuits intended to be used on off line power supply as a primary side switch. in a monolithic structure housed in DIP-8 or SO-8 package it includes a PWM driver, a Power MOSFET with 730V breakdown voltage, a start-up circuit and several protection circuit. It takes advantage from minimizing the external part count, reducing the products size and power consumption.The application note describes the results obtained when VIPer12A is used in mobile charger application.ParametersLimitsInput voltage range 90 to 264VACInput frequency range 50-60HzOutput voltage 5V Output current 800mAOutput power 4W Efficiency72% typicalLine regulation0.5%Load regulation1%Output ripple voltage 30mVppSafetyShort circuit protectionb s lc )Os ol e t ePr od u c t () -O bs o e t eP r od u t (sl s l c )Ob so e t ePr od u c t () -O bs o e t eP r od u t (s3. PCB LAY-OUTThe layout of the switching power supply is very important in order to minimize noise and interference.The high switching current loop areas should be kept as small as possible to reduce the radiated electromagnetic emissions. Figure 1 shows the board layout.In order to meet safety agencies' requirements, there needs to be an adequate clearance of about 6mm between the high and low voltage sides of the circuit.The power grounds need to be separated from the small signal grounds. The current in the power ground changes very quickly in time; resulting in large transient that induces voltage shifts, which in turn can disturb critical, sensitive small signal currents. Any disturbance or shift of ground in the small signal ground will upset critical reference paths. Therefore, poor grounding routing can manifest itself as poor load regulation, or excessive switching noises on the output.Figure 1: Demo board bottom foil (not in scale)4. GENERAL CIRCUIT DESCRIPTIONThis board is a fly-back regulator delivering 0.8A at 5V. The AC input is rectified and filtered by the diode D1, D2, D3, D4, the bulk capacitor C1, and C2 to generate the high voltage DC bus applied to the primary winding of the transformer, TR1. C1, L1, and C2 provide EMI filtering for the circuit.D9, D10 form the snubber circuit needed to reduce the leakage spike and voltage ringing on the drain pin of VIPer12A. The output voltage is regulated with a TL431 (U3) via an optocoupler (U2) to the feedback pin. The output voltage ripple is controlled with the capacitor, C7, with an additional LC PI filter configuration made up of L2 and C8. It is possible to modify the output voltages by changing the transformer turns ratio and modifying the resistance values of R6 and R7 in the feedback loop.O ptio n EO p tio n A O p tio n BE C R 20R 101N L060180T1D 81N5822C 7431R 3220l s l c )Ob so e t ePr od u c t () -O bs o e t eP r od u t (s5. CHARGER APPLICATION 5.1 Schematic general descriptionAs the total input power dissipation at no load condition of this solution is less than 0.1W, we have to put our attention to save the power losses of each component as much as possible. Below we will introduce details for the major approaches which we adopt in this demo board.5.2 Solutions for energy saving (A) Losses of VIPer12A controller.As on this demo board, the power losses of the control part of VIPer12A can be calculated by formula (1).P viper = V dd * I dd1 (1)Shown in datasheet:Where:- V dd is the supply voltage of the control part of VIPer12A (range:9V-38V)- I dd1 is the operation current of the control part of VIPer12A (typical value: 4.5mA)The V dd is set by considering two operative conditions; if we want to save the power of VIPer12A, we must lower the V dd value as much as possible, and at the same time guarantee the V dd higher than 10V which the required normal operation value of VIPer12A (with 1V margin).The 10V V dd value fixes the suitable turn ratio between secondary and auxiliary winding.(B) Optimized voltage source for optocoupler.In a fly-back topology, the voltage source of optocoupler primary side is normally connected to the V dd of the IC directly, but in this board, in order to save energy, another winding is inserted in the transformer for supplying the optocoupler; the voltage supplied with this winding is lower than the V dd value (typical value 3V).(C) Snubber circuit configuration.An RCD clamp is a popular cheap solution, however it dissipates power even at no load condition: there is at least a reflected voltage across the clamp resistor at all times. The power losses on resistor can be calculated using the formula below:Where V R is the reflected voltage; R min is the resistor value; L LK is the leakage inductance; I lim is the peak current limitation value of VIPer12A and f sw is the switching frequency.As at no load condition, the energy of ½*L LK *I lim *f sw can be neglected, then the losses of RCD could be considered as:P R =V R *V R /R minIn this case with V R =70V, R min =82K Ω, P R is around 60mWIt is possible to save this 60mW power at no load condition using the transil clamp to replace the RCD configuration in the snubber circuit.P RV R2Rmin-----------12-L LK I lim 2f sw ⋅⋅⋅+=l -O bs o e t eP r od u When no load is applied on secondary side, VIPer12A works in burst mode by skipping some switching cycles and this behavior is shown in figure 3. Thanks to this feature, VIPer12A can save a lot of the switching losses reducing the standby power consumptionl s Ob so e t ePr od u c t () -bs o As shown in the figures 6a, 6b the maximum overshoot and undershoot value of output voltage are less than 150mV at transient tests.(50mV / division)(50mV / division)l c )-bs o e t eP r od u t (sFigures 7 and 8 show the drain voltage and drain current during normal operation at full load. The power supply operates in the continuous current mode at low line and in discontinue current mode at high line input as seen from the waveforms 6. TRANSFORMER SPECIFICATION Table 3.Winding description Symbol Number Wire size Start pin End pinRemarksl s l c )Ob so e t ePr od u c t () -O bs o e t eP r od u t (s7. BILL OF MATERIALS Table 4. Component list8. CONCLUSIONSWhen the board works in standby, it consumes less than 0.1W meeting the "Blue Angel" Norm. The total power consumption measured at 100Vdc input with zero load at output is approximately 50mW, while at 380Vdc input this value is about 80mW.This unit operates in burst mode when the output load is reduced to zero and normal operation is resumed automatically when the power gets back to a level higher than the standby power. The output voltage remains regulated even when the board operates in burst mode.Symbol Part list descriptionNoteC1,C2Elect Cap 4.7µF/400V C447nF/25VC5Elect Cap 33µF/25V C6Elect Cap 10µF/6.3V C7Elect Cap 470µF/16V C8Elect Cap 220µF/10V C10Film 100nF/50V C11Y cap 1nF/1KVR010Ω Fuse R1,R20ΩR3220ΩR4 1.5K ΩTL431:1.5K/TS431:Remove R643K ΩR743K Ω/130K ΩTL431:43K/TS431:130KD1,D2,D3,D41N4007D6,D71N4148D81N5822D9STTH1L06D10P6KE180L1680µH L2 4.7µHT1 2.7mH EE-16 Vertical U1STMicroelectronics VIPer12AU2PC817U3TL431/TS431l s l c )Ob so e t ePr od u c t () -O bs o e t eP r od u t (sInformation furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.The ST logo is a registered trademark of STMicroelectronics.All other names are the property of their respective owners© 2004 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America。

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To understand this behavior the circuit of a step-down converter will be analyzed.
Figure 1: Standard buck-converter with synchronous rectification X1 represents the HS-MOSFET with its output capacitance. The synchronous rectifier is represented by X2 – also with its inherent output capacitance. During the freewheeling period of the current in X2, the voltage at the phase node is clamped to GND via the body diode of the synchronous rectifier and should never fall below about -1 V. However, reality shows otherwise. Therefore it can be concluded that the circuit shown in fig. 1 is not representing the elements causing the negative voltage spike to occur. After introduction of parasitic inductances into the critical commutation loop the analysis of the turn-off event reveals the reason for the negative spike (fig. 2).源自3 6 8 11 15 15
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AN: Negative Spike in Buck Converters
1. Circuit Analysis
The negative spike occurs during control-MOSFET (HS-FET) turn-off. The voltage at the phase node falls rapidly, crosses zero and reaches a rather significant negative voltage (perhaps of the same or even higher magnitude as the input voltage of the circuit) for a few nanoseconds before quickly declining.
Version 0.94, January 12 - 2012
Jen s Ejur y July 13, 2006 San Jo se, C A
OptiM OS5 Gen5 SF ET5
Application Note Buck Converter: Negative Spike at Phase Node
In case the MOSFET does not reach avalanche the term VBRDSS(X1) in the above equation can be replaced by the maximum voltage across the MOSFET. This maximum voltage across the MOSFET will always be higher than Vin during the turn off event as long as a parasitic inductance L stray is present. Therefore, even in the most common case when the MOSFET is not reaching avalanche (as switching speed is slow and energy stored in the stray inductance can be dissipated in the switching MOSFET while overshoot voltage will be limited by the output capacitance of X2) undershoot at the phase node depends on: ratio between L2 and Lstray input voltage
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AN: Negative Spike in Buck Converters
Figure 3: Analysis schematic for negative spike event The phase node voltage can be calculated by applying the Kirchhoff law for voltages with respect to the phase node:
2. Switching Loss
From the equations above one can see that the only design variables to reduce the negative spike lay within the board layout and package choice for the MOSFETs and capacitors as the choice of the package will influence Lstray and its distribution. To reduce the undershoot voltage L2/Lstray should be small. One way to accomplish that is to enlarge L1. This however would be a bad choice as it increases Lstray and will lead to more dynamic power loss. The impact of Lstray on dissipated energy can be calculated as:
by Jens Ejury

N e v e r s t o p t h i n k i n g.
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AN: Negative Spike in Buck Converters
Introduction
This application note is discussing the observable negative spike in modern hard-switching step-down converter applications. Ways to deal with the phenomenon and the root cause will be revealed.
Content
# Description Page
1 2 3 4 5 6
Circuit Analysis………………………………..………………………………………… Switching Loss ……………………………….………………………………………… Detailed Spike Analysis…………………..….………………………………………… Driver …………………………………………...………………………………………… Summary ……………………………………….………………………………………… References …………………………………….…………………………………………
An assumption for further considerations is that the voltage drop across X2 is zero as the forward voltage of the body diode (~0.7 V) is small compared to the observable spike.
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AN: Negative Spike in Buck Converters
Figure 2: Highlighting the critical loop inductance, i.e. the current commutation path Lstray is the total value of the critical loop inductance consisting of L1 and L2. L2 is the part of L stray that is located in the synchronous rectification path, i.e. between GND and phase node. L1 is the part of the L stray that is not part of L2. Another assumption is that the HS-MOSFET is switching so fast that the current transition is only limited by the stray inductance Lstray. This will provide the worst case for the negative spike. When the HS-MOSFET turns off the current through it will decrease. The resulting di/dt then induces a voltage on the parasitic inductance L1. Since the output current in the inductor L can be considered constant for the switching event the current ramp-up in stray inductance L2 has to occur at the same di/dt as in L1. The induced voltage across L1 and L2 can be that high that in a worst case scenario the HS-MOSFET reaches avalanche breakdown and the voltage is clamped by the MOSFET. In this worst case scenario the MOSFET is represented by a Zener-diode as shown on the right hand side in fig. 3.