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(完整word版)PEP人教版小学英语五年级下册课堂同步练习试题全册,推荐文档

五年级（下）第一单元第1课时学案Unit 1 My dayPart A Let’s talk【学习目标】1．能够听懂、会说句型：When do you finish class in the morning? We finish class at 1o’clock.并能在实际情景中运用。

能够正确使用usually这个频度副词。

2．能在Role play部分用本课时目标语言询问同学的作息时间，并能对结果做简单的反思。

【重点难点】重点：能够熟练使用句型：―When do you finish class in the morning? We finish class at 1o’clock.问答活动时间。

难点：能够在情境中熟练使用句型：―When do you …?问答活动时间。

【新知预习】写出下列单词或词组的意思。

1. finish class ______________2. after lunch_________3. start _____________4. Spain__________5. too late_____________【课堂探究】探究1 根据汉意写单词。

1. 吃午餐__________________2. 回学校_____________3. 吃晚餐________________4.什么时候_____________5. 或者________________探究2 翻译下列句子。

When do you finish class in the morning? ___________________________________Classes start at 3 o’clock. __________________________________【针对练习】单项选择。

1.---________ do you go to bed?--- At 9:00.A.WhatB. whenC. When2.I eat dinner _____ 6 o’clock.A. aB. atC. on【达标练习】Ⅰ. 选择正确答案。

LMK00101SQXNOPB;LMK00101SQNOPB;LMK00101SQENOPB;LMK00101BEVALNOPB;中文规格书,Datasheet资料

LMK00101January 16, 2012Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input1.0 General DescriptionThe LMK00101 is a high performance, low noise LVCMOS fanout buffer which can distribute 10 ultra-low jitter clocks from a differential, single ended, or crystal input. The LMK00101 supports synchronous output enable for glitch free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, tele-com, server and storage area networking, RRU LO reference distribution, medical and test equipment applications.The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00101 can be easily configured through pin programming.2.0 Target Applications■LO Reference Distribution for RRU Applications■SONET, Ethernet, Fibre Channel Line Cards■Optical Transport Networks■GPON OLT/ONU■Server and Storage Area Networking■Medical Imaging■Portable Test and Measurement■High-end A/V 3.0 Features■10 LVCMOS/LVTTL Outputs, DC to 200 MHz ■Universal Input—LVPECL—LVDS—HCSL—SSTL—LVCMOS / LVTTL■Crystal Oscillator Interface—Crystal Input Frequency: 10 to 40 MHz■Output Skew: 6 ps■Additive Phase Jitter—30 fs at 156.25 MHz (12 kHz to 20 MHz)■Low Propagation Delay■Operates with 3.3 or 2.5 V Core Supply Voltage ■Adjustable Output Power Supply—1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank ■32 pin LLP Package 5.0 x 5.0 x 0.8 mm4.0 Functional Block Diagram30146901TRI-STATE® is a registered trademark of National Semiconductor Corporation.© 2012 Texas Instruments Incorporated301469 LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input5.0 Connection Diagram32-Pin LLP Package301469026.0 Pin DescriptionsPin #Pin Name Type DescriptionDAP DAP -The DAP should be grounded1CLKout0Output LVCMOS Output2, 6Vddo Power Power Supply for Bank A (CLKout0 to CLKout4) CLKout pins.19,23Vddo Power Power Supply for Bank B (CLKout5 to CLKout9) CLKout pins.3CLKout1Output LVCMOS Output 4,9,15,16,21,25,26,32GND GND Ground5CLKout2Output LVCMOS Output 7CLKout3Output LVCMOS Output 8CLKout4Output LVCMOS Output10Vdd Power Supply for operating core and input buffer 11OSCin Input Input for Crystal 12OSCout Output Output for Crystal 13CLKin0Input Input Pin14CLKin0*Input Optional complimentary input pin 17CLKout5Output LVCMOS Output 18CLKout6Output LVCMOS Output 20CLKout7Output LVCMOS Output 22CLKout8Output LVCMOS Output 24CLKout9Output LVCMOS Output27CLKin1*Input Optional Complimentary Input Pin 28CLKin1Input Input Pin29SEL1Input MSB for Input Clock Selection. This pin has an internal pull-down resistor.30SEL0Input LSB for Input Clock Selection. This pin has an internal pull-down resistor.31OEInputOutput Enable. This pin has an internal pull-down resistor. 2L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t7.0 Absolute Maximum Ratings (Note 1, Note 2)If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.Parameter Symbol Ratings Units Core Supply Voltage Vdd-0.3 to 3.6VOutput Supply Voltage Vddo-0.3 to 3.6V Input Voltage V IN-0.3 to Vdd + 0.3V Storage Temperature Range T STG-65 to 150°CLead Temperature (solder 4 s)T L+260°C Junction Temperature T J+125°C8.0 Recommended Operating ConditionsParameter Symbol Min Typ Max Units Ambient Temperature T A-402585°CCore Supply Voltage Vdd 2.375 3.3 3.45V Output Supply Voltage (Note 3)Vddo 1.425 3.3Vdd VNote 1:"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.Note 2:This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.Note 3:Vddo should be less than or equal to Vdd(Vddo≤ Vdd)9.0 Package Thermal Resistance32-Lead LLPPackage Symbols Ratings UnitsThermal resistance from junction to ambienton 4-layer Jedec board (Note 4)θJA50° C/WThermal resistance from junction to case(Note 5)θJC (DAP)20° C/WNote 4:Specification assumes 5 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias play a key role in improving the thermal performance of the LLP. For best thermal dissipation it is recommended that the maximum number of vias be used on the board layout.Note 5:Case is defined as the DAP (die attach pad).LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input10.0 Electrical Characteristics(2.375 V ≤ Vdd ≤ 3.45 V, 1.425 ≤ Vddo ≤ Vdd, -40 °C ≤ T A ≤ 85 °C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, T A = 25 °C, at the Recommended Operation Conditions at the time of product charac-terization and are not guaranteed). Test conditions are: F test = 100 MHz, Load = 5 pF in parallel with 50 Ω unless otherwise stated.SymbolParameterTest ConditionsMinTypMaxUnitsTotal Device CharacteristicsVddCore Supply Voltage2.3752.5 or3.33.45VVddo Output Supply Voltage 1.425 1.5,1.8,2.5, or3.3Vdd VI VddCore CurrentNo CLKin1625mAV ddo = 3.3 V, F test = 100 MHz 24 V ddo = 2.5 V, F test = 100 MHz 20 I Vddo[n]Current for Each OutputV ddo = 2.5 V,OE = High, F test = 100 MHz5 mAV ddo = 3.3 V,OE = High, F test = 100 MHz7 OE = Low 0.1 I Vdd + I VddoTotal Device Current with Loads onall outputsOE = High @ 100 MHz95 mAOE = Low16Power Supply Ripple Rejection (PSRR)PSRRRipple Induced Phase Spur Level100 kHz, 100 mVpp Ripple Injected on V dd , V ddo = 2.5 V-44dBcOutputs (Note 6)Skew Output Skew Measured between outputs,referenced to CLKout06 ps f CLKoutOutput Frequency(Note 7)DC 200MHzt Rise Rise/Fall Time V dd = 3.3 V, V ddo = 1.8 V, C L = 10 pF500 psV dd = 2.5 V, V ddo = 2.5 V, C L = 10 pF 300 V dd = 3.3 V, V ddo = 3.3 V, C L = 10 pF200 V CLKout Low Output Low Voltage 0.1V V CLKout High Output High Voltage Vddo-0.1 R CLKoutOutput Resistance50 ohm t jRMS Additive Jitterf CLKout = 156.25 MHz,CMOS input slew rate ≥ 2 V/ns C L = 5 pF, BW = 12 kHz to 20 MHz30fs 4L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u tSymbol Parameter Test ConditionsMin Typ Max UnitsDigital Inputs (OE, SEL0, SEL1)V Low Input Low Voltage Vdd = 2.5 V 0.4VV High Input High Voltage Vdd = 2.5 V 1.3 Vdd = 3.3 V1.6 I IH High Level Input Current 50uAI IL Low Level Input Current -5 5CLKin0/0* and CLKin1/1* Input Clock Specifications, (Note 9, Note 10)I IH High Level Input Current V CLKin = Vdd 20uA I IL Low Level Input Current(Note 8)V CLKin = 0 V-20 uA V IH Input High Voltage Vdd VV ILInput Low VoltageGND V CMDifferential InputCommon Mode Input Voltage(Note 12)V ID = 150 mV0.5 Vdd-1.2VV ID = 350 mV 0.5 Vdd-1.1V ID = 800 mV0.5 Vdd-0.9V ID Differential Input Voltage Swing CLKin driven differentially 0.15 1.5V OSCin/OSCout Pinsf OSCinInput Frequency (Note 7)Single-Ended Input, OSCout floatingDC200MHzf XTALCrystal Frequency Input Range Fundamental Mode Crystal ESR < 200 Ω ( f Xtal ≤ 30 MHz )ESR < 120 Ω ( f Xtal > 30 MHz )(Note 11, Note 7)10 40MHzC OSCinShunt Capacitance1 pFNote 6:AC Parameters for CMOS are dependent upon output capacitive loading Note 7:Guaranteed by characterization.Note 8:V IL should not go below -0.3 volts.Note 9:See Section 12.1 Differential Voltage Measurement Terminology for definition of V ID and V OD .Note 10:Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.Note 11:The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal.Note 12:When using differential signals with V CM outside of the acceptable range for the specified V ID , the clock must be AC coupled.LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input30146942Iddo per Output vs Frequency50100150200250051015C U R R E N T (m A )FREQUENCY (MHz)Cload = 10 pFVddo = 1.5 V Vddo = 1.8 V Vddo = 2.5 V Vddo = 3.3 V 30146976Note 13:Test conditions: LVCMOS Input, slew rate ≥ 2 V/ns, C L = 5 pF in parallel with 50 6L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t12.0 Measurement Definitions12.1 Differential Voltage Measurement TerminologyThe differential voltage of a differential signal can be de-scribed by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to under-stand and discern between the two different definitions when used.The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measure-ment is typically VID or VODdepending on if an input or outputvoltage is being described.The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with re-spect to the inverting signal. The symbol for this second measurement is VSSand is a calculated parameter. Nowherein the IC does this signal exist with respect to ground, it onlyexists in reference to its differential pair. VSScan be measured directly by oscilloscopes with floating references, otherwisethis value can be calculated as twice the value of VODas de-scribed in the first sectionFigure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitionsside-by-side for outputs. The VIDand VODdefinitions showVAand VBDC levels that the non-inverting and inverting sig-nals toggle between with respect to ground. VSSinput and output definitions show that if the inverting signal is consid-ered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.VIDand VODare often defined in volts (V) and VSSis oftendefined as volts peak-to-peak (VPP).30146912FIGURE 1. Two Different Definitions for Differential Input Signals30146913FIGURE 2. Two Different Definitions for Differential Output Signals LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input13.0 Functional DescriptionThe LMK00101 is a 10 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz. It fea-tures a 3:1 input multiplexer with a crystal oscillator input,single supply or dual supply (lower power) operation, and pin-programmable device configuration. The device is offered in a 32-pin LLP package.13.1 V dd and V ddo Power Supplies (Note 14, Note 15)Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply (3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply operation, dual supply op-eration enables lower power consumption and output-level compatibility.Bank A (CLKout0 to CLKout4) and Bank B (CLKout5 to CLK-out9) may also be operated at different V ddo voltages, provid-ed neither V ddo voltage exceeds V dd .Note 14:Care should be taken to ensure the V ddo voltage does not exceed the Vdd voltage to prevent turning-on the internal ESD protection circuitry.Note 15:DO NOT DISCONNECT OR GROUND ANY OF THE V ddo PINS as the V ddo pins are internally connected within an output bank.13.2 CLOCK INPUTSThe LMK00101 has three different inputs, CLKin0/CLKin0*,CLKin1/CLKin1*, and OSCin that can be driven in different manners that are described in the following sections.13.2.1 SELECTION OF CLOCK INPUTClock input selection is controlled using the SEL0 and SEL1pins as shown in Table 1. Refer to Section 14.1 Driving the Clock Inputs for clock input requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Section 14.2Crystal Interface for more information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal.TABLE 1. Input SelectionSEL1SEL0Input 00CLKin0, CLKin0*01CLKin1, CLKin1*1XOSCin (Crystal Mode)13.2.1.1 CLKin/CLKin* PinsThe LMK00101 has two differential inputs (CLKin0/CLKin0*and CLKin1/CLKin1*) that can be driven single-ended or dif-ferentially. They can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and singled ended sig-nals that meet the input requirements under the “CLKin0/0*and CLKin1/1* Input Clock Specifications” portion of the Sec-tion 10.0 El ectrical Characteristics and (Note 12). Refer to Section 14.1 Driving the Clock Inputs for more details on driv-ing the LMK00101 inputs.In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them, Table 2 fol-lowing will be the state of the outputs.TABLE 2. CLKinX Input vs. Output States CLKinX CLKinX*Output State Open Open Logic Low Logic Low Logic Low Logic Low Logic High Logic Low Logic High Logic LowLogic HighLogic Low13.3 CLOCK OUTPUTSThe LMK00101 has 10 LVCMOS outputs.13.3.1 Output Enable PinWhen the output enable pin is held High, the outputs are en-abled. When it is held Low, the outputs are held in a Low state as shown in Table 3.TABLE 3. Output Enable Pin StatesOE Outputs Low Disabled (Hi-Z)HighEnabledThe OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from Low to High, the outputs will initially have an impedance of about 400 Ω to ground until the second falling edge of the input clock. Starting with the second falling edge of the input clock,the outputs will buffer the input. If the OE pin is taken from Low to High when there is no input clock present, the outputs will either go High or Low and stay a that state; they will not oscillate. When the OE pin is taken from High to Low the out-puts will become Low after the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising edge.13.3.2 Using Less than Ten OutputsAlthough the LMK00101 has 10 outputs, not all applications will require all of these. In this case, the unused outputs should be left floating with a minimum copper length (Note 16) to minimize capacitance. In this way, this output will con-sume minimal output current because it has no load.Note 16:For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. 8L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t14.0 Application Information14.1 Driving the Clock InputsThe LMK00101 has two differential inputs (CLKin0/CLKin0*and CLKin1/CLKin1*) that can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, and other differential and single ended signals that meet the input requirements specified in Sec-tion 10.0 Electrical Characteristics . The device can accept a wide range of signals due to its wide input common mode voltage range (V CM ) and input voltage swing (V ID )/dynamic range. AC coupling may also be employed to shift the input signal to within the V CM range.To achieve the best possible phase noise and jitter perfor-mance, it is mandatory for the input to have a high slew rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this rea-son, a differential input signal is recommended over single-ended because it typically provides higher slew rate and common-mode noise rejection.While it is recommended to drive CLKin0 and CLKin1 with a differential signal input, it is possible to drive them with a sin-gle ended clock. The single-ended input slew rate should be as high as possible to minimize performance degradation.The CLKinX input has an internal bias voltage of about 1.4 V,so the input can be AC coupled as shown in Figure 3, Figure 4, or Figure 5 depending upon the application.30146938FIGURE 3. Single-Ended LVCMOS Input, AC Coupling,Near and Far End Termination30146943FIGURE 4. Single-Ended LVCMOS Input, AC Coupling,Near End Termination30146944FIGURE 5. Single-Ended LVCMOS Input, AC Coupling,Far End Termination A single ended clock may also be DC coupled to CLKinX as shown in Figure 6. If the DC coupled input swing has a com-mon mode level near the devices internal bias of 1.4 V, then only a 0.1 µF bypass cap is required on CLKinX*. Otherwise,if the input swing is not optimally centered near the internal bias voltage, then CLKinX* should be externally biased to the midpoint voltage of the input swing. This can be achieved us-ing external biasing resistors, R B1 and R B2, or another low-noise voltage reference. The external bias voltage should be within the specified input common voltage (VCM) range. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest.30146939FIGURE 6. Single-Ended LVCMOS Input, DC Couplingwith Common Mode Biasing If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 7. Configurations similar to Figure 4 or Figure 5 could also be used as long as the OSCout pin is left floating. The input clock should be AC coupled to the OSCin pin, which has an internally generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alterna-tive input to multiplex an external clock, it is recommended to use either differential input (CLKinX) since it offers higher op-erating frequency, better common mode, improved power supply noise rejection, and greater performance over supply voltage and temperature variations.LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input30146903FIGURE 7. Driving OSCin with a Single-Ended ExternalClock 14.2 Crystal InterfaceThe LMK00101 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal in-terface is shown in Figure 8.30146904FIGURE 8. Crystal InterfaceThe load capacitance (C L ) is specific to the crystal, but usually on the order of 18 to 20 pF. While C L is specified for the crys-tal, the OSCin input capacitance (C IN = 1 pF typical) of the device and PCB stray capacitance (C STRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C 1 and C 2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:C L = (C 1 * C 2) / (C 1 + C 2) + C IN + C STRAY(1)Typically, C 1 = C 2 for optimum symmetry, so Equation 1 can be rewritten in terms of C 1only:C L = C 12 / (2 * C 1 ) + C IN + C STRAY(2)Finally, solve for C 1:C 1 = (C L - C IN - C STRAY ) * 2(3)Section 10.0 Electrical Characteristics provides crystal inter-face specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause pre-mature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation.The power dissipated in the crystal, P XTAL , can be computed by:P XTAL = I RMS 2 * R ESR * (1 + C 0 / C L )2(4)Where:•I RMS is the RMS current through the crystal.•R ESR is the maximum equivalent series resistance specified for the crystal.•C L is the load capacitance specified for the crystal.•C 0 is the minimum shunt capacitance specified for the crystal.I RMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active.As shown in Figure 8, an external resistor, R LIM , can be used to limit the crystal drive level if necessary. If the power dissi-pated in the selected crystal is higher than the drive level specified for the crystal with R LIM shorted, then a larger resis-tor value is mandatory to avoid overdriving the crystal. How-ever, if the power dissipated in the crystal is less than the drive level with R LIM shorted, then a zero value for R LIM can be used.As a starting point, a suggested value for R LIM is 1.5 k Ω14.3 Power Supply Ripple RejectionIn practical system applications, power supply noise (ripple)can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance.When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00101, it can produce narrow-band phase modulation as well as am-plitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the car-rier (measured in dBc).For the LMK00101, power supply ripple rejection (PSRR),was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the V ddo supply. The PSRR test setup is shown in Figure 9.30146940FIGURE 9. PSRR Test SetupA signal generator was used to inject a sinusoidal signal onto the V ddo supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the V ddo pins of the device. A lim-iting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions:•Ripple amplitude: 100 mVpp on V ddo = 2.5 V •Ripple frequency: 100 kHzAssuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:10L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t分销商库存信息:NATIONAL-SEMICONDUCTORLMK00101SQX/NOPB LMK00101SQ/NOPB LMK00101SQE/NOPB LMK00101BEVAL/NOPB。

我的大学生活英语作文150词

我的大学生活英语作文150词下面是小编精心整理提供的关于大学生活的英语，供大家阅读参考。

我的大学生活英语作文1：In my understanding, if we refer to an ideal college life as a formal western dinner, then a high GPA, that is, Grade Point Average, should be the main course, while an active part in activities, together with associations, means the appetizer. Some romances, of course, play the role as desserts. They are the 3 key elements for an ideal college life.Those, however, are not what college life is all about. As we all know, college is wildly different from middle school. It connects not only adolescence to adulthood, but also the ivory tower to the real society. Therefore, the ideal college life is that I become matured both physically and mentally, and that I obtain qualified academic knowledge and get well prepared for society at the same time.Under this circumstance, I never expect my college life to be too ideal, or you can call it too perfect. It is not realistic to make all things on my own way, with everyone liking me, winning the first prize all the time, and so on. Of course, I’d like to lead a carefree life. However, this does little good to my future. What really helps is hardships like failure, betrayal, and unjust treatment. Only after experiencing those can I know what society is like, and what life is like.To conclude my speech, I wanna say, some positive experiences are surely part of the ideal college life. But, I should not forget about the negative sides. They are not less necessary.我的大学生活英语作文2：With time goes by, it becomes a bit hard for me to remember everything about myself at the first day of my college life. However, there was one thing for sure that I did feel quite excited and curious about my university. There is no doubt that students like me have struggled for a long time so that can be permitted to enter the university.随着时间的流逝，记得在我的第一天大学生活对我来说变得有点困难了。

通信工程专业英语教案

Ancient systems and optical telegraphy
Early telecommunications included smoke signals and drums. Talking drums1 were used by natives in Africa, New Guinea and South America, and smoke signals in North America and China. Contrary to what one might think, these systems were often used to do more than merely announce the presence of a military camp.
Telephone
The electric telephone was invented in the 1870s; it was based on earlier work with harmonic (multi-signal) telegraphs. The first commercial telephone services were set up in 1878 and 1879 on both sides of the Atlantic in the cities of New Haven and London. Alexander Graham Bell held the master patent for the telephone that was needed for such services in both countries. All other patents for electric telephone devices and features flowed from this master patent.

UPC1862资料

The mark shows major revised points.©1991, 1996Document No. S11431EJ3V0DS00 (3rd edition)Date Published December 1997 N CP(K)Printed in Japan2BLOCK DIAGRAMSSICSO VSSIHDF HDOHKO SGND HSOF1HSOF2HSOF3AFCF SV CC BGPE NHSO CPO FIO VSO N/P SCOCV CC1TINTCINACCFCKOCKFCOUT APCF CGND SCOF1SCOF2SCOF3CV CC2CV CC3VCOO DIVS ESCIRemark AFC :Automatic Frequency ControlACC :Automatic Color saturation level Control APC :Automatic Phase ControlSelecting divide ratio by DIVS pinSelecting TV transmission by N/P pinDIVS Divide ratioN/P pinTV transmissionH 1/8H PAL Open EXT IN with pin 18LNTSCL1/4In PAL, only correspond 4f SC (DIVS = L).System Block DiagramApplication to Process of Digital Video SignalAnalog34PIN CONFIGURATION (Top View)36-pin plastic shrink SOP (300 mil)SSI CSO VSSI HDF HDO HKO SGND HSOF1HSOF2HSOF3AFCF SV CC BGPE NHSO CPO FIO VSO N/PCV CV CVACCF:Chroma ACC FilterAFCF:Horizontal Sync AFC FilterAPCF:Chroma APC FilterBGPE:Burst Gate Pulse from ExternalCGND:Chroma GNDCIN:Chroma InputCKF:Color Killer FilterCKO:Color Killer OutputCOUT:Chroma OutputCPO:Clamp Pulse OutputCSO:Composite Sync OutputCV CC1-CV CC3:Chroma V CCDIVS:Divider Setting InputESCI:External Subcarrier InputFIO:Field ID OutputHDF:Horizontal Sync Detect FilterHDO:Horizontal Sync Detect OutputHKO:Horizontal Sync Killer OutputHSOF1-HSOF3:32f H VCO FilterNHSO:Negative Horizontal Sync OutputN/P:NTSC/PAL Mode SelectSCO:Subcarrier OutputSCOF1-SCOF3:f SC VCO FilterSGND:Sync GNDSSI:Horizontal Sync Separation InputSV CC:Sync V CCTINT:Tint ControlVCOO:VCO OutputVSO:Vertical Sync OutputVSSI:Vertical Sync Separation Input5PIN FUNCTIONS(1/12)6Note Chroma burst amplitude from pin 4: 150 mV p-p7Note Chroma burst amplitude from pin 4: 150 mV p-p 8Note Chroma burst amplitude from pin 4: 150 mV p-p910Note When only 0.3 V p-p sync signal is input to pin 36Note When only 0.3 V p-p sync signal is input to pin 36ELECTRICAL SPECIFICATIONSABSOLUTE MAXIMUM RATINGS (T A = 25 °C, unless otherwise specified)Parameter Symbol Ratings UnitSupply voltage V CC7VInput signal voltage (Chroma signal)e i43V p-pInput signal voltage (H sync separation)e i363V p-pInput signal voltage (V sync separation)e i343V p-pInput signal voltage (EXT)e i18V CC V p-pTint control signal voltage e c3V CC V Output current I O–7mAPermissible package power dissipation P D570 (T A = 75°C)mW (when mounted on PCB)Operating ambient temperature T A–10 to +75°C Storage temperature T stg–40 to +125°CCaution Expose to Absolute Maximum Rating for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently.The device should be operated within the limits specified under DC and AC Characteristics.RECOMMENDED OPERATING CONDITIONSParameter Symbol MIN.TYP.MAX.Unit Supply voltage V CC 4.5 5.0 5.5VInput signal voltage (Chroma signal)e i4150mV p-p Input signal voltage (H sync separation)e i36 1.0V p-pInput signal voltage (V sync separation)e i34 1.0V p-pInput signal voltage (EXT IN HIGH voltage)e iH18 2.0VInput signal voltage (EXT IN LOW voltage)e iL180.8V Divider selector voltage 1 (1/8)V17 (8) 4.8V Divider selector voltage 2 (1/4)V17 (4)0.2VTint control voltage V3 2.5VNTSC/PAL select voltage (PAL)V19P 4.5VNTSC/PAL select voltage (NTSC)V19N0.5VELECTRICAL CHARACTERISTICS (at T A = 25±3 °C, RH ≤ 70 %, V CC = 5 V, unless otherwise specified)Chroma sectionParameter Symbol Condition MIN.TYP.MAX.UnitSupply current I CC (C)V CC (C) = 5 V172125mAof chroma section No current on pin 2, 14 and 15ACC amplitude ACC1Fluctuation of chroma output level at +6 dB–2.00+2.0dB characteristic 1change of chroma input burst signal(0 dB = 150 mV p-p)ACC amplitude ACC2Fluctuation of chroma output level at –20 dB–5.0–1.0+1.0dB characteristic 2change of chroma input burst signal(0 dB = 150 mV p-p)Color killer set point e KS Input level at killer ON with chroma input burst–45–39–33dBsig. (0 dB = 150 mV p-p) being attenuatedColor residual of color killer e KR Residual level of chroma output in Killer ON--15mV p-pstate when chroma input burst signal of150 mV p-p is inputChroma output level E COUT Chroma output level when chroma input burst 1.1 1.3 1.5V p-psignal of 150 mV p-p is inputColor killer output E CKOH (1)High level of color killer output at color killer 2.7 3.5-V High level (1)OFFI OH = –400 µAColor killer output E CKOH (2)High level of color killer output at color killer 3.5 4.0-V High level (2)OFFI OH = –20 µAColor killer output E CKOL Low level of color killer output at color killer ON-0.20.4V Low level I OL = +2 mAAPC lock-in range f P Frequency pulled by APC with chroma input±400±600-Hzburst frequency changed (f SC conversion)VCO control sensitivityβP Rate of variation of frequency when APC filter8.010.012.0Hz/mVpin is changed from –0.025 V to +0.025 V(f SC conversion)Phase variable rangeθCONT Amount of phase shift when voltage of phase±40±55-degcontrol pin is set at 2.5 V + 1 VVCO output level e VCOO VCO output level when chroma input burst 1.0 1.3 1.6V p-psignal of 150 mV p-p is inputf SC output level e SCO f SCO output level when chroma input burst210300390mV p-psignal of 150 mV p-p is inputDivider select voltage VDIVSL1/4 freq. division if V DIVS < V DIVSL--0.5VV DIVSH EXT IN with V DIVS : OPEN4.5--V 1/8 freq. division if V DIVSH < V DIVSNTSC/PAL select voltage V N/PT f V = 60 Hz if V N/P < V N/PT 1.7 2.0 2.3Vf V = 50 Hz if V N/PT < V N/PSync sectionParameter Symbol Condition MIN.TYP.MAX.UnitSupply current I CC (1)V CC (1) = 5 V121518mA of Sync section No current on pin 25DC level of H sync V SSI Voltage of pin 36 when connected to GND via 1.9 2.2 2.5V separation input10 kΩ resistorDC level of V sync V VSSI Voltage of pin 34 when connected to GND via 1.9 2.2 2.5V separation input10 kΩ resistorSync separation output E CSOH1High level of sync separation output when only 2.7 3.8-V High level (1)0.3 V p-p sync signal is input to pin 36I OH = –400 µASync separation output E CSOH2High level of sync separation output when only 3.5 4.3-V High level (2)0.3 V p-p sync signal is input to pin 36I OH = –20 µASync separation output E CSOL Low level of sync separation output when only-0.10.4V Low level0.3 V p-p sync signal is input to pin 36I OL = +2 mAHD output E NHSOH1High level of synchronized HD output when 2.7 3.8-V High level (1)only 0.3 V p-p sync signal is input to pin 36I OH = –400 µAHD output E NHSOH2High level of synchronized HD output when 3.5 4.3-V High level (2)only 0.3 V p-p sync signal is input to pin 36I OH = –20 µAHD output E NHSOL High level of synchronized HD output when-0.10.4V Low level only 0.3 V p-p sync signal is input to pin 36I OL = +2 mAVD output E VSOH1High level of synchronized VD output when 2.7 3.8-V High level (1)only 0.3 V p-p sync signal is input to pin 36I OH = –400 µAVD output E VSOH2High level of synchronized VD output when 3.5 4.3-V High level (2)only 0.3 V p-p sync signal is input to pin 36I OH = –20µAVD output E VSOL High level of synchronized VD output when-0.10.4V Low level only 0.3 V p-p sync signal is input to pin 36I OL = +2 mAClamp output E CPOH1High level of synchronized Clamp output when 2.7 3.8-V High level (1)only 0.3 V p-p sync signal is input to pin 36I OH = –400 µAClamp output E CPOH2High level of synchronized Clamp output when 3.5 4.3-V High level (2)only 0.3 V p-p sync signal is input to pin 36I OH = –20 µAClamp output E CPOL High level of synchronized Clamp output when-0.10.4V Low level only 0.3 V p-p sync signal is input to pin 36I OL= +2 mAParameter Symbol Condition MIN.TYP.MAX.UnitField ident. output E FIOH1High level of synchronized Field ident. output 2.7 3.8-V High level (1)when only 0.3 V p-p sync signal is input to pin 36I OH = –400 µAField ident. output E FIOH2High level of synchronized Field ident. output 3.5 4.3-V High level (2)when only 0.3 V p-p sync signal is input to pin 36I OH = –20 µAField idnet. output E FIOL High level of synchronized Field ident. output-0.10.4V Low level when only 0.3 V p-p sync signal is input to pin 36I OL = +2 mAH detection output E FIOH1High level of asynchronized H detect output 2.7 3.8-V High level (1)without H sync inputI OH = –400 µAH detection output E FIOH2High level of asynchronized H detect output 3.5 4.3-V High level (2)without H sync inputI OH = –20 µAH detection output E FIOL High level of synchronized H detect output-0.10.4V Low level when only 0.3 V p-p sync signal is input to pin 36I OL= +2 mAH sync lock-in range f HP Frequency range that can be pulled when only±400±500-Hz0.3 V p-p sync signal is input to pin 36 and Hsync frequency is varied (f SC conversion)Horizontal VCO controlβH Rate of variation of frequency when APC filter–1.6–1.3–0.9Hz/mV sensitivity pin is changed form 3.0 V to 3.4 V without Hsync input (f SC conversion)Horizontal VCO free-run f HO Frequency difference of HD output from f H–100–25+50Hz frequency when H sync input is not appliedPulse width of HD output P WNHSO Pulse width of synchronized HD output when 3.8 4.0 4.2µsonly 0.3 V p-p sync signal is input to pin 36Pulse width of VD output P WVSO1Pulse width of synchronized VD ODD- 6.0-H NoteP WVSO2output when only 0.3 V p-p syncEVEN- 5.5-H Note signal is input to pin 36Pulse width of Clamp output P WCPO Pulse width of synchronized Clamp output when 3.4 3.6 3.8µsonly 0.3 V p-p sync signal is input to pin 36Oscillation start voltage of V ST Output voltage at HD when V CC is gradually-- 4.2V horizontal VCO increased from 0 V without H sync inputH killer output Low level E HKOL Low level of synchronized H killer output when--0.4Vonly 0.3 V p-p sync signal is input to pin 36Change value of Chroma outputBurst gate input V BGPE1Burst gate pulse input voltage when Clamp 1.6 1.9 2.0V Threshold level 1voltage begins Low level is gradually increasedfrom 0 V without signal inputNote H: Horizontal scanning period21Parameter Symbol Condition MIN.TYP.MAX.UnitBurst gate input V BGPE2Burst gate pulse input voltage when Clamp 3.8 4.0 4.2V Threshold level 2voltage begins High level is graduallyincreased from V BGPE1 without signal inputVertical free-running f V1 (50)Frequency ratio of HD output to VD output-f H/352-Hz frequency 1H sync input: No signalf V1 (60)Pin 33 input: V CC-f H/288-HzV sync input: V CCVertical free-running f V2 (50)Same as f V1 with the following exception-f H/288-Hz frequency 2f V2 (60)V sync input: GND-f H/240-Hz Vertical free-running f V3 (50)Same as f V1 with the following exception-f H/368-Hz frequency 3f V3 (60)Pin 33 input: GND-f H/296-Hz Vertical free-running f V4 (50)Same as f V1 with the following exception-f H/272-Hzfrequency 4f V4 (60)Pin 33 input: GND-f H/232-Hz V sync input: GND22TIMING CHARTS (Horizontal Period)Comp VideoInputComp SyncOutput(CSO)HD Output(NHSO)CLAMPOutput(CPO)23CAUTION AT DESIGNINGResonatorsNEC evaluates µPC1862 using resonators which are shown below in design and development process.If the different product is used as a resonator, electrical specification value described in this document is not assured.And when connecting resonator to external circuit, there is need to consider temperature specification, voltage fluctuation and product variation. In this case, normal operation is not assured in the application circuit including the different product.Use the resonators which are shown below when you design circuit.32 f H VCO resonator X1:in application example circuitX1(PAL):CSB500F2 (MURATA)(NTSC):CSB503F2 (MURATA)nf SC VCO resonator X2X2:HC-49/U (KINSEKI, µPC1860 adoption)Reference data of 4f SC, 8f SC VCO resonator (KINSEKI)Item NTSC for 4f SC NTSC for 8f SC PAL for 4f SCName HC-49/UFrequency14.31818 MHz28.63636 MHz17.34475 MHzOvertone Order Fundamental (AT cut)Fundamental (BT cut)Fundamental (AT cut)Operating Temperature–10 to +70°CFrequency Permitted±30 × 10–6±50 × 10–6±30 × 10–6 Tolerance (25±5°C)Frequency Temperature±30 × 10–6±100 × 10–6±30 × 10–6 Specification (to 25°C)Equivalent Serial Resistance50 Ω or lessParallel Capacitance7.0 pF or less3rd harmonic standard3rd harmonic frequency is over–3rd harmonic frequency is over3f O (42.95454 MHz) + 7.5 kHz3f O (53.203425 MHz) + 7.5 kHz25Recommended patternThe µPC1862 generates system clock for synchronous signal processing and clock generate processing.If the supply voltage, line placement and routing are not set appropriately that the µPC1862 cannot generate correct system clock.Though the recommended pattern is not shows in this document, note points shown below at designing.1.For synchronous section and chroma section, each power supply must be isolated.2.Lines to pin 9 to pin 13 should be as thick and short as possible.3.Connect resonator as near IC as possible. Don’t put GND line between resonator pins for parasitism capacitance. 2628Care Point for Planning of Application Circuit 1.Processing of V CC pinPlease isolate Chroma. V CC from Sync. V CC as follows. If you have external processing block of digital signal, don’t directly supply of the block’s V DD .2.Application of no using Chroma pinIf you don’t use Chroma pin but use Sync pin on µPC1862, you process pin 1 to pin 18 as follows.3.Application of no using Sync pinIf you don’t use Sync pin but use Chroma pin on µPC1862, you process pin 19 to pin 36 as follows. In this case, you need to input a pin 24 with burst gate pulse from external.In this application, you can’t use output of pin 20 to pin 23.F0.01 F µµinput29PACKAGE DRAWING36 PIN PLASTIC SHRINK SOP (300 mil)detail of lead end5°±5P36GM-80-300B-3ITEM MILLIMETERS INCHES A B C D E F G H I J K 15.54 MAX.0.8 (T.P.)1.8 MAX.1.557.7±0.30.97 MAX.0.612 MAX.0.005±0.0030.071 MAX.0.303±0.0120.2200.039 MAX.NOTEL M 0.100.6±0.21.15.60.0040.024+0.008–0.009Each lead centerline is located within 0.10mm (0.004 inch) of its true position (T .P.) at maximum material condition.0.0430.0610.031 (T.P.)0.20+0.10–0.050.008+0.004–0.002N0.100.0040.014+0.004–0.0030.350.125±0.075+0.10–0.05RECOMMENDED SOLDERING CONDITIONSWhen soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices.For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”(C10535E).Surface Mount DeviceµPC1862GS: 36-pin plastic shrink SOP (300 mil)Process Conditions SymbolInfrared ray reflow Peak temperature: 235 °C or below (Package surface temperature),IR35-00-2Reflow time: 30 seconds or less (at 210 °C or higher),Maximum number of reflow processes: 2 times.VPS Peak temperature: 215 °C or below (Package surface temperature),VP15-00-2Reflow time: 40 seconds or less (at 200 °C or higher),Maximum number of reflow processes: 2 times.Wave Soldering Solder temperature: 260 °C or below, Flow time: 10 seconds or less,WS60-00-1Maximum number of flow process: 1 time,Pre-heating temperature: 120 °C or below (Package surface temperature).Partial heating method Pin temperature: 300 °C or below,–Heat time: 3 seconds or less (Per each side of the device).Caution Apply only one kind of soldering condition to a device, except for “Partial heating method”, or the device will be damaged by heat stress.30[MEMO]31[MEMO]The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from useof such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.NEC devices are classified into the following three quality grades:"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications ofa device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.Standard:Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronicequipment and industrial robotsSpecial:Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designedfor life support)Specific:Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.Anti-radioactive design is not implemented in this product.M4 96.5。

33389资料

Document Number: MC33389Rev. 5.0, 3/2007Freescale Semiconductor Advance Information* This document contains certain information on a new product.Specifications and information herein are subject to change without notice.© Freescale Semiconductor, Inc., 2007. All rights reserved.System Basis Chip with Low Speed Fault Tolerant CANThe 33389 is a monolithic integrated circuit combining manyfunctions frequently used by automotive Engine Control Units (ECUs). It incorporates a low speed fault tolerant CAN transceiver.Features•Dual Low Drop Voltage Regulators, with Respectively 100 mA and 200 mA Current Capabilities, Current Limitation, and Over Temperature Detection with Pre-warning • 5.0 V Output Voltage for V1 Regulator•Three Operational Modes (Normal, Stand-by, and Sleep Modes) Separated from the CAN Interface Operating Modes•Low Speed 125 kBaud Fault Tolerant CAN Interface, Compatible with 33388 Stand Alone Physical Interface •V1 Regulator Monitoring and Reset Function•Three External High Voltage Wake-Up Inputs, Associated with V3 V BAT Switch•100 mA Output Current Capability for V3 V BAT Switch Allowing Drive of External Switches or Relays•Low Stand-by and Sleep Current Consumption•V BAT Monitoring and V BAT Failure Detection Capabilities •DC Operating Voltage up to 27 V •40 V Maximum Transient Voltage•Programmable Software Window Watchdog and Reset•Wake-Up Capabilities (CAN Interface, Local Programmable Cycle Wake•INterface with the MCU through the SPI•Pb-Free Packaging Designated by Suffix Codes VW and EGFigure 1. 33389 Simplified Application DiagramSYSTEM BASIS CHIP33389ORDERING INFORMATIONDevice Temperature Range (T A )PackageMC33389CDH/R2-40 to 125°CHSOP-20MC33389CVW/R2MC33389CDW/R2SO-28MC33389DDW/R2Analog Integrated Circuit Device Data33389DEVICE VARIATIONSDEVICE VARIATIONSTable 1. Device VariationsFreescale Part No.V1 UndervoltageMC33389CDH MC33389CVW MC33389CDW In V1 undervoltage condition, device remains in permanent reset state until V1 returns to normal conditions. V1 is protected by overcurrent and overtemperature functions.MC33389DDWThe sole difference between the C version and the D version is V1 Reset Threshold. Reference V1 Reset Threshold on V1 on page 9.INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33389 Simplified Internal Block Diagram33389 Analog Integrated Circuit Device DataAnalog Integrated Circuit Device Data33389PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33389 Pin ConnectionsTable 1. 33389 Pin Definitions: HSOSP 20-LeadA functional description of each pin can be found in the Functional Pin Description section beginning on page 17.Pin NumberPin NameFormal Name Definition1TX Transmitter DataTransmitter input of the LS CAN interface2V1Voltage Regulator One This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.3RX Receiver DataReceiver output of the LS CAN interface 4RST Reset This is an Input/Output pin.5INT Interrupt Output This output is asserted LOW when an enabled interrupt condition occurs.6MISO Master In/Slave Out This pin is the tri-state output from the shift register. 7MOSI Master Out/Slave In This pin is for the input of serial instruction data. 8SCLK System Clock This pin clocks the internal shift registers.9CS Chip Select This pin communicates with the system MCU and enables SPI communication.10 - 12L0 - L2Level 0 - 2 inputs(L0: L2)Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode.13RTH RTH Pin for the connection of the bus termination to CANH 14CANLCAN Low CAN low input/output15GND Ground This pin is the ground of the integrated circuit.16CANH CAN HighCAN high input/output17V2Voltage Regulator Two This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.18RTL RTL Pin for the connection of the bus termination to CANL 19VBAT Voltage Battery This pin is voltage supply from the battery.20V3Voltage RegulatorThreeThis pin is a 10 Ω switch to V BAT , used to supply external contacts or relays.Analog Integrated Circuit Device Data 33389PIN CONNECTIONSTable 2. 33389 Pin Definitions: SOICW 28-LeadA functional description of each pin can be found in the Functional Pin Description section beginning on page 17.Pin NumberPin Name Formal Name Definition1TXTransmitter Data Transmitter input of the LS CAN interface2V1Voltage Regulator OneThis 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.3RXReceiver Data Receiver output of the LS CAN interface 4RST Reset This is an Input/Output pin.5INT Interrupt This output is asserted LOW when an enabled interrupt condition occurs.6 -9 20 - 23GND GroundThese device ground pins are internally connected to the package lead frame to provide a 33389-to-PCB thermal path.10MISO Master In/Slave OutThis pin is the tri-state output from the shift register. 11MOSIMaster Out/Slave In This pin is for the input of serial instruction data. 12SCLKSystem Clock This pin clocks the internal shift registers.13CS Chip Select This pin communicates with the system MCU and enables SPI communication.14, 15, 16L0: L2Wake-up Input (L0: L2)Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode.17NCNo Connect This pin does not connect.18RTH Thermal Resistance High Pin for the connection of the bus termination to CANH 19CANLCAN Low CAN low input/output 24CANHCAN High CAN high input/output25V2Voltage Regulator TwoThis 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.26RTL Thermal Resistance LowPin for the connection of the bus termination to CANL 27VBAT Voltage Battery This pin is voltage supply from the battery.28V3Voltage Regulator ThreeThis pin is a 10 Ω switch to V BAT , used to supply external contacts or relays.Analog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 3. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingsSymbol Value UnitELECTRICAL RATINGS DC Voltage at VBAT Pin V BAT -0.3 to 27V Transient Voltage at VBAT Pint < 500 ms (load dump)V BAT 40V DC Voltage at Pins CANH and CANL V BAT -20 to 27V Transient Voltage at Pins CANH and CANL 0.0 < V2 < 5.5, V BAT > 0.0, t < 500 msV BAT-40 to 40VCoupled Transient Voltage at Pins CANH and CANLWith 100 Ω Termination Resistors, Coupled Through 1.0 nF (1)V BAT-100 to 100 VDC Voltage at Pins V1 and V2V BAT -0.3 to 6.0V DC Current at Output Pins RX, MISO, RST, INT V BAT -20 to 20mA DC Voltage at Input Pins TX, MOSI, CS, RST V BAT -0.3 to 6.0V DC Voltage at Pins L0, L1, L20.0 < V BAT < 40 V V BAT-0.3 to 40VCurrent at Pins L0, L1, L2V BAT -15mA Transient Current at Pin V3V BAT -30 to 20mA DC Voltage at pins RTH and RTLV BAT -0.3 to 40V ESD Voltage on any Pin (HBM 100 pF, 1.5 K)V BAT -2.0 to 2.0kV ESD Voltage on L0, L1, L2, CANH, CANL, VBAT V BAT -2.0 to 2.0kV ESD Voltage on any Pin (MM 200 pF, 0 Ω)V BAT-150 to 150VTHERMAL RATINGSOperating Junction Temperature T J -40 to 150°C Ambient Temperature T A -40 to 125°C Storage TemperatureT S-55 to 165°CNotes1.Pulses 1, 2, 3a, and 3b according to ISO7637.Analog Integrated Circuit Device Data 33389ELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTHERMAL RESISTANCERTH, RTL Termination ResistanceR RTHRTL 500 to 16 kΩJunction to Heatsink Thermal Resistance for HSOP-2033% Power on V1, 66% on V2 (including CAN) (2) R AJC3.1°C/WJunction to Pin Thermal Resistance for SO-28WD (3) R AS/P 17°C/W Thermal Shutdown TemperatureT SD 165°C Peak Package Reflow Temperature During Reflow (4), (5)T PPRTNote 5°CNotes2.Refer to thermal management in device description section.3.Refer to thermal management in device section. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 of SO28WB package.4.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits maycause malfunction or permanent damage to the device.5.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package ReflowTemperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Table 3. Maximum Ratings (continued)All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingsSymbolValueUnitAnalog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 4. Static Electrical CharacteristicsCharacteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitPOWER INPUT (VBAT)Nominal VBAT Operating Range V BAT 5.5—18V Functional VBAT Operating Range V BAT 5.5—27V V BAT Threshold for BAT FAIL Flag BAT FAIL2.0— 4.0V Delay for Signalling BAT FAIL TFAIL—150400µs Overvoltage V BAT Threshold BAT HIGH 182022V Delay for Setting BAT HIGH Flag T HIGH 4.01850µs Supply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP1—75125µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = -40°C to 25°C I SLEEP2——210µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Enabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP3—105155µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Enabled V BAT = 12 V, T J = -40°C to 25°C I SLEEP4——250µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP5——300µASupply Current in Stand-by Mode I STB2—0.5 1.0mA Supply Current in Normal Mode Normal Mode with I(V1) = 1 I(V2) = 0Bus in Recessive State I NREC—3.57.0mAPOWER OUTPUT V1 Output Voltage 0 mA < I OUT < 100 mA 5.5 V < V BAT < 27 V V1NOM4.855.05.15VV1 Output Voltage I OUT =< 100 mA 27 V < V BAT < 40 V V14.85.05.2VV1 Drop Voltage I OUT =< 100 mA (6)V1DROP —0.350.5VNotes6.Measured when V1 has dropped 100mV below its nominal valueAnalog Integrated Circuit Device Data 33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED) V1 Output Current Limitation V1NOM - 100 mVI1MAX130170200mAV1 Overtemperature Shut OFF Threshold Junction TemperatureTV1H 160—190°CV1 Pre-Warning Temperature Threshold Junction TemperatureTV1L 130—160°CV1 Temperature Threshold Difference TV1H-TV1L20—40°C V1 Reset Threshold on V15.5 V < V BAT < 27 V (C Version)(D Version)VR1 4.1V2 - 0.4 4.3V1 - 0.284.8V1 - 0.1VV1 Reset Active V1 RangeV1R 1.0VR1—V V1 Reverse Current from V1 to V BAT and GND V1 = 4.9 V, 0 < V BAT < 4.9 V IREV——1.0mAV2 Output Voltage0 mA < I OUT < 200 mA 5.5 V < V BAT < 40 V V2NOM 4.75 5.0 5.25 VV2 Drop Voltage I OUT = 200 mA (7)V2DROP —0.2 0.5VV2 Drop Voltage I OUT = 20 mA (7)V2DROP —0.050.15VV2 Output Current Limitation V2NOM -100 mVI1MAX220280350mAV2 Threshold on V2 to Report V2 OFF V2 Nominal V R24.14.554.75VV R2 Delay TimeV R220—70µs V2 Overtemperature Pre-Warning Threshold V2 Junction TemperatureT V2L130—160°CV2 Overtemperature Switch-OFF Threshold V2 Junction Temperature T V2H155—185°CV2 Line Regulation 9.0 V < V BAT < 16.5V2LR1-15—+15mVV2 Load Regulation 4.0 mA < I LOAD < 200 mA V2LR2-75—+75mVV2 Line Ripple Rejection 100 Hz, 1.0 V PP on V BAT (8)V2LRR3055—dBNotes7.Measured when V1 has dropped 100mV below its nominal value 8.Guaranteed by design; however, it is not production testedTable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitAnalog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED) V2 Percentage Difference V2-V1V BAT > 9.0, I V1 = 20 mA, I V2 = 40 mA V2V2-V1-3.0—3.0%V3 High Level Voltage DropI V3 = -50 mA, 9.0 V < V BAT < 40 V V3DROP—0.41.0VV3 High Level Voltage DropI V3 = -50 mA, 6.0 V < V BAT < 9.0 V V3DROP——1.5VV3 Leakage Output Limitation 5.5 V < V BAT < 27 V I3LIM100150250mAV3 Leakage Current V3 = 0 (V3 OFF)I3LEAK——15µAV3 Overtemperature Detection Junction TemperatureT V3155—185°CV3 Voltage with -30 mA (negative current for Relay Switch OFF) No Functional Error Allowed for t < 100 msV V30.3—0.5VCAN Transceiver V2 for Forced Bus Stand-by Mode (Fail Safe) VRC2 3.0 3.9 4.7V CANH/L Differential Receiver, Threshold VoltageV CANTH -3.2—-2.5V CANH/L Differential Receiver, Dominant to Recessive Threshold (Bus Failures 1, 2, and 5)V CANDRTH-3.2—-2.5VCANH Recessive Output Voltage TX = High, R(RTH) < 4.0 k V CANH——0.2VCANL Recessive Output Voltage TX = High, R(RTH) < 4.0 k V CANLV2-0.2——VCANH Output Voltage, DominantTX = 0 V, BusNormal Mode, I CANH = - 40 mA V CANHV2-1.4——VCANL Output Voltage, DominantTX = 0 V, Bus Normal Mode, I CANL = - 40 mA V CANL——1.4VCANH Output Current Limit (V CANH = 0.0 V, TX = 0)I CANH5075100mACANL Output Current Limit (V CANL = 14 V, TX = 0)I CANL5095130mADetection Threshold for Short Circuit to Battery Voltage Bus Normal ModeV CANH -V CANL7.37.98.9VDetection Threshold for Short Circuit to Battery Voltage Bus Stand-by ModeV CANHV BAT /2+3—V BAT /2+5VCANH Output Current, Failure 3Bus Stand-by Mode V CANH = 12 V I CANHF3—5.010µACANL Output Current, Failure 4Bus Stand-by Mode, V CANL = 0.0 V, V BAT = 12 VI CANLF4—0.02.0µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED)CANL Wake-Up Voltage ThresholdBus Stand-by ModeV WAKEL 2.5 3.3 3.9VCANH Wake-Up Voltage ThresholdBus Stand-by ModeV WAKEH 1.2 2.0 2.7VWake-Up Threshold Difference V WAKEL -V WAKEH0.2——V CANH Single Ended Receiver ThresholdFailures 4, 6, and 7V CANH 1.5 1.85 2.15VCANL Single Ended Receiver ThresholdFailures 3 and 8V CANL 2.8 3.05 3.4VCANL Pull-Up CurrentBus Normal ModeI CANLPU457590µACANH Pull Down CurrentBus Normal ModeI CANLPD457590µA Receiver Differential Input Impedance CANH/CANL R DIFF100—180kΩDifferential Receiver Common Mode Voltage Range V COM-8.0—8.0V RTL to V2 Switch on ResistanceI OUT < -10 mA, Bus Normal Operating ModeR RTL102570ΩRTL to Battery Switch Series ResistanceBus Stand-by ModeR RTL8.012.520kΩRTH to Ground Switch on ResistanceI OUT < 10 mA, All ModesR RTH—2570ΩCONTROL INTERFACEHigh Level Input Voltage VIH0.7 V1—V1 + 0.3 V VCS Threshold for SPI Wake-UpSBC in Sleep Mode, V1 < 1.5 VV CSTH— 2.2—VCS Filter Time for SPI Wake-UpSBC in Sleep Mode, V1 < 1.0 Vt CSFT—— 3.0µsLow Level Input Voltage VIL-0.3—0.3 V1V High Level Input Current on CSV I = 4.0 VI CSH-100—-20µALow Level Input Current on CSV I = 1.0 VI CSL-100—-20µATX High Level Input CurrentV I = 4.0 VI TXH-200-80-25µATX Low Level Input CurrentV I = 1.0 VI TXL-800-320-100µASI, SCLK Input Current0 < V IN < V1I SISLK-10—+10µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT, -40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.Characteristic Symbol Min Typ Max UnitELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSCONTROL INTERFACE (CONTINUED)RX, INT, MISO High Level Output Voltage I 0 = -250 µAV OHV1 - 0.9—V1VRX, INT, MISO Low Level Output Voltage I 0 = -1.5 mAV OL0.0—0.9VRX, INT, MISO Tri-Stated SO Output Current 0 V < V SO < V1I Z-2.0—+2.0µARST High Level Input Voltage V IH 0.7 V1—V1 + 0.3 V —RST Low Level Input Voltage V IL -0.3—-0.3 V1V RST High Level Output Current 10.0 < V OUT < 0.5 V1I RSTH1-50-30-10µARST High Level Output Current 20.5 < V OUT < V1I RSTH2—-300—µARST Low Level Output Voltage (I 0 = 1.5 mA)1.0 V < V BAT < 27 VV RST0.0—0.9VLX/Wake-Up Positive Switching Threshold 6.0 V <V BAT < 16 VV WUP3.03.74.5VLX/Wake-Up Negative Switching Threshold 6.0 V <V BAT < 16 V V WUN2.53.03.8VLX/Wake-Up Hysteresis 6.0 V <V BAT < 16 VV HYS—700—mALX/Wake-Up Leakage Current 0 < V WU < V BAT I LXWU -5.0—+5.0µA LX Input Current at 40 VV IN—350600µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 5. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.Characteristic Symbol Min Typ Max Unit MICROCONTROLLER INTERFACEAC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Recessive toDominant StateC LOAD - 10 nF, 133 Ω Termination Resistorst CANRD 3.5 5.010V/µsAC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Dominant toRecessive StateC LOAD - 10 nF, 133 Ω Termination Resistorst CANDR 2.0 3.510V/µsAC Propagation Delay TX to RX LowC LOAD - 10 nF, 133 Ω Termination Resistorst DH— 1.2 2.0µsAC Propagation Delay TX to RX HighC LOAD - 10 nF, 133 Ω Termination Resistorst DL— 2.0 3.0µsWake-Up Filter Time tWUFT8.02038µs RST Duration after V1 High t RES— 1.0—ms SCLK Clock Period t PSCLK500——ns SCLK Clock High Time t WSCLKH175——ns SCLK Clock Low Time t WSCLKL175——ns Falling Edge of CS to Rising Edge of SCLK t LEAD25050—ns Falling Edge of SCLK to Rising Edge of CS t LEAD25050—nsSI to Falling Edge of SCLK t SISU12525—ns Falling Edge of SCLK to SI t SI(HOLD)12525—nsSO Rise Time (C L = 200 pF)t RSO—2575nsSO Fall Time (C L = 200 pF)t FSO—2575ns SI, CS, SCLK Incoming Signal Rise Time t RSI——200ns SI, CS, SCLK Incoming Signal Fall Time t FSI——200—Time from Falling Edge of CS to SOLow Impedance High Impedance t SO(EN)t SO(DIS)——200200nsTime from Rising Edge of SCLK to SO Data Valid0.2 V1 or V2 < SO > 0.8 V1 or V2, C L = 200 pFt VALID—50125—Running Mode Oscillator Tolerance (Normal Request, Normal and Stand-byModes (9))RMOT-12—+12%Software Watchdog Timing 1 (9)tSW1 4.4 5.0 5.6msSoftware Watchdog Timing 2 (9)tSW28.81011.2msSoftware Watchdog Timing 3 (9)tSW317.62022.4msSoftware Watchdog Timing 4 (9)tSW4283236ms Notes9.Software watchdog timing accuracy is based on the running mode oscillator toleranceELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSMICROCONTROLLER INTERFACE (CONTINUED)Software Watchdog Timing 5 (10)t SW544.85158ms Software Watchdog Timing 6 (10)t SW6657483ms Software Watchdog Timing 7 (10)t SW788100112ms Software Watchdog Timing 8 (10).t SW8167190213ms Sleep Mode Oscillator Tolerance (10)SMOT -30—+30%Cyclic Sense/FWU Timing 1 Sleep Mode (10)t CY122.43246.6ms Cyclic Sense/FWU Timing 2 Sleep Mode (10)t CY244.86483.2ms Cyclic Sense/FWU Timing 3 Sleep Mode (10)t CY389.6128166.4ms Cyclic Sense/FWU Timing 4 Sleep Mode (10)t CY4179256333ms Cyclic Sense/FWU Timing 5 Sleep Mode (10)t CY5358512665ms Cyclic Sense/FWU Timing 6 Sleep Mode (10).t CY671710241331ms Cyclic Sense/FWU Timing 7 Sleep Mode (10) t CY7143420482662ms Cyclic Sense/FWU Timing 8 Sleep Mode (10)t CY85734819210650ms Ground Shift Threshold 1 (11)CAN Transceiver Active in Two Wire Operation GS1-1.0-0.7-0.3VGround Shift Threshold 2 (11)CAN Transceiver Active in Two Wire Operation GS2-1.5-1.2-0.8VGround Shift Threshold 3 (11)CAN Transceiver Active in Two Wire Operation GS3-2.0-1.7-1.3VGround Shift Threshold 4 (11)CAN Transceiver Active in Two Wire Operation GS4-2.6-2.2-1.7VBUS TRANSMITTERAC Minimum Dominant Time for Wake-Up on CANL or CANH Bus Stand-by Mode, V BAT = 12 V t WAKE4.0—40µsAC Failure 3 Detection Time Bus Normal Mode t AC3D10—60µsAC Failure 3 Recovery Time Bus Normal Mode t AC3R10—60µsAC Failure 6 Detection Time Bus Normal Mode t AC6D50—400µsAC Failure 6 Recovery Time Bus Normal Modet AC6R150—1000µsAC Failure 4, 7, and 8 Detection Time Bus Normal Modet AC478D0.75—4.0msNotes10.Cyclic sense and forced wake-up timing accuracy are based on the Sleep mode oscillator tolerance.11.No overlap between two adjacent thresholds.Table 5. Dynamic Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSBUS TRANSMITTER (CONTINUED)AC Failure 4, 7, and 8 Recovery Time Bus Normal Modet AC478R10—60µsAC Failure 3, 4, and 7 Detection Time Bus Stand-by Mode, V BAT = 12 V t AC347D0.8—8.0msAC Failure 3, 4 and 7 Recovery Time Bus Stand-by Mode, V BAT = 12 Vt AC347R—2.5—msAC Edge Count Difference Between CANH/CANL for Failures 1, 2, 5 Detection Bus Normal ModeCAN 125D—3.0——AC Edge Count Difference Between CANH/CANL for Failures 1, 2, 5 Recovery Bus Normal ModeCAN 125R—3.0——TX Permanent Dominant Timer Disable Time Bus Normal and Failure Modes t TXD0.75—4.0msPOWER INPUT TIMING V1 Reset Delay Time t D 2.0—20µs V1 Line Regulation9.0 V < V BAT < 16.5, I LOAD = 10 mA t D -152.0+15mVV1 Line Regulation5.5 V < V BAT < 27 V I LOAD = 10 mA t D -5010+50mVV1 Load Regulation1.0 mA < I LOAD < 100 mA t D -50—+50mVV1 Line Ripple Rejection100 Hz, 1.0 V PP on V BAT = 12 V, I LOAD = 100 mA (12)t D 3055—dBV1 Line Transient ResponseV BAT from 12 V to 40 V in 1.0 µs, (10 µF, ESR = 3 Ω)t D —27—mVV1 Load Transient ResponseI LOAD from 10 µA to 100 mA in 1.0 µs (CLOAD = 10 µF, ESR = 3 Ω) (13)t D —400—mVV1 Load Transient ResponseI LOAD from 10 µA to 100 mA in 1.0 µs (CLOAD = 10 µF, ESR= 0.1 Ω)t D—16—mVNotes12.Guaranteed by design. Not production tested.13.This condition does not produce a resetTable 5. Dynamic Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICS TIMING DIAGRAMSTIMING DIAGRAMSFigure 4. Input Timing Switch CharacteristicsSISCLKCSDon’t Care Don’t CareDon’t CareValidValidt LEAD t WSCLKH t WSCLKLt R t F t LAGt SISUt SI(HOLD)FUNCTIONAL DESCRIPTIONINTRODUCTION FUNCTIONAL DESCRIPTIONINTRODUCTIONThe System Basis Chip (SBC) is an integrated circuit dedicated to car body applications. It includes three main blocks:1. A dual voltage regulator2.Reset, watchdog, wake-up inputs, cyclic wake-up3.CAN low speed fault tolerant physical interfaceSuppliesTwo low drop regulators and one switch to V BAT are provided to supply the ECU microcontroller or peripherals, with independent control and monitoring through SPI.FUNCTIONAL PIN DESCRIPTIONTRANSMIT AND RECEIVE DATA (TX AND RX) The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TX is an input and controls the CANH and CANL line state (dominant when TX is LOW, recessive when TX is HIGH). RX is an output and reports the bus state.VOLTAGE REGULATOR ONE AND TWO(V1 AND V2)The V1 pin is a 3% low drop voltage regulator dedicated to the microcontroller supply (nominal 5V supply).The V2 pin is a low drop voltage regulator dedicated to the peripherals supply (nominal 5V supply).RESET (RST)The RST (reset) pin is an input/output pin. The typical reset duration from SBC to microcontroller is 1ms. If longer times are required, an external capacitor can be used. SBC provides two RST output pull-up currents. A typical 30µA pull up when Vreset is below 2.5V and a 300uA pull up when reset voltage is higher than 2.5V. RST is also an input for the SBC. It means the MC33389 is forced to Normal Request mode after RST is released by the microcontroller INTERRUPT (INT)The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared.INT output also reports a wake-up event.GROUND (GND)This pin is the ground of the integrated circuit.MASTER IN/ SLAVE OUT (MISO)MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin.MASTER OUT/ SLAVE IN (MOSI)MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin.SYSTEM CLOCK (SCLK)This pin clocks the internal shift registers for SPI communication.CHIP SELECT (CS)CS is the Chip Select pin of the serial peripheral interface (SPI). When this pin is LOW, the SPI port of the device is selected.LEVEL 0-2 INPUTS (L0: L2)The L0: L2 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by the SPI. These inputs can be used as wake-up events for the SBC.NO CONNECT (NC)No pin connection.TERMINATION RESISTANCE (HIGH AND LOW?) (RTH AND RTL)External CAN bus high and low termination resistance pins are connected to these pins.CAN HIGH AND CAN LOW OUTPUTS(CANH AND CANL)The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TX input level, and the state of CANH and CANL is reported through RX output. VOLTAGE BATTERY (VBAT)This pin is the voltage supply from the battery.VOLTAGE REGULATOR THREE (V3)This pin is a 10 Ω switch to VBAT, which is used to supply external contacts or relays.。

CDCE925 时钟芯片

• Flexible Clock Driver – Three User-Definable Control Inputs [S0/S1/S2] e.g., SSC Selection, Frequency Switching, Output Enable or Power Down – Programmable SSC Modulation – Enables 0-PPM Clock Generation – Generates Common Clock Frequencies Used With Texas Instruments DaVinci™, OMAP™, DSPs – Generates Highly Accurate Clocks for Video, Audio, USB, IEEE1394, RFID, Bluetooth®, WLAN, Ethernet™, and GPS
Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristic of each PLL.
16 Xout 15 S1/SDA 14 S2/SCL 13 Y1 12 GND 11 Y2 10 Y3
9 Vddout
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DaVinci, OMAP, Pro-Clock are trademarks of Texas Instruments.

国际贸易标准分类(简)

国际贸易标准分类（Standard International Trade Classification，简称：SITC）为用于国际贸易商品的统计和对比的标准分类方法。

现行“国际贸易标准分类”于1950年7月12日由联合国经济社会理事会正式通过，目前为世界各国政府普遍采纳的商品贸易分类体系。

到2006年为止，该标准分类经历了四次修改，最近的一次修改为第四次修订版，于2006年3月获联合国统计委员会第三十七届会议通过。

该分类法将商品分为为10大类、63章、223组、786个分组和1924个项目。

在它的编号中第一位数字表示类、第二位数字表示章、第三位数字表示组、第四位数字表示分组。

如果对分组再进行细分，五位数即表示品目，六位数字表示细目。

具体分类0 -食品和活畜00 -活的动物以外的其他动物的分裂00 - Live animals other than animals of division01 -肉及肉制品 01 - Meat and meat preparations02 -乳制品和鸟蛋 02 - Dairy products and birds' eggs03 -鱼（不是海洋哺乳动物），甲壳类，软体动物和水生无脊椎动物 03 - Fish (not marine mammals), crustaceans, molluscs and aquatic invertebrates, and preparations thereof04 -谷物和谷物制品 04 - Cereals and cereal preparations05 -蔬菜和水果 05 - Vegetables and fruit06 -糖，糖制品及蜂蜜 06 - Sugars, sugar preparations and honey07 -咖啡，茶，可可，香料，及其制造 07 - Coffee, tea, cocoa, spices, and manufactures thereof08 -喂养（不包括没有碾磨的谷物）08 - Feeding stuff for animals (not including unmilled cereals)09 -杂项食品产品和筹备工作09 - Miscellaneous edible products and preparations1 -饮料和烟草1 - Beverages and tobacco11 -饮料11 - Beverages12 -烟草及烟草制品 12 - Tobacco and tobacco manufactures2 -粗材料，不能食用，除燃料2 - Crude materials, inedible, except fuels21 -皮，表皮和毛皮，原料 21 - Hides, skins and furskins, raw22 -石油种子和含油果实 22 - Oil-seeds and oleaginous fruits23 -天然橡胶（包括合成和再生）23 - Crude rubber (including synthetic and reclaimed)24 -软木及木 24 - Cork and wood25 -纸浆及废纸 25 - Pulp and waste paper26 -纺织纤维（毛条除外和其他精梳羊毛）及其废料（不成纱或布料制造的）26 - Textile fibres (other than wool tops and other combed wool) and their wastes (not manufactured into yarn or fabric)27 -原油肥料，矿产和原油（不包括煤，石油和宝石）27 - Crude fertilizers, other than those of division 56, and crude minerals (excluding coal, petroleum and precious stones)28 -金属矿砂及金属废料 28 - Metalliferous ores and metal scrap29 -原油动物和植物材料制2 9 - Crude animal and vegetable materials, nes3 -矿物燃料，润滑剂和相关材料 3 - Mineral fuels, lubricants and related materials32 -煤，焦煤及煤球 32 - Coal, coke and briquettes33 -石油，石油产品及副产品 33 - Petroleum, petroleum products and related materials34 -天然气(天然和制造的) 34 - Gas, natural and manufactured35 -电流 35 - Electric current4 -动物和植物油，油脂和蜡 4 - Animal and vegetable oils, fats and waxes41 -动物油脂 41 - Animal oils and fats42 -固定油脂，原油，成品或分馏 42 - Fixed vegetable fats and oils, crude, refined or fractionated43 -动物或植物油脂，加工过的;不宜食的混合物或动物或植物脂肪或油类，不另说明 43 - Animal or vegetable fats and oils, processed; waxes of animal or vegetable origin; inedible mixtures or preparations of animal or vegetable fats or oils, n.e.s5 -化学品及有关产品，不另说明 5 -Chemicals and related products, n.e.s.51 -有机化工产品 51 - Organic chemicals52 -无机化学品 52 - Inorganic chemicals53 -染料，鞣革料 53 - Dyeing, tanning and colouring materials54 -医药产品 54 - Medicinal and pharmaceutical products55 -精油及香膏和香水原料;厕所，抛光和清洗的准备工具 55 - Essential oils and resinoids and perfume materials; toilet, polishing and cleansing preparations56 -肥料（除组272） 56 - Fertilizers (other than those of group 272)57 -初级形状塑料 57 - Plastics in primary forms58 -在非塑料，初级形状 58 - Plastics in non-primary forms59 -化学材料及制品，不另说明 59 - Chemical materials and products, n.e.s6 -主要以材料分类的制成品 6 - Manufactured goods classified chiefly by material61 -皮革，皮革制品，不另说明，并经处理的毛皮 61 - Leather, leather manufactures, nes, and dressed furskins62 -橡胶制品，不另说明 62 - Rubber manufactures, nes63 -软木及木制品（不包括家具） 63 - Cork and wood manufactures (excluding furniture)64 -纸，纸板和纸浆的文章，纸或纸板 64 - Paper, paperboard and articles of paper pulp, of paper or of paperboard65 -纺织纱线，织物，制成品，不另说明，以及相关产品 65 - Textile yarn, fabrics, made-up articles, nes, and related products66 -非金属矿产制品，不另说明 66 - Non-metallic mineral manufactures, nes67 -钢铁 67 - Iron and steel68 -有色金属 68 - Non-ferrous metals69 -金属制品 69 - Manufactures of metals, nes7 -机械和运输设备 7 - Machinery and transport equipment71 -发电机械设备 71 - Power-generating machinery and equipment72 -个别工业专用机械 72 - Machinery specialized for particular industries73 -金属加工机械 73 - Metalworking machinery74 -一般工业机械和设备和机器零件，不另说明 74 - General industrial machinery and equipment, nes, and machine parts, nes75 -办公室机器和自动资料处理仪器 75 - Office machines and automatic data-processing machines76 -电信和录音及音响设备和仪器 76 - Telecommunications andsound-recording and reproducing apparatus and equipment77 -电气机械，仪器和用具，巢，及零件（包括非电气同行，电家庭型设备） 77 - Electrical machinery, apparatus and appliances, nes, and electrical parts thereof (including non-electrical counterparts, nes, of electrical household-type equipment)78 -道路车辆（包括气垫车辆） 78 - Road vehicles (including air-cushion vehicles)79 -其他运输设备 79 - Other transport equipment8 -杂项制品 8 - Miscellaneous manufactured articles81 -预制建筑物，管道，发热及照明装置和设备，不另说明 81 - Prefabricated buildings; sanitary, plumbing, heating and lighting fixtures and fittings, nes82 -家具及其零件，床上用品，床垫，床垫，软座垫及类似的填充制品 82 - Furniture, and parts thereof; bedding, mattresses, mattress supports, cushions and similar stuffed furnishings83 -旅游用品，手袋及类似容器 83 - Travel goods, handbags and similar containers84 -服装及衣服配件 84 - Articles of apparel and clothing accessories85 -鞋子 85 - Footwear87 -专业，科学及控制用仪器及器具 87 - Professional, scientific and controlling instruments and apparatus, nes88 -摄影仪器，设备和供应品，光学产品;钟表 88 - Photographic apparatus, equipment and supplies and optical goods, nes; watches and clocks89 -杂项制品,不另说明 89 - Miscellaneous manufactured articles, nes9 -分类商品，而不是其他地方的贸易标准分类交易 9 - Commodities and transactions not classified elsewhere in the SITC91 -邮政包裹并无按实物 91 - Postal packages not classified according to kind93 -特殊交易和商品并无按实物 93 - Special transactions and commodities not classified according to kind96 -硬币（金币除外），没有法定货币 96 - Coin (other than gold coin), not being legal tender97 -金，非货币（不包括黄金矿砂及其精矿） 97 - Gold, non-monetary (excluding gold ores and concentrates)。

DS1302Z

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: /errata .FEATURESReal-Time Clock Counts Seconds, Minutes,Hours, Date of the Month, Month, Day of the Week, and Year with Leap-Year Compensation Valid Up to 210031 x 8 RAM for Scratchpad Data Storage Serial I/O for Minimum Pin Count 2.0V to 5.5V Full Operation Uses Less than 300nA at 2.0VSingle-Byte or Multiple-Byte (Burst Mode)Data Transfer for Read or Write of Clock or RAM Data8-Pin DIP or Optional 8-Pin SO for SurfaceMountSimple 3-Wire Interface TTL-Compatible (V CC = 5V)Optional Industrial Temperature Range:-40°C to +85°CDS1202 CompatibleUnderwriters Laboratory (UL) Recognized PIN CONFIGURATIONSORDERING INFORMATIONPART TEMP RANGE PIN-PACKAGE TOP MARK* DS1302 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302+ 0°C to +70°C 8 PDIP (300 mils) DS1302 DS1302N -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302N+ -40°C to +85°C 8 PDIP (300 mils) DS1302 DS1302S 0°C to +70°C 8 SO (208 mils) DS1302S DS1302S+ 0°C to +70°C 8 SO (208 mils) DS1302S DS1302SN -40°C to +85°C 8 SO (208 mils) DS1302S DS1302SN+ -40°C to +85°C 8 SO (208 mils) DS1302S DS1302Z 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302Z+ 0°C to +70°C 8 SO (150 mils) DS1302Z DS1302ZN -40°C to +85°C 8 SO (150 mils) DS1302ZN DS1302ZN+ -40°C to +85°C 8 SO (150 mils) DS1302ZN DS1302S-16 0°C to +70°C 16 SO (300 mils) DS1302S16 DS1302SN-16-40°C to +85°C16 SO (300 mils)DS1302SN16+ Denotes a lead-free/RoHS-compliant device.*An N anywhere on the top mark indicates an industrial temperature grade device. A + anywhere on the top mark indicates a lead-free device.DS1302Trickle-Charge Timekeeping Chip查询DS1302N供应商DETAILED DESCRIPTIONThe DS1302 trickle-charge timekeeping chip contains a real-time clock/calendar and 31 bytes of static RAM. It communicates with a microprocessor via a simple serial interface. The real-time clock/calendar provides seconds, minutes, hours, day, date, month, and year information. The end of the month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year. The clock operates in either the 24-hour or 12-hour format with an AM/PM indicator.Interfacing the DS1302 with a microprocessor is simplified by using synchronous serial communication. Only three wires are required to communicate with the clock/RAM: CE, I/O (data line), and SCLK (serial clock). Data can be transferred to and from the clock/RAM 1 byte at a time or in a burst of up to 31 bytes. The DS1302 is designed to operate on very low power and retain data and clock information on less than 1µW.The DS1302 is the successor to the DS1202. In addition to the basic timekeeping functions of the DS1202, the DS1302 has the additional features of dual power pins for primary and backup power supplies, programmable trickle charger for V CC1, and seven additional bytes of scratchpad memory.OPERATIONFigure 1 shows the main elements of the serial timekeeper: shift register, control logic, oscillator, real-time clock, and RAM.TYPICAL OPERATING CHARACTERISTICS (V CC = 3.3V, T A = +25°C, unless otherwise noted.)PIN DESCRIPTIONPIN8 16NAME FUNCTION1 1 V CC2Primary Power-Supply Pin in Dual Supply Configuration. V CC1 is connected to a backup source to maintain the time and date in the absence of primary power. The DS1302 operates from the larger of V CC1 or V CC2. When V CC2 is greater than V CC1 + 0.2V, V CC2 powers the DS1302. When V CC2 is less than V CC1, V CC1 powers the DS1302.2 3 X1 3 5 X2 Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator is designed for operation with a crystal having a specified load capacitance of 6pF.For more information on crystal selection and crystal layout considerations, refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks . The DS1302 can also be driven by an external 32.768kHz oscillator. In thisconfiguration, the X1 pin is connected to the external oscillator signal and the X2 pinis floated. 4 8 GND Ground5 9 CE Input. CE signal must be asserted high during a read or a write. This pin has an internal 40k Ω (typ) pulldown resistor to ground. Note: Previous data sheet revisionsreferred to CE as RST . The functionality of the pin has not changed. 6 12 I/OInput/Push-Pull Output. The I/O pin is the bidirectional data pin for the 3-wireinterface. This pin has an internal 40k Ω (typ) pulldown resistor to ground. 7 14 SCLKInput. SCLK is used to synchronize data movement on the serial interface. This pinhas an internal 40k Ω (typ) pulldown resistor to ground.8 16 V CC1Low-Power Operation in Single Supply and Battery-Operated Systems and Low-Power Battery Backup. In systems using the trickle charger, the rechargeableenergy source is connected to this pin. UL recognized to ensure against reverse charging current when used with a lithium battery.— 2, 4, 6, 7, 10,11, 13, 15N.C. No ConnectionOSCILLATOR CIRCUITThe DS1302 uses an external 32.768kHz crystal. The oscillator circuit does not require any external resistors or capacitors to operate. Table 1 specifies several crystal parameters for the external crystal. Figure 2 shows a functional schematic of the oscillator circuit. If using a crystal with the specified characteristics, the startup time is usually less than one second.CLOCK ACCURACYThe accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error will be added by crystal frequency drift caused by temperature shifts. External circuit noise coupled into the oscillator circuit may result in the clock running fast. Figure 3 shows a typical PC board layout for isolating the crystal and oscillator from noise. Refer to Application Note 58: Crystal Considerations for Dallas Real-Time Clocks for detailed information.Table 1. Crystal Specifications*PARAMETER SYMBOL MIN TYP MAX UNITS Nominal Frequency f O 32.768 kHz Series Resistance ESR45k ΩLoad CapacitanceC L 6 pF*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer toApplication Note 58: Crystal Considerations for Dallas Real-Time Clocks for additional specifications.Figure 2. Oscillator Circuit Showing Internal Bias NetworkFigure 3. Typical PC Board Layout for CrystalCOMMAND BYTEFigure 4 shows the command byte. A command byte initiates each data transfer. The MSB (bit 7) must be a logic 1. If it is 0, writes to the DS1302 will be disabled. Bit 6 specifies clock/calendar data if logic 0 or RAM data if logic 1. Bits 1 to 5 specify the designated registers to be input or output, and the LSB (bit 0) specifies a write operation (input) if logic 0 or read operation (output) if logic 1. The command byte is always input starting with the LSB (bit 0). Figure 4. Address/Command ByteCE AND CLOCK CONTROLDriving the CE input high initiates all data transfers. The CE input serves two functions. First, CE turns on the control logic that allows access to the shift register for the address/command sequence. Second, the CE signal provides a method of terminating either single-byte or multiple-byte CE data transfer.A clock cycle is a sequence of a rising edge followed by a falling edge. For data inputs, data must be valid during the rising edge of the clock and data bits are output on the falling edge of clock. If the CE input is low, all data transfer terminates and the I/O pin goes to a high-impedance state. Figure 5 shows data transfer. At power-up, CE must be a logic 0 until V CC > 2.0V. Also, SCLK must be at a logic 0 when CE is driven to a logic 1 state.DATA INPUTFollowing the eight SCLK cycles that input a write command byte, a data byte is input on the rising edge of the next eight SCLK cycles. Additional SCLK cycles are ignored should they inadvertently occur. Data is input starting with bit 0.DATA OUTPUTFollowing the eight SCLK cycles that input a read command byte, a data byte is output on the falling edge of the next eight SCLK cycles. Note that the first data bit to be transmitted occurs on the first falling edge after the last bit of the command byte is written. Additional SCLK cycles retransmit the data bytes should they inadvertently occur so long as CE remains high. This operation permits continuous burst mode read capability. Also, the I/O pin is tri-stated upon each rising edge of SCLK. Data is output starting with bit 0.BURST MODEBurst mode can be specified for either the clock/calendar or the RAM registers by addressing location 31 decimal (address/command bits 1 through 5 = logic 1). As before, bit 6 specifies clock or RAM and bit 0 specifies read or write. There is no data storage capacity at locations 9 through 31 in the Clock/Calendar Registers or location 31 in the RAM registers. Reads or writes in burst mode start with bit 0 of address 0.When writing to the clock registers in the burst mode, the first eight registers must be written in order for the data to be transferred. However, when writing to RAM in burst mode it is not necessary to write all 31 bytes for the data to transfer. Each byte that is written to will be transferred to RAM regardless of whether all 31 bytes are written or not. CLOCK/CALENDARThe time and calendar information is obtained by reading the appropriate register bytes. Table 2 illustrates the RTC registers. The time and calendar are set or initialized by writing the appropriate register bytes. The contents of the time and calendar registers are in the binary-coded decimal (BCD) format.The day-of-week register increments at midnight. Values that correspond to the day of week are user-defined but must be sequential (i.e., if 1 equals Sunday, then 2 equals Monday, and so on.). Illogical time and date entries result in undefined operation.When reading or writing the time and date registers, secondary (user) buffers are used to prevent errors when the internal registers update. When reading the time and date registers, the user buffers are synchronized to the internal registers the rising edge of CE.The countdown chain is reset whenever the seconds register is written. Write transfers occur on the falling edge of CE. To avoid rollover issues, once the countdown chain is reset, the remaining time and date registers must be written within 1 second.The DS1302 can be run in either 12-hour or 24-hour mode. Bit 7 of the hours register is defined as the 12- or 24-hour mode-select bit. When high, the 12-hour mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, bit 5 is the second 10-hour bit (20–23 hours). The hours data must be re-initialized whenever the 12/24 bit is changed.CLOCK HALT FLAGBit 7 of the seconds register is defined as the clock halt (CH) flag. When this bit is set to logic 1, the clock oscillator is stopped and the DS1302 is placed into a low-power standby mode with a current drain of less than 100nA. When this bit is written to logic 0, the clock will start. The initial power-on state is not defined.WRITE-PROTECT BITBit 7 of the control register is the write-protect bit. The first seven bits (bits 0 to 6) are forced to 0 and always read 0 when read. Before any write operation to the clock or RAM, bit 7 must be 0. When high, the write-protect bit prevents a write operation to any other register. The initial power-on state is not defined. Therefore, the WP bit should be cleared before attempting to write to the device.TRICKLE-CHARGE REGISTERThis register controls the trickle-charge characteristics of the DS1302. The simplified schematic of Figure 6 shows the basic components of the trickle charger. The trickle-charge select (TCS) bits (bits 4 to 7) control the selection of the trickle charger. To prevent accidental enabling, only a pattern of 1010 enables the trickle charger. All other patterns will disable the trickle charger. The DS1302 powers up with the trickle charger disabled. The diode select (DS) bits (bits 2 and 3) select whether one diode or two diodes are connected between V CC2 and V CC1. If DS is 01, one diode is selected or if DS is 10, two diodes are selected. If DS is 00 or 11, the trickle charger is disabled independently of TCS. The RS bits (bits 0 and 1) select the resistor that is connected between V CC2 and V CC1. The resistor selected by the resistor select (RS) bits is as follows:RS BITS RESISTOR TYPICAL VALUE00 None None01 R1 2kΩ10 R2 4kΩ11 R3 8kΩIf RS is 00, the trickle charger is disabled independently of TCS.Diode and resistor selection is determined by the user according to the maximum current desired for battery or super cap charging. The maximum charging current can be calculated as illustrated in the following example. Assume that a system power supply of 5V is applied to V CC2 and a super cap is connected to V CC1. Also assume that the trickle charger has been enabled with one diode and resistor R1 between V CC2 and V CC1. The maximum current I MAX would therefore be calculated as follows:I MAX = (5.0V – diode drop) / R1 ≈ (5.0V – 0.7V) / 2kΩ≈ 2.2mAAs the super cap charges, the voltage drop between V CC2 and V CC1 decreases and therefore the charge current decreases.CLOCK/CALENDAR BURST MODEThe clock/calendar command byte specifies burst mode operation. In this mode, the first eight clock/calendar registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0.If the write-protect bit is set high when a write clock/calendar burst mode is specified, no data transfer will occur to any of the eight clock/calendar registers (this includes the control register). The trickle charger is not accessible in burst mode.At the beginning of a clock burst read, the current time is transferred to a second set of registers. The time information is read from these secondary registers, while the clock may continue to run. This eliminates the need to re-read the registers in case of an update of the main registers during a read.RAMThe static RAM is 31 x 8 bytes addressed consecutively in the RAM address space.RAM BURST MODEThe RAM command byte specifies burst mode operation. In this mode, the 31 RAM registers can be consecutively read or written (see Table 2) starting with bit 0 of address 0.REGISTER SUMMARYA register data format summary is shown in Table 2.CRYSTAL SELECTIONA 32.768kHz crystal can be directly connected to the DS1302 via pins 2 and 3 (X1, X2). The crystal selected for use should have a specified load capacitance (C L) of 6pF. For more information on crystal selection and crystal layout consideration, refer to Application Note 58:Crystal Considerations for Dallas Real-Time Clocks.Table 2. Register Address/DefinitionRTCREADWRITE BIT 7 BIT 6BIT 5BIT 4BIT 3 BIT 2 BIT 1BIT 0RANGE81h 80h CH 10 Seconds Seconds 00–59 83h 82h10 Minutes Minutes 00–591085h 84h 12/240 AM /PMHour Hour 1–12/0–23 87h 86h 0 0 10 Date Date 1–3189h 88h 0 0 010MonthMonth 1–12 8Bh 8Ah 0 0 0 0 0 Day 1–7 8Dh 8Ch 10 Year Year 00–99 8Fh 8Eh WP 0 0 0 0 0 0 0 — 91h 90h TCS TCS TCS TCS DS DS RS RS—CLOCK BURSTBFh BEhRAMC1h C0h 00-FFh C3h C2h 00-FFh C5h C4h 00-FFh . . . . . .. ..FDh FCh00-FFhRAM BURSTFFh FEhFigure 6. Programmable Trickle ChargerABSOLUTE MAXIMUM RATINGSVoltage Range on Any Pin Relative to Ground……………………………………………………………….-0.5Vto +7.0V Operating Temperature Range, Commercial………………………………………………………………….0°C to +70°C Operating Temperature Range, Industrial (IND)……………………………………………………………-40°C to +85°C Storage Temperature Range……………………………………………………………………………..….-55°C to +125°C Soldering Temperature (leads, 10 seconds)………………………………………………………………..………….260°C Soldering Temperature (surface mount)………………………………………………..…….See IPC/JEDEC J-STD-020Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.RECOMMENDED DC OPERATING CONDITIONS(T A = 0°C to +70°C or T A = -40°C to +85°C.) (Note 1)PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSSupply Voltage V CC1, V CC2V CC1,V CC2(Notes 2, 10) 2.0 3.3 5.5 V Logic 1 Input V IH (Note 2) 2.0V CC +0.3V V CC = 2.0V -0.3 +0.3Logic 0 Input V IL V CC = 5V (Note 2) -0.3 +0.8VDC ELECTRICAL CHARACTERISTICS(T A = 0°C to +70°C or T A = -40°C to +85°C.) (Note 1)PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSInput Leakage I LI (Notes 5, 13) 85 500 µA I/O LeakageI LO (Notes 5, 13)85500µALogic 1 Output (I OH = -0.4mA)V CC = 2.0V 1.6Logic 1 Output (I OH = -1.0mA) V OH V CC = 5V (Note 2) 2.4 VLogic 0 Output (I OL = 1.5mA) V CC = 2.0V 0.4Logic 0 Output (I OL = 4.0mA) V OL V CC = 5V (Note 2) 0.4 VV CC1 = 2.0V 0.4Active Supply Current (Oscillator Enabled) I CC1A V CC1 = 5V CH = 0(Notes 4, 11) 1.2 mAV CC1 = 2.0V 0.2 0.3Timekeeping Current (Oscillator Enabled) I CC1T V CC1 = 5V CH = 0(Notes 3, 11,13) 0.45 1 µAV CC1 = 2.0V 1 100V CC1 = 5V 1 100Standby Current (Oscillator Disabled)I CC1S INDCH = 1(Notes 9, 11, 13) 5 200 nA V CC2 = 2.0V 0.425Active Supply Current (Oscillator Enabled) I CC2A V CC2 = 5V CH = 0(Notes 4, 12) 1.28 mAV CC2 = 2.0V 25.3Timekeeping Current (Oscillator Enabled) I CC2TV CC2 = 5V CH = 0(Notes 3, 12)81 µAV CC2 = 2.0VCH = 1(Notes 9, 12) 25Standby Current (Oscillator Disabled)I CC2SV CC2 = 5V80µAR12 R24 Trickle-Charge Resistors R38k Ω Trickle-Charge Diode Voltage DropV TD0.7 VCAPACITANCE(T A = +25°C)PARAMETER SYMBOL MIN TYP MAX UNITS Input Capacitance C I10 pFI/O Capacitance C I/O 15 pFAC ELECTRICAL CHARACTERISTICS(T A = 0°C to +70°C or T A = -40°C to +85°C.) (Note 1)PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSV CC = 2.0V 200Data to CLK Setup t DCV CC = 5V(Note 6) 50 ns V CC = 2.0V 280CLK to Data Hold t CDHV CC = 5V (Note 6) 70 ns V CC = 2.0V 800CLK to Data Delay t CDDV CC = 5V(Notes 6, 7, 8) 200 ns V CC = 2.0V 1000CLK Low Time t CLV CC = 5V(Note 6) 250 ns V CC = 2.0V 1000CLK High Time t CHV CC = 5V(Note 6) 250 ns V CC = 2.0V 0.5CLK Frequency t CLKV CC = 5V(Note 6) DC 2.0 MHz V CC = 2.0V 2000CLK Rise and Fall t R , t FV CC = 5V500 ns V CC = 2.0V 4CE to CLK Setup t CC V CC = 5V(Note 6) 1 µsV CC = 2.0V 240CLK to CE Hold t CCHV CC = 5V(Note 6) 60 ns V CC = 2.0V 4CE Inactive Time t CWH V CC = 5V(Note 6) 1 µsV CC = 2.0V 280CE to I/O High Impedance t CDZ V CC = 5V (Note 6) 70 nsV CC = 2.0V 280SCLK to I/O High Impedance t CCZV CC = 5V (Note 6) 70 nsNote 1:Limits at -40°C are guaranteed by design and are not production tested. Note 2: All voltages are referenced to ground.Note 3: I CC1T and I CC2T are specified with I/O open, CE and SCLK set to a logic 0.Note 4: I CC1A and I CC2A are specified with the I/O pin open, CE high, SCLK = 2MHz at V CC = 5V; SCLK = 500kHz, V CC = 2.0V. Note 5: CE, SCLK, and I/O all have 40k Ω pulldown resistors to ground.Note 6: Measured at V IH = 2.0V or V IL = 0.8V and 10ns maximum rise and fall time. Note 7: Measured at V OH = 2.4V or V OL = 0.4V. Note 8: Load capacitance = 50pF.Note 9: I CC1S and I CC2S are specified with CE, I/O, and SCLK open.Note 10: V CC = V CC2, when V CC2 > V CC1 + 0.2V; V CC = V CC1, when V CC1 > V CC2. Note 11: V CC2 = 0V. Note 12: V CC1 = 0V.Note 13:Typical values are at +25°C.CHIP INFORMATION TRANSISTOR COUNT: 11,500 THERMAL INFORMATIONPACKAGE THETA-JA(°C/W)THETA-JC(°C/W)8 DIP 110 40 8 SO (150 mils) 170 40 8 SO (208 mils) 113 31 16 SO (300 mils) 105 22PACKAGE INFORMATION(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to /DallasPackInfo.)information, go to /DallasPackInfo.)information, go to /DallasPackInfo.)DSXXXX Description16 of 16Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product. No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.PACKAGE INFORMATION (continued)(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to /DallasPackInfo .)。

描写钟表的作文150字

描写钟表的作文150字
英文回答：
Clocks are an essential part of our daily lives. They help us keep track of time and ensure that we are punctual for our appointments and meetings. Personally, I have a beautiful antique grandfather clock in my living room that has been in my family for generations. It has a rich, deep chime that fills the room and adds a sense of warmth and nostalgia to the space. The rhythmic ticking of the clock
is like a comforting heartbeat in the background of my home.
中文回答：
钟表是我们日常生活中不可或缺的一部分。

它们帮助我们掌握
时间，确保我们准时赴约和开会。

就我个人而言，在我的客厅里有
一架美丽的古董祖父钟，这已经在我家族中传承了好几代。

它有着
深沉悠扬的钟声，填满整个房间，为空间增添了一种温馨和怀旧的
感觉。

钟表的有规律的滴答声就像是我家中的一种舒心的背景音乐。

linux系统delay函数

linux系统delay函数“[Linux系统delay函数]”，我将为你一步一步回答，向你解释这个主题，帮助你理解Linux系统下的delay函数。

第一步：引言和概述（150-200字）在Linux系统中，delay函数是一种用于实现延迟操作的函数。

在编程中，我们经常需要在程序的某些位置实现延迟，以便正确处理数据、控制流和用户输入。

delay函数提供了一种简单而有效的方法来实现这一目标。

本文将详细讨论Linux系统下的delay函数，包括其工作原理、用法和一些常见的使用案例。

我们还将提供代码示例和进一步的资源，以帮助读者更好地理解和应用delay函数。

第二步：delay函数的工作原理（200-300字）delay函数的工作原理是利用系统定时器来实现延迟。

在Linux系统中，系统定时器是一个硬件或软件组件，用于测量和跟踪时间。

delay函数使用系统定时器来生成一段延迟，并使程序在这段时间内等待。

具体来说，当我们调用delay函数时，它会读取系统定时器的当前值，并将其与期望的延迟时间相比较。

如果当前值小于延迟时间，delay函数将等待一段时间，然后再次读取系统定时器的值，以检查是否已达到所需的延迟时间。

这个过程会一直重复，直到达到所需的延迟时间为止。

延迟时间通常以毫秒为单位，但具体取决于系统定时器的精度和计时单位。

因此，在使用delay函数时，我们应该明确指定延迟的时间单位，并确保所选的单位与系统定时器一致。

第三步：delay函数的用法（200-300字）要在Linux程序中使用delay函数，我们需要包含相关头文件，如<time.h>。

该头文件提供了与时间相关的函数和结构体的定义。

使用delay函数的一般语法如下：cpp#include <time.h>void delay(unsigned int milliseconds) {获取开始时间unsigned int start_time = clock();将毫秒转换为时钟滴答数unsigned int delay_ticks = milliseconds * CLOCKS_PER_SEC / 1000;等待到达指定的延迟滴答数while (clock() < start_time + delay_ticks) {空循环，直到达到延迟时间}}上述代码展示了一个简单的delay函数实现，它使用clock函数获取系统时钟，并通过计算将毫秒转换为时钟滴答数。

Si5366

Preliminary Rev. 0.3 2/08Copyright © 2008 by Silicon Laboratories Si5366This information applies to a product under development. Its characteristics and specifications are subject to change without notice.Si5366P RECISION C LOCK M ULTIPLIER /J ITTER A TTENUATORDescriptionThe Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems,including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8kHz to 707MHz and generates five frequency-multiplied clock outputs ranging from 8kHz to 1050MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates.The Si5366 is based on Silicon Laboratories' 3rd-generation DSPLL ® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is digitally programmable,providing jitter performance optimization at the application level. Operating from a single 1.8 or 2.5V supply, the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.ApplicationsSONET/SDH OC-48/STM-16 and OC-192/STM-64 line cardsGbE/10GbE, 1/2/4/8/10GFC line cards ITU G.709 line cards Optical modulesTest and measurement Synchronous EthernetFeaturesSelectable output frequencies ranging from 8kHz to 1050MHzUltra-low jitter clock outputs w/jitter generation as low as 0.3ps rms (50kHz–80MHz)Integrated loop filter with selectable loop bandwidth (60Hz to 8.4kHz)Meets OC-192 GR-253-CORE jitter specifications Four clock inputs w/manual or automatically controlled hitless switchingFive clock outputs with selectable signal format (LVPECL, LVDS, CML, CMOS)SONET frame sync switching and regeneration Support for ITU G.709 FEC ratios (255/238, 255/237, 255/236) LOL, LOS, FOS alarm outputsPin-controlled output phase adjust Pin-programmable settingsOn-chip voltage regulator for 1.8 ±5% or 2.5V ±10% operationSmall size: 14x 14mm 100-pin TQFPPb-free, RoHS compliantP RELIMINARY D ATA S HEETSi53662Preliminary Rev. 0.3Table 1. Performance Specifications(V DD=1.8 ±5% or 2.5V ±10%, T A=–40 to 85 ºC)Parameter Symbol Test Condition Min Typ Max Unit Temperature Range T A–402585ºC Supply Voltage V DD 2.25 2.5 2.75V1.71 1.8 1.89V Supply Current I DD f OUT = 622.08 MHzAll CKOUTs enabledLVPECL format output—394435mAOnly CKOUT1 enabled—253284mAf OUT = 19.44 MHzAll CKOUTs enabledCMOS format output—278321mAOnly CKOUT1 enabled—229261mATristate/Sleep Mode—165TBD mAInput Clock Frequency (CKIN1, CKIN2, CKIN3, CKIN4)CK F Input frequency and clock mul-tiplication ratio pin-selectablefrom table of values usingFRQSEL and FRQTBL set-tings. Consult Silicon Laborato-ries configuration softwareDSPLL sim or Any-Rate Preci-sion Clock Family ReferenceManual at /tim-ing (click on Documentation) fortable selections.0.008—707.35MHzInput Clock Frequency(CKIN3, CKIN4 used asFSYNC inputs)CK F0.008——MHzOutput Clock Frequency(CKOUT1, CKOUT2,CKOUT3, CKOUT4,CKOUT5 used as fifthhigh-speed output)CK OF0.008—1049.76MHzCKOUT5 used as framesync output (FS_OUT)CK OF0.008——MHz 3-Level Input PinsInput Mid Current I IMM See Note 2.–2—2µA Input Clocks (CKIN1, CKIN2, CKIN3, CKIN4)Differential Voltage Swing CKN DPP0.25— 1.9V PP Common Mode Voltage CKN VCM 1.8V ±5%0.9— 1.4V2.5V ±10% 1.0— 1.7V Rise/Fall Time CKN TRF20–80%—11nsDuty Cycle (Minimum Pulse Width)CKN DC Whichever is smaller40—60%2——nsOutput Clocks (CKOUT1, CKOUT2, CKOUT3, CKOUT4, CKOUT5/FS_OUT)Common Mode V OCM LVPECL100Ω loadline-to-line V DD–1.42—V DD–1.25VDifferential Output Swing V OD 1.1— 1.9V Single Ended OutputSwingV SE0.5—0.93V Rise/Fall Time CKO TRF20–80%—230350ps Notes:1.For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate PrecisionClock Family Reference Manual. This document can be downloaded from /timing(click onDocumentation).2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family ReferenceManual. In most designs, an external resistor voltage divider is recommended.Si5366Preliminary Rev. 0.33Duty CycleCKO DC 45—55%PLL Performance Jitter GenerationJ GENf IN = f OUT = 622.08 MHz,LVPECL output format 50kHz–80MHz —0.3TBDps rms12kHz–20MHz —0.3TBD ps rms Jitter Transfer J PK —0.050.1dB Phase NoiseCKO PNf IN = f OUT = 622.08 MHz100 Hz offset —TBD TBD dBc/Hz 1 kHz offset —TBD TBD dBc/Hz 10 kHz offset —TBD TBD dBc/Hz 100 kHz offset —TBD TBD dBc/Hz 1 MHz offset—TBD TBD dBc/Hz Subharmonic Noise SP SUBH Phase Noise @ 100kHz Offset—TBD TBD dBc Spurious Noise SP SPURMax spur @ n x F3(n > 1, n x F3 < 100MHz)—TBDTBDdBcPackageThermal Resistance Junction to AmbientθJAStill Air—40—ºC/WTable 2. Absolute Maximum RatingsParameterSymbol Value Unit DC Supply Voltage V DD –0.5 to 3.6V LVCMOS Input VoltageV DIG –0.3 to (V DD + 0.3)V Operating Junction Temperature T JCT –55 to 150ºC Storage Temperature RangeT STG–55 to 150ºC ESD HBM Tolerance (100 pF, 1.5 k Ω); All pins except CKIN+/CKIN– 2 kV ESD MM Tolerance; All pins except CKIN+/CKIN–200 V ESD HBM Tolerance (100 pF, 1.5 k Ω); CKIN+/CKIN–700V ESD MM Tolerance; CKIN+/CKIN–150VLatch-Up ToleranceJESD78 CompliantNote:Permanent device damage may occur if the Absolute Maximum Ratings are exceeded. Functional operation should berestricted to the conditions as specified in the operation sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.Table 1. Performance Specifications (Continued)(V DD =1.8 ±5% or 2.5V ±10%, T A =–40 to 85 ºC)ParameterSymbol Test Condition MinTyp Max Unit Notes:1.For a more comprehensive listing of device specifications, please consult the Silicon Laboratories Any-Rate PrecisionClock Family Reference Manual. This document can be downloaded from /timing (click on Documentation).2. This is the amount of leakage that the 3 level input can tolerate from an external driver. See the Family ReferenceManual. In most designs, an external resistor voltage divider is recommended.Si53664Preliminary Rev. 0.3Figure 1. Typical Phase Noise PlotJitter Bandwidth RMS Jitter (fs) OC-48, 12 kHz to 20 MHz374OC-192, 20 kHz to 80 MHz388OC-192, 4 MHz to 80 MHz181OC-192, 50 kHz to 80 MHz377 Broadband, 800 Hz to 80 MHz420Si5366Preliminary Rev. 0.35Figure 2.Si5366 Typical Application CircuitSi53666Preliminary Rev. 0.31. Functional DescriptionThe Si5366 is a jitter-attenuating precision clock multiplier for high-speed communication systems, including SONET OC-48/OC-192, Ethernet, and Fibre Channel. The Si5366 accepts four clock inputs ranging from 8kHz to 707MHz and generates five frequency-multiplied clock outputs ranging from 8kHz to 1050MHz. By default the four clock inputs are at the same frequency and the five clock outputs are at the same frequency. Two of the output clocks can be divided down further to generate an integer sub-multiple frequency. Optionally, the fifth clock output can be configured as a 8kHz SONET/SDH frame synchronization output that is phase aligned with one of the high-speed output clocks. The input clock frequency and clock multiplication ratio are selectable from a table of popular SONET, Ethernet, and Fibre Channel rates. In addition to providing clock multiplication in SONET and datacom applications, the Si5366 supports SONET-to-datacom frequency translations. Silicon Laboratories offers a PC-based software utility, DSPLL sim, that can be used to look up valid Si5366 frequency translations. This utility can be downloaded from /timing (click on Documentation). The Si5366 is based on Silicon Laboratories' 3rd-generation DSPLL® technology, which provides any-rate frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components. The Si5366 PLL loop bandwidth is selectable via the BWSEL[1:0] pins and supports a range from 60Hz to 8.4kHz. The DSPLL sim software utility can be used to calculate valid loop bandwidth settings for a given input clock frequency/clock multiplication ratio.The Si5366 supports hitless switching between input clocks in compliance with GR-253-CORE and GR-1244-CORE that greatly minimizes the propagation of phase transients to the clock outputs during an input clock transition (<200ps typ). Manual and automatic revertive and non-revertive input clock switching options are available via the AUTOSEL input pin. The Si5366 monitors the four input clocks for loss-of-signal and provides a LOS alarm when it detects missing pulses on any of the four input clocks. The device monitors the lock status of the PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. If a potential phase cycle slip is detected, the LOL output is set high. The Si5366 monitors the frequency of CKIN1, CKIN3, and CKIN4 with respect to a reference frequency applied to CKIN2, and generates a frequency offset alarm (FOS) if the threshold is exceeded. This FOS feature is available for SONET applications in which both the monitored frequency on CKIN1, CKIN3, and CKIN4 and the reference frequency are integer multiples of 19.44 MHz. Both Stratum 3/3E and SONET Minimum Clock (SMC) FOS thresholds are supported. The Si5366 provides a digital hold capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. During digital hold, the DSPLL is locked to an input frequency that existed a fixed amount of time before the error event occurred, eliminating the effects of phase and frequency transients that may occur immediately preceding digital hold.The Si5366 has five differential clock outputs. The signal format of the clock outputs is selectable to support LVPECL, LVDS, CML, or CMOS loads. If not required, unused clock outputs can be powered down to minimize power consumption. The phase difference between the selected input clock and the output clocks is adjustable in 200ps increments for system skew control. For system-level debugging, a bypass mode is available which drives the output clock directly from the input clock, bypassing the internal DSPLL. The device is powered by a single 1.8 or 2.5V supply.1.1. External ReferenceAn external, 38.88MHz clock or a low-cost 114.285MHz 3rd overtone crystal is used as part of a fixed-frequency oscillator within the DSPLL. This external reference is required for the device to perform jitter attenuation. Silicon Laboratories recommends using a high-quality crystal. Specific recommendations may be found in the Family Reference Manual. An external 38.88MHz clock from a high quality OCXO or TCXO can also be used as a reference for the device. In digital hold, the DSPLL remains locked to this external reference. Any changes in the frequency of this reference when the DSPLL is in digital hold, will be tracked by the output of the device. Note that crystals can have temperature sensitivities.1.2. Further DocumentationConsult the Silicon Laboratories Any-Rate Precision Clock Family Reference Manual (FRM) for detailed information about the Si5366. Additional design support is available from Silicon Laboratories through your distributor.Silicon Laboratories has developed a PC-based software utility called DSPLL sim to simplify device configuration, including frequency planning and loop bandwidth selection. The FRM and this utility can be downloaded from /timing; click on Documentation.Si5366Preliminary Rev. 0.372. Pin Descriptions: Si5366Table 3. Si5366 Pin DescriptionsPin #Pin NameI/OSignal LevelDescription1, 2, 23, 24, 25, 47, 48, 52, 53, 72, 73, 74, 75,90NCNo Connect.These pins must be left unconnected for normal operation.3RST I LVCMOSExternal Reset.Active low input that performs external hardware reset ofdevice. Resets all internal logic to a known state and forces the device registers to their default value. Clock outputs are dis-abled during reset. After rising edge of RST signal, the device will perform an internal self-calibration when a valid input signal is present.This pin has a weak pull-up.Si53668Preliminary Rev. 0.34FRQTBLI3-LevelFrequency Table Select.This pin selects SONET/SDH, datacom, or SONET/SDH to datacom frequency translation table.L =SONET/SDH.M =Datacom.H =SONET/SDH to Datacom.This pin has both weak pull-ups and weak pull-downs and defaults to M. Some designs may require an external resistor voltage divider when driven by an active device that will tri-state.5, 6, 15, 27, 62, 63, 76, 79, 81, 84, 86, 89, 91, 94, 96, 99,100V DD V DDSupplyV DD .The device operates from a 1.8 or 2.5 V supply. Bypass capac-itors should be associated with the following V DD pins:Pins Bypass Cap 5, 60.1 µF 150.1 µF 270.1 µF 62, 630.1 µF 76, 79 1.0 µF 81, 840.1 µF 86, 890.1 µF 91, 940.1 µF 96, 99, 1000.1 µF 7, 8, 14, 18, 19, 26, 28, 31, 33, 36, 38, 41, 43, 46, 64, 65GND GND SupplyGround.This pin must be connected to system ground. Minimize the ground path impedance for optimal performance.9C1B O LVCMOSCKIN1 Invalid Indicator.This pin is an active high alarm output associated with CKIN1. Once triggered, the alarm will remain high until CKIN1 is vali-dated.0=No alarm on CKIN1.1=Alarm on CKIN1.10C2B O LVCMOSCKIN2 Invalid Indicator.This pin is an active high alarm output associated with CKIN2. Once triggered, the alarm will remain high until CKIN2 is vali-dated.0=No alarm on CKIN2.1=Alarm on CKIN2.11C3B O LVCMOSCKIN3 Invalid Indicator.This pin is an active high alarm output associated with CKIN3.0=No alarm on CKIN3.1=Alarm on CKIN3.Table 3. Si5366 Pin Descriptions (Continued)Pin #Pin Name I/O Signal Level DescriptionSi5366Preliminary Rev. 0.3912ALRMOUTOLVCMOSAlarm Output Indicator.This pin is an active high alarm output associated with CKIN4 or the frame sync alignment alarm.0=ALRMOUT not active.1=ALRMOUT active.1357CS0_C3A CS1_C4AI/O LVCMOInput Clock Select/CKINn Active Clock Indicator.Input : If manual clock selection mode is chosen(AUTOSEL =L), the CS[1:0] pins function as the man-ual input clock selector control.These inputs are internally deglitched to prevent inad-vertent clock switching during changes in the CSn input state. If configured as input, these pins must not float.Output : If automatic clock detection is chosen (AUTOSEL = Mor H), these pins function as the CKINn active clock indicator output.0 = CKINn is not the active input clock.1 = CKINn is currently the active input clock to thePLL.1617XA XBIANALOGExternal Crystal or Reference Clock.An external crystal or an external clock should be connected to these pins. Frequency of crystal or external clock is set by the RATE pins. The quality of the selected crystal or external clock affects the quality of the part's output; refer to the Family Refer-ence Manual for external reference selection and interfacing. 20FS_SW I LVCMOSFSYNC Inputs to Clock Selection Enable.If CK_CONF =1, this pin enables the use of the CKIN3 and CKIN4 loss-of-signal indicators as inputs to the clock selection state machine.0=Do not use CKIN3 and CKIN4 LOS indicators as inputs to the clock selection state machine.1=Use CKIN3 and CKIN4 LOS indicators as inputs to the clock selection state machine.This pin has a weak pull-down.21FS_ALIGN I LVCMOSFSYNC Alignment Control.If CK_CONF =1, a logic high on this pin causes the FS_OUT phase to be realigned to the rising edge of the currently active input sync (CKIN3 or CKIN4).0=No realignment.1=Realignment.This pin has a weak pull-down.Table 3. Si5366 Pin Descriptions (Continued)Pin #Pin Name I/O Signal Level DescriptionCS[1:0]Active Input Clock00CKIN101CKIN210CKIN311CKIN4Si536610Preliminary Rev. 0.322AUTOSEL I3-Level Manual/Automatic Clock Selection.Three level input that selects the method of input clock selec-tion to be used.L=Manual.M=Automatic non-revertive.H=Automatic revertive.This pin has both weak pull-ups and weak pull-downs anddefaults to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.2930CKIN4+CKIN4–I MULTI Clock Input 4.Differential clock input. This input can also be driven with a sin-gle-ended signal. CKIN4 serves as the frame sync input asso-ciated with the CKIN2 clock when CK_CONF=1.3242RATE0RATE1I3-Level External Crystal or Reference Clock Rate.Three-level inputs that select the type and rate of external crys-tal or reference clock to be applied to the XA/XB port. Refer tothe Family Reference Manual for settings. These pins haveboth a weak pull-up and a weak pull-down and default to M.Some designs may require an external resistor voltage dividerwhen driven by an active device.3435CKIN2+CKIN2–I MULTI Clock Input 2.Differential input clock. This input can also be driven with a sin-gle-ended signal.37DBL2_BY I3-Level CKOUT2 Disable/PLL Bypass Mode Control.Controls enable of CKOUT2 divider/output buffer path and PLLbypass mode.L=CKOUT2 Enabled.M=CKOUT2 Disabled.H=BYPASS Mode with CKOUT2 enabled.This pin has both weak pull-ups and weak pull-downs anddefaults to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.3940CKIN3+CKIN3–I MULTI Clock Input 3.Differential clock input. This input can also be driven with a sin-gle-ended signal. CKIN3 serves as the frame sync input asso-ciated with the CKIN1 clock when CK_CONF=1.4445CKIN1+CKIN1–I MULTI Clock Input 1.Differential clock input. This input can also be driven with a sin-gle-ended signal.49LOL O LVCMOS PLL Loss of Lock Indicator.This pin functions as the active high PLL loss of lock indicator.0=PLL locked.1=PLL unlocked.Table 3. Si5366 Pin Descriptions (Continued)Pin #Pin Name I/O Signal Level DescriptionPin #Pin Name I/O Signal Level Description50DBL_FS I3-Level FS_OUT Disable.This pin performs the following functions:L=Normal operation. Output path is active and signal format isdetermined by SFOUT inputs.M=CMOS signal format. Overrides SFOUT signal format toallow FS_OUT to operate in CMOS format while the clock out-puts operate in a differential output format.H=Powerdown. Entire FS_OUT divider and output buffer pathis powered down.This pin has both weak pull-ups and weak pull-downs anddefaults to M.Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.51CK_CONF I LVCMOS Input Clock Configuration Control.This pin controls the input clock configuration.0=CKIN1, 2, 3, 4 inputs, no FS_OUT alignment.1=CKIN1, 3 and CKIN2, 4 clock/FSYNC pairs.This pin has a weak pull-down.54DEC I LVCMOS Coarse Skew Decrement.A pulse on this pin decreases the input to output device skewby 1/f OSC (approximately 200ps). Detailed operations and tim-ing characteristics for this pin may be found in the Any-RatePrecision Clock Family Reference Manual. There is no limit onthe range of skew adjustment by this method. If both INC andDEC are tied high, phase buildout is disabled and the devicemaintains a fixed-phase relationship between the selectedinput clock and the output clock during an input clock switch.Detailed operations and timing characteristics for this pin maybe found in the Any-Rate Precision Clock Family ReferenceManual.This pin has a weak pull-down.55INC I LVCMOS Coarse Skew Increment.A pulse on this pin increases the input to output skew by 1/f OSC(approximately 200ps). Detailed operations and timing charac-teristics for this pin may be found in the Any-Rate PrecisionClock Family Reference Manual. There is no limit on the rangeof skew adjustment by this method. If both INC and DEC aretied high, phase buildout is disabled and the device maintains afixed-phase relationship between the selected input clock andthe output clock during an input clock switch. Detailed opera-tions and timing characteristics for this pin may be found in theAny-Rate Precision Clock Family Reference Manual.Note:INC does not increase skew if NI_HS=4.This pin has a weak pull-down.56FOS_CTL I3-Level Frequency Offset Control.This pin enables or disables use of the CKIN2 FOS referenceas an input to the clock selection state machine.L=FOS Disabled.M=Stratum 3/3E FOS Threshold.H=SONET Minimum Clock FOS Threshold.This pin has both weak pull-ups and weak pull-downs anddefaults to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.58C1A O LVCMOS CKIN1 Active Clock Indicator.This pin serves as the CKIN1 active clock indicator.0=CKIN1 is not the active input clock.1=CKIN1 is currently the active input clock to the PLL.59C2A O LVCMOS CKIN2 Active Clock Indicator.This pin serves as the CKIN2 active clock indicator.0=CKIN2 is not the active input clock.1=CKIN2 is currently the active input clock to the PLL.60 61BWSEL0BWSEL1I3-Level Bandwidth Select.These pins are three level inputs that select the DSPLL closedloop bandwidth. Detailed operations and timing characteristicsfor these pins may be found in the Any-Rate Precision ClockFamily Reference Manual.These pins have both weak pull-ups and weak pull-downs anddefault to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.66 67DIV34_0DIV34_1I3-Level CKOUT3 and CKOUT4 Divider Control.These pins control the division of CKOUT3 and CKOUT4 rela-tive to the CKOUT2 output frequency. Detailed operations andtiming characteristics for these pins may be found in the Any-Rate Precision Clock Family Reference Manual.These pins have both weak pull-ups and weak pull-downs anddefault to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.68 69 70 71FRQSEL0FRQSEL1FRQSEL2FRQSEL3I3-Level Multiplier Select.These pins are three level inputs that select the input clock andclock multiplication setting according to the Any-Rate PrecisionClock Family Reference Manual, depending on the FRQTBLsetting.These pins have both weak pull-ups and weak pull-downs anddefault to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.Pin #Pin Name I/O Signal Level Description77 78CKOUT3+CKOUT3–O MULTI Clock Output 3.Differential output clock with a frequency specified by FRQSELand FRQTBL settings. Output is differential for LVPECL, LVDS,and CML compatible modes. For CMOS format, both outputpins drive identical single-ended clock outputs.80 95SFOUT1SFOUT0I3-Level Signal Format Select.Three level inputs that select the output signal format (commonmode voltage and differential swing) for all of the clock outputsexcept FS_OUT. See DBL_FS pin descripition.These pins have both weak pull-ups and weak pull-downs anddefault to M. Some designs may require an external resistorvoltage divider when driven by an active device that will tri-state.82 83CKOUT1–CKOUT1+O MULTI Clock Output 1.Differential output clock with a frequency specified by FRQSELand FRQTBL. Output signal format is selected by SFOUT pins.Output is differential for LVPECL, LVDS, and CML compatiblemodes. For CMOS format, both output pins drive identical sin-gle-ended clock outputs.85DBL34I LVCMOS Output 3 and 4 Disable.Active high input. When active, entire CKOUT3 and CKOUT4divider and output buffer path is powered down. CKOUT3 andCKOUT4 outputs will be in tristate mode during powerdown.This pin has a weak pull-up.87 88FS_OUT–FS_OUT+O MULTI Frame Sync Output.Differential 8 kHz frame sync output or fifth high-speed clockoutput with a frequency specified by FRQSEL and FRQTBL.Output signal format is selected by SFOUT pins. Detailed oper-ations and timing characteristics for this pin may be found inthe Any-Rate Precision Clock Family Reference Manual. Out-put is differential for LVPECL, LVDS, and CML compatiblemodes. For CMOS format, both output pins drive identical sin-gle-ended clock outputs.Pin #Pin Name I/O Signal Level DescriptionSFOUT[1:0]Signal FormatHH ReservedHM LVDSHL CMLMH LVPECLMM ReservedML LVDS—LowSwingLH CMOSLM DisabledLL Reserved92 93CKOUT2+CKOUT2–O MULTI Clock Output 2.Differential output clock with a frequency specified by FRQSELand FRQTBL. Output signal format is selected by SFOUT pins.Output is differential for LVPECL, LVDS, and CML compatiblemodes. For CMOS format, both output pins drive identical sin-gle-ended clock outputs.97 98CKOUT4–CKOUT4+O MULTI Clock Output 4.Differential output clock with a frequency specified by FRQSELand FRQTBL settings. Output signal format is selected bySFOUT pins. Output is differential for LVPECL, LVDS, andCML compatible modes. For CMOS format, both output pinsdrive identical single-ended clock outputs.GND PAD GND PAD GND Supply Ground Pad.The ground pad must provide a low thermal and electricalimpedance to a ground plane.Pin #Pin Name I/O Signal Level Description3. Ordering GuideOrdering Part Number Package ROHS6, Pb-Free Temperature Range Si5366-C-GQ100-Pin 14x14mm TQFP Yes–40 to 85°C4. Package Outline: 100-Pin TQFPFigure3 illustrates the package details for the Si5366. Table4 lists the values for the dimensions shown in the illustration.Table 4. 100-Pin Package Diagram DimensionsDimension Min Nom Max Dimension Min Nom Max A—— 1.20E16.00 BSCA10.05—0.15E114.00 BSCA20.95 1.00 1.05E2 3.85 4.00 4.15b0.170.220.27L0.450.600.75c0.09—0.20aaa——0.20D16.00 BSC bbb——0.20D114.00 BSC ccc——0.08D2 3.85 4.00 4.15ddd——0.08e0.50BSCθ0º 3.5º7ºNotes:1.All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.3. This package outline conforms to JEDEC MS-026, variant AED-HD.4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small BodyComponents.5. Recommended PCB LayoutTable 5. PCB Land Pattern DimensionsDimension MIN MAXe0.50BSC.E15.40 REF.D15.40 REF.E2 3.90 4.10D2 3.90 4.10GE13.90—GD13.90—X—0.30Y 1.50REF.ZE—16.90ZD—16.90R10.15 REFR2— 1.00Notes (General):1.All dimensions shown are in millimeters (mm) unless otherwise noted.2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.3. This Land Pattern Design is based on IPC-7351 guidelines.4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition(LMC) is calculated based on a Fabrication Allowance of 0.05mm.Notes (Solder Mask Design):1.All metal pads are to be non-solder mask defined (NSMD). Clearance between the soldermask and the metal pad is to be 60 µm minimum, all the way around the pad.Notes (Stencil Design):1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should beused to assure good solder paste release.2. The stencil thickness should be 0.125mm (5 mils).3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.4. A 4x4 array of 0.80mm square openings on 1.05mm pitch should be used for the centerground pad.Notes (Card Assembly):1. A No-Clean, Type-3 solder paste is recommended.2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification forSmall Body Components.。

【通用文档】clocks(200字).doc

Clocks(200字)There are many clocks in the Brown’s house. They are in different rooms.A big clock stands in a corner of the sitting room. It is a very, very old clock, but it still keeps good time. Mr. Brown winds it once a week.美文欣赏1、走过春的田野，趟过夏的激流，来到秋天就是安静祥和的世界。

秋天，虽没有玫瑰的芳香，却有秋菊的淡雅，没有繁花似锦，却有硕果累累。

秋天，没有夏日的激情，却有浪漫的温情，没有春的奔放，却有收获的喜悦。

清风落叶舞秋韵，枝头硕果醉秋容。

秋天是甘美的酒，秋天是壮丽的诗，秋天是动人的歌。

2、人的一生就是一个储蓄的过程，在奋斗的时候储存了希望；在耕耘的时候储存了一粒种子；在旅行的时候储存了风景；在微笑的时候储存了快乐。

聪明的人善于储蓄，在漫长而短暂的人生旅途中，学会储蓄每一个闪光的瞬间，然后用它们酿成一杯美好的回忆，在四季的变幻与交替之间，散发浓香，珍藏一生！3、春天来了，我要把心灵放回萦绕柔肠的远方。

让心灵长出北归大雁的翅膀，乘着吹动彩云的熏风，捧着湿润江南的霡霂，唱着荡漾晨舟的渔歌，沾着充盈夜窗的芬芳，回到久别的家乡。

我翻开解冻的泥土，挖出埋藏在这里的梦，让她沐浴灿烂的阳光，期待她慢慢长出枝蔓，结下向往已久的真爱的果实。

4、好好享受生活吧，每个人都是幸福的。

人生山一程，水一程，轻握一份懂得，将牵挂折叠，将幸福尽收，带着明媚，温暖前行，只要心是温润的，再遥远的路也会走的安然，回眸处，愿阳光时时明媚，愿生活处处晴好。

5、漂然月色，时光随风远逝，悄然又到雨季，花，依旧美；心，依旧静。

月的柔情，夜懂；心的清澈，雨懂；你的深情，我懂。

人生没有绝美，曾经习惯漂浮的你我，曾几何时，向往一种平实的安定，风雨共度，淡然在心，凡尘远路，彼此守护着心的旅程。

clock

game[ɡeim]n.游戏；比赛
computer game电子游戏，计算机游戏
Do you like computer game?
你喜欢电脑游戏吗？
key[ki:]n.钥匙
notebook['nəutbuk]
n.笔记本，笔记簿；手册
ring[riŋ]戒指,环
call[kɔ:l]打电话
at[æt]在……(里面或附近),
collection[kə'lekʃən]n.收藏品；
every['evri]adj.每一的，每个的；每隔…的
day[dei]n.一天；白昼；时期
everyday['evridei]adj.每天的，日常的
only['əunli]adv.只，仅仅；
Unit7
how much[mʌtʃ]多少，多少钱,
pants[pænts]n.裤子；短裤
case[keis]n.箱,盒；
pencil case文具盒，铅笔盒
backpack['bækpæk]
n.双肩背包，背包；
sharpener['ʃɑ:pənə]
n.卷笔刀；磨具；研磨
pencil sharpener卷笔刀
dictionary['dikʃənəri]
n.字典；词典[复数dictionaries ]
short[ʃɔ:t]adj.短的；矮的；不足的
long[lɔŋ, lɔ:ŋ]adj.长的；
clerk[klɑ:k, klə:k]n.职员，办事员；
help[help]vt.帮助；援助
want[wɔnt, wɔ:nt]vt.需要；想要
here you are给你
welcome['welkəm]不必客气的

AD9826

AD9826–SPECIFICATIONS
ANALOG SPECIFICATIONS
Parameter MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 2-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY (ENTIRE SIGNAL PATH) ADC Resolution Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes ANALOG INPUTS Input Signal Range (Programmable)1 Allowable Reset Transient1 Input Limits2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise @ PGA Minimum Total Output Noise @ PGA Maximum Channel-to-Channel Crosstalk @ 15 MSPS @ 6 MSPS POWER SUPPLY REJECTION AVDD = 5 V Ϯ 0.25 V DIFFERENTIAL VREF (at 25°C) CAPT–CAPB TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode POWER DISSIPATION 3-Channel Mode 1-Channel Mode –40 –65 4.75 3.0 5.0 5.0 75 5 200 400 300

ics950218

Integrated CircuitSystems, Inc.ICS950218Preliminary Product Preview*MULTISEL1/REF1VDDREFX1X2GND*FS2/PCICLK0*FS3/PCICLK1SEL48_24#/PCICLK2VDDPCI *FS4/PCICLK3PCICLK4PCICLK5GND PCICLK6PCICLK7PCICLK8PCICLK9VDDPCI Vtt_PWRGD#RESET#GND*FS0/48MHz *FS1/24_48MHzAVDD481**REF0/MULTSEL0*GND VDDCPU CPUCLKT2CPUCLKC2GND PD#CPUCLKT0CPUCLKC0VDDCPU CPUCLKT1CPUCLKC1GND I REF AVDD GNDVDD3V663V66_03V66_1GND 3V66_23V66_48MHz/SEL66_48#SCLK SDATA*Block Diagram950218 Rev A 01/23/02Recommended Application:CK-408 clock with driven mode only for Brookdale and Brookdale-G chipset with P4 processor.Output Features:• 3 - Pairs of differential CPU clocks (differential currentmode)• 3 - 3V66 @ 3.3V •10 - PCI @ 3.3V • 1 - 48MHz @ 3.3V fixed • 2 - REF @ 3.3V, 14.318MHz • 1 - 48_66MHz selectable @ 3.3V fixed • 1 - 24_48MHz selectable @ 3.3V Features/Benefits:•Programmable output frequency.•Programmable output divider ratios.•Programmable output rise/fall time.•Programmable output skew.•Programmable spread percentage for EMI control.•Watchdog timer technology to reset systemif system malfunctions.•Programmable watch dog safe frequency.•Support I 2C Index read/write and block read/writeoperations.•Uses external 14.318MHz crystal.Key Specifications:•CPU Output Jitter <150ps •3V66 Output Jitter <250ps •CPU Output Skew <100psProgrammable Timing Control Hub for P 448-Pin 300-mil SSOPSDA T 2t i B 7t i B 6t i B 5t i B 4t i B K L C U P C z H M 66V 3z H M K L C I C P z H M 4S F 3S F 2S F 1S F 0S F 0000000.20100.8600.430000100.50100.0700.530001000.80100.2700.630001100.11100.4700.730010000.41100.6700.830010100.71100.8700.930011000.02100.0800.040011100.32100.2800.140100000.62100.2700.630100100.03103.4701.730101000.63100.8600.430101100.04100.0700.530110000.44100.2700.630110100.84100.4700.730111000.25100.6700.830111100.65100.8700.931000000.06100.0800.041000100.46100.2800.141001006.66106.6603.331001100.07100.8600.431010000.57100.0700.531010100.08100.2700.631011000.58100.4700.731011100.09100.6700.831100008.6608.6604.331100102.00108.6604.331101006.33108.6604.331101104.00208.6604.331110006.6606.6603.331110100.00106.6603.331111000.00206.6603.331111133.33106.6603.33Frequency Table1 This output has 2X drive* Internal Pull-up resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GNDPRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.2Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewPin DescriptionThe ICS950218 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR memory.It provides all necessary clock signals for such a system.The ICS950218 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I 2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.General DescriptionRE B M U N N I P EM A N N I P E P Y T NO I T P I R C S E D 11L E S T L U M N I .s t u p t u o U P C r o f r e i l p i t l u m t n e r r u c e h t g n i t c e l e s r o f t u p n i L T T V L V 3.31F E R T U O .t u p t u o k c o l c e c n e r e f e r z H M 813.41,V 3.3,42,81,9,264,93,23D D V R W P yl p p u s r e w o p V 3.331X N I 2X m o r f r o t s i s e r k c a b d e e f d n a )F p 33(p a c d a o l l a n r e t n i s a h ,t u p n i l a t s y r C 42X T U O )F p 33(p a c d a o l l a n r e t n i s a H .z H M 813.41y l l a n i m o n ,t u p t u o l a t s y r C ,92,12,31,574,34,63D N G R W P yl p p u s V 3.3r o f s n i p d n u o r G 62S F N I .n o r e w o p t a d e h c t a l t u p n I .t i b t c e l e s y c n e u q e r f t u p n i c i g o L 0K L C I C P T U O tu p t u o k c o l c I C P V 3.373S F N I .n o r e w o p t a d e h c t a l t u p n I .t i b t c e l e s y c n e u q e r f t u p n i c i g o L 1K L C I C P T U O tu p t u o k c o l c I C P V 3.38#42_84L E S N I ,z H M 84=h g i H .t u p t u o z H M 84.42e h t r o f y c n e u q e r f e h t s t c e l e s s i h T zH M 42=w o L 2K L C I C P T U O tu p t u o k c o l c I C P V 3.3014S F N I .n o r e w o p t a d e h c t a l t u p n I .t i b t c e l e s y c n e u q e r f t u p n i c i g o L 3K L C I C P T U O t u p t u o k c o l c I C P V 3.311,21,41,51,61,71)2,4:9(K L C I C P T U O st u p t u o k c o l c I C P V 3.391#D G R W P _t t V N I S F n e h w e n i m r e t e d o t d e s u e b o r t s e v i t i s n e s l e v e l a s i t u p n i L T T V L t n a r e l o t V 5s i h T d e l p m a s e b o t y d a e r e r a d n a d i l a v e r a s t u p n i L E S I T L U M d n a )0:4()w o l e v i t c a (02#T E S E R T U O .t u o e m i t r e m m i t g o d h c t a w r o e u l a v y c n e u q e r f r o f l a n g i s t e s e r m e t s y s e m i t l a e R .w o l e v i t c a s i l a n g i s s i h T 13,03,82)0:2(66V 3T U O BU H r o f s t u p t u o k c o l c z H M 66d e x i F V 3.3220S F N I .n o r e w o p t a d e h c t a l t u p n I .t i b t c e l e s y c n e u q e r f t u p n i c i g o L z H M 84T U O .t u p t u o k c o l c z H M 84d e x i F V 3.3321S F N I .n o r e w o p t a d e h c t a l t u p n I .t i b t c e l e s y c n e u q e r f t u p n i c i g o L z H M 84_42T U O .t u p t u o z H M 84r o 42e l b a t c e l e S 52A T A D S O /I I r o f n i p a t a D 2t n a r e l o t V 5y r t i u c r i c C 62K L C S N I I r o f n i p k c o l C 2tn a r e l o t V 5y r t i u c r i c C 72#84_66L E S N I z H M 84=w o L ,z H M 66=h g i H t u p t u o z H M 84_6V 3e h t r o f y c n e u q e r f e h t s t c e l e s s i h T z H M 84_66V 3T U O t u p t u o z H M 84r o 66e l b a t c e l e S 33D N G R W P LL P E R O C r o f d n u o r G 43D D V A R W P la n i m o n V 3.3L L P E R O C r o f r e w o P 53F E R I T U O n i p s i h T .s r i a p K L C U P C e h t r o f t n e r r u c e c n e r e f e r e h t s e h s i lb a t s e n i p s i h T e h t h s i l b a t s e o t r e d r o n i d n u o r g o t d e i t r o t s i s e r n o i s ic e r pde x if a s e r i u q e r .t n e r r u c e t a i r p o r p p a 24#D P N I w o l a o t n i e c i v e d e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s A e r a l a t s y r c e h t d n a O C V e h t d n a d e l b a s i d e r a s k c o l c l a n r e t n i e h T .e t a t s r e w o p .s m 3n a h t r e t a e r g e b t o n l l i w n w o d r e w o p e h t f o y c n e t a l e h T .d e p p o t s 73,04,44)0:2(C K L C U P C T U O s t u p t u o t n e r r u c e r a e s e h T .s t u p t u o U P C r i a p l a i t n e r e f f i d f o s k c o l c "y r o t n e m e l p m o C ".s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e d n a 83,14,54)0:2(T K L C U P C T U O d n a s t u p t u o t n e r r u c e r a e s e h T .s t u p t u o U P C r i a p l a i t n e r e f f i d f o s k c o l c "e u r T ".s a i b e g a t l o v r o f d e r i u q e r e r a s r o t s i s e r l a n r e t x e 840L E S T L U M N I .s t u p t u o U P C r o f r e i l p i t l u m t n e r r u c e h t g n i t c e l e s r o f t u p n i L T T V L V 3.30F E R TU O .t u p t u o k c o l c e c n e r e f e r z H M 813.41,V 3.33Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewMaximum Allowed Currentn o i t i d n o C n o i t p m u s n o c y l p p u s V 3.3x a M ,s d a o l p a c e t e r c s i d x a M V564.3=d d V DN G r o d d V =s t u p n i c i t a t s l l A e d o M n w o d r e w o P )0=#N W D R W P (A m 04ev i t c A l l u F Am 063CPUCLK Swing Select Functions4Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewGeneral I 2C serial interface informationHow to Write:Controller (host) sends a start bit.•Controller (host) sends the write address D2 (H)•ICS clock will acknowledge•Controller (host) sends the begining byte location = N •ICS clock will acknowledge•Controller (host) sends the data byte count = X •ICS clock will acknowledge•Controller (host) starts sending Byte N through Byte N + X -1(see Note 2)•ICS clock will acknowledge each byte one at a time •Controller (host) sends a Stop bitHow to Read:•Controller (host) will send start bit.•Controller (host) sends the write address D2 (H)•ICS clock will acknowledge•Controller (host) sends the begining byte location = N•ICS clock will acknowledge•Controller (host) will send a separate start bit.•Controller (host) sends the read address D3 (H)•ICS clock will acknowledge•ICS clock will send the data byte count = X •ICS clock sends Byte N + X -1•ICS clock sends Byte 0 through byte X (if X (H)was written to byte 8).•Controller (host) will need to acknowledge each byte •Controllor (host) will send a not acknowledge bit •Controller (host) will send a stop bit*See notes on the following page .5Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 0: Functionality and frequency select register (Default=0)Notes:1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.ti B no i t p i r c s e D DW P t i B )4:7,2(2t i B 7t i B 6t i B 5t i B 4t i B K L C U P C zH M 66V 3zH M K L C I C P z H M %d ae r p S 1e t o N 4S F 3S F 2S F 1S F 0S F 0000000.20100.8600.43d a e r p s r e t n e C %52.0-/+0000100.50100.0700.53d a e r p s r e t n e C %52.0-/+0001000.80100.2700.63d a e r p s r e t n e C %52.0-/+0001100.11100.4700.73d a e r p s r e t n e C %52.0-/+0010000.41100.6700.83d a e r p s r e t n e C %52.0-/+0010100.71100.8700.93d a e r p s r e t n e C %52.0-/+0011000.02100.0800.04d a e r p s r e t n e C %52.0-/+0011100.32100.2800.14d a e r p s r e t n e C %52.0-/+0100000.62100.2700.63d a e r p s r e t n e C %52.0-/+0100100.03103.4701.73d a e r p s r e t n e C %52.0-/+0101000.63100.8600.43d a e r p s r e t n e C %52.0-/+0101100.04100.0700.53d a e r p s r e t n e C %52.0-/+0110000.44100.2700.63d a e r p s r e t n e C %52.0-/+0110100.84100.4700.73d a e r p s r e t n e C %52.0-/+0111000.25100.6700.83d a e r p s r e t n e C %52.0-/+0111100.65100.8700.93d a e r p s r e t n e C %52.0-/+1000000.06100.0800.04d a e r p s r e t n e C %52.0-/+1000100.46100.2800.14d a e r p s r e t n e C %52.0-/+1001006.66106.6603.33d a e r p s r e t n e C %52.0-/+1001100.07100.8600.43d a e r p s r e t n e C %52.0-/+1010000.57100.0700.53d a e r p s r e t n e C %52.0-/+1010100.08100.2700.63d a e r p s r e t n e C %52.0-/+1011000.58100.4700.73d a e r p s r e t n e C %52.0-/+1011100.09100.6700.83d a e r p s r e t n e C %52.0-/+1100008.6608.6604.33d a e r p s r e t n e C %52.0-/+1100102.00108.6604.33d a e r p s r e t n e C %52.0-/+1101006.33108.6604.33d a e r p s r e t n e C %52.0-/+1101104.00208.6604.33d a e r p s r e t n e C %52.0-/+1110006.6606.6603.33d a e r p s n w o D %5.0-o t 01110100.00106.6603.33d a e r p s n w o D %5.0-o t 01111000.00206.6603.33d a e r p s n w o D %5.0-o t 01111133.33106.6603.33da e r p s n w o D %5.0-o t 03t i B s t u p n i d e h c t a l ,t c e l e s e r a w d r a h yb d e tc e l e s s i y c n e u q e r F -04:7,2t i B y bde t c e l e s s i y c n e u q e r F -101t i B la m r o N -0el b a n e m u r t c e p s d a e r p S -10t i B s t u p n i h c t a l y b d e t c e l e s e b l l i w y c n e u q e r f e f a s g o d h c t a W -0)0:4(ti b 01e t y B y b d e m m a r g o r p e b l l i w y c n e u q e r f e f a s g o d h c t a W -106Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 1: Output Control Register (1 = enable, 0 = disable)Byte 3: Output Control Register (1 = enable, 0 = disable)Byte 2: Output Control Register (1 = enable, 0 = disable)Byte 4: Output Control Register (1 = enable, 0 = disable)t i B #n i P D W P no i t p i r c s e D 7t i B 44,5412C /T U P C 6t i B 73,8311C /T U P C 5t i B 04,1410C /T U P C 4t i B -X k c a b d a e R 4S F 3t i B -X k c a b d a e R 3S F 2t i B -X k c a b d a e R 2S F 1t i B -X k c a b d a e R 1S F 0t i B -Xkc a b da e R 0S F t i B #n i P D W P no i t p i r c s e D 7t i B -1d e v r e s e R 6t i B 7119_K L C I C P 5t i B 6118_K L C I C P 4t i B 5117_K L C I C P 3t i B 4116_K L C I C P 2t i B 2115_K L C I C P 1t i B 1114_K L C I C P 0t i B 0113_K L C I C P t i B #n i P D W P no i t p i r c s e D 7t i B -X )k c a b d a e r (0L E S i t l u M 6t i B -X )k c a b d a e R (1L E S i t l u M 5t i B 1310-66V 34t i B 0311-66V 33t i B 8410F E R 2t i B 111F E R 1t i B 7213_66V 30t i B 8212_66V 3Notes:1. PWD = Power on Default2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,CPUCLKC off, and external resistor termination will bring CPUCLKC low.t i B #n i P D W P no i t p i r c s e D 7t i B 3211_z H M 846t i B 2210_z H M 845t i B -1e l b a s i D =0,e l b a n E =1t c e t e d t f i h s r a e g t e s e R 4t i B -0I =1;e r a w d r a h y b #42_84l e S =02C 3t i B -0z H M 84=1,z H M 42=0,#42_84l e S 2t i B 812_K L C I C P 1t i B 711_K L C I C P 0t i B 61_K L C I C P7Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 7: Revision ID and Device ID RegisterByte 8: Byte Count Read Back RegisterByte 5: Programming Edge Rate (1 = enable, 0 = disable)Byte 6: Vendor ID Register (1 = enable, 0 = disable)t i B e m a N D W P n o i t p i r c s e D 7t i B 7e t y B 0w o h d n a t n u o c e t y b e r u g i f n o c l l i w r e t s i g e r s i h t o t g n i t i r W :e t o N s i t l u a f e d ,k c a b d a e r e b l l i w s e t y b y n a m F 0H .s e t y b 51=6t i B 6e t y B 05t i B 5e t y B 04t i B 4e t y B 03t i B 3e t y B 12t i B 2e t y B 11t i B 1e t y B 10t i B 0e t y B 1t i B e m a N D W P n o i t p i r c s e D 7t i B 7D I e c i v e D 0e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v D I e c i v e D .e s a c s i h t n i "H 82"6t i B 6D I e c i v e D 05t i B 5D I e c i v e D 14t i B 4D I e c i v e D 03t i B 3D I e c i v e D 12t i B 2D I e c i v e D 01t i B 1D I e c i v e D 00t i B 0D I e c i v e D 0t i B em a N D W P no i t p i r c s e D 7t i B 3t i B D I n o i s i v e R X n o i s i v e r s 'e c i v e d l a u d i v i d n i n o d e s a b e b l l i w s e u l a v D I n o i s i v e R 6t i B 2t i B D I n o i s i v e R X 5t i B 1t i B D I n o i s i v e R X 4t i B 0t i B D I n o i s i v e R X 3t i B 3t i B D I r o d n e V 0)d e v r e s e R (2t i B 2t i B D I r o d n e V 0)d e v r e s e R (1t i B 1t i B D I r o d n e V 0)d e v r e s e R (0t i B 0t i B D I r o d n e V 1)d e v r e s e R (t i B #n i P D W P no i t p i r c s e D 7t i B X X )k c a b d a e R (#42_84l e S 6t i B X X )k c a b d a e R (#84_66l e S 5t i B X 1)d e v r e s e R (4t i B X 1)d e v r e s e R (3t i B X 0I y b =1;e r a w d r a h y b #84_66l e S =02C 2t i B X 1z H M 66=1,z H M 84=0,#84_66l e S 1t i B X 1ti b l o r t n o c 66V 3.c n y s A U P C h t i w s u o n o r h c n y s a z H M 23/46=I C P /66V 3:0U P C h t i w s u o n o r h c n y s z H M 3.33/6.66=I C P /66V 3:10t i B X)d e v r e s e R (8Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 10: Programming Enable bit 8 Watchdog Control RegisterByte 11: VCO Frequency M Divider (Reference divider) Control RegisterByte 12: VCO Frequency N Divider (VCO divider) Control RegisterByte 9: Watchdog Timer Count Registert i B e m a N D W P n o i t p i r c s e D 7t i B 7D W 0 X o t d n o p s e r r o c s t i b 8e s e h t f o n o i t a t n e s e r p e r l a m i c e d e h T ed o m m r a l a o t se o g t i e r of e b t i a w l l i w r e m i tg o dh c t a w e h t s m 092si p u r e w o p t a t l u a f e D .g n i t t e s e f a s e h t o t y c n e u q e r f e h t t e s e r d n a .s d n o c e s 3.2=s m 092 86t i B 6D W 05t i B 5D W 04t i B 4D W 03t i B 3D W 12t i B 2D W 01t i B 1D W 00t i B 0D W 0t i B e m a N D W P no i t p i r c s e D 7t i B 8v i d N X 8t i b r e d i v i d N 6t i B 6v i d M X e h t o t d s o p s e r r o c )0:6(v i d M f o n o i t a t n e s e r p s e r l a m i c e d e h T e h t o t l a u q e s i p u r e w o p t a t l u a f e D .e u l a v r e d i v i d e c n e r e f e r .n o i t c e l e s s t u p n i d e h c t a l 5t i B 5v i d M X 4t i B 4v i d M X 3t i B 3v i d M X 2t i B 2v i d M X 1t i B 1v i d M X 0t i B 0v i d M Xt i B e m a N D W P n o i t p i r c s e D 7t i B 7v i d N X e h t o t d n o p s e r r o c )0:8(v i d N f o n o i t a t n e s e r p e r l a m i c e d e h T eh t o t l a u q e s i p u r e w o p t a t l u a f e D .e u l a v r e d i v i d O C V .11e t y B n i d e t a c o l s i 8v i d N e c i t o N .n o t c e l e s s t u p n i d e h c t a l 6t i B 6v i d N X 5t i B 5v i d N X 4t i B 4v i d N X 3t i B 3v i d N X 2t i B 2v i d N X 1t i B 1v i d N X 0t i B 0v i d N Xt i B e m a N D W P no i t p i r c s e D 7t i B m a r g o r P e l b a n E 0ti b e l b a n E g n i m m a r g o r P 10e t y B r o s e h c t a l W H y b d e t c e l e s e r a s e i c n e u q e r F .g n i m m a r g o r p o n =0I l l a e l b a n e =2.g n i m a r g o r p C 6t i B e l b a n E D W 0.t i b e l b a n E g o d h c t a W .e l b a n E =1,e l b a s i d =0.e u l a v d e h c t a l N E D W e t i r w r e v o l l i w t i b s i h T 5t i B m r a l A D W 0su t a t s m r a l a =1l a m r o n =0s u t a t S m r a l A g o d h c t a W 4t i B 4F S 0e f a s e h t e r u g i f n o c l l i w s t i b e s e h t o t g n i t i r W .s t i b y c n e u q e r f e f a s g o d h c t a W el b a t 4:7,2t i B 0e t y B o t g n i d n o p s r r o c y c n e u q e r f 3t i B 3F S 12t i B 2F S 01t i B 1F S 00t i B 0F S 09Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 14: Spread Spectrum Control RegisterByte 15: Output Divider Control RegisterByte 13: Spread Spectrum Control RegisterByte 16: Output Divider Control Registert i B e m a N D W P n o i t p i r c s e D 7t i B 7S S X d a e r p s e h t m a r g o r p l l i w t i b )0:21(m u r t c e p S d a e r p S e h T e h t n o d e s a b d e t a l u c l a c e b o t s d e e n t n e c e r p d a e r p S .e g a t n e c e r p d a e r p s d n a t n u o m a g n i d a e r p s ,e l i f o r p g n i d a e r p s ,y c n e u q e r f O C V d a e r p s r o f e r a w t f o s S C I e s u o t d e d n e m m o c e r s i t I .y c n e u q e r f .r e d i v i d S F d e h c t a l s i n o r e w o p t l u a f e D .g n i m m a r g o r p 6t i B 6S S X5t i B 5S S X4t i B 4S S X3t i B 3S S X2t i B 2S S X 1t i B 1S S X 0t i B 0S S Xt i B e m a N D W P no i t p i r c s e D 7t i B d e v r e s e R X d e v r e s e R 6t i B d e v r e s e R X d e v r e s e R 5t i B d e v r e s e R X de v r e s e R 4t i B 21S S X 21t i B m u r t c e p S d a e r p S 3t i B 11S S X 11t i B m u r t c e p S d a e r p S 2t i B 01S S X 01t i B m u r t c e p S d a e r p S 1t i B 9S S X 9t i B m u r t c e p S d a e r p S 0t i B 8S S X8t i B m u r t c e p S d a e r p S t i B e m a N D W P no i t p i r c s e D 7t i B 3V I D U P C X 4e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c 2U P C o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o F .y l l a u d i v i d n i s t i b .r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D .1e l b a T 6t i B 2V I D U P C X 5t i B 1V I D U P C X 4t i B 0V I D U P C X 3t i B 3v i D U P C X ai v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c )0:1(U P C r e f e r e l b a t n o i t c e l e s r e d i v i d r o F .y l l a u d i v i d n i s t i b 4e s e h t .r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D .1e l b a T o t 2t i B 2v i D U P C X 1t i B 1v i D U P C X 0t i B 0v i D U P C Xt i B e m a N D W P no i t p i r c s e D 7t i B 3v i D 66V 3X ai v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c )2:3(66V 3r e f e r e l b a t n o i t c e l e s r e d i v i d r o F .y l l a u d i v i d n i s t i b 4e s e h t .r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D .1e l b a T o t 6t i B 2v i D 66V 3X 5t i B 1v i D 66V 3X 4t i B 0v i D 66V 3X 3t i B 3v i D 66V 3X ai v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c )0:1(66V 3r e f e r e l b a t n o i t c e l e s r e d i v i d r o F .y l l a u d i v i d n i s t i b 4e s e h t .r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D .1e l b a T o t 2t i B 2v i D 66V 3X 1t i B 1v i D 66V 3X 0t i B 0v i D 66V 3X10Third party brands and names are the property of their respective owners.Integrated CircuitSystems, Inc.ICS950218Preliminary Product PreviewByte 17: Output Divider Control RegisterByte 18: Group Skew Control RegisterByte 19: Group Skew Control RegisterTable 1Table 2)2:3(v i D 00100111)0:1(v i D 002/4/8/61/103/6/21/42/015/01/02/04/117/41/82/65/)2:3(v i D 00100111)0:1(v i D 004/8/61/23/103/6/21/42/015/01/02/04/119/81/63/27/t i B e m a N D W P n o i t p i r c s e D 7t i B V N I _)2:3(66V 3X t i b n o i s r e v n I e s a h P )2:3(66V 36t i B V N I _)0:1(66V 3X t i b n o i s r e v n I e s a h P )0:1(66V 35t i B V N I _U P C X t i b n o i s r e v n I e s a h P 2_K L C U P C 4t i B VN I _U P C X t i b n o i s r e v n I e s a h P K L C U P C 3t i B 3v i D I C P Xs t i b 4e s e h t a i v d e r u g i f n o c e b n a c o i t a r r e d i v i d k c o l c I C P .2e l b a T o t r e f e r e l b a t n o i t c e l e s r e d i v i d r o F .y l l a u d i v i d n i .r e d i v i d S F d e h c t a l s i p u r e w o p t a t l u a f e D 2t i B 2v i D I C P X1t i B 1v i D I C P X 0t i B 0v i D I C P Xt i B e m a N D W P no i t p i r c s e D 7t i B 1w e k S _U P C 0o t t c e p s e r h t i w 2T /C K L C U P C e h t y a l e d s t i b 2e s e h T )0:1(T /C K L C U P C s p 057=11s p 005=01s p 052=10s p 0=006t i B 0w e k S _U P C 15t i B d e v r e s e R 0d e v r e s e R 4t i B d e v r e s e R 0de v r e s e R 3t i B 1w e k S _U P C 0e h t y a l e d s t i b 2e s e h T )0:1(T /C K L C U P C o t t c e p s e r h t i w k c o l c 2T /C K L C U P C s p 052=10s p 0=00s p 057=11s p 005=012t i B 0w e k S _U P C 11t i B d e v r e s e R 0d e v r e s e R 0t i B de v r e s e R 0de v r e s e R t i B e m a N D W P e c n e u q e S g n i m m a r g o r P 7t i B l o r t n o c s t i b 4e s e h T )2:3(66V 3-U P C 00000s p 0d e v r e s e R 6t i B 10100s p 051d e v r e s e R 5t i B 01000s p 003d e v r e s e R 4t i B 01100s p 054d e v r e s e R 3t i B l o r t n o c s t i b 4e s e h T )0:1(66V 3-U P C 01101s p 006d e v r e s e R 2t i B 11110sp 057de v r e s e R 1t i B 01111s p 009d e v r e s e R 0t i B 0d e v r e s e R de v r e s e RByte 20: Group Skew Control RegisterByte 21: Slew Rate Control RegisterByte 22: Slew Rate Control Register Byte 23: Slew Rate Control Registerti B em a N D W P no i t p i r c s e D 7t i B 1w e l S _2_K L C I C P 1.s t i b l o r t n o c e t a r w e l s k c o l c 2K L C I C P ka e w =01;l a m r o n =11:g n o r t s =106t i B 1w e l S _2_K L C I C P 05t i B 0w e l S _)0:1(K L C I C P 1.s t ib l o r t n oc e t a r w e l s k c o l c )0:1(K L C I C P k a e w =01;l a m r o n =11:g n o r t s =104t i B 0w e l S _)0:1(K L C I C P 03t i B 1w e l S _)2:3(66V 31.s t i b l o r t n o c e t a r w e l s k c o l c )1:2(66V 3k a e w =01;l a m r o n =11:g n o r t s =102t i B 1w e l S _)2:3(66V 301t i B 1w e l S _)0:1(66V 31.s t i b l o r t n o c e t a r w e l s k c o l c )0:1(66V 3ka e w =01;l a m r o n =11:g n o r t s =100t i B 0w e l S _)0:1(66V 30t i B e m a N D W P no i t p i r c s e D 7t i B 1w e l S F E R 1.s t i b l o r t n o c e t a r w e l s k c o l c F E R k a e w =01;l a m r o n =11:g n o r t s =106t i B 0w e l S F E R 05t i B 1w e l S )7:9(I C P 1.s t i b l o r t n o c e t a r w e l s k c o l c ))7:9(I C P k a e w =01;l a m r o n =11:g n o r t s =104t i B 0w e l S )7:9(I C P 03t i B )5:6(I C P 1w e l S 1.s t i b l o r t n o c e t a r w e l s k c o l c )5:6(I C P k a e w =01;l a m r o n =11:g n o r t s =102t i B )5:6(I C P 0w e l S 01t i B )3:4(I C P 1w e l S 1.s t i b l o r t n o c e t a r w e l s k c o l c )3:4(I C P ka e w =01;l a m r o n =11:g n o r t s =100t i B )3:4(I C P 0w e l S 0t i B e m a N D W P n o i t p i r c s e D 7t i B d e v r e s e R X de v r e s e R 6t i B d e v r e s e R X5t i B d e v r e s e R 14t i B d e v r e s e R 03t i B 1w e l S z H M 841.s t i b l o r t n o c e t a r w e l s k c o l c z H M 84k k a e w =01;l a m r o n =11:g n o r t s =102t i B 0w e l S z H M 8401t i B 1w e l S z H M 84_421.s t i b l o r t n o c e t a r w e l s k c o l c z H M 84_42k a e w =01;l a m r o n =11:g n o r t s =100t i B 0w e l S z H M 84_420t i B e m a N D W P e c n e u q e S g n i m m a r g o r P 7t i B l o r t n o c s t i b 4e s e h T )0:9(I C P -U P C 10000s p 0d e v r e s e R 6t i B 00100s p 051d e v r e s e R 5t i B 01000s p 003d e v r e s e R 4t i B 01100s p 054d e v r e s e R 3t i B de v e r s e R 11101s p 006d e v r e s e R 2t i B 0111sp 057de v r e s e R 1t i B 01111s p 009d e v r e s e R 0t i B 0d e v r e s e R de v r e s e RAbsolute Maximum RatingsSupply V oltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 VLogic Inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V DD +0.5 VAmbient Operating Temperature. . . . . . . . . . . . . . . . . 0°C to +70°CCase Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°CStorage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°CStresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.。

AD9826KRSZRL资料

FUNCTIONAL BLOCK DIAGRAM
AVDD AVSS CML CAPT CAPB AVDD AVSS DRVDD DRVSS
VINR
CDS 9-BIT DAC
PGA BANDGAP REFERENCE
AD9826
OEB
VING
CDS 9-BIT DAC
PGA
3:1 MUX
16-BIT ADC
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE) 1V TYP RESET TRANSIENT 4V p-p MAX INPUT SIGNAL RANGE GND
2
The PGA Gain is approximately “linear in dB” and follows the equation: Gain =
Complete 16-Bit Imaging Signal Processor AD9826
PRODUCT DESCRIPTION
The AD9826 is a complete analog signal processor for imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC, and Programmable Gain Amplifier (PGA), multiplexed to a high-performance 16-bit A/D converter. The AD9826 can operate at speeds greater than 15 MSPS with reduced performance. The CDS amplifiers may be disabled for use with sensors that do not require CDS, such as Contact Image Sensors (CIS), CMOS active pixel sensors, and Focal Plane Arrays. The 16-bit digital output is multiplexed into an 8-bit output word, which is accessed using two read cycles. There is an optional single byte output mode. The internal registers are programmed through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode. The AD9826 operates from a single 5 V power supply, typically consumes 400 mW of power, and is packaged in a 28-lead SSOP.

Clocks(时钟)

Clocks by Jerome K. JeromeThere are two kinds of clocks. There is the clock that is always wrong, and that knows it is wrong, and glories in it; and there is the clock that is always right--except when you rely upon it, and then it is more wrong than you would think a clock _could_ be in a civilized country.I remember a clock of this latter type, that we had in the house when I was a boy, routing us all up at three o'clock one winter's morning. We had finished breakfast at ten minutes to four, and I got to school a little after five, and sat down on the step outside and cried, because I thought the world had come to an end; everything was so death-like!The man who can live in the same house with one of these clocks, and not endanger his chance of heaven about once a month by standing up and telling it what he thinks of it, is either a dangerous rival to that old established firm, Job, or else he does not know enough bad language to make it worth his while to start saying anything at all.The great dream of its life is to lure you on into trying to catch a train by it. For weeks and weeks it will keep the most perfect time. If there were any difference in time between that clock and the sun, you would be convinced it was the sun, not the clock, that wanted seeing to. You feel that if that clock happened to get a quarter of a second fast, or the eighth of an instant slow, it would break its heart and die.It is in this spirit of child-like faith in its integrity that, one morning, you gather your family around you in the passage, kiss your children, and afterward wipe your jammy mouth, poke your finger in the baby's eye, promise not to forget to order the coals, wave at last fond adieu with the umbrella, and depart for the railway-station.I never have been quite able to decide, myself, which is the more irritating to run two miles at the top of your speed, and then to find, when you reach the station, that you are three-quarters of an hour too early; or to stroll along leisurely the whole way, and dawdle about outside the booking-office, talking to some local idiot, and then to swagger carelessly on to the platform, just in time to see the train go out!As for the other class of clocks--the common or always-wrong clocks--they are harmless enough. You wind them up at the proper intervals,and once or twice a week you put them right and "regulate" them, as you call it (and you might just as well try to "regulate" a London tom-cat). But you do all this, not from any selfish motives, but from a sense of duty to the clock itself. You want to feel that, whatever may happen, you have done the right thing by it, and that no blame can attach to you.So far as looking to it for any return is concerned, that you never dream of doing, and consequently you are not disappointed. You ask what the time is, and the girl replies:"Well, the clock in the dining-room says a quarter past two."But you are not deceived by this. You know that, as a matter of fact, it must be somewhere between nine and ten in the evening; and, remembering that you noticed, as a curious circumstance, that the clock was only forty minutes past four, hours ago, you mildly admire its energies and resources, and wonder how it does it.I myself possess a clock that for complicated unconventionality and light-hearted independence, could, I should think, give points to anything yet discovered in the chronometrical line. As a mere time-piece, it leaves much to be desired; but, considered as a self-acting conundrum, it is full of interest and variety.I heard of a man once who had a clock that he used to say was of no good to any one except himself, because he was the only man who understood it. He said it was an excellent clock, and one that you could thoroughly depend upon; but you wanted to know it--to have studied its system. An outsider might be easily misled by it."For instance," he would say, "when it strikes fifteen, and the hands point to twenty minutes past eleven, I know it is a quarter to eight."His acquaintanceship with that clock must certainly have given him an advantage over the cursory observer!But the great charm about my clock is its reliable uncertainty. It works on no method whatever; it is a pure emotionalist. One day it will be quite frolicsome, and gain three hours in the course of the morning, and think nothing of it; and the next day it will wish it were dead, and be hardly able to drag itself along, and lose two hours out of every four, and stop altogether in the afternoon, too miserable to do anything; and then,getting cheerful once more toward evening, will start off again of its own accord.I do not care to talk much about this clock; because when I tell the simple truth concerning it, people think I am exaggerating.It is very discouraging to find, when you are straining every nerve to tell the truth, that people do not believe you, and fancy that you are exaggerating. It makes you feel inclined to go and exaggerate on purpose, just to show them the difference. I know I often feel tempted to do so myself--it is my early training that saves me.We should always be very careful never to give way to exaggeration; it is a habit that grows upon one.And it is such a vulgar habit, too. In the old times, when poets and dry-goods salesmen were the only people who exaggerated, there was something clever and _distingue_ about a reputation for "a tendency to over, rather than to under-estimate the mere bald facts." But everybody exaggerates nowadays. The art of exaggeration is no longer regarded as an "extra" in the modern bill of education; it is an essential requirement, held to be most needful for the battle of life.The whole world exaggerates. It exaggerates everything, from the yearly number of bicycles sold to the yearly number of heathens converted--into the hope of salvation and more whiskey. Exaggeration is the basis of our trade, the fallow-field of our art and literature, the groundwork of our social life, the foundation of our political existence. As schoolboys, we exaggerate our fights and our marks and our fathers' debts. As men, we exaggerate our wares, we exaggerate our feelings, we exaggerate our incomes--except to the tax-collector, and to him we exaggerate our "outgoings"; we exaggerate our virtues; we even exaggerate our vices, and, being in reality the mildest of men, pretend we are dare-devil scamps.We have sunk so low now that we try to _act_ our exaggerations, and to live up to our lies. We call it "keeping up appearances;" and no more bitter phrase could, perhaps, have been invented to describe our childish folly.If we possess a hundred pounds a year, do we not call it two? Ourlarder may be low and our grates be chill, but we are happy if the "world" (six acquaintances and a prying neighbor) gives us credit for one hundred and fifty. And, when we have five hundred, we talk of a thousand, and the all-important and beloved "world" (sixteen friends now, and two of them carriage-folks!) agree that we really must be spending seven hundred, or at all events, running into debt up to that figure; but the butcher and baker, who have gone into the matter with the housemaid, know better.After awhile, having learned the trick, we launch out boldly and spend like Indian Princes--or rather _seem_ to spend; for we know, by this time, how to purchase the seeming with the seeming, how to buy the appearance of wealth with the appearance of cash. And the dear old world--Beelzebub bless it! for it is his own child, sure enough; there is no mistaking the likeness, it has all his funny little ways--gathers round, applauding and laughing at the lie, and sharing in the cheat, and gloating over the thought of the blow that it knows must sooner or later fall on us from the Thor-like hammer of Truth.And all goes merry as a witches' frolic--until the gray morning dawns.Truth and fact are old-fashioned and out-of-date, my friends, fit only for the dull and vulgar to live by. Appearance, not reality, is what the clever dog grasps at in these clever days. We spurn the dull-brown solid earth; we build our lives and homes in the fair-seeming rainbow-land of shadow and chimera.To ourselves, sleeping and waking there, _behind_ the rainbow, there is no beauty in the house; only a chill damp mist in every room, and, over all, a haunting fear of the hour when the gilded clouds will melt away, and let us fall--somewhat heavily, no doubt--upon the hard world underneath.But, there! of what matter is _our_ misery, _our_ terror? To the stranger, our home appears fair and bright. The workers in the fields below look up and envy us our abode of glory and delight! If _they_ think it pleasant, surely _we_ should be content. Have we not been taught to live for others and not for ourselves, and are we not acting up bravely to the teaching--in this most curious method?Ah! yes, we are self-sacrificing enough, and loyal enough in our devotion to this new-crowned king, the child of Prince Imposture andPrincess Pretense. Never before was despot so blindly worshiped! Never had earthly sovereign yet such world-wide sway!Man, if he would live, _must_ worship. He looks around, and what to him, within the vision of his life, is the greatest and the best, that he falls down and does reverence to. To him whose eyes have opened on the nineteenth century, what nobler image can the universe produce than the figure of Falsehood in stolen robes? It is cunning and brazen and hollow-hearted, and it realizes his souls ideal, and he falls and kisses its feet, and clings to its skinny knees, swearing fealty to it for evermore!Ah! he is a mighty monarch, bladder-bodied King Humbug! Come, let us build up temples of hewn shadows wherein we may adore him, safe from the light. Let us raise him aloft upon our Brummagem shields. Long live our coward, falsehearted chief!--fit leader for such soldiers as we! Long live the Lord-of-Lies, anointed! Long live poor King Appearances, to whom all mankind bows the knee!But we must hold him aloft very carefully, oh, my brother warriors! He needs much "keeping up." He has no bones and sinews of his own, the poor old flimsy fellow! If we take our hands from him, he will fall a heap of worn-out rags, and the angry wind will whirl him away, and leave us forlorn. Oh, let us spend our lives keeping him up, and serving him, and making him great--that is, evermore puffed out with air and nothingness--until he burst, and we along with him!Burst one day he must, as it is in the nature of bubbles to burst, especially when they grow big. Meanwhile, he still reigns over us, and the world grows more and more a world of pretense and exaggeration and lies; and he who pretends and exaggerates and lies the most successfully, is the greatest of us all.The world is a gingerbread fair, and we all stand outside our booths and point to the gorgeous-colored pictures, and beat the big drum and brag. Brag! brag! Life is one great game of brag!"Buy my soap, oh ye people, and ye will never look old, and the hair will grow again on your bald places, and ye will never be poor or unhappy again,; and mine is the only true soap. Oh, beware of spurious imitations!""Buy my lotion, all ye that suffer from pains in the head, or the stomach, or the feet, or that have broken arms, or broken hearts, or objectionable mothers-in-law; and drink one bottle a day, and all your troubles will be ended.""Come to my church, all ye that want to go to Heaven, and buy my penny weekly guide, and pay my pew-rates; and, pray ye, have nothing to do with my misguided brother over the road. _This_ is the only safe way!""Oh, vote for me, my noble and intelligent electors, and send our party into power, and the world shall be a new place, and there shall be no sin or sorrow any more! And each free and independent voter shall have a bran new Utopia made on purpose for him, according to his own ideas, with a good-sized, extra-unpleasant purgatory attached, to which he can send everybody he does not like. Oh! do not miss this chance!"Oh! listen to my philosophy, it is the best and deepest. Oh! hear my songs, they are the sweetest. Oh! buy my pictures, they alone are true art. Oh! read my books, they are the finest.Oh! _I_ am the greatest cheesemonger, _I_ am the greatest soldier, _I_ am the greatest statesman, _I_ am the greatest poet, _I_ am the greatest showman, _I_ am the greatest mountebank, _I_am the greatest editor, and _I_ am the greatest patriot. _We_ are the greatest nation. _We_ are the only good people. _Ours_ is the only true religion. Bah! how we all yell!How we all brag and bounce, and beat the drum and shout; and nobody believes a word we utter; and the people ask one another, saying: "How can we tell who is the greatest and the cleverest among all these shrieking braggarts?"And they answer:"There is none great or clever. The great and clever men are not here; there is no place for them in this pandemonium of charlatans and quacks. The men you see here are crowing cocks. We suppose the greatest and the best of _them_ are they who crow the loudest and the longest; that is the only test of _their_ merits."Therefore, what is left for us to do, but to crow? And the best andgreatest of us all, is he who crows the loudest and the longest on this little dunghill that we call our world!Well, I was going to tell you about our clock.It was my wife's idea, getting it, in the first instance. We had been to dinner at the Buggles', and Buggles had just bought a clock--"picked it up in Essex," was the way he described the transaction. Buggles is always going about "picking up" things. He will stand before an old carved bedstead, weighing about three tons, and say:"Yes--pretty little thing! I picked it up in Holland;" as though he had found it by the roadside, and slipped it into his umbrella when nobody was looking!Buggles was rather full of this clock. It was of the good old-fashioned "grandfather" type. It stood eight feet high, in a carved-oak case, and had a deep, sonorous, solemn tick, that made a pleasant accompaniment to the after-dinner chat, and seemed to fill the room with an air of homely dignity.We discussed the clock, and Buggles said how he loved the sound of its slow, grave tick; and how, when all the house was still, and he and it were sitting up alone together, it seemed like some wise old friend talking to him, and telling him about the old days and the old ways of thought, and the old life and the old people.The clock impressed my wife very much. She was very thoughtful all the way home, and, as we went upstairs to our flat, she said, "Why could not we have a clock like that?" She said it would seem like having some one in the house to take care of us all--she should fancy it was looking after baby!I have a man in Northamptonshire from whom I buy old furniture now and then, and to him I applied. He answered by return to say that he had got exactly the very thing I wanted. (He always has. I am very lucky in this respect.) It was the quaintest and most old-fashioned clock he had come across for a long while, and he enclosed photograph and full particulars; should he send it up?From the photograph and the particulars, it seemed, as he said, the very thing, and I told him, "Yes; send it up at once."Three days afterward, there came a knock at the door--there had been other knocks at the door before this, of course; but I am dealing merely with the history of the clock. The girl said a couple of men were outside, and wanted to see me, and I went to them.I found they were Pickford's carriers, and glancing at the way-bill, I saw that it was my clock that they had brought, and I said, airily, "Oh, yes, it's quite right; bring it up!"They said they were very sorry, but that was just the difficulty. They could not get it up.I went down with them, and wedged securely across the second landing of the staircase, I found a box which I should have judged to be the original case in which Cleopatra's Needle came over.They said that was my clock.I brought down a chopper and a crowbar, and we sent out and collected in two extra hired ruffians and the five of us worked away for half an hour and got the clock out; after which the traffic up and down the staircase was resumed, much to the satisfaction of the other tenants.We then got the clock upstairs and put it together, and I fixed it in the corner of the dining-room.At first it exhibited a strong desire to topple over and fall on people, but by the liberal use of nails and screws and bits of firewood, I made life in the same room with it possible, and then, being exhausted, I had my wounds dressed, and went to bed.In the middle of the night my wife woke me up in a great state of alarm, to say that the clock had just struck thirteen, and who did I think was going to die?I said I did not know, but hoped it might be the next-door dog.My wife said she had a presentiment it meant baby. There was no comforting her; she cried herself to sleep again.During the course of the morning, I succeeded in persuading her that she must have made a mistake, and she consented to smile once more. In the afternoon the clock struck thirteen again.This renewed all her fears. She was convinced now that both baby and I were doomed, and that she would be left a childless widow. I triedto treat the matter as a joke, and this only made her more wretched. She said that she could see I really felt as she did, and was only pretending to be light-hearted for her sake, and she said she would try and bear it bravely.The person she chiefly blamed was Buggles.In the night the clock gave us another warning, and my wife accepted it for her Aunt Maria, and seemed resigned. She wished, however, that I had never had the clock, and wondered when, if ever, I should get cured of my absurd craze for filling the house with tomfoolery.The next day the clock struck thirteen four times and this cheered her up. She said that if we were all going to die, it did not so much matter. Most likely there was a fever or a plague coming, and we should all be taken together.She was quite light-hearted over it!After that the clock went on and killed every friend and relation we had, and then it started on the neighbors.It struck thirteen all day long for months, until we were sick of slaughter, and there could not have been a human being left alive for miles around.Then it turned over a new leaf, and gave up murdering folks, and took to striking mere harmless thirty-nines and forty-ones. Its favorite number now is thirty-two, but once a day it strikes forty-nine. It never strikes more than forty-nine. I don't know why--I have never been able to understand why--but it doesn't.It does not strike at regular intervals, but when it feels it wants to and would be better for it. Sometimes it strikes three or four times within the same hour, and at other times it will go for half-a-day without striking at all.He is an odd old fellow!I have thought now and then of having him "seen to," and made to keep regular hours and be respectable; but, somehow, I seem to have grown to love him as he is with his daring mockery of Time.He certainly has not much respect for it. He seems to go out of his way almost to openly insult it. He calls half-past two thirty-eight o'clock,Clocksand in twenty minutes from then he says it is one!Is it that he really has grown to feel contempt for his master, and wishes to show it? They say no man is a hero to his valet; may it be that even stony-face Time himself is but a short-lived, puny mortal--a little greater than some others, that is all--to the dim eyes of this old servant of his? Has be, ticking, ticking, all these years, come at last to see into the littleness of that Time that looms so great to our awed human eyes?Is he saying, as he grimly laughs, and strikes his thirty-fives and forties: "Bah! I know you, Time, godlike and dread though you seem. What are you but a phantom--a dream--like the rest of us here? Ay, less, for you will pass away and be no more. Fear him not, immortal men. Time is but the shadow of the world upon the background of Eternity!"11。

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Clocks(150字)
There are many clocks in the Brown’s house. They are in different rooms.A big clock stands in a corner of the sitting room. It is a very, very old clock, but it still keeps good time. Mr. Brown winds it once a week.
情感语录
1.爱情合适就好，不要委屈将就，只要随意，彼此之间不要太大压力
2.时间会把最正确的人带到你身边，在此之前，你要做的，是好好的照顾自己
3.女人的眼泪是最无用的液体，但你让女人流泪说明你很无用
4.总有一天，你会遇上那个人，陪你看日出，直到你的人生落幕
5.最美的感动是我以为人去楼空的时候你依然在
6.我莫名其妙的地笑了，原来只因为想到了你
7.会离开的都是废品，能抢走的都是垃圾
8.其实你不知道，如果可以，我愿意把整颗心都刻满你的名字
9.女人谁不愿意青春永驻，但我愿意用来换一个疼我的你
10.我们和好吧，我想和你拌嘴吵架，想闹小脾气，想为了你哭鼻子，我想你了
11.如此情深，却难以启齿。

其实你若真爱一个人，内心酸涩，反而会说不出话来
12.生命中有一些人与我们擦肩了，却来不及遇见；遇见了，却来不及相识；相识了，却来不及熟悉，却还要是再见
13.对自己好点，因为一辈子不长；对身边的人好点，因为下辈子不一定能遇见
14.世上总有一颗心在期待、呼唤着另一颗心
15.离开之后，我想你不要忘记一件事：不要忘记想念我。

想念我的时候，不要忘记我也在想念你
16.有一种缘分叫钟情，有一种感觉叫曾经拥有，有一种结局叫
命中注定，有一种心痛叫绵绵无期
17.冷战也好，委屈也罢，不管什么时候，只要你一句软话，一个微笑或者一个拥抱，我都能笑着原谅
18.不要等到秋天，才说春风曾经吹过;不要等到分别，才说彼此曾经爱过
19.从没想过，自己可以爱的这么卑微，卑微的只因为你的一句话就欣喜不已
20.当我为你掉眼泪时，你有没有心疼过。