EDA 技术实用教程 课后作业答案

作业3-6
module Mux3_1(a1,a2,a3,s0,s1,outy); input a1,a2,a3,s0,s1;
output outy;
reg outy;
reg temp;
always @(a2,a3,s0)
begin
if(s0 == 1'b0)
temp = a2;
else
temp = a3;
end
always @(a1, temp,s1)
begin
if(s1 == 1'b0)
outy = a1;
else
outy = temp;
end
endmodule
作业3-7 半减器
module H_suber(x,y,diff,s_out);
input x,y;
output diff,s_out;
reg s_out;
wire diff;
assign diff = x ^ y;
always @(x,y)
begin
if(x < y)
s_out = 1'b1;
else
s_out = 1'b0;
end
endmodule
全减器
module F_suber(x,y,sub_in,diffr,sub_out); input x,y,sub_in;
output diffr,sub_out;
wire diffr,sub_out;
wire H_diff,H_sout,s_out;
assign sub_out = s_out || H_sout;
H_suber U1 (.x(x),.y(y),.diff(H_diff),.s_out(H_sout));
H_suber U2 (.x(H_diff),.y(sub_in),.diff(diffr),.s_out(s_out));
Endmodule
8位全减器
module Bit8_suber(X,Y,Sub_in,Diff,Sub_out);
input[7:0] X,Y;
input Sub_in;
output[7:0] Diff;
output Sub_out;
wire[7:0] Diff;
wire Sub_out;
wire[6:0] sub_out;
F_suber U1(.x(X[0]),.y(Y[0]),.sub_in(Sub_in),.diffr(Diff[0]),.sub_out(sub_out[0]));
F_suber U2(.x(X[1]),.y(Y[1]),.sub_in(sub_out[0]),.diffr(Diff[1]),.sub_out(sub_out[1])); F_suber U3(.x(X[2]),.y(Y[2]),.sub_in(sub_out[1]),.diffr(Diff[2]),.sub_out(sub_out[2])); F_suber U4(.x(X[3]),.y(Y[3]),.sub_in(sub_out[2]),.diffr(Diff[3]),.sub_out(sub_out[3])); F_suber U5(.x(X[4]),.y(Y[4]),.sub_in(sub_out[3]),.diffr(Diff[4]),.sub_out(sub_out[4])); F_suber U6(.x(X[5]),.y(Y[5]),.sub_in(sub_out[4]),.diffr(Diff[5]),.sub_out(sub_out[5])); F_suber U7(.x(X[6]),.y(Y[6]),.sub_in(sub_out[5]),.diffr(Diff[6]),.sub_out(sub_out[6])); F_suber U8(.x(X[7]),.y(Y[7]),.sub_in(sub_out[6]),.diffr(Diff[7]),.sub_out(Sub_out)); Endmodule
作业3-13
A
module DFF_A(D,EN,CLK,RST,Q,Q1);
input D,EN,CLK,RST;
output Q,Q1;
reg Q;
wire Q1;
wire D_temp;
assign D_temp = D && EN;
assign Q1 = (~D_temp)||RST;
always @(negedge RST or posedge CLK)
begin
if(!RST)
Q <= 1'b0;
else
if(EN)
Q <= D;
else
Q <= Q;
endmodule
B
module DFF_B (A,B,C,D,Y);
input A,B,C,D;
output Y;
reg Y;
wire temp1,temp2,temp3;
assign temp1 = A || B;
assign temp2 = C && D;
assign temp3 = temp1 ^ temp2; always @(A,temp1,temp3)
begin
if(temp1)
Y = temp3;
else
Y = A;
end
endmodule
C
module DFF_C(RST,D,CLK,Q,DOUT); input RST,D,CLK;
output Q,DOUT;
reg Q,DOUT;
reg D_temp1;
wire D_temp2;
assign D_temp2 = D ^ D_temp1; always @(RST,D)
begin
if(RST)
D_temp1 = 1'b0;
else
D_temp1 = D;
end
always @(posedge CLK)
begin
Q <= D_temp1;
DOUT <= D_temp2;
endmodule
D
module DFF_D(SET,D,CLK,EN,RESET,Q);
input SET,D,CLK,EN,RESET;
output Q;
reg Q;
wire SET_temp;
assign SET_temp = (~RESET) && SET;
always @(posedge CLK or posedge RESET or posedge SET_temp) begin
if(RESET)
Q <= 1'b0;
else
if(SET_temp)
Q <= 1'b1;
else
if(EN)
Q <= D;
else
Q <= Q;
end
endmodule
8-2.用Mealy机类型，写出控制ADC0809采样的状态机。

module ADC0809(D,CLK,EOC,RST,ALE,START,OE,ADDA,Q,LOCK_T); input[7:0] D;
input CLK,RST;
input EOC;
output ALE;
output START,OE;
output ADDA,LOCK_T;
output[7:0] Q;
reg START,ALE, OE;
reg[4:0] cs;
reg[7:0] REGL;
reg LOCK;
parameter s0=0,s1=1,s2=2,s3=3,s4=4;
always @(posedge CLK or posedge RST) begin
if(RST) cs<=s0;
else begin
case(cs)
s0 : begin
START=0;ALE=0;OE=0;LOCK=0;
cs<=s1;
end
s1 : begin
START=1;ALE=1;OE=0;LOCK=0;
cs<=s2;
end
s2 : begin
START=0;ALE=0;OE=0;LOCK=0;
if(EOC==1’b1) cs<=s3;
else cs<=s2
end
s3 : begin
START=0;ALE=0;OE=1;LOCK=0;
cs<=s4;
end
s4 : begin
START=0;ALE=0;OE=1;LOCK=1;
cs<=s0;
end
default : begin
START=0;ALE=0;OE=0;LOCK=0;
cs<=s0;
end
endcase
end
end
always @(posedge LOCK)
if(LOCK) REGL<=D;
assign ADDA=0;
assign Q=REGL;
assign LOCK_T=LOCK;
endmodule
8-3.根据图8-31(a)所示的状态图，分别按照图8-31(b)和图8-31(c)写出对应结构的Verilog状态机。

并根据表8-2，分别用三种不同编码方式实现此二状态机，并讨论它们的容错措施。

(1)对(b)图：
module b(CLK,RESET,ina,outa)
input[2:0] ina;
input CLK,RESET;
output[3:0] outa;
reg[3:0] cs;
reg[3:0] outa;
parameter s0=0,s1=1,s2=2,s3=3;
always @(posedge CLK or posedge RESET) begin
if(RESET) cs<=s0;
else begin
case(cs)
s0 : begin
cs<=s1;
begin if(ina==3’b101) outa<=4’b0010;
else if(ina==3’b111) outa<=4’b1100;
end
end
s1 : begin
outa<=4’b1001;
begin if(ina==3’b000) cs<=s1;
else if(ina==3’b110) cs<=s2;
end
end
s2 : begin
outa<=4’b1111;
begin if(ina==3’b100) cs<=s2;
else if(ina==3’b011) cs<=s2;
else if(ina==3’b100) cs<=s3;
end
end
s3 : begin
begin if(ina==3’b101) outa<=4’b1101;
else if(ina==3’b011) outa<=4’b1110;
end
cs<=s0;
end
default : begin
cs<=s0;
begin if(ina==3’b101) outa<=4’b0010;
else if(ina==3’b111) outa<=4’b1100;
end
end
endcase
end
end
endmodule
(2)对(c)图：
module c(CLK,RESET,ina,outa)
input[2:0] ina;
input CLK,RESET;
output[3:0] outa;
reg[3:0] SIGNAL1,SIGNAL2;
reg[3:0] outa;
parameter s0=0,s1=1,s2=2,s3=3;
always @(posedge CLK or posedge RESET) begin if(RESET) SIGNAL2<=s0;
else SIGNAL2<=SIGNAL1;
end
always @(SIGNAL2 or ina) begin
case(SIGNAL2)
s0 : begin
SIGNAL1<=s1;
begin if(ina==3’b101) outa<=4’b0010;
else if(ina==3’b111) outa<=4’b1100;
end
end
s1 : begin
outa<=4’b1001;
begin if(ina==3’b000) SIGNAL1<=s1;
else if(ina==3’b110) SIGNAL1<=s2;
end
end
s2 : begin
outa<=4’b1111;
begin if(ina==3’b100) SIGNAL1<=s2;
else if(ina==3’b011) SIGNAL1<=s1;
else if(ina==3’b100) SIGNAL1<=s3;
end
end
s3 : begin
SIGNAL1<=s0;
begin if(ina==3’b101) outa<=4’b1101;
else if(ina==3’b011) outa<=4’b1110;
end
end
default : begin
SIGNAL1<=s0;
begin if(ina==3’b101) outa<=4’b0010;
else if(ina==3’b111) outa<=4’b1100;
end
end
endcase
end
endmodule。