HC123资料

TL F 5206MM54HC123A MM74HC123A Dual Retriggerable Monostable Multivibrator
January 1988
MM54HC123A MM74HC123A
Dual Retriggerable Monostable Multivibrator
General Description
The MM54 74HC123A high speed monostable multivibra-tors (one shots)utilize advanced silicon-gate CMOS tech-nology They feature speeds comparable to low power Schottky TTL circuitry while retaining the low power and high noise immunity characteristic of CMOS circuits
Each multivibrator features both a negative A and a posi-tive B transition triggered input either of which can be used as an inhibit input Also included is a clear input that when taken low resets the one shot The ’HC123can be triggered on the positive transition of the clear while A is held low and B is held high
The ’HC123A is retriggerable That is it may be triggered repeatedly while their outputs are generating a pulse and the pulse will be extended
Pulse width stability over a wide range of temperature and supply is achieved using linear CMOS techniques The out-put pulse equation is simply PW e (R EXT )(C EXT ) where PW is in seconds R is in ohms and C is in farads All inputs are protected from damage due to static discharge by diodes to V CC and ground
Features
Y Typical propagation delay 25ns Y Wide power supply range 2V–6V
Y Low quiescent current 80m A maximum (74HC Series)Y Low input current 1m A maximum Y Fanout of 10LS-TTL loads
Y Simple pulse width formula T e RC Y Wide pulse range 400ns to %(typ)Y Part to part variation g 5%(typ)
Y
Schmitt Trigger A B inputs enable infinite signal input rise and fall times
Connection Diagram
Dual-In-Line Package
TL F 5206–1
Top View
Order Number MM54HC123A or MM74HC123A
Timing Component
TL F 5206–2
Note Pin 6and Pin 14must be
hard-wired to GND
Truth Table
Inputs Outputs
Clear A B Q Q L X X L H X H X L H X X L
L H H L u
H
v
H
u
L
H
H e High Level L e Low Level
u e Transition from Low to High v e
Transition from High to Low
e One High Level Pulse
e One Low Level Pulse X e Irrelevant
C 1995National Semiconductor Corporation RRD-B30M105 Printed in U S A
Absolute Maximum Ratings(Notes1 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC)b0 5V to a7 0V DC Input Voltage(V IN)b1 5V to V CC a1 5V DC Output Voltage(V OUT)b0 5V to V CC a0 5V Clamp Diode Current(I IK I OK)g20mA DC Output Current per pin(I OUT)g25mA DC V CC or GND Current per pin(I CC)g50mA Storage Temperature Range(T STG)b65 C to a150 C Power Dissipation(P D)
(Note3)600mW S O Package only500mW Lead Temperature(T L)
(Soldering10seconds)260 C Operating Conditions
Min Max Units Supply Voltage V CC V DC Input or Output Voltage V CC V V IN V OUT
Operating Temp Range(T A)
MM HC b a C MM HC b a C Input Rise or Fall Times
(Clear Input)
V CC e V
t r t f ns V CC e V ns
V CC e V ns
DC Electrical Characteristics(Note4)
T A e25 C74HC54HC
Symbol Parameter Conditions V CC T A eb40to85 C T A eb55to125 C Units
Typ Guaranteed Limits
V IH Minimum High Level Input V V Voltage V V
V V V IL Maximum Low Level Input V V Voltage V V
V V V OH Minimum High Level V IN e V IH or V IL
Output Voltage l I OUT l s m A V V
V V
V V
V IN e V IH or V IL V
l I OUT l s mA V V
l I OUT l s mA V V V OL Maximum Low Level V IN e V IH or V IL
Output Voltage l I OUT l s m A V V
V V
V V
V IN e V IH or V IL V
l I OUT l s mA V V
l I OUT l s mA V V I IN Maximum Input Current V IN e V CC or GND V g g g m A
Pins
I IN Maximum Input Current V IN e V CC or GND V g g g m A
all other pins
I CC Maximum Quiescent Supply V IN e V CC or GND V m A
Current standby I OUT e m A
I CC Maximum Active Supply V IN e V CC or GND V m A
Current per R C EXT e V CC V mA monostable V mA Note1 Maximum Ratings are those values beyond which damage to the device may occur
Note2 Unless otherwise specified all voltages are referenced to ground
Note3 Power Dissipation Temperature Derating
Plastic‘‘N’’Package b12mW C from65 C to85 C
Ceramic‘‘J’’Package b12mW C from100 C to125 C
Note4 For a power supply of5V g10%the worst-case output voltages(V OH V OL)occur for HC at4 5V Thus the4 5V values should be used when designing with this supply Worst-case V IH and V IL occur at V CC e5 5V and4 5V respectively (The V IH value at5 5V is3 85V )The worst-case leakage current(I IN I CC and I OZ)occur for CMOS at the higher voltage and so the6 0V values should be used
2
AC Electrical Characteristics V CC e5V T A e25 C C L e15pF t r e t f e6ns Symbol Parameter Conditions Typ Limit Units
t PLH Maximum Trigger Propagation Delay ns
A B or Clear to Q
t PHL Maximum Trigger Propagation Delay ns
A B or Clear to Q
t PHL Maximum Propagation Delay Clear to Q ns t PLH Maximum Propagation Delay Clear to Q ns t W Minimum Pulse Width A B or Clear ns t REM Minimum Clear Removal Time ns
t WQ MIN Minimum Output Pulse Width C EXT e pF ns
R EXT e k X
t WQ Output Pulse Width C EXT e pF m s
R EXT e k X
AC Electrical Characteristics C L e50pF t r e t f e6ns(unless otherwise specified)
T A e25 C 74HC54HC
Symbol Parameter Conditions V CC T A eb40to85 C T A eb55to125 C Units
Typ Guaranteed Limits
t PLH Maximum Trigger Propagation V ns Delay A B or Clear to Q V ns
V ns t PHL Maximum Trigger Propagation V ns Delay A B or Clear to Q V ns
V ns t PHL Maximum Propagation Delay V ns Clear to Q V ns
V ns t PLH Maximum Propagation Delay V ns Clear to Q V ns
V ns t W Minimum Pulse Width V ns
A B Clear V ns
V ns t REM Minimum Clear V ns Removal Time V ns
V ns t TLH t THL Maximum Output V ns Rise and Fall Time V ns
V ns t WQ MIN Minimum Output C EXT e pF V m s Pulse Width R EXT e k X V ns
R EXT e k X V CC e V V ns t WQ Output Pulse Width C EXT e m F Min V ms
R EXT e k X Max V ms C IN Maximum Input pF
Capacitance Pins
C IN Maximum Input pF
Capacitance other inputs
C P
D Power Dissipation Note pF
Capacitance
Note5 C PD determines the no load dynamic power consumption P D e C PD V CC2f a I CC V CC and the no load dynamic current consumption I S e C PD V CC f a I CC
3
Logic Diagram
TL F 5206–5 Theory of Operation
TL F 5206–6 j POSITIVE EDGE TRIGGER m POSITIVE EDGE RE-TRIGGER(PULSE LENGTHENING)
k NEGATIVE EDGE TRIGGER n RESET PULSE SHORTENING
l POSITIVE EDGE TRIGGER o CLEAR TRIGGER
FIGURE1
TRIGGER OPERATION
As shown in Figure1and the logic diagram before an input trigger occurs the one shot is in the quiescent state with the Q output low and the timing capacitor C EXT completely charged to V CC When the trigger input A goes from V CC to GND(while inputs B and clear are held to V CC)a valid trig-ger is recognized which turns on comparator C1and N-
channel transistor N1j At the same time the output latch is set With transistor N1on the capacitor C EXT rapidly dis-charges toward GND until V REF1is reached At this point the output of comparator C1changes state and transistor N1turns off Comparator C1then turns off while at the same time comparator C2turns on With transistor N1off the capacitor C EXT begins to charge through the timing re-4
sistor R EXT toward V CC When the voltage across C EXT equals V REF2 comparator C2changes state causing the output latch to reset (Q goes low)while at the same time disabling comparator C2 This ends the timing cycle with the monostable in the quiescent state waiting for the next trig-ger
A valid trigger is also recognized when trigger input
B goes from GND to V C
C (while input A is at GN
D and input clear is at V CC k ) The ’HC123A can also be triggered when clear goes from GND to V CC (while A is at GND and B is at V CC o )
It should be noted that in the quiescent state C EXT is fully charged to V CC causing the current through resistor R EXT to be zero Both comparators are ‘‘off’’with the total device current due only to reverse junction leakages An added feature of the ’HC123A is that the output latch is set via the in-put trigger without regard to the capacitor voltage Thus prop-agation delay from trigger to Q is independent of the value of C EXT R EXT or the duty cycle of the input waveform RETRIGGER OPERATION
The ’HC123A is retriggered if a valid trigger occurs l fol-lowed by another trigger m before the Q output has re-turned to the quiescent (zero)state Any retrigger after the timing node voltage at the R C EXT pin has begun to rise from V REF1 but has not yet reached V REF2 will cause an increase in output pulse width T When a valid retrigger is initiated m the voltage at the R C EXT pin will again drop to V REF1before progressing along the RC charging curve
toward V CC The Q output will remain high until time T after the last valid retrigger
Because the trigger-control circuit flip-flop resets shortly af-ter C X has discharged to the reference voltage of the lower reference circuit the minimum retrigger time t rr is a function of internal propagation delays and the discharge time of C X
t rr 20a
187V CC b 0 7a 565a (0 256V CC )C X
V CC b 0 7 2Another removal retrigger time occurs when a short clear
pulse is used Upon receipt of a clear the one shot must charge the capacitor up to the upper trip point before the one shot is ready to receive the next trigger This time is dependent on the capacitor used and is approximately
t rr e 196a
640V CC b 0 7
a
522a (0 3V CC )C X
(V CC b 0 7)2
ns
RESET OPERATION
These one shots may be reset during the generation of the output pulse In the reset mode of operation an input pulse on clear sets the reset latch and causes the capacitor to be fast charged to V CC by turning on transistor Q1n When the voltage on the capacitor reaches V REF2 the reset latch will clear and then be ready to accept another pulse If the clear input is held low any trigger inputs that occur will be inhibited and the Q and Q outputs of the output latch will not change Since the Q output is reset when an input low level is detected on the Clear input the output pulse T can be made significantly shorter than the minimum pulse width specification
Typical Output Pulse Width vs Timing Components TL F 5206–7
Typical Distribution of Output Pulse Width Part to Part
TL F 5206–8Typical 1ms Pulse Width Variation vs Supply
TL F 5206–9
Minimum R EXT vs Supply Voltage TL F 5206–10Typical 1ms Pulse Width Variation vs Temperature
TL F 5206–11
Note R and C are not subjected to temperature The C is polypropylene
5
M M 54H C 123A M M 74H C 123A D u a l R e t r i g g e r a b l e M o n o s t a b l e M u l t i v i b r a t o r
Physical Dimensions inches (millimeters)
Dual-In-Line Package (J)
Order Number MM54HC123AJ or MM74HC123AJ
NS Package Number J16A
Dual-In-Line Package (N)Order Number MM74HC123AN NS Package Number N16E
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