多功能数字钟设计讲义

多功能数字钟设计
一、设计要求：
1、采用24小时制：时、分、秒计时、显示。

2、具有手动校准功能：分为时校准、分校准。

用1个拨码开关，2个按键控制：①设置开关set、分校准键adj_m_in、时校准键adj_h_in;
set=‘0’ and adj_m_in=‘0’时，分校准；
set=‘0’ and adj_h_in=‘0’时，时校准。

每当按下一次校准键时，时增1小时，分增1分钟。

②同正常计时用同一组计数器。

3、秒复位：只对秒复位，用一个按键（reset_in)控制。

4、闹钟功能：
①闹钟设置只控制时、分；与校时用相同的3个控制信号：
set=‘1’ and adj_m_in=‘0’时，分设置；set=‘1’ and adj_h_in=‘0’时，时设置。

②计时用另一组独立的计数器。

设有止闹控制，由止闹控制开关close实现。

5、整点报时：仿中央人民广播电台整点报时信号，从59分50秒起每两秒钟发出一次低音（512hz)“嘟”信号，持续半秒，响5次，最后一次高音（1024hz)“嘀”信号，持续半秒。

功能划分
输入输出信号端
输入信号：
Scanclk：时钟信号；实验箱提供最小时钟1.2Hz，计时实际需要1Hz, 程序中加有1024分
频，故scanclk频率约为1024Hz。

Set：设置键；设定闹表定时时、分；计时时、分校准；用拨码开关，拨上为定时，拨下为校准。

Reset_in：异步复为信号；只对秒计时复位。

adj_h_in,adj_m_in：时、分校准，闹钟定时控制
close：止闹信号；闹钟响后，close为1止闹；用实验箱的拨码开关。

输出信号：
scanout:：扫描信号；用于顺序点亮6个数码管。

（用1—6位）
led_out：七段数码管段码；高位为g。

sound_out：声音输出接喇叭或峰鸣器。

point_out：数码管间的点；隔两个数码管点亮一个。

功能描述
通用计数器：
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
ENTITY counter IS
GENERIC( count_value: INTEGER:=9);
PORT
(clk,clr,en: IN STD_LOGIC;
co : OUT STD_LOGIC;
count : OUT INTEGER RANGE 0 TO count_value);
END counter;
ARCHITECTURE a OF counter IS
SIGNAL cnt: INTEGER RANGE 0 TO count_value;
BEGIN
PROCESS (clk,clr)
BEGIN
IF clr = '1' THEN cnt <= 0;
ELSIF (clk'EVENT AND clk = '1') THEN
IF en = '1' THEN
IF cnt = count_value THEN cnt <= 0;
ELSE cnt <= cnt + 1;
END IF;
END IF;
END IF;
END PROCESS;
co<= '1' when cnt = count_value else '0';
count <= cnt;
END a;
数字钟的实体说明部分
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
entity TIMER is PORT(
scanclk,reset_in,adj_h_in,adj_m_in,set,close: in std_logic; led_out: out std_logic_vector(6 downto 0); scan_out: out integer range 0 to 5; sound_out: out std_logic; point_out: out std_logic ); end entity;
㈠时钟信号生成功能部分
signal clk1s: std_logic; --1s 计数时钟 signal cnt: std_logic_vector( 9 downto 0); signal dy : std_logic; --整点报时控制时钟 generat_1s_clock: PROCESS (scanclk) BEGIN IF (scanclk'EVENT AND scanclk = '1') THEN cnt <= cnt + 1; END IF; clk1s <= cnt(9); --scanclk 1024分频 END PROCESS;
PROCESS (clk1s,reset) BEGIN IF reset = '1' THEN dy<='0'; ELSIF (clk1s'EVENT AND clk1s = '1') THEN
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all;
entity TIMER is PORT(
scanclk,reset_in,adj_h_in,adj_m_in,set,close: in std_logic; led_out: out std_logic_vector(6 downto 0); scan_out: out integer range 0 to 5; sound_out: out std_logic; point_out: out std_logic ); end entity;
architecture rtl of TIMER is
Begin
dy <= not dy; --clk1s 2分频
END IF;
END PROCESS;
㈡计时功能（用元件例化语句实现）
㈡计时功能（用元件例化语句实现）
signal reset ,adj_h,adj_m: std_logic;
signal c_sh_en, c_ml_en, c_mh_en, c_h_en : std_logic;
signal c_h_en1, c_ml_en1 , c_mh_en1 : std_logic;
signal enable,disable: std_logic;
signal sl,c_ml: integer range 0 to 9;
signal c_mh, sh: integer range 0 to 5;
signal c_h: integer range 0 to 23;
component counter IS
GENERIC( count_value: INTEGER);
PORT
(clk,clr,en : IN STD_LOGIC;
co : OUT STD_LOGIC;
count : OUT INTEGER RANGE 0 TO count_value);
END component;
元件例化
reset<=not reset_in; --reset_in为按钮输入，通用计数器clr位‘1’状态有效
adj_m<=not adj_m_in;
adj_h<=not adj_h_in;
enable<='1';
disable<=‘0’; --用于不需要复位元件的clr端
c_ml_en <= (not set and adj_m) or (c_ml_en1 and c_sh_en);
c_mh_en <= (c_mh_en1 and c_ml_en);
c_h_en <= (not set and adj_h) or (c_sh_en and c_ml_en1 and c_mh_en1 and c_h_en1); CNT1S: counter
generic map( count_value => 9)
port map(clk=>clk1s,clr=>reset,en=>enable,co=>c_sh_en,count=>sl);
CNT10S: counter
generic map( count_value => 5)
port map(clk=>clk1s,clr=>reset,en=>c_sh_en,co=>c_ml_en1,count=>sh);
CNT1M: counter
generic map( count_value => 9)
port map(clk=>clk1s,clr=>disable,en=>c_ml_en,co=>c_mh_en1,count=>c_ml);
CNT10M: counter
generic map( count_value => 5)
port map(clk=>clk1s,clr=>disable,en=>c_mh_en,co=>c_h_en1,count=>c_mh);
CNT_H: counter
generic map( count_value => 23)
port map(clk=>clk1s,clr=>disable,en=>c_h_en,count=>c_h);
㈢闹表计时功能描述
signal s_ml_en , s_mh_en, s_h_en : std_logic; signal s_mh,: integer range 0 to 5; signal s_ml: integer range 0 to 9; signal s_h: integer range 0 to 23;
s_ml_en <= set and adj_m; s_h_en <= set and adj_h; SET1M: counter
generic map( count_value => 9)
port map(clk=>clk1s,clr=>disable,en=>s_ml_en,co=>s_mh_en,count=>s_ml); SET10M: counter
generic map( count_value => 5)
port map(clk=>clk1s,clr=>disable,en=>s_mh_en,count=>s_mh); SET_H: counter
generic map( count_value => 23)
port map(clk=>clk1s,clr=>disable,en=>s_h_en,count=>s_h);
㈣显示功能描述
clk1s
disable
Signal scan:integer range 0 to 5;
process (scanclk) begin
if scanclk'event and scanclk='1' then if scan = 5 then scan<=0; else scan <= scan + 1; end if; end if; end process;
Scan_out<= scan;
⒉多路选择器
signal hh ： integer range 0 to 2; Signal hl,ml,sl: integer range 0 to 9; signal sh,mh: integer range 0 to 5; signal h: integer range 0 to 23;
h<=c_h when set = '0' else s_h; hh<=1 when h>=10 and h<20 else 2 when h>=20 else
10h 1h 10M 1M 10s 1s
Scan= 0：sl
1：sh 2：ml 3：mh 4：hl 5：hh
0;
hl<=(h-0) when h<10 else
(h-10) when h>=10 and h<20 else
(h-20);
mh<=c_mh when set = '0' else s_mh;
ml<=c_ml when set = '0' else s_ml;
②时、分、秒去参加译码的选择Signal hex:integer range 0 to 10;
with scan select
hex<=hh when 5,
hl when 4,
mh when 3,
ml when 2,
sh when 1,
sl when others;
⒊七段显示译码signal led: STD_LOGIC_VECTOR (6 downto 0);
led_out<= NOT led;
with hex select
led<="1111001" when 1, --1
"0100100" when 2, --2
"0110000" when 3, --3
"0011001" when 4, --4
"0010010" when 5, --5
"0000010" when 6, --6
"1111000" when 7, --7
"0000000" when 8, --8
"0010000" when 9, --9
"1000000" when 0, --0
"1111111" when others;
⒋小数点显示
with scan select
point_out <='0' when 5,
clk1s when 4,
'0' when 3,
clk1s when 2,
'0' when 1,
'0' when others;
㈤报时、闹铃
signal sound,sound1,sound2,sound3: std_logic;
sound1 <= cnt(0) when s_ml=c_ml and s_mh=c_mh and s_h=c_h else '0';
--闹铃
sound2 <= scanclk when c_ml=0 and c_mh=0 and sh=0 and sl=0 and clk1s=‘1’ else ‘0’; ---整点报时（频率scanclk,持续时间半秒）
sound3 <= cnt(0) when c_ml=9 and c_mh=5 and sh=5 and dy=‘0’ and clk1s=‘1’ else ‘0’; ---59’ 50’’开始报时（频率610Hz,持续半秒）
sound<=sound1 or sound2 or sound3;
sound_out <= sound when close = '0' else '0';。