design_flow_pads

DEF File Cadence Silicon Ensemble DEF File Cadence ICFB Verilog Model Modelsim
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Standard Cell Placement
Standard Cell Routing Export to Other Formats, SPICE Verification Verilog Verification
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Introduction
• This tutorial will guide you through the synthesis of a fully placed-and-routed design from a VHDL entity. • The tutorial will use the following CAD tools: - Synopsys Design Compiler - Cadence Design Planner - Cadence Silicon Ensemble - Cadence ICFB - Modelsim QHDL
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Adding I/O Pads (Synopsys Design Compiler)
9. Using another script file (topchip_pads.script), we will add I/O Pads to the verilog netlist topchip_pads_int.v. 10. Type dc_shell –f topchip_pads.script 11. This will generate another verilog netlist file, topchip_pads.v, in the directory synopsys/gate.
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Major Changes in This Revision
• Added explanation for Display Options and Find forms. • Added section on „checking for shorts between VDD and GND‟ in the ICFB section.
Synopsys Design Compiler
• This tool will convert a VHDL model to a Verilog model. It requires the use of the following userprovided files: - Library file, in .db format. - Script file (file extension .script) - The VHDL file to be converted to Verilog. • At this stage, we will be using Design Compiler to generate a Verilog model, without pads, of a VHDL file called topchip_gold_pads.
Mississippi State University Dallas Semiconductor
VHDL to Place-and-Route Design Flow Tutorial
By: Wei Lii Tan Advisor: Dr. Robert Reese
This revision: October 30, 2001
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The Example Design
• The design we will be using as an example for this tutorial is a VHDL model of a Dallas Semiconductor DS1620k temperature sensing kit. • The interface reads the temperature from the DS1620k, then outputs the data to a sevensegment digit display. • The design also includes some simple gates for debugging, such as a NAND gate, NOR gate, inverter, and a DFF. • A simple counter is included in the design too.
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What is the .db file for?
• The database (.db) file holds information about the standard cell library used to implement the VHDL design. • It provides information about the standard cells: the names of the standard cells, input/output ports, as well as timing characteristics and functionality.
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Getting Rid of Unwanted Characters
6. Change to the synopsys/gate directory. 7. Run the perl script called myfilter.pl on the verilog netlist file, by typing: perl myfilter.pl topchip_pads_int.v 8. This will filter out all the unwanted characters from the netlist file.
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Why use a script file?
• Using a script file with dc_shell is equivalent to typing the exact commands in dc_shell interactively. • A script file automates the process of typing in all the commands manually.
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Design Flow
VHDL Model Synopsys Design Compiler VHDL -> Verilog Conversion Verilog Verification
Verilog Model
Modelsim Verilog Model
Cadence Design Planner
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Synopsys Design Compiler
• The VHDL file that we will be using is topchip_pads.vhd. • Using a script file with Design Compiler, we will convert this VHDL model to verilog. • The script file is called topchip_pads_int.script, and can be found in the synopsys/run_syn directory.
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Introduction
• The following conventions will be used in this tutorial: - File names will be in italics, e.g. /ccs/issl/micro/users/tan/myfile.vhd - User input (e.g. what you need to type) will be in boldface, e.g. type swsetup cadence-ncsu • It is highly recommended that you go through the „no pads‟ tutorial before you start on this one.
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Getting Rid of Unwanted Characters
• Cadence‟s family of CAD tools have strict rules about naming ports and nets. Therefore, we need to get rid of some unwanted symbols in our Verilog netlist, so that we won‟t run into problems further down the road, when using the Cadence Tools. • Symbols like front-slashes, back-slashes, and other numerical operators are not allowed in net names, if you are using Cadence tools.
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The Example Design
The main top-level signals in the design are: • inv_in, inv_out: input and output for simple inverter • nand2in_a, nand2in_b, nand2_out: inputs and output for simple NAND gate. • nor2in_a, nor2in_b, nor2_out: inputs and output for simple NOR gate. • _csb_6_ to _csb_0_: Signals for MSB of the seven-segment digit display. • _lsb_6_ to _lsb_0_: Signals for LSB of the sevensegment digit display.
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Copying Example Files
• Copy the entire directory /ccs/issl/micro/users/tan/tutorials/design_flow into your work directory • *important*All directories will start with your_work_directory/design_flow, unless specified otherwise.
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Design Compiler
1. 2. 3. 4. Change to the directory synopsys/run_syn Type swsetup synopsys Type dc_shell –f topchip_pads_int.script The „-f‟ option tells design compiler to use a script file, and not run in interactive mode. 5. After design compiler finishes (it should take about 5 minutes to finish the compilation), a verilog netlist file called topchip_pads.v should be created in the directory synopsis/gate.