第三章 EM78447单片机硬件结构概要

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ELAN EM78F811N 8位微控制器产品规格书说明书

产品规格书版本1.5义隆电子股份有限公司2021.07商标告之:IBM 为一个注册商标，PS/2是IBM 的商标之一。

Windows 是微软公司的商标。

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义隆电子股份有限公司总公司:地址: 30076新竹科学工业园区创新一路12号电话: +886 3 563-9977 传真: +886 3 563-9966 *****************.tw http :// 香港分公司:义隆电子(香港)股份有限公司地址:九龙观塘巧明街95号世达中心19楼A 室电话: +852 2723-3376 传真: +852 2723-7780美国:Elan InformationTechnology Group (U.S.A.) 地址: 10268 Bandley Drive Suite 101 , Cupertino , CA 95014,USA 电话: +1 408 366-8225 传真: +1 408 366-8225深圳分公司:义隆电子(深圳)有限公司地址:518057深圳市南山区高新技术产业园南区高新南六道迈科龙大厦8A电话: +86 755 2601-0565 传真: +86 755 2601-0500 ******************.cn上海分公司:义隆电子(上海)有限公司地址:上海市浦东新区盛荣路88弄3号703室(盛大天地源创谷内)电话：+86 21 5080-3866 ******************.cn目录目录1 综述 (1)2 特性 (1)3 引脚配置 (2)3.1 10-Pin MSOP (2)3.2 16-Pin DIP/SOP (2)3.3 14-Pin SOP (2)4 引脚描述 (3)5 系统概述 (5)5.1 内存图 (5)5.2 模块图 (6)6 功能描述 (7)6.1 操作寄存器 (7)6.1.1 R0:IAR (间接寻址寄存器) (7)6.1.2 R1 :TCC(定时器时钟) (7)6.1.3 R2:PC (程序计数器和堆栈) (7)6.1.4 R3 :SR(状态寄存器) (10)6.1.5 R4 :RSR(RAM选择寄存器) (10)6.1.6 Bank 0 R5 ~ R6, R8 (Port 5 ~ Port 6, Port 8) (10)6.1.7 Bank 0 R9:TBLP (指令TBRD表指针寄存器) (11)6.1.8 Bank 0 RA:WUPC (唤醒控制寄存器) (11)6.1.9 Bank 0 RB:EECR (EEPROM控制寄存器) (12)6.1.10 Bank 0 RC: EEPA (128 字节 EEPROM 地址) (12)6.1.11 Bank 0 RD: EEPD (128字节EEPROM 数据) (12)6.1.12 Bank 0 RE: OMCR (模式选择寄存器) (12)6.1.13 Bank 0 RF: ISR1 (中断状态寄存器 1) (15)6.1.14 R10 ~ R3F (15)6.1.15 Bank 1 R5~R7 (16)6.1.16 Bank 1 R8 (IRC 选择寄存器) (16)6.1.17 Bank 1 R9: TM1CR1 (定时器/计数器 1控制寄存器1) (16)6.1.18 Bank 1 RA: TM1CR2(定时器/计数器 1控制寄存器 2) (17)6.1.19 Bank 1 RB: TM1DAH (定时器/计数器 1数据缓冲A高字节) (18)6.1.20 Bank 1 RC: TM1DAL (定时器/计数器 1数据缓冲A低字节) (18)6.1.21 Bank 1 RD: TM1DBH (定时器/计数器 1数据缓冲B高字节) (18)6.1.22 Bank 1 RE: TM1DBL (定时器/计数器 1数据缓冲B低字节) (18)6.1.23 Bank 1 RF: ISR2 (中断状态寄存器 2) (19)6.1.24 Bank 2 R5:AISR (ADC输入选择寄存器) (19)6.1.25 Bank 2 R6: ADCON (A/D控制寄存器) (20)6.1.26 Bank 2 R7: ADCON2 (A/D控制寄存器2) (21)6.1.27 Bank 2 R8 : ADDH (AD高 8位数据缓存) (22)6.1.28 Bank 2 R9 : ADDL (AD低4位数据缓存) (22)6.1.29 Bank 2 RA: URCR (UART控制寄存器) (22)6.1.30 Bank 2 RB: URS (UART 状态寄存器) (23)6.1.31 Bank 2 RC: URTD (UART 发送数据缓冲寄存器) (24)6.1.32 Bank 2 RD: URRDL (UART 接收数据低位缓冲寄存器) (24)目录6.1.33 Bank 2 RE: URRDH (UART 接收数据高位缓冲寄存器) (24)6.1.34 Bank 2 RF (24)6.1.35 Bank 3 R5 (24)6.1.36 Bank 3 R6 : TBHP(指令TBRD的表指针寄存器) (24)6.1.37 Bank 3 R7: CMP2CON(比较器2控制寄存器) (25)6.1.38 Bank 3 R8 ~ RC (25)6.1.39 Bank 3 RD :TC3CR (定时器3控制) (25)6.1.40 Bank 3 RE :TC3D (定时器 3 数据缓存) (27)6.1.41 Bank 3 RF (27)6.2 特殊功能寄存器 (28)6.2.1 A (累加器) (28)6.2.2 CONT (控制寄存器) (28)6.2.3 IOC5 ~ IOC6, IOC8 (I/O端口控制寄存器) (28)6.2.4 IOC7, IOC9 (28)6.2.5 IOCA:WDTCR (WDT 控制寄存器) (29)6.2.6 IOCB: P6PDCR (下拉控制寄存器2) (29)6.2.7 IOCC: P6ODCR (漏极开路控制寄存器) (30)6.2.8 IOCD: P9PHCR (上拉控制寄存器2) (30)6.2.9 IOCE:IMR2 (中断屏蔽寄存器2) (31)6.2.10 IOCF: IMR1(中断屏蔽寄存器1) (31)6.3 TCC/WDT 与预分频器 (33)6.4 I/O 端口 (34)6.4.1 使用端口6输入状态改变唤醒/中断功能 (36)6.5 复位和唤醒 (37)6.5.1 复位 (37)6.5.2 总结唤醒和中断模式操作 (39)6.5.3 寄存器初始值的总结 (42)6.5.4 状态寄存器的T和P状态 (49)6.6 中断 (50)6.7 数据EEPROM (52)6.7.1 数据EEPROM控制寄存器 (52)6.7.2 编程步骤 / 举例示范 (52)6.8 模拟数字转换器(ADC) (53)6.8.1 A/D 取样时间 (53)6.8.2 A/D 转换时间 (54)6.8.3 睡眠期间的A/D转换 (54)6.8.4 编程步骤/注意事项 (55)6.9 定时器/计数器1 (TM1) (58)6.9.1 定时器/计数器模式 (58)6.9.2 窗口模式 (59)6.9.3 捕捉模式 (60)6.9.4 可编程分频输出模式和脉冲宽度调制模式 (62)6.9.5 蜂鸣器 (63)6.10 定时器/计数器3 (63)6.11 UART (65)6.11.1 UART 模式 (66)6.11.2 发送 (67)目录6.11.3 接收 (67)6.11.4 波特率发生器 (68)6.11 .5 UART 时序 (68)6.12 比较器 (69)6.12.1 外部参考信号 (69)6.12.2 内部参考电压 (70)6.12.3 比较器输出 (70)6.12.4 中断 (70)6.12.5 从睡眠至唤醒 (70)6.12.6 比较器初始化步骤 (71)6.13 振荡器 (71)6.13.1 振荡模式 (71)6.13.2 晶振 / 陶瓷谐振器(晶体) (72)6.13.3 外部RC振荡模式 (73)6.13.4 内部 RC 振荡模式 (74)6.14 代码选项寄存器 (75)6.14.1 代码选项寄存器 (Word 0) (75)6.14.2 代码选项寄存器(Word 1) (77)6.14.3 客户ID寄存器(Word 2) (78)6.15 上电注意事项 (79)6.16 外部上电复位电路 (79)6.17 残留电压保护 (80)6.18 指令集 (81)7片上调试系统(OCDS) (84)7.1 片上调试的限制 (84)8 时序图 (85)9 绝对最大额定参数 (86)10 DC电气特性 (87)11 AC电气特性 (92)A 编码与制造信息 (93)B 封装类型 (94)C 封装结构 (95)C.1 EM78F811NMS10 (95)C.2 EM78F811NSO14 (96)C.3 EM78F811NAD16 (97)C.4 EM78F811NASO16A (98)D 品质保证和可靠性 (99)D.1 地址缺陷检测 (99)目录规格修订历史目录用户应用注意事项(使用此IC前，应注意如下描述的注意事项，它包含重要信息)1. 如果IRC频率从A频率变为B频率，MCU需要等待一些时间才可以工作。

北台湾科学技术学院电子系.

指令週期
2 1 or 2 1 or 2 1 1 1 1 1 1
PC (Page,k) A R + 1 skip if zero R R + 1 skip if zero A K A R R A R R
北台湾科學技術學院電子系
EM78447S 指令集
指
OR OR RET RETI RETL RLCA RLC K K R R
令
動
WDT 0 A A K A A R R A R
作
旗標影響
Z,C,DC T,P Z Z Z
ROM 13bit
512
RAM 8bit
11
I/O Pins
32
INT (E/I)
3 (1/2) 3 (1/2) 2 (1/1) 3 (1/2) 3 (1/2) 6 (1/5)
SPI 一 AD 一
Timer 8-bit
1
WDT
Pin No
14
Special Functio n
一
EM78P153
YES
一
一一 SPI AD, PWM
WDT 一 Watch Dog Timer OTP 一 One Time Programming. PWM 一 Pulse Width Modulation
Serial Peripheral Interface. Analog to Digit Converter.
PAGE 1-5
旗標影響
Z,C,DC Z,C,DC Z,C,DC Z Z Z
指令週期
1 1 1 1 1 1
BC
BS CALL
R,b
R,b k
R(b) 0

EMC系列单片机原理及应用技术

第一章 EM78系列单片机简介台湾义隆公司推出的八位EM78系列单片机已有多年，并广泛应用在家用电器、工业控制、仪器等方面，其优良的单片机结构和性能为用户所认同，但与AT89系列、PIC系列、Z86系列、GMS97系列等单片机比较而言，EM78系列单片机进入内地市场稍晚一些，所以一般人并不太了解。

本章将对EM78系列单片机的主要特点作一个概述，供大家参考（以EM78X56为例）。

第一章一、先进的单片机结构EM78系列单片机将众多功能集于一身，这其中包括ALU、ROM、RAM、I/O、堆栈、中断控制器、定时/计数器、看门狗、电压检测器、复位电路、振荡电路等，成为真正意义上的单片机小系统。

第二章二、优越的数据处理性能EM78系列单片机采用RISC结构设计、单周期、单字节及流水线指令、五级堆栈、RAM 数量从32~157个，最短指令周期100ns，程序页面为1K（多至4页），与其它一些单片机相比，EM78系列单片机具有更高、更快的运行处理速度。

第三章三、强大的单片机新功能这包括：①①三个中断源：定时器中断、I/O唤醒中断、外部信号输入中断②②R-OPTION功能：如果用户程序有几个版本，希望能放在同一ROM内，则通过R-OPTION功能便可实现此想法，R-OPTION功能设置是在相关I/O上上拉或下拉电阻，通过判断相关I/O的状态来选择执行内部何种版本程序。

③③内置电压检测器：当电源电压掉在一额定值以下时单片机始终处于复位状态，以此提高系统的复位性能。

④④低功耗设计：正常工作电流2mA、休眠状态电流1μA⑤⑤多功能I/O口：可程序设置为I/O上拉、下拉、开路等方式⑥⑥I/O唤醒功能：通过I/O变化唤醒处于休眠状态的单片机⑦⑦内置看门狗定时器：提高单片机抗干扰能力第四章四、灵活的功能选择设计通过软件分别设置：①①指令周期的时钟周期数（2/4）②②特殊指令的指令周期数（1/2）③③振荡方式（内部RC、外部RC 、XTAL低频、XTAL高频等）④④R-OPTION功能开/关⑤⑤WDT开/关第五章五、通俗易懂的指令系统EM78系列单片机指令系统采用与大家熟知的MCS-51指令风格设计，共计58条指令，大家通过较短的时间便能掌握运用。

EM78P447S单片机入门与实作系列讲座——第8讲 SIM447的系统命令(上)

应用举例：将卜进制数０Ｈ转换六Ｆ
成二进制数００１Ｉ００１１Ｂ。
＞Ｂ０ＦＯ（）ＨｌｌＦ：Ｘ０Ｄｌｌ
应用举例：下面第１命令将使模条
拟器执行０ＲＭ单元中的一条指令后号Ｏ
时，均町以用标号代替地址
动时，会在命令会话则区看到提示信息：
ｓｏｅｅａｄｕｓｃｐＤｌｙＡｊｔ
Ｆ３Ｆ３
ｏＩＳＨＩＰＴＣＨ１－３
行被打断之处继续连续执行；果命令中如给出两个分别作为起始点和停止点的地
命令格式：Ｔ【址】地
功能说明：单步执行。当程序执行过程中遇到指令ＣＬ时，会进入子程序ＡＬ仍然以单步方式继续执行，其余同于Ｐ命令：ＳＭ４Ｉ４７系统为该命令定义了一个
快捷键｛７。Ｆ）
６ＤＹ．ＳＭ— — 符号查错功能关闭命令
暂停；第２条命令将执行５号单元中的
一
命令格式：ＤＹＳＭ功能说明：在调试过程中关闭符号
化调试功能。与命令ＥＹ的功能恰好ＳＭ
相反。
９Ｍ． —— 特定寄存器修改命令
２Ｇ． —— 连续执行命令
键被按动一次或两次时，会在命令会话则区看到提示信息：Ｎ＝＞ＨＧ或ＩＴＩＨ

台湾义隆单片机硬件结构

第二章 EM78系列单片机硬件结构EM78系列单片机是采用低功耗、高速CMOS工艺制造的8位单片机，本章将以EM78X56（包括EM78156、EM78256、EM78456）为例来讲述EM78系列单片机的内部结构、存贮器、中断、I/O、看门狗、振荡器和电压检测器等特点。

2.1. 主要功能特点·采用8位数据总线和13位指令总线独立分离的Harvard结构设计。

·采用RISC指令集，共有57条单字节指令，其中99%为单周期指令（对程序计数器PC指针进行写操作除外）。

·1K～4KX13的程序存贮器（有OTP和掩膜二个版本）。

·48个通用数据寄存器可直接寻址使用。

·14个特殊功能寄存器。

·具有一个结构选择寄存器用于设置振荡器的工作方式等。

·具有五级堆栈令程序嵌套更自由。

·两个双向三态I/O口，12个I/O线，可分别设置为上拉、下拉或集电极开路等。

·具有三个硬件中断和一个软件中断。

·两种工作模式：正常工作模式 2mA/5V休眠模式 1μA/5V(可由I/O唤醒)·具有R-OPTION功能，即用电阻的上拉、下拉来选择内部程序的执行。

·一个带8位预置器的8位定时/计数器，一个看门狗定时器（WDT）。

·采用先进的加密方法保证用户代码不被读出。

·工作电压：2.5～5.5V 工作频率DC～36MHZ、工作温度0℃～70℃。

2.2. EM78X56型号分类、命名方法及管脚功能说明2.2.1. 型号分类(表2.1)：2.2.2. 命名方法:EM 78 P 156 A P封装形式P-DIP M-SOIC S-SSOP内置电压检测功能 A-有 B-无类型名P：OTP；没有“P”为MASK版本单片机系列号EMC公司字头2.2.3. EM78X56管脚功能描述图2.1 EM78156管脚图(EM78256和EM78456管脚同上)2.3. EM78内部结构框图EM78X56在片内集成了一个8位算术运算单元ALU和工作寄存器ACC、1K～4KROM、56个RAM、12个I/O口，8位预置器（Prescaler）及8位计数器（TCC）、振荡器、看门狗、五级堆栈、中断控制器、指令寄存器、译码器和其它一些寄存器等。

EM78系列单片机硬件结构

2.2.1. 型号分类(表 2.1)：
型号 EM78156 EM78256 EM78456
ROM（Bit）
RAM（Byte）
I/O
1KX13
56
12
2KX13
56
12
4KX13
56
12
2.2.2. 命名方法:
EM 78 P 156 A P
最短指令周期 111ns 111ns 111ns
第3页
封装形式 P-DIP M-SOIC 内置电压检测功能 A-有类型名
第二章 EM78 系列单片机硬件结构
武汉威帆 (027)87644346
第二章 EM78 系列单片机硬件结构
EM78 系列单片机是采用低功耗、高速 CMOS 工艺制造的 8 位单片机，本章将以 EM78X56 （包括 EM78156、EM78256、EM78456）为例来讲述 EM78 系列单片机的内部结构、存贮器、中断、I/O、看门狗、振荡器和电压检测器等特点。
2.1. 主要功能特点
·采用 8 位数据总线和 13 位指令总线独立分离的 Harvard 结构设计。
·采用 RISC 指令集，共有 57 条单字节指令，其中 99%为单周期指令（对程序计数器
PC 指针进行写操作除外）。
·1K～4KX13 的程序存贮器（有 OTP 和掩膜二个版本）。
·48 个通用数据寄存器可直接寻址使用。
S-SSOP B-无
P：OTP；没有“P”为 MASK 版本单片机系列号
EMC 公司字头
第二章 EM78 系列单片机硬件结构
武汉威帆 (027)87644346
2.2.3. EM78X56 管脚功能描述
图 2.1 EM78156 管脚图(EM78256 和 EM78456 管脚同上)

EM78指令说明

总线技术
串口基础
串口编程
电力线通信
蓝牙技术
Modem技术
2. AND 与
语法AND A，R
编码0 0010 10rr rrrr
操作A&R®A
对标志位影响Z
说明无
举例P6口和R10寄存器相与，结果输出至P6口：
综合技术
|
计算机应用
|
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操作A+K®A
对标志位影响Z，C，DC
说明无
举例实现A=0X01+0X01：
MOV A，@0X01
ADD A，@0X01
充电器设计
电池
另类电源
变压器
稳压技术
广电技术
安防监控
AGAIN：
CLR 0
INC 0X04
MOV A, 0X04
XOR A, 0X3F
JBS 0X03, 2
JMP AGAIN
END：
2.4. 位寻址
ADD Reg_B, A ； add Reg_B with A, and
； save in Reg_B
... 等等。
(3)位操作型指令（ bit oriented ）：如
BC，JBS...等等。
EM78指令说明【字体：小大】
EM78指令说明
作者：程序匠人文章来源：不详点击数：1156 更新时间：2004-11-26

EM78P447

OTP ROMEM78P447S8-BIT MICRO-CONTROLLERVersion 1.2OTP ROMSpecification Revision HistoryVersion Content1.0 Initialversion1.1 Change Power on reset content 06/25/20031.2 Add the device characteristic at section 6.3 5/11/2004 Application NoteAN-001: Seven-segment and I/O PortAN-002: Keystroke Times Displayed by Seven-segmentAN-003: Jumping out of DELAY Subroutine Loop by External KeystrokeAN-004: LED with Controlled Rotating DirectionAN-005: Sing a Song "Draw" of EM78447AN-006: Stepping MotorAN-007: EM78P447S v.s. EM78P447 on the DC characteristics and program timingAN-008: About EM78P447S Sleep2 mode settingEM78P447S is an 8-bit microprocessor with low-power and high-speed CMOS technology. It is equipped with 4K*13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides a PROTECTION bit to prevent user’s code in the OTP memory from being intruded. Seven OPTION bits are also available to meet user’s requirements.With its OTP-ROM feature, the EM78P447S is able to offer a convenient way of developing and verifying user’s programs. Moreover, user can take advantage of ELAN Writer to easily program his developmentcode.OTP ROM 2. FEATURES• Operating voltage range: 2.3V~5.5V.• Operating temperature range: 0°C~70°C.• Operating frequency range( base on 2 clocks)* Crystal mode: DC~20MHz at 5V, DC~8MHz at 3V, DC~4MHz at 2.3V.* RC mode: DC~4MHz at 5V, DC~4MHz at 3V, DC~4MHz at 2.3V.• Low power consumption:* Less then 2.2 mA at 5V/4MHz* Typically 30 µA, at 3V/32KHz* Typically 1 µA, during sleep mode• 4K × 13 bits on chip ROM• One security register to prevent intrusion of OTP memory codes• One configuration register to accommodate user’s requirements• 148× 8 bits on chip registers(SRAM, general purpose register)• 3 bi-directional I/O ports• 5 level stacks for subroutine nesting• 8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt• Two clocks per instruction cycle• Power down (SLEEP) mode• Two available interruptions* TCC overflow interrupt* External interrupt• Programmable free running watchdog timer• 10 programmable pull-high pins• 2 programmable open-drain pins• 2 programmable R-option pins• Package types:* 28 pin DIP 600 mil : EM78P447SAP* 28 pin SOP (SOIC) 300 mil : EM78P447SAM* 28 pin SSOP 209 mil : EM78P447SAS* 32 pin DIP 600 mil : EM78P447SBP* 32 pin SOP (SOIC) 450 mil : EM78P447SBWM• The transient point of system frequency between HXT and LXT is around 400KHzOTP ROM3. PIN ASSIGNMENTTCC VDD NC Vss /INT P50P51P53P60P61P62P63P64P52/RESET OSCI OSCO P77P76P75P74P72P71P70P67P66P65P73P55P54P56P57TCC VDD NC Vss /INT P50P51P53P60P61P62P63P64P52/RESET OSCI OSCO P77P76P75P74P72P71P70P67P66P65P73TCC VDD Vss /INT P50P51P53P60P61P62P63P64P52/RESET OSCI OSCO P77P76P75P74P72P71P70P67P66P65P73VssFig. 1 Pin AssignmentTable 1 EM78P447SAP and EM78P447SAM Pin DescriptionSymbol Pin No. TypeFunctionVDD 2-* Power supply.OSCI 27 I* XTAL type: Crystal input terminal or external clock input pin.* RC type: RC oscillator input pin.OSCO 26 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.* RC type: Instruction clock output.* External clock signal input.TCC 1 I* The real time clock/counter (with Schmitt trigger input pin) must be tied toVDD or VSS if not in use./RESET 28 I* Input pin with Schmitt trigger. If this pin remains at logic low, the controllerwill also remain in reset condition.P50~P53 6~9 I/O * P50~P53 are bi-directional I/O pins.P60~P67 10~17 I/O* P60~P67 are bi-directional I/O pins. These can be pulled-high internallyby software control.P70~P77 18~25 I/O* P70~P77 are bi-directional I/O pins.* P74~P75 can be pulled-high internally by software control.* P76~P77 can have open-drain output by software control. * P70 and P71 can also be defined as the R-option pins./INT 5 I * External interrupt pin triggered by falling edge. VSS 4 - * Ground. NC 3 - * No connection.OTP ROMTable 2 EM78P447SAS Pin DescriptionSymbol Pin No. TypeFunctionVDD 3-* Power supply.OSCI 27 I* XTAL type: Crystal input terminal or external clock input pin.* RC type: RC oscillator input pin.OSCO 26 I/O * XTAL type: Output terminal for crystal oscillator or external clock input pin.* RC type: Instruction clock output.* External clock signal input.TCC 2 I* The real time clock/counter (with Schmitt trigger input pin) must be tied toVDD or VSS if not in use./RESET 28 I* Input pin with Schmitt trigger. If this pin remains at logic low, the controllerwill also remain in reset condition.P50~P53 5~8 I/O * P50~P53 are bi-directional I/O pins.P60~P679~13,15~17I/O * P60~P67 are bi-directional I/O pins. These can be pulled -high internally by software control. P70~P77 18~25 I/O* P70~P77 are bi-directional I/O pins.* P74~P75 can be pulled -high internally by software control.* P76~P77 can have open-drain output by software control. * P70 and P71 can also be defined as the R-option pins./INT 4 I * External interrupt pin triggered by falling edge. VSS 1,14 - * Ground.Table 3 EM78P447SBP and EM78P447SBWM Pin DescriptionSymbol Pin No.Type FunctionVDD4 -* Power supply.OSCI 29 I* XTAL type: Crystal input terminal or external clock input pin.* RC type: RC oscillator input pin.OSCO 28 I/O* XTAL type: Output terminal for crystal oscillator or external clock input pin.* RC type: Instruction clock output. * External clock signal input.TCC 3 I* The real time clock/counter (with Schmitt trigger input pin), must be tiedto VDD or VSS if not in use./RESET 30 I* Input pin with Schmitt trigger. If this pin remains at logic low, the controllerwill keep in reset condition.P50~P57 8~11,2~1,32~31I/O * P50~P57 are bi-directional I/O pins.P60~P67 12~19 I/O* P60~P67 are bi-directional I/O pins. These can be pulled -high internallyby software control.P70~P77 20~27 I/O* P70~P77 are bi-directional I/O pins.* P74~P75 can be pulled-high internally by software control.* P76~P77 can have open-drain output by software control. * P70 and P71 can also be defined as the R-option pins./INT 7 I * External interrupt pin triggered by falling edge. VSS 6 - * Ground. NC 5 - * No connection.OTP ROM4. FUNCTION DESCRIPTIONP 50P 51P 52P 53P 54P 55P 56P 57P 60P 61P 62P 63P 64P 65P 66P 67P 70P 71P 72P 73P 74P 75P 76P 77Fig. 2 Functional Block Diagram4.1 Operational Registers1. R0 (Indirect Addressing Register)R0 is not a physically implemented register. Its major function is to act as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4).2. R1 (Time Clock /Counter)• Increased by an external signal edge, which is defined by TE bit (CONT-4) through the TCC pin, or by the instruction cycle clock.• Writable and readable as any other registers. • Defined by resetting PAB (CONT-3).• The prescaler is assigned to TCC, if the PAB bit (CONT-3) is reset.• The contents of the prescaler counter will be cleared only when TCC register is written a value.OTP ROM3. R2 (Program Counter) & Stack• Depending on the device type, R2 and hardware stack are 10-bit wide. The structure is depicted in Fig.3.• Generating 1024×13 bits on-chip OTP ROM addresses to the relative programming instruction codes. One program page is 1024 words long.• R2 is set as all "0"s when under RESET condition.• "JMP" instruction allows direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to go to any location within a page.• "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed into the stack. Thus, the subroutine entry address can be located anywhere within a page.• "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top-level stack.• "ADD R2,A" allows the contents of ‘A’ to be added to the current PC, and the ninth and tenth bits of the PC are cleared.• "MOV R2,A" allows to load an address from the "A" register to the lower 8 bits of the PC, and the ninth and tenth bits of the PC are cleared.• Any instruction that writes to R2 (e.g. "ADD R2,A", "MOV R2,A", "BC R2,6",⋅⋅⋅⋅⋅) will cause the ninth and tenth bits (A8~A9) of the PC to be cleared. Thus, the computed jump is limited to the first 256 locations of a page.• All instruction are single instruction cycle (fclk/2 or fclk/4) except for the instruction that would change the contents of R2. Such instruction will need one more instruction cycle.000H FFFH001H User Memory 002HFig. 3 Program Counter OrganizationOTP ROMFig. 4 Data Memory ConfigurationOTP ROM4. R3 (Status Register)7 6 5 4 3 2 1 0GP PS1 PS0 T P Z DC C • Bit 7 (GP) General read/write bit.• Bits 6 (PS1) ~ 5 (PS0) Page select bits. PS1~PS0 are used to pre-select a program memory page.When executing a "JMP", "CALL", or other instructions which causes the program counter to change(e.g. MOV R2, A), PS1~PS0 are loaded into the 11th and 12th bits of the program counter and selectone of the available program memory pages. Note that RET (RETL, RETI) instruction does not change the PS0~PS1 bits. That is, the return will always be to the page from where the subroutine was called, regardless of the PS1~PS0 bits current setting.PS1 PS0 Program memory page [Address]0 0 Page 0 [000-3FF]0 1 Page 1 [400-7FF]1 0 Page2 [800-BFF]1 1 Page 3 [C00-FFF]• Bit 4 (T) Time-out bit. Set to 1 with the "SLEP" and "WDTC" commands, or during power up, and reset to 0 with the WDT time-out.• Bit 3 (P) Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command.• Bit 2 (Z) Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero.• Bit 1 (DC) Auxiliary carry flag.• Bit 0 (C) Carry flag5. R4 (RAM Select Register)• Bits 7~6 determine which bank is activated among the 4 banks.• Bits 5~0 are used to select the registers (address: 00~3F) in the indirect addressing mode.• If no indirect addressing is used, the RSR can be used as an 8-bit general-purpose read/writer register.• See the configuration of the data memory in Fig. 4.6. R5~R7 (Port 5 ~ Port7)• R5, R6 and R7 are I/O registers7. R8~R1F and R20~R3E (General Purpose Register)• R8~R1F, and R20~R3E (including Banks 0~3) are general-purpose registers.OTP ROM8. R3F (Interrupt Status Register)Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0- - - - EXIF - - TCIF • Bit 3 (EXIF) External interrupt flag. Set by falling edge on /INT pin, flag cleared by software• Bit 0 (TCIF) the TCC overflow interrupt flag. Set as TCC overflows; flag cleared by software.• Bits 1, 2, 4~7 are not used and read are as “0”.• "1" means interrupt request, "0" means non-interrupt.• R3F can be cleared by instruction, but cannot be set by instruction.• IOCF is the interrupt mask register.• Note that reading R3F will obtain the result of the R3F "logic AND" and IOCF.4.2 Special Purpose Registers1. A (Accumulator)• Internal data transfer, or instruction operand holding.• It cannot be addressed.2. CONT (Control Register)7 6 5 4 3 2 1 0/PHEN /INT TS TE PAB PSR2 PSR1 PSR0 • Bit 7 (/PHEN) Control bit used to enable the pull-high of P60~P67, P74 and P75 pins0: Enable internal pull-high.1: Disable internal pull-high.• CONT register is both readable and writable.• Bit 6 (/INT) Interrupt enable flag0: masked by DISI or hardware interrupt1: enabled by ENI/RETI instructions• Bit 5 (TS) TCC signal source0: internal instruction cycle clock1: transition on TCC pin• Bit 4 (TE) TCC signal edge0: increment if the transition from low to high takes place on TCC pin1: increment if the transition from high to low takes place on TCC pin• Bit 3 (PAB) Prescaler assignment bit.OTP ROM0: TCC1: WDT•Bit 2 (PSR2) ~ Bit 0 (PSR0)TCC/WDT prescaler bits.PSR2 PSR1PSR0 TCC Rate WDT Rate0 0 0 1:2 1:10 0 1 1:4 1:20 1 0 1:8 1:40 1 1 1:16 1:81 0 0 1:32 1:161 0 1 1:64 1:321 1 0 1:128 1:641 1 1 1:256 1:1283. IOC5 ~ IOC7 (I/O Port Control Register)• "1" put the relative I/O pin into high impedance, while "0" defines the relative I/O pin as output.• IOC5 and IOC7 registers are both readable and writable.4. IOCB (Wake-up Control Register for Port6)7 6 5 4 3 2 1 0/WUE7 /WUE6 /WUE5 /WUE4 /WUE3 /WUE2 /WUE1 /WUE0 • Bit 7 (/WUE7) Control bit is used to enable the wake-up function of P67 pin.• Bit 6 (/WUE6) Control bit is used to enable the wake-up function of P66 pin.• Bit 5 (/WUE5) Control bit is used to enable the wake-up function of P65 pin.• Bit 4 (/WUE4) Control bit is used to enable the wake-up function of P64 pin.• Bit 3 (/WUE3) Control bit is used to enable the wake-up function of P63 pin.• Bit 2 (/WUE2) Control bit is used to enable the wake-up function of P62 pin.• Bit 1 (/WUE1) Control bit is used to enable the wake-up function of P61 pin.• Bit 0 (/WUE0) Control bit is used to enable the wake-up function of P60 pin.0: Enable internal wake-up.1: Disable internal wake-up.• IOCB Register is both readable and writable.5. IOCE (WDT Control Register)7 6 5 4 3 2 1 0SLPCROC - - /WUEWDTE- ODE• Bit 6 (ODE) Control bit is used to enable the open-drain of P76 and P77 pins0: Disable open-drain output.OTP ROM1: Enable open-drain output.The ODE bit can be read and written.• Bit 5 (WDTE) Control bit used to enable Watchdog timer.The WDTE bit is useful only when ENWDT, the CODE Option bit, is "0". It is only when the ENWDT bit is "0" that WDTE bit. is able to disabled/enabled the WDT.0: Disable WDT.1: Enable WDT.The WDTE bit is not used if ENWDT, the CODE Option bit ENWDT, is "1". That is, if the ENWDT bit is "1", WDT is always disabled no matter what the WDTE bit status is.The WDTE bit can be read and written.• Bit 4 (SLPC) This bit is set by hardware at the low level trigger of wake-up signal and is cleared by software. SLPC is used to control the oscillator operation. The oscillator is disabled (oscillator is stopped, and the controller enters into SLEEP2 mode) on the high-to-low transition and is enabled (controller is awakened from SLEEP2 mode) on low-to-high transition. In order to ensure the stable output of the oscillator, once the oscillator is enabled again, there is a delay for approximately 18ms1 (oscillator start-up timer, OST) before the next instruction of the program is executed. The OST is always activated by a wake-up event from sleep mode regardless of the Code Option bit ENWDT status is "0" or otherwise. After waking up, the WDT is enabled if the Code Option ENWDT is "1". The block diagram of SLEEP2 mode and wake-up invoked by an input trigger is depicted in Fig. 5. The SLPC bit can be read and written.• Bit 3 (ROC) ROC is used for the R-option. Setting ROC to "1" will enable the status of R-option pins (P70, P71) for the controller to read. Clearing ROC will disable the R-option function. Otherwise, the R-option function is introduced. Users must connect the P71 pin or/and P70 pin to VSS with a 430KΩ external resistor (Rex). If Rex is connected/disconnected with VDD, the status of P70 (P71) will be read as "0"/"1" (refer to Fig. 7(b)). The ROC bit can be read and written.• Bit 0 (/WUE) Control bit is used to enable the wake-up function of P74 and P75.0: Enable the wake-up function.1: Disable the wake-up function.The /WUE bit can be read and written.• Bits 1~2, and 7 Not used.1 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%Vdd = 3V, set up time period = 19.6ms ± 30%OTP ROM6. IOCF (Interrupt Mask Register)7 6 5 4 3 2 1 0 - - - - EXIE - -TCIE • Bit 3 (EXIE) EXIF interrupt enable bit. 0: disable EXIF interrupt 1: enable EXIF interrupt• Bit 0 (TCIE) TCIF interrupt enable bit. 0: disable TCIF interrupt 1: enable TCIF interrupt • Bits 1, 2 and 4~7 Not used.• Individual interrupt is enabled by setting its associated control bit in the IOCF to "1".• Global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction (refer to Fig. 9).• IOCF register is both readable and writable.Fig. 5 Sleep Mode and Wake-Up Circuits on I/O Ports Block DiagramOTP ROM4.3 TCC/WDT & PrescalerAn 8-bit counter is available as prescaler for the TCC or WDT. The prescaler is available for either the TCC or WDT only at any given time, and the PAB bit of the CONT register is used to determine the prescaler assignment. The PSR0~PSR2 bits determine the ratio. The prescaler is cleared each time the instruction is written to TCC under TCC mode. The WDT and prescaler, when assigned to WDT mode, are cleared by the “WDTC” or “SLEP” instructions.Fig. 6 depicts the circuit diagram of TCC/WDT.• R1 (TCC) is an 8-bit timer/counter. The clock source of TCC can be internal or external clock input (edge selectable from TCC pin). If TCC signal source is from internal clock, TCC will increase by 1 at every instruction cycle (without prescaler). Referring to Fig. 6, CLK=Fosc/2 or CLK=Fosc/4 selection is determined by the CODE Option bit CLK status. CLK=Fosc/2 is used if CLK bit is "0", and CLK=Fosc/4 is used if CLK bit is "1". If TCC signal source comes from external clock input, TCC is increased by 1 at every falling edge or rising edge of TCC pin.• The watchdog timer is a free running on-chip RC oscillator. The WDT will keep on running even after the oscillator driver has been turned off (i.e. in sleep mode). During normal operation or sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during normal mode by software programming. Refer to WDTE bit of IOCE register. Without prescaler, the WDT time-out period is approximately 18 ms1 (default).Fig. 6 TCC and WDT Block Diagram1 <Note>: Vdd = 5V, set up time period = 16.2ms ± 30%Vdd = 3V, set up time period = 19.6ms ± 30%OTP ROM4.4 I/O PortsThe I/O registers, Port 5, Port 6, and Port 7, are bi-directional tri-state I/O ports. The functions of Pull-high, R-option, and Open-drain can be performed internally by CONT and IOCE respectively. There is input status change wake-up function on Port 6, P74, and P75. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 5, Port 6, and Port 7 are shown in Figures. 7(a) and (b) respectively.Fig. 7 (a) The I/O Port and I/O Control Register CircuitFig.7(b) The I/O Port with R-Option (P70, P71) CircuitOTP ROM4.5 RESET and Wake-up1. RESETA RESET is initiated by one of the following events-(1) Power on reset, or(2) /RESET pin input “low”, or(3) WDT timeout. (if enabled)The device is kept in a RESET condition for a period of approx. 18ms1 (one oscillator start-up timer period) after the reset is detected. Once the RESET occurs, the following functions are performed (refer to Fig.8).• The oscillator starts or is running• The Program Counter (R2) is set to all "1".• When power is switched on, bits 5~6 of R3 and the upper 2 bits of R4 are cleared.• All I/O port pins are configured as input mode (high-impedance state).• The Watchdog timer and prescaler are cleared.• Upon power on, the bits 5~6 of R3 are cleared.• Upon power on, the upper 2 bits of R4 are cleared.• The bits of CONT register are set to all "1" except bit 6 (INT flag).• IOCB register is set to ”1” (disable P60 ~ P67 wake-up function).• Bits 3 and 6 of IOCE register are cleared, and Bits 0, 4, and 5 are set to "1".• Bits 0 and 3 of R3F register and Bits 0 and 3 of IOCF registers are cleared.The sleep (power down) mode is asserted by executing the “SLEP” instruction. While entering sleep mode, WDT (if enabled) is cleared but keeps on running. The controller can be awakened by-(1) External reset input on /RESET pin;(2) WDT time-out (if enabled)The above two cases will cause the controller EM78P447S to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up).In addition to the basic SLEEP1 MODE, EM78P447S has another sleep mode (designated as SLEEP2 MODE and is invoked by clearing the IOCE register “SLPC” bit). In the SLEEP2 MODE, the controller can be awakened by-1 NOTE: Vdd = 5V, set up time period = 16.2ms ± 30%Vdd = 3V, set up time period = 19.6ms ± 30%OTP ROM(A) Any of the wake-up pins is “0” as illustrated in Figure. 5. Upon waking, the controller will continueto execute the succeeding address. Under this case, before entering SLEEP2 MODE, thewake-up function of the trigger sources (P60~P67 and P74~P75) should be selected (e.g., inputpin) and enabled (e.g., pull-high, wake-up control). It should be noted that after waking up, theWDT is enabled if the Code Option bit ENWDT is “0”. The WDT operation (to be enabled ordisabled) should be appropriately controlled by software after waking up.(B) WDT time-out (if enabled) or external reset input on /RESET pin will trigger a controller reset.Table 4 Usage of Sleep1 and Sleep2 ModeUsage of Sleep1 and Sleep2 ModeSLEEP2 SLEEP1(a) Before SLEEP (a) Before SLEEP1. Set Port6 or P74 or P75 Input 1. Execute SLEP instruction2. Enable Pull-High and set WDT prescaler over1:1 (Set CONT.7 and CONT.3 ~ CONT.0)3. Enable Wake-up (Set IOCB or IOCE.0)4. Execute Seep2 (Set IOCE.4)(b) After Wake-up (b) After Wake-up1. Next instruction 1. Reset2. Disable Wake-up3. Disable WDT (Set IOCE.5)If Port6 Input Status Changed Wake-up is used to wake-up the EM78P447S (Case [a] above), the following instructions must be executed before entering SLEEP2 mode:MOV A, @11111111b; Set Port6 inputIOW R6MOV A, @0xxx1010b ; Set Port6 pull-high, WDT prescaler, prescaler must set over 1:1CONTWMOV A, @00000000b; Enable Port6 wake-up functionIOW RBMOV A, @xx00xxx1b ; Enable SLEEP2IOW REAfter Wake-upNOPMOV A, @11111111b; Disable Port6 wake-up functionIOW RBMOV A, @ xx01xxx1b; Disable WDTIOW RENote:After waking up from the SLEEP2 mode, WDT is automatically enabled. The WDT enabled/disabledoperation after waking up from SLEEP2 mode should be appropriately defined in the software.To avoid reset from occurring when the port6 status changed interrupt enters into interrupt vector oris used to wake-up the MCU, the WDT prescaler must be set above 1:1 ratio.OTP ROMTable 5 The Summary of the Initialized Register ValuesAddress Name Reset Type Bit 7Bit 6Bit 5Bit 4Bit 3 Bit 2 Bit 1Bit 0Name C57C56C55C54C53 C52 C51C50BitType A B A B A B A B- - - - N/A IOC5 Power-On 01010101 1 1 1 1andWDT 01010101 1 1 1 1 /RESETWake-Up from Pin Change0P0P0P0P P P P PName C67C66C65C64C63 C62 C61C60BitN/A IOC6 Power-On 1 1 1 1 1 1 1 1 /RESETWDT 1 1 1 1 1 1 1 1andChange P P P P P P P PPinWake-UpfromName C77C76C75C74C73 C72 C71C70BitN/A IOC7 Power-On 1 1 1 1 1 1 1 1WDT 1 1 1 1 1 1 1 1and/RESETChange P P P P P P P PPinWake-UpfromName /PHEN/INT TS TE PAB PSR2 PSR1PSR0BitN/A CONT Power-On 1 0 1 1 1 1 1 1andWDT 1 P 1 1 1 1 1 1 /RESETChange P P P P P P P PPinWake-UpfromName - - - - - - - -BitR0(IAR) Power-On U U U U U U U U 0x00WDT P P P P P P P Pand/RESETChange P P P P P P P PPinWake-UpfromName - - - - - - - -BitR1(TCC) Power-On 0 0 0 0 0 0 0 0 0x01WDT 0 0 0 0 0 0 0 0and/RESETChange P P P P P P P PPinfromWake-UpName - - - - - - - -BitR2(PC) Power-On 1 1 1 1 1 1 1 1 0x02WDT 1 1 1 1 1 1 1 1 /RESETandWake-Up from Pin Change**0/P**0/P**0/P**0/P**0/P **0/P **0/P**0/PName GP PS1PS0T P Z DC CBit0x03R3(SR) Power-On 0 0 0 1 1 U U U /RESET and WDT 0 0 0 t t P P P Wake-Up from Pin Change P P P t t P P PName RSR.1RSR.0- - - - - -BitR4(RSR) Power-On 0 0 U U U U U U 0x04WDT 0 0 P P P P P P /RESETandPinChange P P P P P P P PfromWake-UpBit Name P57P56P55P54P53 P52 P51P50 0x05 R5(P5) Power-On U U U U U U U U/RESET and WDT P P P P P P P P Wake-Up from Pin Change P P P P P P P PName P67P66P65P64P63 P62 P61P60Bit0x06 R6(P6) Power-On U U U U U U U UWDT P P P P P P P Pand/RESETPinChange P P P P P P P PfromWake-UpName P77P76P75P74P73 P72 P71P70Bit0x07 R7(P7) Power-On U U U U U U U U /RESETWDT P P P P P P P PandChange P P P P P P P PPinWake-UpfromName X X X X EXIF X X TCIFBitR3F(ISR) Power-On U U U U 0 U U 0 0x3F/RESET and WDT U U U U 0 U U 0OTP ROMWake-Up from Pin Change U U U U P U U PName /WUE7/WUE6/WUE5/WUE4/WUE3 /WUE2 /WUE1/WUE0Bit0x0B IOCB Power-On 1 1 1 1 1 1 1 1WDT 1 1 1 1 1 1 1 1 /RESETandChange P P P P P P P PPinfromWake-UpName X ODE WDTE SLPC ROC X X /WUEBit0x0E IOCE Power-On U 0 1 1 0 U U 1 /RESET and WDT U 0 1 1 0 U U 1 Wake-Up from Pin Change U P 1 1 P U U PBitName X X X X EXIE X X TCIE 0x0F IOCF Power-On U U U U 0 U U 0 /RESET and WDT U U U U 0 U U 0 Wake-Up from Pin Change U U U U P U U PName - - - - - - - -Bit0x08 R8 Power-On 0 0 0 0 0 0 0 0WDT 0 0 0 0 0 0 0 0and/RESETPinChange P P P P P P P P Wake-UpfromName - - - - - - - -Bit0x09~R9~R3E Power-On U U U U U U U U 0x3EWDT P P P P P P P P /RESETandChange P P P P P P P PPinfromWake-Up** To execute next instruction after the ”SLPC” bit status of IOCE register being on high-to-low transition.X: Not used. U: Unknown or don’t care. -: not defined. P: Previous value before reset. t: Check Table 62. The Status of RST, T, and P of STATUS RegisterA RESET condition is initiated by one of the following events:1. A power-on condition,2. A high-low-high pulse on /RESET pin, and3. Watchdog timer time-out.The values of T and P (listed in Table 5 below) are used to verify the event that triggered the processor to wake up.Table 6 shows the events that may affect the status of T and P.Table 6 The Values of RST, T and P after RESETReset Type T PPower on 1 1/RESET during Operating mode *P *P/RESET wake-up during SLEEP1 mode 1 0/RESET wake-up during SLEEP2 mode *P *PWDT during Operating mode 0 *PWDT wake-up during SLEEP1 mode 0 0WDT wake-up during SLEEP2 mode 0 *PWake-Up on pin change during SLEEP2 mode *P *P*P: Previous status before reset。

深圳市瑞丰汇 EM78 系列单片机仿真系统说明书

----EM78系列单片机仿真系统使用说明----台湾义隆8位单片机仿真系统用于在线仿真开发EM78PXX系列各种型号的单片机。

包括仿真系统软件（WICE）和仿真系统硬件（在线仿真板）。

其结构简单，使用方便，调试功能强大，是广大工程师的有力开发工具。

一. 仿真系统硬件----仿真板包括底板（控制电路、SRAM等）和上板（CPU板）组成。

底板通过打印口连接到PC机。

上板通过排线连接到用户的目标板。

其系统结构框图如下：----更换不同的上板（CPU板）即可仿真不同型号的单片机，以下列出部分上板型号：----1. EM153上板（153CPU板）：仿真EM78P153S----2. EM456上板（456CPU板）：仿真EM78P156EL----3. EM447上板（447CPU板）：仿真EM78P447SA/SB----4. EM451上板（451CPU板）：仿真EM78P451----5. EM458上板（458CPU板）：仿真EM78P458A/459A二. 仿真系统软件WICE----WICE是一套运行于WINDOWS环境的义隆8位单片机仿真软件，它将编辑，汇编，仿真功能集成在同一开发环境中，极大地方便了用户的操作。

1. 汇编语言格式----WICE要求源代码语句格式为：[标号[：]] [操作码] [操作数] [，操作数] [；注释]其中括号的内容为选，且各单元中的字符不区分大小写，如“MOV”和“mov”是完全一样的。

各单元之间以空白或跳格键（Tab）来分隔。

----标号：标号后的冒号可有可无，但隔行放置必须加上冒号，同时加上冒号也可加强程序的可读性。

标号内的字符可包括大小写英文字母（A~Z，a~z），数字（0~9）及底线（_），但标号必须以字母开头，标号最长不能超3过1个字符。

----操作码：可以是指令或伪指令。

----操作数：操作数的数目及类型由操作码决定，它可以是程序地址代码，寄存器代码或常数。

智能晾衣架的设计

基于义隆EM78447A的智能晾衣架的设计摘要：如何解决由于人不在家，所晾衣服被雨水淋湿的问题呢？作者利用义隆单片机EM78447A芯片设计出一种智能晾衣架,它能够自动识别晴天和雨天,智能地为我们服务。

本文详细介绍该智能晾衣架的硬件电路（雨滴传感器、光照传感器、单片机硬件电路、电机驱动电路）的电路原理及其软件设计.关键词：EM78447A 智能晾衣架设计Abstract:How solve the problem that the clothes being dried in the sun are soaked by rain when you are absent? In order to do that， The author designed a kind of intelligent clothesrack which can distinguish sunny days from rainy days automatically by using righteousness prosperous monolithic integrated circuit EM78447A chip , the intelligence serves for us. In this article the hardware electric circuit (raindrop sensor, illumination sensor, monolithic integrated circuit hardware electric circuit, motor—driven electric circuit）principles of the intelligent clothesrack and its software designing are detailedKey word: The EM78447A, intelligent clothesrack， design0．引言每当下雨的时候,又恰好无人在家，然而你的衣服却晾在阳台上，你就会想我该怎么办呢？基于这个问题,我们设想：假如有一台智能型的晾衣架，它能够自动识别晴天和雨天，智能地为我们服务,多好啊！下面就给大家介绍我们的作品——晴雨智能晾衣架。

78K0单片机C语言教程共159页

XT2 32kHz
XT1
(3)高速内置时钟 78K0内置8MHz时钟，如无特殊要求，可利用内置时钟。
78F0547D单片机时钟的控制：
①主时钟通过执行STOP指令或设置主OSC控制寄存器(MOC)和处理器时钟控制寄存器 (PCC)，可停止振荡。
②子时钟通过设置处理器时钟控制寄存器(PCC)和时钟工作模式选择寄存器(OSCCTL)可停止振荡。
单片机的发展历史
➢第一代：七十年代后期， 4 位逻辑控制器件发展到 8 位。 NMOS 工艺（速度低，功耗大、集成度低）。代表产品： MC6800 和 Intel 8048
➢第二代：八十年代初， CMOS 工艺，并逐渐被高速低功耗的 HMOS 工艺代替。代表产品： MC146805 和 Intel 8051
课堂实施方案
主动提问题讨论，每人20个，每个1分
单片机应用系统硬件组成
数字量检测
光电隔离
单
模拟量检测
A/D转换
I/O
扩
片
开关量检测
光电隔离
展
机
开关量控制
光电隔离
D/A转换 I/O接口显示器
键盘
伺服驱动输出
通用外设
NEC单片机教学实验仪简介
1 实验仪外观、布局和图纸
CAN总线包含SJA1000和 CTM1050T芯片
③高速内置时钟通过执行STOP指令或设置内置振荡器模式寄存器(RCM)，可停止振荡。
✓ 主时钟/子时钟/高速内置时钟3者只能选择其一工作，其余2个要停止。
④低速内置时钟(看门狗定时器(WDT)所用的240kHz时钟信号) RESET释放后，低速内置振荡器开始工作。若Option byte中设定了“低速内置振荡器可以使用软件停止”，那么可以通过设置内置振荡器模式寄存器(RCM)来停止振荡。

EM78系列单片机的编程技巧_王永生【参考2书】

堆栈（5级）
CONT
IOC5 IOC6 IOC7
IOCE IOCF
10H R10 11H (16×8通用寄存器）
…
…
1FH R1F
00
01
10
11
20H
31×8位 31×8位 31×8位 31×8位
…
体寄存器体寄存器体寄存器体寄存器
3BH
(体0)
(体1)
(体2)
(体3)
3FH
R3F
图１ＥＭ７８系列单片机ＲＡＭ结构图
图３中，Ｐａｇｅ０存放的主要是比较常用的子程序，如
系统初始化程序、键盘扫描、液晶显示等；Ｐａｇｅ１存放
的是一些数据处理程序，如不同Ｂａｎｋ的数据拷贝，十
六进制转为二进制压缩ＢＣＤ码等程序；Ｐａｇｅ２存放的加密算法程序，这是笔者项目开发中最重要的部分，所以单独的放在一个Ｐａｇｅ内；Ｐａｇｅ３主要是对ＩＣ
00H R0 01H R1(TCC) 02H R2 03H R3(Status) 04H R4(RSR) 05H R5(Port5) 06H R6(Port6) 07H R7(Port7) 08H R8 09H R9 0AH RA 0BH RB 0CH RC 0DH RD 0EH RE 0FH RF
；调用显示屏清零程序
……
……
ＬＣＤ＿ＣＬＥＡＲ：
ＢＣＲＳＲ，７
；到Ｂａｎｋ０
ＢＣＲＳＲ，６
ＭＯＶＡ，＠０Ｂ００００００００
ＭＯＶＬｃｄ＿ａｄｄｒｅｓｓ，Ａ
……
如上面程序所示，在调用ＬＣＤ＿ＣＬＥＡＲ之前访问了
用了这种方法取得了很好的效果。

EM78系列单片机的开发工具及编程器

第六章EM78系列单片机的开发工具及编程器EM78单片机的开发工具一般包括：（1）宏汇编（交叉汇编）（2）仿真器（3）程序烧写器。

单片机的开发过程如下：1)用编辑软件（如：EDIT、PE2等）输入源程序（扩展名DT）2)用宏汇编（ASM456/ASM447）对源程序（*。

DT）进行汇编。

3)使用仿真器（ICE456/447）进行程序调试。

仿真调试正确转向下一步，不正确则修改源程序再转向“2”开始。

4)将调试完毕的目标码（*.CDS）用烧写器烧入EM78单片机中。

5)将烧好的单片机插入实际电路中检查，若正确则开发完毕，否则修改程序转向“2”开始。

下面分别介绍上述三种开发工具。

6.1.宏汇编（交叉汇编）与汇编语言格式6.1.1.宏汇编程序ASM456是EM78154/156/256/456的汇编程序。

ASM447是EM78247/447的汇编程序。

ASM456/447是台湾义隆电子公司设计的针对EM78单片机的汇编软件，该软件也包含在仿真器(E8-ICE)的集成调试软件中，也可以直接在仿真器软件中汇编，也可以单独使用。

对源程序汇编后会产生如下文件：*.dt：源程序*.std：提供给程序设计者参考的标准文件*.cds：即一般所谓的目标文件（object文件）.ice：提供给仿真器（E8-ICE）显示使用*.lin 及*.adr：提供给仿真器（E8-ICE）的数据库使用注：*.ice 及*.std为可读的文本文件，其余为不可读。

若汇编失败，将产生一个*.err文件，内为错误信息，以便设计者排错用。

6.1.2.汇编语言格式以下就该编译器的語法，作一詳盡介紹。

(1)键入格式本编译器並不对字之大写或小写作区別，如 "MOV"， "Mov"， "mOV"，和 "MoV" 在解释上是不做区別的。

(2)在常数之前请加小鼠标"@"，其它如寄存器(r)及位(b)之前則不加"@"。

EM78指令系统

2. EM78 指令概述
EM78 系列单片机共有的 47 条（EM78P447 和 451、458 有 48 条）指令，其寬度为 13 位。每一个指令码可分割成两部份，第一部分为标示指令功能的运算码（ OPCODE ），第二部份則指出运算時所需之參数，亦即运算码（ OPERAND ）。而指令的类型大致可分为下列四种：
深圳博巨兴有限公司
EM78 指令系统
目
录
EM78 指令系统.................................................................................................................................. 1 1. 程序基本格式..................................................................................................................... 2 2. EM78 指令概述..................................................................................................................3 3. EM78 指令寻址方式..........................................................................................................4 3.1. 立即数寻址.........................................................................................................4 3.2. 直接寻址.............................................................................................................4 3.3. 间接寻址.............................................................................................................4 3.4. 位寻址.................................................................................................................5 4. EM78 基本指令说明..........................................................................................................5 5. EM78 扩展指令说明........................................................................................................18 6. 指令速查表...............................................................................................................21

单片机霓虹灯设计

单片机霓虹灯设计作者：来源：本站原创点击数：3605 更新时间：2007年06月12日【摘要】介绍了基于EM78P447SB单片机、自制光电耦合器制作的低成本高性能霓虹灯控制器的线路、工作原理、编程方法和使用经验。

该控制器具有相当高的性价比。

1引言霓虹灯控制器属于定制产品，很难工厂化批量生产。

由于市场竞争日趋激烈，该产品的高利润时代已经结束，市场迫切需要低成本高性能的霓虹灯控制器制造技术。

台湾义隆电子公司生产的EM78P447SB单片机是一次写录的芯片，内部有4K的ROM，振荡脉冲外围线路仅是一个电阻和一个电容，有三个口24位输出控制，性价比相当高，非常适合制作霓虹灯程序控制器。

但用单片机制作的霓虹灯程序控制器一般都需要光电耦合器实现高低压隔离，防止程序跑飞死机。

市场上光电耦合器价格一般都比较高。

为了降低成本，在保证高低压隔离能力没有降低的前提下，本设计采用自制的光电耦合器。

同时，为进一步降低成本，该霓虹灯控制器的花样变化速度调节及全亮维修功能均采用不增加硬件成本的方法，这样，进一步提高了性价比。

霓虹灯是一种冷阴极辉光放电管，其幅射光谱具有极强的穿透大气的能力，色彩鲜艳绚丽、多姿，发光效率明显优于普通的白炽灯，它的线条结构表现力丰富，可以加工弯制成任何几何形状，满足设计要求，通过电子程序控制，可变幻色彩的图案和文字受到人们的欢迎。

霓虹灯的亮、美、动特点，是目前任何电光源所不能替代的，在各类新型光源不断涌现和竞争中独领风骚。

由于霓虹灯是冷阴极辉光放电，因此一支质量合格的霓虹灯其寿命可达20000--30000小时。

随着我国经济的飞速发展，霓虹灯的品种、规格也已基本系列化，可供各种用途的选择，其质量已逐步向国际水平靠拢，随着我国加入WTO与国际水平的差距将越来越小，在不久的将来必将赶超国际先进水平，但在目前市场竞争的条件下，也确有少数厂商缺乏诚信，在一些用户不懂霓虹灯的性能、质量的情况下，生产、制作低劣产品在市场上低价倾销，影响霓虹灯的声誉。