FT2232中文资料
FMMT2222中文资料
FMMT2222 FMMT2222A
C B E
ABSOLUTE MAXIMUM RATINGS.
PARAMETER Collector-Base Voltage Collector-Emitter Voltage Emitter-Base Voltage Continuous Collector Current Power Dissipation at Tamb=25°C SYMBOL VCBO VCEO VEBO IC Ptot FMMT2222 60 30 5 600 330 -55 to +150 FMMT2222A 75 40 6 UNIT V V V mA mW °C
µA
IC=10mA, IB=0 IE=10µA, IC=0 VCB=50V, IE=0 VCB=60V, IE=0 VCB=50V, IE=0, Tamb=150°C VCB=60V, IE=0, Tamb=150°C VEB=3V, IC=0 VCE=60V, VEB(off)=3V IC=150mA, IB=15mA* IC=500mA, IB=50mA* IC=150mA, IB=15mA* IC=500mA, IB=50mA* IC=0.1mA, VCE=10V* IC=1mA, VCE=10V IC=10mA, VCE=10V* IC=10mA, VCE=10V, Tamb=-55°C IC=150mA, VCE=10V* IC=150mA, VCE=1V* IC=500mA, VCE=10V*
STORAGE TIME AND FALL TIME TEST CIRCUIT
+30V
=100µs <5ns .8 V =500µs
1N916
-3V
FT232RL电路原理图_中文手册_引脚图
本节总结了FT232RL设备的增强功能和主要功能。
有关详细信息，请参阅设备引脚输出说明和功能说明部分。
集成时钟电路-前几代FTDI的USB UART设备需要外部晶体或陶瓷谐振器。
时钟电路现在已经集成到设备上，这意味着没有晶体或陶瓷谐振器必修的。
但是，如果需要，可以使用外部12MHz晶体作为时钟源。
集成EEPROM-前几代FTDI的USB UART设备需要一个外部EEPROM，如果设备使用USB供应商ID（VID）、产品ID（PID）、序列号和产品描述字符串，而不是设备本身的默认值。
这个外部EEPROM现已集成到FT232R芯片上所有设计都可以选择更改产品描述字符串。
内部EEPROM的用户区域是可用于存储附加数据。
内部EEPROM是可编程的电路，通过USB没有任何额外的接口电压要求。
预编程EEPROM-FT232R提供了其内部EEPROM预编程序列号这是每个设备所独有的。
在大多数情况下，这将消除对设备EEPROM编程的需要。
集成USB电阻器-前几代FTDI的USB UART设备需要两个外部串联电阻器在USBDP 和USBDM线路上，以及USBDP上的1.5 kΩ上拉电阻器。
这三个电阻现在已经集成到设备上。
集成AVCC过滤-前几代的FTDI的USB UART设备有一个单独的AVCC引脚-向内部锁相环供电。
该引脚需要外部R-C过滤器。
单独的AVCC引脚现在内部连接到VCC，滤波器现在已集成到芯片上。
更少的外部组件-集成晶体、EEPROM、USB电阻和AVCC滤波器将大大减少成本与以前的FT232BM相比，使用FT232R的USB接口设计可以降低材料成本。
发送和接收缓冲区平滑-FT232R的256字节接收缓冲区和128字节发送缓冲区利用新的缓冲区平滑技术，允许高数据吞吐量。
可配置的CBUS I/O引脚选项-现在有5条可配置的控制总线（CBUS）线路。
选项是TXDEN-RS485设计的传输启用，PWREN#-大功率电源控制，总线供电设计，TXLED#-用于在传输数据时脉冲LED，RXLED#-用于在接收数据时脉冲LED，TX和RXLED#-其中在传输或接收数据时，将脉冲LED，SLEEP#-表示设备进入USB暂停模式，CLK48/CLK24/CLK12/CLK6-48MHz、24MHz、12MHz和6MHz时钟输出信号选项。
FT2232H_EEPROM_93LC56
// main function
int _tmain(int argc, _TCHAR* argv[])
{
FT_HANDLE ftHandle;
FT_STATUS ftStatus;
DWORD numDevs;
FT_DEVICE_LIST_INFO_NODE *devInfo;
// Include the following 2 lines in your header-file
#pragma comment(lib, "FTD2XX.lib")
#include "FTD2XX.h"
//============================================================================
}
printf("==========================================\n");
//============================== READ EEPROM USER AREA (130 Bytes)=========================================
printf(" VendorId=0x%x\n",ftData.VendorId);
printf(" ProductId=0x%x\n",ftData.ProductId);
printf(" Manufacturer=%s\n",ftData.Manufacturer);
devInfo = (FT_DEVICE_LIST_INFO_NODE*)malloc(sizeof(FT_DEVICE_LIST_INFO_NODE)*numDevs);
DLP-2232MSP;中文规格书,Datasheet资料
D L P -2232M S PLEAD FREEUSB / MICROCONTROLLER MODULEThe DLP-2232MSP combines the same USB interface used in the DLP-2232H and the DLP-1232H modules with a Texas Instruments microcontroller to form a rapid development tool. TheMSP430F2618 microcontroller is preprogrammed with basic functionality for accessing the port pins and can be reprogrammed with user firmware via a 10-pin header using a device programmer (purchased separately).FEATURES:• Send/receive data over a high-speed USB 2.0 interface to a host computer• 32 digital I/O lines (8 can be configured as A/D inputs; 2 can be configured as D/A outputs) plus the 8-bit data bus available for interfacing to user electronics• Texas Instruments 16-bit RISC architecture processor with 116K bytes FLASH ROM, 8K bytes RAM, a multi-channel,12-bit A/D converter and dual, 12-bit D/A converters• “Token I/O” code preprogrammed into the MSP430F2618’s FLASH memory for basic port pin input/output capability including access to the A/D and D/A converters• The FLASH memory can be easily erased and reprogrammed utilizing a user-supplied compatible programmer• No in-depth knowledge of USB is required as all USB protocols are handled automatically by the on-board FT2232H and its support circuitry• Royalty-free device drivers eliminate the need for USB driver development in most cases • USB bulk or isocronous data-transfer modes• Required 5V supply can be taken directly from the USB port or supplied by user electronics • USB 1.1 and USB 2.0 compatible• USB VID, PID, serial number and product-description strings stored in an on-board EEPROM memory• Royalty-Free Virtual COM Port (VCP) Drivers for:- Windows 2000, Server 2003 and Server 2008- Windows XP and XP 64 bit- Windows Vista and Vista 64 bit- Windows 7- Windows CE 4.2-, 5.0- and 5.2-based OS- MAC OS-X- Linux (tested using kernel 2.6.32)•Royalty-Free D2XX Direct Drivers (USB drivers + DLL S/W interface) for:- Windows 2000, Server 2003 and Server 2008- Windows XP and XP 64 bit- Windows Vista and Vista 64 bit- Windows 7- Windows CE 4.2-, 5.0- and 5.2-based OSOS-X-MAC- Linux (tested using kernel 2.6.32)APPLICATION AREAS:• Prototype development•USB ISDN and ADSL modems•USB interface for digital cameras•USB interface for MP3 players•High-speed USB instrumentation•USB smart-card readers•Set top box (STB) PC-USB interface•USB hardware modems•USB wireless modems•USB bar code readers1.0 GENERAL DESCRIPTIONThe DLP-2232MSP provides a cost-effective, microcontroller-based method of interfacing an electronic peripheral to a host computer via USB.To send data from the peripheral to the host computer, the microcontroller simply writes thebyte-wide data into the FT2232H when TXE# is low. If the FT2232H’s transmit buffer fills up or is busy storing the previously written byte, it will take TXE# high in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host.When the host sends data to the peripheral over USB, the FT2232H will take RXF# low to let the microcontroller know that at least one byte of data is available. The microcontroller then reads the data until RXF# goes high indicating that no more data is available to be read.By using FTDI’s Virtual COM Port Drivers, the peripheral looks like a standard COM port to the application software. Commands to set the baud rate are ignored--the FT2232H always transfers data at its fastest rate regardless of the application’s baud-rate setting. The latest versions of the drivers are available for download from DLP Design’s website at .2.0 DRIVER SOFTWAREFTDI's VCP (Virtual COM Port) driver-executable files are provided royalty free on the condition that they are used only with designs incorporating an FTDI device (i.e. the FT2232H on theDLP-2232MSP). The latest version of the drivers can be downloaded from or .The VCP driver download file is a combined set of drivers for Windows 7, Windows Vista and Windows 2000/XP. Unzip the file to a blank floppy disk or folder on your PC. (The drivers can coexist on the same floppy disk or folder since the INF files determine which set of drivers to load for each operating system version.) Once loaded, the VCP drivers allow the application software running on your host PC to communicate with the DLP-2232MSP as though it were connected to a COM(RS-232) port.In addition to VCP drivers, FTDI's D2XX direct drivers offer an alternative solution to the VCP drivers that allow application software to interface with the DLP-2232MSP using a DLL instead of a Virtual COM Port. The architecture of the D2XX drivers consists of a Windows WDM driver that communicates with the device via the Windows USB stack and a DLL that interfaces the application software (written in VC++, C++ Builder, Delphi, VB, etc.) to the WDM driver. An INF installation file, uninstaller program and D2XX Programmer’s Guide complete the package.The D2XX direct drivers add support for simultaneous access and control of multiple FT2232H devices. The extended open function (FT_OpenEx) allows the device to be opened by either its product description or serial number, both of which can be programmed to be unique. The list devices function (FT_ListDevices) allows the application software to determine which devices are currently available for use, again by product description or by serial number.Download FTDI Application Notes AN232-03, AN232-05, AN232-06 and AN232-07 for detailed instructions on how to install and remove the drivers.3.0 EEPROM WRITE UTILITYThe DLP-2232MSP has the option to accept manufacturer-specific information that is written into on-board EEPROM memory. Parameters that can be programmed include the VID and the PID identifiers, the manufacturer's product string or a serial number.MPROG is an EEPROM serializer and testing utility from FTDI for the FT2232H device. MPROG is based on the new D2XX drivers and will work on Windows 7, Windows Vista and Windows 2000/XP platforms. You must install the latest release of the CDM drivers in order to run this application. (Refer to the MPROG User’s Guide for details on the program’s use.)4.0 QUICK START GUIDEThis guide requires the use of a Windows 7/Vista/2000/XP PC that is equipped with a USB port.1. Download the WHQL-certified CDM device drivers from either or. Unzip the drivers onto a blank floppy disk or into a folder on the hard drive.Note: The DLP-2232MSP can be configured to receive its operating power from the USB port or from user electronics. Pins 24 and 25 or the barrel jack allow for this configuration. (Refer to the Pinout Description in the next section for details on the DLP-2232MSP electrical interface.)**The board will not operate until a power source has been connected.**2. Connect the DLP-2232MSP board to the PC via a standard A-B, 6-foot USB cable. This actioninitiates the loading of the USB drivers. When prompted, select the folder where the CDM device drivers were stored in Step 1. Windows will then complete the installation of the device drivers for the DLP-2232MSP board. The next time the DLP-2232MSP board is attached, the host PC will immediately load the correct drivers without any prompting. Reboot the PC if prompted to do so.The DLP-2232MSP is shipped with default VID, PID, etc. values programmed into the EEPROM memory. You only need to run MPROG if you want to change the default values.At this point, the DLP-2232MSP is ready for use. Note that the DLP-2232MSP will appearnon-responsive if data sent from the host PC is not read from the FT2232H device by theMSP430F2618 microcontroller. The token firmware with which the DLP-2232MSP comes preloaded will read data sent by the host by default. Custom user firmware should also follow this protocol. 5.0 TOKEN I/OThe MSP430F2618 microcontroller on the DLP-2232MSP comes preprogrammed with firmware that provides rudimentary access to the port pins via either the VCP or DLL drivers. Features include the ability to read and write individual port pins.The firmware in the DLP-2232MSP also provides access to the MSP430F2618’s A/D converter, D/A converter and communications. Commands sent to the Token I/O firmware must adhere to a specific communications protocol. Each command sequence contains the following information:Byte 0: Number of bytes in command sequenceByte 1: CommandByte 2…n: Parameter/data bytesFor example, setting Port Pin P1.1 high would require the following string of bytes:0x04, 0x30, 0x11, 0x00, 0x01Definition of the Bytes:0x04 – Number of bytes in command0x30 – Command for digital port pin access0x11 – Affected port pin0x00 – Set port pin to output0x01 – Desired state of port pinThe port pins equate to hexadecimal numeric constants as defined here:PORT 1:0x10 = P1.0 MSP430F2618 Pin 12, DLP-2232MSP module Pin J1.120x11 = P1.1 MSP430F2618 Pin 13, DLP-2232MSP module Pin J1.13PORT 2:0x20 = P2.0 MSP430F2618 Pin 20, DLP-2232MSP module Pin J1.140x21 = P2.1 MSP430F2618 Pin 21, DLP-2232MSP module Pin J1.160x22 = P2.2 MSP430F2618 Pin 22, DLP-2232MSP module Pin J1.180x23 = P2.3 MSP430F2618 Pin 23, DLP-2232MSP module Pin J1.200x24 = P2.4 MSP430F2618 Pin 24, DLP-2232MSP module Pin J1.190x25 = P2.5 MSP430F2618 Pin 25, DLP-2232MSP module Pin J1.170x26 = P2.6 MSP430F2618 Pin 26, DLP-2232MSP module Pin J1.150x27 = P2.7 MSP430F2618 Pin 27, DLP-2232MSP module Pin J1.21PORT 3:0x30 = P3.0 MSP430F2618 Pin 20, DLP-2232MSP module Pin J1.390x31 = P3.1 MSP430F2618 Pin 21, DLP-2232MSP module Pin J1.410x32 = P3.2 MSP430F2618 Pin 22, DLP-2232MSP module Pin J1.370x33 = P3.3 MSP430F2618 Pin 23, DLP-2232MSP module Pin J1.380x34 = P3.4 MSP430F2618 Pin 24, DLP-2232MSP module Pin J1.360x35 = P3.5 MSP430F2618 Pin 25, DLP-2232MSP module Pin J1.40PORT 5:0x50 = P5.0 MSP430F2618 Pin 44, DLP-2232MSP module Pin J1.430x51 = P5.1 MSP430F2618 Pin 45, DLP-2232MSP module Pin J1.450x52 = P5.2 MSP430F2618 Pin 46, DLP-2232MSP module Pin J1.440x53 = P5.3 MSP430F2618 Pin 2, DLP-2232MSP module Pin J1.460x54 = P5.4 MSP430F2618 Pin 48, DLP-2232MSP module Pin J1.470x55 = P5.5 MSP430F2618 Pin 49, DLP-2232MSP module Pin J1.480x56 = P5.6 MSP430F2618 Pin 50, DLP-2232MSP module Pin J1.500x57 = P5.7 MSP430F2618 Pin 51, DLP-2232MSP module Pin J1.49PORT 6:0x60 = P6.0/A0 MSP430F2618 Pin 59, DLP-2232MSP module Pin J1.20x61 = P6.1/A1 MSP430F2618 Pin 60, DLP-2232MSP module Pin J1.30x62 = P6.2/A2 MSP430F2618 Pin 61, DLP-2232MSP module Pin J1.40x63 = P6.3/A3 MSP430F2618 Pin 2, DLP-2232MSP module Pin J1.50x64 = P6.4/A4 MSP430F2618 Pin 3, DLP-2232MSP module Pin J1.70x65 = P6.5/A5 MSP430F2618 Pin 4, DLP-2232MSP module Pin J1.80x66 = P6.6/A6/DAC0 MSP430F2618 Pin 5, DLP-2232MSP module Pin J1.90x67 = P6.7/A7/DAC1 MSP430F2618 Pin 6, DLP-2232MSP module Pin J1.10The source code for the Token I/O firmware (developed using the CCS C compiler) is available as a free download upon purchase and receipt of the hardware. Example Visual C++ source code developed using Microsoft Visual C for communicating with the DLP-2232MSP via the Token I/O firmware is also available for download. (The Windows source code also contains the port pin definitions listed above.)5.1 TOKEN I/O COMMAND SET0x27 – Ping – Host NotificationLength: 2 BytesParameters: NoneReturns: 1 Byte: ASCII “S” or hex 0x53Function:This function returns an ASCII ‘S’ to tell the host that the module is up and running Example:0x02, 0x27 – Causes the module to return a 0x53 to the host0x28 – Flash LED – Toggle the LEDLength: 2 BytesParameters: NoneReturns: 1 Byte: command echo acknowledgement=0x28Function:This function will cause the module’s green LED to flash brieflyExample:0x02, 0x28 – Causes the LED to toggle briefly0x29 – LED On/OffLength: 3 BytesParameters: 1 Byte: 0=Turn LED Off; 1=Turn LED OnReturns: 1 Byte: command echo acknowledgement=0x29Function:This function will turn the module’s green LED on or offExample:0x03, 0x29, 0x01 - Turns on the LED0x30 – Digital I/O Read/WriteLength: 4 or 5 BytesParameters: 2 or 3 Bytes:1. Port Selection – Select the desired MSP430F2618 port pin (refer to the port listunder the previous section)2. Port Direction: 1=Input; 0=Output3. Port Value if Byte 2 specifies OutputReturns: 2 Bytes for Input=Value on port pin; command echo acknowledgement=0x301 byte for Output=command echo acknowledgement=0x30Function:This function will read from or write to the selected port pinExample:0x04, 0x30, 0x60, 0x00, 0x01 – Sets Port 6 Pin 0 high0x40 – A/D ConversionLength: 3 BytesParameters:Mode: 0=Single conversion, 1=Continuous conversions (~1 per second)Note: Setting the ADC mode to continuous (1) starts an infinite loop. The ADCwill perform a conversion approximately once a second and report the result tothe host. To exit, break the code using the debugger or reset the module. Returns: 2 Bytes: The 12-bit voltage data; MSB firstFunction:This function will enable A/D conversion on the selected channel and ADC, pause 10uS, perform the A/D conversion and then return 2 bytes to the host (MSB first).Command 0x42 must have been previously called to configure the desired analogchannel as an A/D input, and 0x43 / 0x44 must have been called to configure thevoltage reference.Example:0x3, 0x40 0x00 – Performs the A/D conversion and, using ADC0, returns 2 bytes of data0x41 – Disable A/DLength: 3 BytesParameters: 0=ADC0, 1=ADC1Returns: 1 Byte: command echo acknowledgement=0x41Function:This function disables the specified A/D converterExample:0x3, 0x41 0x01 – Disables A/D Converter 10x42 – Select A/D InputLength: 3 BytesParameters:0x00=Select input A0 (P6.0)0x01=Select input A1 (P6.1)0x02=Select input A2 (P6.2)0x03=Select input A3 (P6.3)0x04=Select input A4 (P6.4)0x05=Select input A5 (P6.5)0x06=Select input A6 (P6.6)0x07=Select input A7 (P6.7)0x08=Select internal input Veref+0x09=Select internal input Vref-/Veref-0x0A=Select internal temperature diode0x0B=Select internal input (Avcc – Avss)/2Returns: 1 Byte: command echo acknowledgement=0x42Function:This function selects the analog input to be used by the specified A/D converter Example:0x3, 0x42 0x03 – Selects analog input A30x43 – External ReferenceLength: 2 BytesParameters: NoneReturns: 1 Byte: command echo acknowledgement=0x43Function:This function sets the A/D and D/A references to be externalExample:0x2, 0x43 – Select External Voltage Reference0x44 – Internal ReferenceLength: 2 BytesParameters: NoneReturns: 1 Byte: command echo acknowledgement=0x44Function:This function sets the A/D and D/A references to be internal; use command 0x50 to select the Internal Voltage Reference valueExample:0x2, 0x44 – Select Internal Voltage Reference0x50 – Select Internal Reference SourceLength: 3 BytesParameters:0=+1.5V, 1=+2.5VReturns: 1 Byte: command echo acknowledgement=0x50Function:This function sets the A/D and D/A internal voltage reference valuesExample:0x3, 0x50 0x00 – Select Internal Voltage Reference of +1.5V0x60 – D/A OutputLength: 5 BytesParameters: 3 Bytes:1. 0=DAC0 output on Port A6; 1=DAC1 output on Port A72. 0x0n (n=MSB 4 bits of 12-bit DAC output value)3. 0xmm (mm=LSB 8 bits of 12-bit DAC output value)Returns: 1 Byte: command echo acknowledgement=0x60Function:This function selects the D/A converter and specifies the output valueExample:0x5, 0x60 0x00 0x01 0x23 – Select DAC 0 to output value 0x123; the actual voltage depends upon the reference selected0x61 – Disable D/ALength: 3 BytesParameters: 0=DAC0; 1=DAC1Returns: 1 Byte: command echo acknowledgement=0x61Function:This function disables the specified D/A converterExample:0x3, 0x61 0x00 – Disables D/A converter 00x70 – UART LoopbackThis command configures UART 1 to loop back any bytes received on its input port to its transmit output port. Port B on the FT2232H must be set to UART mode with a baud rate of 115200. Once set any bytes sent through Port B of the FT2232H will be echoed back. This command initiates an infinite loop in which all bytes sent are looped back. To exit, break the code using the debugger or reset the module.Length: 2 BytesParameters: NoneReturns: 1 Byte: command echo acknowledgement=0x70(After a command is sent, subsequent bytes sent to the UART via FT2232HPort B will be echoed back)Function:This function configures UART 1 to loop back received bytesExample:0x2, 0x70 – UART 1 loopback enabledTABLE 1: DLP-2232MSP PINOUT DESCRIPTION1252650PIN # DESCRIPTION1 GROUND2 P6.0/A0 (I/O)Port 6 Pin 0 connected to the MSP430F2618 Digital I/O P6.3 and Analog Input 03 P6.1/A1 (I/O) Port 6 Pin 1 connected to the MSP430F2618 Digital I/O P6.3 and Analog Input 14 P6.1/A2 (I/O) Port 6 Pin 2 connected to the MSP430F2618 Digital I/O P6.3 and Analog Input 25 P6.3/A3 (I/O) Port6 Pin 3 connected to the MSP430F2618 Digital I/O P6.3 and Analog Input 36 GROUND7 P6.3/A4 (I/O) Port 6 Pin 4 connected to the MSP430F2618 Digital I/O P6.4 and Analog Input 48 P6.3/A5 (I/O) Port 6 Pin 5 connected to the MSP430F2618 Digital I/O P6.5 and Analog Input 59 P6.3/A6/DAC0 (I/O) Port 6 Pin 6 connected to the MSP430F2618 Digital I/O P6.6, Analog Input 6 and D/A output DAC010 P6.3/A7/DAC1 (I/O) Port 6 Pin 7 connected to the MSP430F2618 Digital I/O P6.7, Analog Input 7 and D/A output DAC0111 GROUND12 P1.0 (I/O) Port 1 Pin 0 connected to the MSP430F2618 Digital I/O P1.013 P1.1 (I/O) Port 1 Pin 1 connected to the MSP430F2618 Digital I/O P1.114 P2.0 (I/O) Port 2 Pin 0 connected to the MSP430F2618 Digital I/O P2.015 P2.6 (I/O) Port 2 Pin 6 connected to the MSP430F2618 Digital I/O P2.616 P2.1 (I/O) Port 2 Pin 1 connected to the MSP430F2618 Digital I/O P2.117 P2.5 (I/O) Port 2 Pin 5 connected to the MSP430F2618 Digital I/O P2.518 P2.2 (I/O) Port 2 Pin 2 connected to the MSP430F2618 Digital I/O P2.219 P2.4 (I/O) Port 2 Pin 4 connected to the MSP430F2618 Digital I/O P2.420 P2.3 (I/O) Port 2 Pin 3 connected to the MSP430F2618 Digital I/O P2.321 P2.7 (I/O) Port 2 Pin 7 connected to the MSP430F2618 Digital I/O P2.722 SWVCC (Out) Power from EXTVCC (Pin 24) controlled via Pin 60 (PWREN#) of theFT2232H and Q1 MOSFET power switch; R8 and C24 control the power-up rate to help limit inrush current23 GROUND24 EXTVCC (In) Use for applying main power (4.4-5.25 volts) to the module; connect to PORTVCC if the module is to be powered by the USB port (typical configuration)25 PORTVCC (Out) Power from USB port—Connect to EXTVCC if the module is to be powered by the USB port (typical configuration); 500mA is the maximum current available to the DLP-2232MSP and target electronics if the USB device is configured for high power26 GROUND27 DB0 (I/O) Line 0 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO28 DB1 (I/O) Line 1 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO29 DB2 (I/O) Line 2 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO30 DB3 (I/O) Line 3 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO31 DB4 (I/O) Line 4 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO32 DB5 (I/O) Line 5 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO33 DB6 (I/O) Line 6 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO34 DB7 (I/O) Line 7 of the data bus between the MSP430F2618 and the FT2232H USB-FIFO35 GROUND36 P3.4 (I/O) Port 3 Pin 4 connected to the MSP430F2618 Digital I/O P3.437 P3.2 (I/O) Port 3 Pin 2 connected to the MSP430F2618 Digital I/O P3.238 P3.3 (I/O) Port 3 Pin 3 connected to the MSP430F2618 Digital I/O P3.339 P3.0 (I/O) Port 3 Pin 0 connected to the MSP430F2618 Digital I/O P3.040 P3.5 (I/O) Port 3 Pin 5 connected to the MSP430F2618 Digital I/O P3.541 P3.1 (I/O) Port 3 Pin 1 connected to the MSP430F2618 Digital I/O P3.142 GROUND43 P5.0 (I/O) Port 5 Pin 0 connected to the MSP430F2618 Digital I/O P5.044 P5.2 (I/O) Port 5 Pin 2 connected to the MSP430F2618 Digital I/O P5.245 P5.1 (I/O) Port 5 Pin 1 connected to the MSP430F2618 Digital I/O P5.146 P5.3 (I/O) Port 5 Pin 3 connected to the MSP430F2618 Digital I/O P5.347 P5.4 (I/O) Port 5 Pin 4 connected to the MSP430F2618 Digital I/O P5.448 P5.5 (I/O) Port 5 Pin 5 connected to the MSP430F2618 Digital I/O P5.5分销商库存信息: DLP-DESIGNDLP-2232MSP。
MMBT2222型号的芯片数据手册说明书
P —— T
C
a
25
50
75
100
125
150
AMBIENT TEMPERATURE T (℃) a
A,Jun,2014
SOT-23 Package Outline Dimensions
MMBT2907
Symbol
A A1 A2 b c D E E1 e e1 L L1 θ
Dimensions In Millimeters
V =-20V CE
T =25 oC a
-20
-30
-40
-50
COLLECTOR CURRENT I (mA) C
-60
2
COLLECTOR POWER DISSIPATION P (mW)
C
10
C ob
1 -0.1
300 250 200 150 100
50 0 0
-1
-10
-20
REVERSE VOLTAGE V (V)
-450uA
-100
-360uA
-50
-0 -0
-1000
-270uA -180uA
I =-90uA
B
-5
-10
-15
-20
COLLECTOR-EMITTER VOLTAGE V (V) CE
V
——
CEsat
I
C
DC CURRENT GAIN h FE
400 300 200 100
0 -1
-1200
tS
VCE=-6V,IC=-150mA,
tf
IB1=- IB2=- 15mA
Min -60 -40 -5
FT2232制作仿真器
Mum计划之MumJTAG——ARM和Blackfin JTAG调试电缆（FT2232电缆）硬件制作距离上次更新已经3个多月了。
这段时间我工作的重点在电磁兼容测试上，这东西估计没有什么人有兴趣吧？其实通过测试很简单，对策也就是那些，就是这事情很烦琐。
幸好我们公司有Schaffner的快瞬、浪涌发生器和ESD枪，在我无数次的实验轰炸下，把某个我设计的产品抗扰度，快瞬由不到1000V提高到4800V（我们公司标准比国标高多了），ESD由不到1000V提高到15000V空气和8000V接触；还有另一个产品，把差模浪涌从炸机提高到1500~2000V，可惜还有待提高。
累死了，光装卸时拧螺钉就拧了能有一千次，后来不行了，申请了个电动螺丝刀……做完测试，我的收获还是很大的，明白了该如何接地、如何屏蔽、如何进行内外互联；相应的，设计产品的风格也变了一些，终于自我感觉入了设计牛X产品的大门了。
下一步还有个可靠性需要摸索，还需努力啊，等加速寿命试验做完了，估计就完成绝世武功目录的学习了，嘿嘿。
感觉这段时间的收获就是在小公司的好处，可以接触到产品设计的每一个细节。
在业余时间，我启动了一个计划——Mum，这是一个用BF系列DSP进行视觉东东开发的计划，分为Mum、MumBurst和MumSW（SW for Silkworm）三个阶段，哈哈，上MOP的同学们可以很快看出来含义。
MumJTAG是整个计划的第一步，这是个FT2232电缆，可以通过OpenOCD调试ARM，通过urjtag和gdbproxy调试Blackfin。
MumJTAG和Hubert Hoegl的USB to JTAG Interface电缆（http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html）是兼容的，但是速度比它快，可以到6MHz，不用它的VID和PID，所以配置文件还需要修改。
至于Blackfin调试，我参考了gnICE （/gf/project/stamp/frs/?action=FrsReleaseBrowse&frs_package_ id=146），但为了和ARM调试兼容，也要修改配置。
FT2232中文资料
FT2232中文资料1 FT2232C概述1.1 电路概览FT2232C是一款USB到UART/FIFO的转换电路，是FTDI公司继第二代FT232BM、FT245BM之后的第三代产品，集成了两片BM芯片的功能。
电路要用48-LD LQFP封装。
FT2232C具有两个多用途的UART/FIFO控制器，可分别配置成不同的工作模式。
一个USB 下游端口转换成两个I/O通道，每个I/O通道相当一个FT232BM或FT245BM，可以单独配置成UART接口或者FIFO接口。
通过对外挂EEPROM的配置，FT2232C还提供一系列新的操作模式，如多协议同步串行机接口，这是专为同步串行协议如JTAG和SPI总线设计的。
还有同步位宽模式、CPU风格的FIFO模式、多协议同步串行机接口模式、MCU主机总线竞争模式及快速光隔离串行机接口模式等。
此外，该电路的驱动能力有很大提高，能够输出较之通常电路3倍的功率，这使得多个电路可能共享总线。
使用FTDI公司提供的虚拟串口（VCP）驱动，对外围接口的使用就像使用PC的标准串口一样。
许多现有软件经过简单重新配置即哥与虚拟串口相接，应用程序与电路间的通信与PC的COM口通信相同。
1.2 电路的特征●只需添加简单配置电路，便可实现由单电路到双通道串/并口的转换；●芯片上集成了全部USB处理协议，使用时不需要另外编写USB固件程序；●2个I/O通道（A/B）相互独立，可配置成2个5V、2个3.3V或一个5V、一个3.3V的逻辑I/O接口；●UART接口支持7或8位数据位，1/2位停止位，奇校验/偶校验/标志位/空位/无奇偶校验；●发送数据的速率为300~1Mb/s(RS-232)或3Mbs(TTL、RS-232/RS-485)；●接口模式和USB描述字符可在外部EEPROM中进行配置，还可以在板子上通过USB对EEPROM进行配置；●4.35V~5.25V的单电压工作围。
1.3 简化功能框图FT2232C的简化功能框图如图1所示，各单元的功能如下：USB收发器单元：提供USB1.1、USB2.0到USB电缆的全速物理接口。
FT2232器件应用
1 FT2232C概述1.1 电路概览FT2232C是一款USB到UART/FIFO的转换电路，是FTDI公司继第二代FT232BM、FT245BM之后的第三代产品，集成了两片BM芯片的功能。
电路要用48-LD LQFP封装。
FT2232C具有两个多用途的UART/FIFO控制器，可分别配置成不同的工作模式。
一个USB 下游端口转换成两个I/O通道，每个I/O通道相当一个FT232BM或FT245BM，可以单独配置成UART接口或者FIFO接口。
通过对外挂EEPROM的配置，FT2232C还提供一系列新的操作模式，如多协议同步串行机接口，这是专为同步串行协议如JTAG和SPI总线设计的。
还有同步位宽模式、CPU风格的FIFO模式、多协议同步串行机接口模式、MCU主机总线竞争模式及快速光隔离串行机接口模式等。
此外，该电路的驱动能力有很大提高，能够输出较之通常电路3倍的功率，这使得多个电路可能共享总线。
使用FTDI公司提供的虚拟串口（VCP）驱动，对外围接口的使用就像使用PC的标准串口一样。
许多现有软件经过简单重新配置即哥与虚拟串口相接，应用程序与电路间的通信与PC的COM口通信相同。
1.2 电路的特征●只需添加简单配置电路，便可实现由单电路到双通道串/并口的转换；●芯片上集成了全部USB处理协议，使用时不需要另外编写USB固件程序；●2个I/O通道（A/B）相互独立，可配置成2个5V、2个3.3V或一个5V、一个3.3V的逻辑I/O接口；●UART接口支持7或8位数据位，1/2位停止位，奇校验/偶校验/标志位/空位/无奇偶校验；●发送数据的速率为300~1Mb/s(RS-232)或3Mbs(TTL、RS-232/RS-485)；●接口模式和USB描述字符可在外部EEPROM中进行配置，还可以在板子上通过USB对EEPROM进行配置；●4.35V~5.25V的单电压工作范围。
1.3 简化功能框图FT2232C的简化功能框图如图1所示，各单元的功能如下：USB收发器单元：提供USB1.1、USB2.0到USB电缆的全速物理接口。
EFM32TG222F32中文资料(Energy Micro)中文数据手册「EasyDatasheet - 矽搜」
2011-05-19 - d0034_Rev0.91
2
芯片中文手册,看全文,戳
初稿
...世界上最节能微控制器
2关于本文档
本文件包含EFM32TG系列微控制器参考材料.所有模块和外围设备EFM32TG系列器件笼统描述.不是所 有模块都存在于所有设备和为每个设备可能会有所不同功能集.这种差异,包括引脚,覆盖在设备 特定数据表.
2.2相关文档
在EFM32TG家庭和ARM Cortex-M3更多文档,能源被发现 微型和ARM网页：
2011-05-19 - d0034_Rev0.91
4
芯片中文手册,看全文,戳
3系统概述
初稿
...世界上最节能微控制器
3.1简介
在EFM32微控制器是世界上最节能微控制器.凭借强大32位ARM Cortex-M3独特组合,创新低功耗 技术,从节能模式,以及多种外设短唤醒时间,该EFM32TG微控制器非常适合于任何电池供电应用 ,以及为需要高性能和低能耗等系统,参见图3.1（第7页）.
该 EFM32T G系 列 单 片 机 革 新 8位 到 32位 市 场 ,一 个
在这两个无与伦比性能和超低功耗组合
主动 - 和睡眠模式. EFM32TG器件功耗低至160μA/ MHz运行中 模式,低至900 nA一个实时计数器运行,欠压和全 RAM和 寄 存 器 防 护 留 .
EFM32T G能 耗 低 ,优 于 其 他 任 何 可 用 8位 ,16位 和 32位 解 决 方 案 .该 EFM32 T G包 括 自 治 区 和 节 能 外 围 设 备 ,高 总 芯 片 级 和 模 拟 集 成 ,以 及 行 业 标 准 32位ARM Cortex-M3处理器性能.
FT2232H D工厂测试实用程序用户指南说明书
Future Technology Devices International Ltd.Application Note AN_127User Guide For FT2232H/D Factory Test UtilityDocument Reference No.: FT_000178Version 1.0Issue Date: 2009-10-20This application note explains how to use the FT2232H/D factory test utility, FT2232_UART, which provides a user interface to program and test the FTDI FT2232H/D devices.Future Technology Devices International Limited (FTDI)Table of Contents1Introduction (2)2Hardware Configuration (3)3Utility Basics (5)3.1Operation (6)4Device EEPROM Parameters (9)4.1Default EEPROM data (9)5Definition of Error Messages (11)6Contact Information (16)Appendix A - Revision History (18)1IntroductionThe FT2232_UART program is intended for use in a FT2232D/H manufacturing test environment. It has a single button user interface and returns a simple pass or fail for USB - RS232 designs. The executable version is hard-coded for use with the default VID and PID. The FT2232H/D default VID/PID is 0403/6010. The source code for this program is provided on the FTDI website at the C# Builder examples page and can be built by VC# 2008. The test program also requires a special cable to operate correctly.The features of FT2232_UART are:1.Auto-detect FT2232D and FT2232H2.Support two testing methods: normal test (uses a RS232 Null Modem cable) and special test (uses acustom cable) to check RI/DCD Pins3.Selection of test only or programming and testing.4.Repeat test feature.The FT2232_UART utility is available as a free download from the FTDI Utilities page of the FTDI website.2Hardware ConfigurationEEPROM Configuration:The FTDI FT2232H/D devices require an external 93C46 EEPROMs organized in 16-bit words. They also support the 93C56 and 93C66 EEPROMs organized in 16-bit words.CABLE Configuration:This utility supports two testing methods. Both require a cable to be manufactured. Users require selecting one test method and manufacturing the appropriate cable. The following details the DB9 female connections for this cable:1.Normal testing cable (RS232 Null cable):DB9 female_1 Pin 3 (TXD) to DB9 female_2 Pin 2 (RXD)DB9 female_1 Pin 2 (RXD) to DB9 female_2 Pin 3 (TXD)DB9 female_1 Pin 7 (RTS) to DB9 female_2 Pin 8 (CTS)DB9 female_1 Pin 8 (CTS) to DB9 female_2 Pin 7 (RTS)DB9 female_1 Pin 6 (DSR) to DB9 female_2 Pin 4 (DTR)DB9 female_1 Pin 5 (GND) to DB9 female_2 Pin 5 (GND)DB9 female_1 Pin 4 (DTR) to DB9 female_2 Pin 6 (DSR)2.Special testing cable:DB9 female_1 Pin 3 (TXD) to DB9 female_2 Pin 2 (RXD)DB9 female_1 Pin 2 (RXD) to DB9 female_2 Pin 3 (TXD)DB9 female_1 Pin 7 (RTS) to DB9 female_2 Pin 8 (CTS)DB9 female_1 Pin 8 (CTS) to DB9 female_2 Pin 7 (RTS)DB9 female_1 Pin 6 (DSR) to DB9 female_2 Pin 4 (DTR)DB9 female_1 Pin 5 (GND) to DB9 female_2 Pin 5 (GND)DB9 female_1 Pin 4 (DTR) to DB9 female_2 Pin 6 (DSR)DB9 female_1 Pin 1(DCD) short to DB9 female_1 Pin 6(DSR) and Pin 9 (RI)DB9 female_2 Pin 1(DCD) short to DB9 female_2 Pin 6(DSR) and Pin 9 (RI)Device connection configuration:Connect the device under test to a PC using a USB cable. Then, depending on the selected test method, connect the RS232 null cable or special cable to the COM port used for testing. This connection is shown in the following diagram3Utility BasicsWhen the FT2232_UART utility is run then the following screen appears:Figure 3-1 FT2232_UART Default GUIThe following sections explain the operation of the GUI shown above.3.1OperationThe FT2232_UART has three functions:Program EEPROM: users can enable or disable the program EEPROM function. The following table describes the functions of this button:Program EEPROM Test Description of operationSelected(default) Update Default data to EEPROMnot selected Do not update EEPROMTable 3.1 EEPROM Data Selection switchFigure 3-2 enable Program EEPROMIf “Program EEPROM” is not selected, then the RS232 function only is tested.Check RI/DCD pins:The default is that this is disabled. This means the utility is set to normal test mode. If enabled then this function puts the utility into a special test mode. This special test mode is a full test of all signals.This function can be enabled/disabled using the “Check RI/DCD Pins” to change the testing methods Check RI/DCD Pins Descriptionnot selected(default) The utility is set to normal mode. Please use theRS232 null cable for testingselected The utility is set to special test mode. Please usethe special cable for testingTable 3.2 Test Method Selection switchFigure 3-3 enable Check RI/DCD PinsRepeat Test: if this function is enabled and “START” is pressed, then the utility will repeat the COM port data commutation testing. If this is not required then disable the “Repeat test” function.Figure 3-4 Enable Repeat test function4Device EEPROM ParametersThe source code for this utility is provided on the FTDI website at the C# Builder examples page and can be built by VC# 2008.The subroutine WriteEEPROM() is available in file “Form1.cs”. Its function is used to program the device external EEPROM.The following sections explain which parameter can be modified using the file “Form1.cs”.4.1Default EEPROM dataIf the device is an FT2232D, the default settings are as below://the EEPROM parameters below can be modified in the file “Form1.cs”.ee2232D.Description = "FT2232D device";ee2232D.Manufacturer = "FTDI";ee2232D.ManufacturerID = "FT";ee2232D.MaxPower = 200;ee2232D.VendorID = 0x0403;ee2232D.ProductID = 0x6010;ee2232D.RemoteWakeup = false;ee2232D.SelfPowered = false;ee2232D.SerialNumber = "FT" + GenSerialNo();//the default serial number is general by current timeIf the device is an FT2232H, the default settings are as below:// the EEPROM parameters below can be modified in the file “Form1.cs”.ee2232h.Description = "FT2232H device";ee2232h.Manufacturer = "FTDI";ee2232h.ManufacturerID = "FT";ee2232h.MaxPower = 200;ee2232h.VendorID = 0x0403;ee2232h.ProductID = 0x6010;ee2232h.RemoteWakeup = false;ee2232h.SelfPowered = false;ee2232h.SerialNumber = "FT" + GenSerialNo();//the default serial number is general by current time5Definition of Error MessagesThe following section shows some error messages which may be displayed if issues occur. It also indicates possible reasons for the failure to help with factory debugging.If the PC cannot detect FT2232H or FT2232D device, please check the device is connected to a PC and the FTDI Driver has been installed.Figure 5-1 Failure message 1If the following message appears, then connect the device to a PC and wait the device to initialize, and press the “START” again.Figure 5-2 Failure massage 2If the following message appears then check that the Null cable is connected correctly or check that the DSR signal schematic design under test.Figure 5-3 Failure message 3If the following message appears then check that the special cable is connected correctly or check the RI signal of the schematic design under test.Figure 5-4 Failure message 4If the following message appears then check that the special cable is connected correctly or check the DCD signal of the schematic design under test.Figure 5-5 Failure message 5If the following message appears then go to /en-us/netframework/default.aspx to download the .NET Framework and install it.Figure 5-6 Failure message 66Contact InformationHead Office – Glasgow, UKFuture Technology Devices International LimitedUnit 1,2 Seaward Place, Centurion Business Park Glasgow G41 1HHUnited KingdomTel: +44 (0) 141 429 2777Fax: +44 (0) 141 429 2758E-mail (Sales) *******************E-mail (Support) *********************E-mail (General Enquiries) *******************Web Site URL Web Shop URL Branch Office – Taipei, TaiwanFuture Technology Devices International Limited (Taiwan) 2F, No. 516, Sec. 1, NeiHu RoadTaipei 114Taiwan , R.O.C.Tel: +886 (0) 2 8791 3570Fax: +886 (0) 2 8791 3576E-mail (Sales) **********************E-mail (Support) ************************E-mail (General Enquiries) **********************Web Site URL Branch Office – Hillsboro, Oregon, USAFuture Technology Devices International Limited (USA) 7235 NW Evergreen Parkway, Suite 600Hillsboro, OR 97123-5803USATel: +1 (503) 547 0988Fax: +1 (503) 547 0987E-Mail (Sales) *********************E-Mail (Support) *********************Web Site URL Branch Office – Shanghai, ChinaFuture Technology Devices International Limited (China) Room 408, 317 Xianxia Road,Shanghai, 200051ChinaTel: +86 21 62351596Fax: +86 21 62351595E-mail (Sales) *********************E-mail (Support)***********************E-mail (General Enquiries) *********************Web Site URL Distributor and Sales RepresentativesPlease visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country.Vinculum is part of Future Technology Devices International Ltd. Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United Kingdom. Scotland Registered Number: SC136640Appendix A - Revision HistoryRevision HistoryVersion 1.0 First Release 20/10/2009。
基于FT2232H的高速数据采集系统设计_王曙
ＦＴＤＩ推 出 的 第 ５ 代 ＵＳＢ－ｔｏ－ＵＡＲＴ／ＦＩＦＯ ＩＣ 支 持 ４８０ Ｍｂ／ｓ ＵＳＢ ２．０ 的 高 速 规 范，并 可 在 各 种 工 业 标 准 的 串 行 或 并 行 接 口 （例 如 ＵＡＲＴ 或 ＦＩＦＯ）下 进 行 配 置。 ＦＴ２２３２Ｈ 提供 两 种 可 配 置 的 接 口，均 可 配 置 为 ＵＡＲＴ、 ＪＴＡＧ、ＳＰＩ、Ｉ２ Ｃ 总 线 或 带 独 立 波 特 率 发 生 器 的 位 响 应 模 式串口。内部集成了 ＵＳＢ 协议引 擎（可 以 控 制 ＵＴＭＩ，处 理 ＵＳＢ ２．０高速接口的各个方面），并 且 集 成 了 整 个 ＵＳＢ 协议。
摘 要：针对各种虚拟仪器对传输速率和开发难度的要求，设计了一种基于新型 ＵＳＢ２．０高速接口的虚拟仪器采集系统。本 系统采用 ＦＴＤＩ公司第五代 ＵＳＢ２．０接口芯片 ＦＴ２２３２Ｈ，利用其异步 ＦＩＦＯ 接口与 ＳＴＭ３２Ｆ１０３的 ＦＳＭＣ 接 口 相 互 传 输 数 据，使用 ＬａｂＶｉｅｗ 设计上位机界面，调用其提供的动态链接库 ＤＬＬ和 ＭＣＵ 固件库，可快速实现高速接口的数据传输。 关键词：ＵＳＢ２．０；ＦＴ２２３２Ｈ；异步 ＦＩＦＯ；ＬａｂＶｉｅｗ；ＦＳＭＣ 中 图 分 类 号 ：ＴＰ２１６．１ 文 献 标 识 码 ：Ａ
信号采集 模 块 和 ＵＳＢ 接 口 模 块 主 要 把 信 号 采 集模块 采 集 到 的 数 据 传 到 ＰＣ 机，也 要 使 ＰＣ 机 的 控
制信息能够传 到 信 号 采 集 模 块 和 ＵＳＢ 接 口 模 块 上，从 而 控制数据采集工作 。其中，ＬａｂＶｉｅｗ 应用程序要能够 对 采 集到的数据进行处理 、显示，以及对下位机采集的控制 。
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DLP-2232H;中文规格书,Datasheet资料
D L P -2232HLEAD-FREED U A L -C H A N NE L H I G H -S P E E D U S B A D A P T E RThe DLP-2232H is DLP Design’s premier USB-to-UART/FIFO interface module based on FTDI’s 5th generation USB 2.0 High Speed (480Mb/s) silicon. The DLP-2232H is manufactured in a lead-free, RoHS-compliant, compact 40-pin, 0.1-inch spaced standard 0.6 inch wide DIP footprint.FEATURES:The DLP-2232H is drop in compatible with the DLP-2232M except for the difference in the VCCIO voltage. The DLP-2232H has a maximum VCCIO of +3.6 Volts, but as inputs it’s IO pins are +5.0 Volt tolerant.The DLP-2232H is shipped from the factory in DLP-2232M compatible mode. Refer to section 2.1 for mode select jumperconfiguration details.The DLP-2232H has the capability of being configured in a variety of industry standard serial or parallel interfaces supporting these features:• Entire USB protocol handled on the module. No USB specific firmware programming required. • USB 2.0 High Speed (480Mbits/Second) and Full Speed (12Mbits/Second) compatible. • Multi-Protocol Synchronous Serial Engine (MPSSE) to simplify synchronous serial protocol (USB to JTAG, I2C, SPI or bit-bang) design.• RS232/RS422/RS485 UART Transfer Data Rate up to 12Mbaud. (RS232 Data Rate limited by external level shifter).• USB to parallel FIFO transfer data rate up to 8 Mbyte/Sec.• Single channel synchronous FIFO mode for transfers up to 25 Mbyte/Sec. • Enhanced bit bang mode interface option with read and write strobes• USB to Fast Serial Interface mode provides a method of communicating with an external device over USB using 4 wires that can have opto-isolators in their path for galvanic isolation • MCU host bus emulation mode uses both ports to emulate a standard 8048/8051 host bus • CPU-style FIFO interface mode simplifies CPU interface design.• FTDI’s royalty-free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases.• Adjustable receive buffer timeout.• Transmit and receive LED drive signals.• FT245B-style FIFO interface option with bidirectional data bus and simple 4 wire handshake interface.• Asynchronous serial UART interface option with full hardware handshaking and modem interface signals.• Fully assisted hardware or X-On / X-Off software handshaking.• UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity. • Auto-transmit enable control for RS485 serial applications using TXDEN pin.• Operational configuration mode and USB Description strings configurable in on-board EEPROM over the USB interface.• Configurable I/O drive strength (4, 8, 12 or 16mA) and slew rate.• Low operating and USB suspend current.• Supports bus powered, self powered and high-power bus powered USB configurations. • UHCI/OHCI/EHCI host controller compatible.• USB Bulk data transfer mode (512 byte packets in High Speed mode).• +3.3V I/O interfacing (+5V Tolerant).• Extended -40°C to 85°C industrial operating temperature range.APPLICATION AREAS:• Upgrading legacy peripherals to USB• Interfacing MCU/PLD/FPGA-based designs to USB• USB to UART (RS232, RS422 or RS485)• USB to FIFO• USB to Fast Serial Interface• USB to JTAG• USB to SPI• USB to I2C• USB to Bit-Bang• USB to CPU target interface (as memory)• USB to MCU (8048/8051 style) host bus emulation• PDA to USB data transfer• USB Smart Card Readers• USB Instrumentation• USB Industrial Control• USB MP3 Player Interface• USB FLASH Card Reader / Writers• Set Top Box PC - USB interface• USB Digital Camera Interface• USB Bar Code Readers• USB audio and low-bandwidth video data transfer• USB hardware modems• USB wireless modemsDRIVER SUPPORT:Royalty-Free Virtual COM Port (VCP) Drivers for:• Windows 2000, Server 2003, Server 2008• Windows XP and XP 64-bit• Windows Vista and Vista 64-bit• Windows 7• Windows CE 4.2, 5.0, and 5.2 based OS• Mac OS-X• Linux 2.6.31 or laterRoyalty-Free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) for:• Windows 2000, Server 2003, Server 2008• Windows XP and XP 64-bit• Windows Vista and Vista 64-bit• Windows 7• Windows CE 4.2, 5.0, and 5.2 based OS• Linux 2.6.31 or laterThe drivers listed above are all available for free download from the DLP Design website and FTDI website .Various third-party drivers are also available for other operating systems; see the FTDI website for details.ABSOLUTE MAXIMUM RATINGS+150°CtoTemperature -65°CStorage•• Ambient Temperature (Power Applied) -40 to +85°C• VCC Supply Voltage -0.5V to +6.00V• DC Input Voltage: Inputs -0.5V to VCC + 0.5V• DC Input Voltage: High-Impedance Bidirectionals -0.5V to VCC + 0.5V• DC Output Current: Outputs 16mAD.C. CHARACTERISTICS (AMBIENT TEMPERATURE: -40 TO 85°C)• VCC Operating-Supply Voltage 4.0 - 5.5V• VCCIO Digital IO Voltage 3.3V• Operating Supply Current 75mA (Normal Operation)500uASuspendUSBSupply•OperatingCurrent1.0 GENERAL DESCRIPTIONThe DLP-2232H USB 2.0 High Speed (480Mb/s) to UART/FIFO uses FTDI’s 5th generation USB silicon. It has the capability of being configured in a variety of industry standard serial or parallel interfaces. The DLP-2232H can be configured for UART, FIFO, Fast serial interface, JTAG, SPI, I2C or bit-bang mode. In addition to these, the DLP-2232H supports a CPU interface FIFO mode and MCU host bus emulation mode.Refer to the FT2232H datasheet for additional detail on how to set up and use these modes.2.0 PIN DESCRIPTIONSThis section describes the operation of the DLP-2232H pins. The function of the I/O pins is determined by the configuration that is stored in the EEPROM connected to the FT2232H IC.The following table details the function of each pin for the specified mode. Note that the convention used throughout this document for active low signals is the signal name followed by a #. Pins marked ** default to tri-stated inputs with an internal 75K Ohm (approx) pull up resistor to VCCIO (3.3V). Pins marked *** may require mode select jumper configuration. This is explained in section 2.1.Table 1: DLP-2232H Pin DefinitionsDLP-2232HPin Pin Functions For Each Supported ModePin #PinNameASYNCSerial(RS232)245 FIFOSYNC245FIFOASYNCBit-bangSYNCBit-bangMPSSEFastSerialI/FCPUTargetHostEmul-ationChannel A40ADBUS0TXD D0 D0 D0 D0 TCK/SKUsesChanB D0 AD039ADBUS1RXD D1 D1 D1 D1 TDI/DO D1 AD1 38ADBUS2RTS# D2 D2 D2 D2 TDO/DI D2 AD2 37ADBUS3CTS# D3 D3 D3 D3 TMS/CS D3 AD3 36ADBUS4DTR# D4 D4 D4 D4 GPIOL0 D4 AD4 35ADBUS5DSR# D5 D5 D5 D5 GPIOL1 D5 AD5 34ADBUS6DCD# D6 D6 D6 D6 GPIOL2 D6 AD6 33ADBUS7RI# D7 D7 D7 D7 GPIOL3 D7 AD7 32 ACBUS0 TXDEN RXF# RXF# ** ** GPIOH0 CS# A831 ACBUS1 **TXE# TXE# WRSTB#WRSTB# GPIOH1 A0 A930 ACBUS2 **RD# RD# RDSTB#RDSTB#GPIOH2 RD# A10 29 ACBUS3 TXLED# WR# WR# ** ** GPIOH3 WR# A1128 ACBUS4 RXLED# SIWUA SIWUA SIWUA SIWUA GPIOH4 SIWUA A1227 ACBUS5**CLKOUT******GPIOH5 **A1326 ACBUS6**OE#******GPIOH6 **A1425 ACBUS7**********GPIOH7 **A15Channel B13 BDBUS0 TXD UsesChan A D0 D0 D0 TCK/SKFSDID0 CS#12 BDBUS1RXD D1D1D1TDI/DIFSCLKD1ALE 11 BDBUS2RTS# D2 D2 D2TDO/DO FSDO D2 RD#10 BDBUS3CTS# D3 D3 D3TMS/CSFSCTSD3WR9 BDBUS4DTR# D4 D4 D4GPIOL0 D4IORDY8 BDBUS5DSR# D5 D5 D5GPIOL1D5CLKOUT7 BDBUS6DCD# D6 D6 D6GPIOL2 D6 I/O0 6 BDBUS7RI# D7 D7 D7GPIOL3 D7 1/01 5 BCBUS0TXDEN RXF# ** ** GPIOH0** 4 BCBUS1**TXE# GPIOH1**3 BCBUS2** RD# GPIOH2**2 BCBUS3RXLED# WR GPIOH3**1 BCBUS4TXLED# SIWUB GPIOH4**24 BCBUS5** ** ** **GPIOH5 ** **171 BCBUS6** ** ** **GPIOH6 ** **182BCBUS7PWRSAV#GPIOH7**Support PinsPin Function14 GND GROUND15 GND GROUND16 VCCSWVCCSW - Use for powering external devices at +3.3V. This voltage is derived from theUSB input +5.0V. It is switched off by the FT2232H PWREN# pin when the device is notenumerated. 500mA is the maximum current available to the USB adapter and targetelectronics if the USB device is configured for high power.19 EXTVCC EXTVCC - Use for applying main power (+4.5 to +5.25 V) to the module. Connect to PORTVCC if the module is to be powered by the USB port (typical configuration).20 PORTVCCPORTVCC - Power from the USB port (typically +5.0 V). Connect to EXTVCC if themodule is to be powered by the USB port (typical configuration). 500mA is themaximum current available to the USB adapter and target electronics if the USB deviceis configured for high power.21 VCCUSBVCCUSB – Filtered power from the USB port (typically +5.0 V). 500mA is the maximumcurrent available to the USB adapter and target electronics if the USB device isconfigured for high power.22 GND GROUND23 GND GROUNDNotes:1. Pin 17 is configured via jumper JP2. Refer to section 2.1 for more details.2. Pin 18 is configured via jumper JP3. Refer to section 2.1 for more details.2.1 JUMPER CONFIGURATIONThe DLP-2232H module was design so that it can be used as a drop in replacement for the DLP-2232M module. The DLP-2232H provides a high speed USB interface compared to the DLP-2232M module’s full speed USB interface.The mode select jumpers (JP1 – JP3) are identified above and on the silkscreen. They are located in the center and top of the DLP-2232H module. These three jumpers control the usage of the DLP-2232H module’s pins 17 and 18 as follows:JP1 (supports option for VCCIO +3.3V to be supplied internally):1. Shunt installed on pins 1 and 2: VCCIO provided internally. Insure that either JP2shunt is in position 1, or no external voltage is applied to pin 17.2. Shunt not installed on pins 1 and 2: VCCIO applied externally (compatible withDLP-2232M). VCCIO must not exceed +3.6V or module can be damaged.JP2 (controls pin 17):1. Shunt installed on pins 1 and 2: BCBUS6 signal available on pin 17.2. Shunt installed on pins 2 and 3: VCCIO input available on pin 17 (compatible withDLP-2232M). VCCIO must not exceed +3.6V or module can be damaged. JP3 (controls pin 18):1. Shunt installed on pins 1 and 2: BCBUS7 signal available on pin 18.2. No shunt installed: Pin 18 unconnected (compatible with DLP-2232M).2.2 TIMING DIAGRAMS - 245 FIFO MODEThe following diagram details the FT2232H operation in 245 FIFO asynchronous mode. For detailed timing on the remaining modes refer to the FT2232H datasheet from FTDI.T I M E D E S C R I P T I O N M I N M A X U N I TT1 RD# Active Pulse Width 50 -nS T2 RD# to RD# Pre-Charge T5 + T6 - nST3 RD# Active to Valid Data* 20 50nSnS T4 Valid Data Hold Time from RD# Inactive* 0 -T5 RD# Inactive to RXF# output active 0 25nS T6 RXF# Inactive After RD Cycle 33 67nST I M E D E S C R I P T I O N M I N M A X U N I TnS T7 WR Active Pulse Width 10 -nS T8 WR to WR Pre-Charge Time 50 -nS T9 Valid Data Setup to WR Falling Edge* 20 -nS T10 Valid Data Hold Time from WR Inactive* 10 -T11 WR Inactive to TXE# 10 25nSnS T12 TXE# Inactive After WR Cycle 49 84*Load = 30pF3.0 APPLICATION NOTESUSB devices transfer data in packets. If data is to be sent from the PC, a packet is built up by the application program and is sent via the device driver to the USB scheduler. This scheduler adds a request to the list of tasks that the USB host controller will perform. This will typically take at least 1 millisecond to execute because it will not pick up the new request until the next USB frame (the frame period is 1 millisecond). There is, therefore, sizeable overhead (depending upon your required throughput) associated with moving data from the application to the USB device. If data is sent one byte at a time by an application, this will severely limit the overall throughput of the system.It must be stressed that in order to achieve maximum throughput, application programs should send or receive data using buffers and not individual characters.4.0 DRIVER SOFTWAREFTDI's VCP (Virtual COM Port) USB driver files are provided royalty free on the condition that they are only used with designs incorporating an FTDI device (i.e. the FT2232H and DLP-2232H). The latest version of the drivers can be downloaded from either or .The CDM driver download file is a combined set of drivers for the Windows operating system and contains both the VCP and D2XX driver versions. To download, simply unzip the file to a folder on your PC. (The drivers can coexist on the same floppy disk or folder since the INF files determine which set of drivers to load for each operating-system version.) Once loaded, the VCP drivers will allow your application software—running on the host PC—to communicate with the DLP-2232H as though it were connected to a COM (RS-232) port.In addition to VCP drivers, FTDI's D2XX direct drivers for Windows offer an alternative solution to the VCP drivers that allow application software to interface with the FT2232H device using a DLL instead of a Virtual COM Port. The architecture of the D2XX drivers consists of a Windows WDM driver that communicates with the FT2232H device via the Windows USB stack and a DLL that interfaces with the application software (written in VC++, C++ Builder, Delphi, VB, etc.) to the WDM driver.The D2XX direct drivers add support for simultaneous access and control of multiple DLP-2232H devices. The extended open function (FT_OpenEx) allows the device to be opened either by its product description or serial number, both of which can be programmed to be unique. The list devices function (FT_ListDevices) allows the application software to determine which devices are currently available for use, again by either product description or serial number.Download FTDI Application Notes AN_103, AN_104, and AN_119 for detailed instructions on how to install the drivers on Windows XP, Vista, and 7 platforms.5.0 EEPROM WRITE UTILITYThe DLP-2232H has the option to accept manufacturer-specific information that is written into EEPROM memory. Parameters that can be programmed include the VID and the PID identifiers, the manufacturer's product string and a serial number.MPROG is the EEPROM programming utility for the FT2232H device. You must install the latest release of the CDM drivers in order to run this application. If you have CDM drivers installed on the PC that is to perform the EEPROM write process, you can run MPROG and update the EEPROM contents with either mode (VCP or D2XX) active.6.0 QUICK START GUIDEThis guide requires the use of a Windows XP/Vista/7 PC that is equipped with a USB port.1. Configure mode select jumpers using the shunts provided. Refer to section2.1 on page 5.2. Download the latest CDM device drivers from either or. Unzip the drivers into a folder on the hard drive.3. Connect the DLP-2232H module to the PC via a USB ‘A’ to mini-B cable. This actioninitiates the loading of the USB drivers. When prompted, select the folder where the device drivers were stored in Step 1. Windows will then complete the installation of the device drivers for the DLP-2232H module. The next time the DLP-2232H module is attached, the host PC will immediately load the correct drivers without any prompting. Reboot the PC if prompted to do so.At this point, the DLP-2232H is ready for use. Note that if the DLP-2232H is configured for 245 FIFO mode that it will appear non-responsive if data sent from the host PC is not read by an attached microcontroller, microprocessor, DSP, FPGA, ASIC, etc.7.0 PIN LOCATIONSTop View(Interface Headers on bottom of PCB)8.0 PIN USAGE EXAMPLESThe following tables highlight two possible configurations for the DLP-2232H module. There are numerous additional combinations available. For the complete DLP-2232H pin list refer to the pin descriptions in section 2.0.CASE 1: Port A: 245 FIFO Synchronous, Port B 245 FIFO AsynchronousP I N#P O R T A P A R A L L E L S Y N C,P O R T B P A R A L L E L A S Y N C S I G N A L U S A G E D E S C R I P T I O N1 SIWUB –The Port B Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode (PWREN# = 1) and remote wakeup is enabled in the EEPROM, strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation (PWREN# = 0), if this pin is strobed low any data in the device TX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimize USB transfer speed for some applications. Tie this pin to VCCIO if not used.2 PORT B WR# - When taken from a high to a low state, WR reads the 8 data lines and writes the byte into the FIFO’s transmit buffer. Data written to the transmit buffer is sent to the host PC within the TX buffer timeout value (default 16mS) and placed in the buffer that was created when the USB port was opened.3 PORT B RD# - When pulled low, RD# takes the 8 data lines from a high-impedance state to the current byte in the FIFO’s buffer. Taking RD# high returns the data pins to a high- impedance state and prepares the next byte (if available) in the FIFO to be read.4 PORT B TXE# - Transmit Buffer Empty: When high, do not write data into the FIFO. When low, data can be written into the FIFO by toggling WR. During reset this signal pin is tri-state. Data is latched into the FIFO on the falling edge of the WR pin.5 PORT B RXF# - Receive Buffer Full : When low, at least 1 byte is present in the FIFO’s receive buffer and is ready to be read with RD#. RXF# goes high when the receive buffer is empty. During reset this signal pin is tri-state. If the Remote Wakeup option is enabled in the internal EEPROM, during USB Suspend Mode (PWREN#=1) RXF# becomes an input. This can be used to wake up the USB host from Suspend Mode by strobing this pin low for a minimum of 20ms which will cause the device to request a resume on the USB bus.6 PORT B DB7 – Port B FIFO Data Bus Bit 77 PORT B DB6 – Port B FIFO Data Bus Bit 68 PORT B DB5 – Port B FIFO Data Bus Bit 59 PORT B DB4 – Port B FIFO Data Bus Bit 410 PORT B DB3 – Port B FIFO Data Bus Bit 311 PORT B DB2 – Port B FIFO Data Bus Bit 212 PORT B DB1 – Port B FIFO Data Bus Bit 113 PORT B DB0 – Port B FIFO Data Bus Bit 014 GROUND15 GROUND19 EXTVCC - Use for applying main power (4.5 to 5.25 volts) to the module. Connect to PORTVCC if the module is to be powered by the USB port (typical configuration).20 PORTVCC - Power from the USB port. Connect to EXTVCC if the module is to be powered by the USB port (typical configuration). 500mA is the maximum current available to the USB adapter and target electronics if the USB device is configured for high power.分销商库存信息: DLP-DESIGNDLP-2232H。
FT2232中文资料
FT2232中文资料FT2232中文资料1 FT2232C概述1.1 电路概览FT2232C是一款USB到UART/FIFO的转换电路，是FTDI公司继第二代FT232BM、FT245BM 之后的第三代产品，集成了两片BM芯片的功能。
电路要用48-LD LQFP封装。
FT2232C具有两个多用途的UART/FIFO控制器，可分别配置成不同的工作模式。
一个USB 下游端口转换成两个I/O通道，每个I/O通道相当一个FT232BM或FT245BM，可以单独配置成UART接口或者FIFO接口。
通过对外挂EEPROM的配置，FT2232C还提供一系列新的操作模式，如多协议同步串行机接口，这是专为同步串行协议如JTAG和SPI总线设计的。
还有同步位宽模式、CPU风格的FIFO模式、多协议同步串行机接口模式、MCU主机总线竞争模式及快速光隔离串行机接口模式等。
此外，该电路的驱动能力有很大提高，能够输出较之通常电路3倍的功率，这使得多个电路可能共享总线。
使用FTDI公司提供的虚拟串口（VCP）驱动，对外围接口的使用就像使用PC的标准串口一样。
许多现有软件经过简单重新配置即哥与虚拟串口相接，应用程序与电路间的通信与PC的COM口通信相同。
1.2 电路的特征●只需添加简单配置电路，便可实现由单电路到双通道串/并口的转换；●芯片上集成了全部USB处理协议，使用时不需要另外编写USB固件程序；●2个I/O通道（A/B）相互独立，可配置成2个5V、2个3.3V或一个5V、一个3.3V的逻辑I/O接口；●UART接口支持7或8位数据位，1/2位停止位，奇校验/偶校验/标志位/空位/无奇偶校验；●发送数据的速率为300~1Mb/s(RS-232)或3Mbs(TTL、RS-232/RS-485)；●接口模式和USB描述字符可在外部EEPROM中进行配置，还可以在板子上通过USB对EEPROM进行配置；●4.35V~5.25V的单电压工作范围。
AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes
Use of FTDI devices in life support and/or safety applications is entirely at the user’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expenseresulting from such use.Future Technology Devices International Limited (FTDI)Unit1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH United KingdomTel.: +44 (0) 141 429 2777 Fax: + 44 (0) 141 429 2758E-Mail (Support): support1@ Web: Copyright © 2010-11 Future Technology Devices International LimitedFuture Technology Devices International Ltd.Application Note AN_108Command Processor for MPSSE and MCU Host Bus Emulation ModesDocument Reference No.: FT_000109Version 1.5Issue Date: 2011-09-09This document provides details of the op-codes used to control the Multi Purpose SynchronousSerial Engine (MPSSE) mode of the FT2232D, FT232H, FT2232H and FT4232H devices.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81TABLE OF CONTENTS1Overview (4)2Data and Clock Definition (5)2.1Data bit Definition (5)2.2Clock Operation (6)3Command Definitions (7)3.1BadCommands (7)3.2Data Shifting Command Overview (7)3.3MSB FIRST (8)3.3.1Clock Data Bytes Out on +ve clock edge MSB first (no read) (8)3.3.2Clock Data Bytes Out on -ve clock edge MSB first (no read) (9)3.3.3Clock Data Bits Out on +ve clock edge MSB first (no read) (9)3.3.4Clock Data Bits Out on -ve clock edge MSB first (no read) (9)3.3.5Clock Data Bytes In on +ve clock edge MSB first (no write) (9)3.3.6Clock Data Bytes In on -ve clock edge MSB first (no write) (10)3.3.7Clock Data Bits In on +ve clock edge MSB first (no write) (10)3.3.8Clock Data Bits In on -ve clock edge MSB first (no write) (10)3.3.9Clock Data Bytes In and Out MSB first (11)3.3.10Clock Data Bits In and Out MSB first (11)3.4LSB FIRST (11)3.4.1Clock Data Bytes Out on +ve clock edge LSB first (no read) (12)3.4.2Clock Data Bytes Out on -ve clock edge LSB first (no read) (13)3.4.3Clock Data Bits Out on +ve clock edge LSB first (no read) (13)3.4.4Clock Data Bits Out on -ve clock edge LSB first (no read) (13)3.4.5Clock Data Bytes In on +ve clock edge LSB first (no write) (13)3.4.6Clock Data Bytes In on -ve clock edge LSB first (no write) (14)3.4.7Clock Data Bits In on +ve clock edge LSB first (no write) (14)3.4.8Clock Data Bits In on -ve clock edge LSB first (no write) (14)3.4.9Clock Data Bytes In and Out LSB first (15)3.4.10Clock Data Bits In and Out LSB first (15)3.5TMS Commands (16)3.5.1Clock Data to TMS pin (no read) (16)3.5.2Clock Data to TMS pin with read (16)3.6Set / Read Data Bits High / Low Bytes (17)3.6.1Set Data bits LowByte (17)3.6.2Set Data bits High Byte (17)Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 813.6.3Read Data bits LowByte (17)3.6.4Read Data bits HighByte (17)3.7Loopback Commands (18)3.7.1Connect TDI to TDO for Loopback (18)3.7.2Disconnect TDI to TDO for Loopback (18)3.8Clock Divisor (19)3.8.1Set TCK/SK Divisor (FT2232D) (19)0xFFFF 91.553 Hz (19)3.8.2Set clk divisor (FT232H/FT2232H/FT4232H) (20)4Instructions for CPU mode (21)4.1Overview (21)4.2CPUMode Read Short Address (21)4.3CPUMode Read Extended Address (21)4.4CPUMode Write Short Address (21)4.5CPUMode Write Extended Address (21)5Instructions for use in both MPSSE and MCU Host Emulation Modes (22)5.1Send Immediate (22)5.2Wait On I/O High (22)5.3Wait On I/O Low (22)6FT232H, FT2232H & FT4232H ONLY (23)6.1Disable Clk Divide by 5 (23)6.2Enable Clk Divide by 5 (23)6.3Enable 3 Phase Data Clocking (24)6.4Disable 3 Phase Data Clocking (24)6.5Clock For n bits with no data transfer (24)6.6Clock For n x 8 bits with no data transfer (24)6.7Clk continuously and Wait On I/O High (24)6.8Clk continuously and Wait On I/O Low (24)6.9Turn On Adaptive clocking (25)6.10Turn Off Adaptive clocking (25)6.11Clock For n x 8 bits with no data transfer or Until GPIOL1 isHigh 256.12Clock For n x 8 bits with no data transfer or Until GPIOL1 is Low257FT232H ONLY (26)Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 7.1Set I/O to only drive on a ‘0’ and tristate on a ‘1’ (26)8Contact Information (27)Appendix A – Revision History (29)1OverviewThe FT2232D, FT232H, FT2232H and FT4232H incorporate a command processor called the Multi-Protocol Synchronous Serial Engine (MPSSE). The purpose of the MPSSE command processor is to communicate with devices which use synchronous protocols (such as JTAG or SPI) in an efficient manner. The FT2232x MCU Host Bus Emulation mode also uses the MPSSE technology to make the chip emulate a standard 8048/8051 MCU host bus.The MPSSE Command Processor unit is controlled using a SETUP command. Various commands are used to clock data out of and into the chip, as well as controlling the other I/O lines.If disabled the MPSSE is held in reset and will not have any effect on the rest of the chip. When enabled, it will take its commands and data from the OUT data written to the OUT pipe in the chip.This is done by simply using the normal WRITE command, as if data were being written to a COM port. Any data read will be passed back in the normal IN pipe. This is done using the normal READ command, as if data were being read from a COM port.NOTE: To ensure that the device driver will not issue IN requests if the buffer is unable to accept data, add a call to FT_SetFlowControl prior to entering MPSSE or MCU Host Bus modes.2Data and Clock Definition2.1Data bit DefinitionThe following table shows the pins used and pin functions enabled in MPSSE mode for each device.2.2Clock OperationThe TCK/CK output pin will do an XOR of the current state of the CLK pin twice. This means that if the clock pin is set low, then the clock will go high then low to be 1 clock cycle. If the clock pin were set high, then the clock will go low then high to be 1 clock cycle.The implications of this are:If the clock starts at an idle state of logic 0:Data can be clocked out on a –ve clock edge.Data can be clocked in on a +ve clock edge.If the clock starts at an idle state of logic 1:Data can be clocked out on a +ve clock edge.Data can be clocked in on a -ve clock edge.3Command DefinitionsThe following section will define the opcodes required to perform specific functions.3.1BadCommandsIf the device detects a bad command it will send back 2 bytes to the PC.0xFA,followed by the byte which caused the bad command.If the commands and responses that are read/written have got out of sequence then this will tell you what the first pattern was that it detected an error. The error may have occurred before this, (for example sending the wrong amount of data after a write command) and will only trigger when bit 7 of the rogue command is high.3.2Data Shifting Command OverviewThe data shifting commands are made up of the following definitions:Bit 0 : -ve CLK on writeBit 1 : bit mode = 1 else byte modeBit 2 : -ve CLK on readBit 3 : LSB first = 1 else MSB firstBit 4 : Do write TDIBit 5 : Do read TDOBit 6 : Do writeTMSBit 7 : 0The write commands to TDI take effect when bits 7 and 6 are '0'. Read TDO will operate with TMS output or TDI output or on its own.3.3MSB FIRSTThe following commands are used when data is transferred with the Most Significant Bit (MSB) first.3.3.1Clock Data Bytes Out on +ve clock edge MSB first (no read)Use if CLK starts at '1'0x10,LengthL,LengthH,Byte1..Byte65536 (max)This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The data is sent MSB first. Bit 7 of the first byte is placed on TDI/D0 then the CLK pin is clocked. The data will change to the next bit on the rising edge of the CLK pin. No data is clocked into the device on TDO/DI.3.3.2Clock Data Bytes Out on -ve clock edge MSB first (no read)Use if CLK starts at '0'0x11,LengthL,LengthH,Byte1..Byte65536 (max)This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The data is sent MSB first. Bit 7 of the first byte is placed on TDI/DO then the CLK pin is clocked. The data will change to the next bit on the falling edge of the CLK pin. No data is clocked into the device TDO/DI.3.3.3Clock Data Bits Out on +ve clock edge MSB first (no read)Use if CLK starts at '1'0x12,Length,Byte1This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data is sent MSB first. Bit 7 of the data byte is placed onTDI/DO then the CLK pin is clocked. The data will change to the next bit on the rising edge of the CLK pin. No data is clocked into the device on TDO/DI.3.3.4Clock Data Bits Out on -ve clock edge MSB first (no read)Use if CLK starts at '0'0x13,Length,Byte1This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data is sent MSB first. Bit 7 of the data byte is placed onTDI/DO then the CLK pin is clocked. The data will change to the next bit on the falling edge of the CLK pin. No data is clocked into the device on TDO/DI.3.3.5Clock Data Bytes In on +ve clock edge MSB first (no write)0x20,LengthL,LengthHThis will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The first bit in will be the MSB of the first byte and so on. The data will be sampled on the rising edge of the CLK pin. No data is clocked out of the device on TDI/DO.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.3.6Clock Data Bytes In on -ve clock edge MSB first (no write)0x24,LengthL,LengthHThis will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of 0x0000will do 1 byte and a length of 0xffff will do 65536 bytes. The first bit in will be the MSB of the first byte and so on. The data will be sampled on the falling edge of the CLK pin. No data is clocked out of the device on TDI/DO.3.3.7Clock Data Bits In on +ve clock edge MSB first (no write)TDO/DI sampled just prior to rising edge0x22,Length,This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted up so that the first bit in may not be in bit 7 but from 6 downwards depending on the number of bits to shift (i.e. a length of 1 bit will have the databit sampled in bit 0 of the byte sent back to the PC). The data will be sampled on the rising edge of the CLK pin. No data is clocked out of the device on TDI/DO.3.3.8Clock Data Bits In on -ve clock edge MSB first (no write)TDO/DI sampled just prior to falling edge0x26,Length,This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted up so that the first bit in may not be in bit 7 but from 6 downwards depending on the number of bits to shift (i.e. a length of 1 bit will have the databit sampled in bit 0 of the byte sent back to the PC). The data will be sampled on the falling edge of the CLK pin. No data is clocked out of the device on TDI/DO.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.3.9Clock Data Bytes In and Out MSB firstThe following commands allow for data to be clocked in and out at the same time most significant bit first.0x31, out on -ve edge, in on +ve edgeLengthL,LengthH,Byte1..Byte65536 (max)or0x34, out on +ve edge, in on -ve edgeLengthL,LengthH,Byte1..Byte65536 (max)3.3.10Clock Data Bits In and Out MSB firstThe following commands allow for data to be clocked in and out at the same time most significant bit first.0x33, out on -ve edge, in on +ve edgeLengthByteor0x36, out on +ve edge, in on -ve edgeLengthByte3.4LSB FIRSTThe following commands are used when data is transferred with the Least Significant Bit (LSB) first.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.4.1Clock Data Bytes Out on +ve clock edge LSB first (no read)Use if CLK starts at '1'0x18,LengthL,LengthH,Byte1..Byte65536 (max)This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The data is sent LSB first. Bit 0 of the first byteis placed on TDI/DO then the CLK pin is clocked. The data will change to the next bit on the rising edge of the CLK pin. No data is clocked into the device on TDO/DI.3.4.2Clock Data Bytes Out on -ve clock edge LSB first (no read)Use if CLK starts at '0'0x19,LengthL,LengthH,Byte1..Byte65536 (max)This will clock out bytes on TDI/DO from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The data is sent LSB first. Bit 0 of the first byte is placed on TDI/DO then the CLK pin is clocked. The data will change to the next bit on the falling edge of the CLK pin. No data is clocked into the device on TDO/DI.3.4.3Clock Data Bits Out on +ve clock edge LSB first (no read)Use if CLK starts at '1'0x1A,Length,Byte1This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data is sent LSB first. Bit 0 of the data byte is placed onTDI/DO then the CLK pin is clocked. The data will change to the next bit on the rising edge of the CLK pin. No data is clocked into the device on TDO/DI.3.4.4Clock Data Bits Out on -ve clock edge LSB first (no read)Use if CLK starts at '0'0x1B,Length,Byte1This will clock out bits on TDI/DO from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data is sent LSB first. Bit 0 of the data byte is placed onTDI/DO then the CLK pin is clocked. The data will change to the next bit on the falling edge of the CLK pin. No data is clocked into the device on TDO/DI.3.4.5Clock Data Bytes In on +ve clock edge LSB first (no write)0x28,LengthL,LengthHThis will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The first bit in will be the LSB of the first byte and so on. The data will be sampled on the rising edge of the CLK pin. No data is clocked out of the device on TDI/DO.3.4.6Clock Data Bytes In on -ve clock edge LSB first (no write)0x2C,LengthL,LengthHThis will clock in bytes on TDO/DI from 1 to 65536 depending on the Length bytes. A length of 0x0000 will do 1 byte and a length of 0xffff will do 65536 bytes. The first bit in will be the LSB of the first byte and so on. The data will be sampled on the falling edge of the CLK pin. No data is clocked out of the device on TDI/DO.3.4.7Clock Data Bits In on +ve clock edge LSB first (no write)TDO/DI sampled just prior to rising edge0x2A,Length,This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted down so that the first bit in may not be in bit 0 but from 1 upwards depending on the number of bits to shift (i.e. a length of 1 bit will have the data bit sampled in bit 7 of the byte sent back to the PC). The data will be sampled on the rising edge of the CLK pin. No data is clocked out of the device on TDI/DO.3.4.8Clock Data Bits In on -ve clock edge LSB first (no write)TDO/DI sampled just prior to falling edge0x2E,Length,This will clock in bits on TDO/DI from 1 to 8 depending on the Length byte. A length of 0x00 will do 1 bit and a length of 0x07 will do 8 bits. The data will be shifted down so that the first bit in may not be in bit 0 but from 1 upwards depending on the number of bits to shift (i.e. a length of 1 bit will have the data bit sampled in bit 7 of the byte sent back to the PC). The data will be sampled on the falling edge of the CLK pin. No data is clocked out of the device on TDI/DO.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.4.9Clock Data Bytes In and Out LSB firstThe following commands allow for data to be clocked in and out at the same time least significant bit first.0x39, out on -ve edge, in on +ve edgeLengthL,LengthH,Byte1..Byte65536 (max)or0x3C, out on +ve edge, in on -ve edgeLengthL,LengthH,Byte1..Byte65536 (max)3.4.10Clock Data Bits In and Out LSB firstThe following commands allow for data to be clocked in and out at the same time least significant bit first.0x3B, out on -ve edge, in on +ve edgeLengthByteor0x3E, out on +ve edge, in on -ve edgeLengthByte3.5TMS CommandsThe following commands are primarily intended for use in JTAG interfaces where the TMS signal has to be controlled to navigate the JTAG state machine.3.5.1Clock Data to TMS pin (no read)0x4A or 0x4BLength,Byte1This will send data bits 6 down to 0 to the TMS pin using the LSB or MSB and -ve or +ve clk , depending on which of the lower bits have been set.0x4A : TMS with LSB first on +ve clk edge - use if clk is set to '1'0x4B : TMS with LSB first on -ve clk edge - use if clk is set to '0'Bit 7 of the Byte1 is passed on to TDI/DO before the first clk of TMS and is held static for the duration of TMS clocking. No read operation will take place.3.5.2Clock Data to TMS pin with read0x6A or 0x6B or 0x6E or 0x6FLength,Byte1This will send data bits 6 down to 0 to the TMS pin using the LSB or MSB and -ve or +ve clk , depending on which of the lower bits have been set.0x6A : TMS with LSB first on +ve clk edge, read on +ve edge - use if clk is set to '1'0x6B : TMS with LSB first on -ve clk edge, read on +ve edge - use if clk is set to '0'0x6E : TMS with LSB first on +ve clk edge, read on -ve edge - use if clk is set to '1'0x6F : TMS with LSB first on -ve clk edge, read on -ve edge - use if clk is set to '0'Bit 7 of the Byte1 is passed on to TDI/DO before the first clk of TMS and is held static for the duration of TMS clocking. The TDO/DI pin is sampled for the duration of TMS and a byte containing the data is passed back at the end of TMS clocking.3.6Set / Read Data Bits High / Low BytesThe following commands are used to set the initial direction and logic state of the pins when first entering MPSSE mode. They are also use to set or read GPIO pins. The low byte would be ADBUS 7-0, and the high byte is ACBUS 7-0.3.6.1Set Data bits LowByte0x80,0xValue,0xDirectionThis will setup the direction of the first 8 lines and force a value on the bits that are set as output. A 1 in the Direction byte will make that bit an output.3.6.2Set Data bits High Byte0x82,0xValue,0xDirectionThis will setup the direction of the high 8 lines and force a value on the bits that are set as output. A 1 in the Direction byte will make that bit an output.3.6.3Read Data bits LowByte0x81,This will read the current state of the first 8 pins and send back 1 byte.3.6.4Read Data bits HighByte0x83,This will read the current state of the high 8 pins and send back 1 byte.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 813.7Loopback CommandsIf loopback is enabled the TDI/DO and TDO/DI pins are internally connected to allow for testing data transfer without an external device.3.7.1Connect TDI to TDO for Loopback0x84,This will connect the TDI/DO output to the TDO/DI input for loopback testing.3.7.2Disconnect TDI to TDO for Loopback0x85,This will disconnect the TDI output from the TDO input for loopback testing.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.8Clock DivisorThe following section defines how to set the speed at which data is clocked in or out of the device.3.8.1Set TCK/SK Divisor (FT2232D)0x86,0xValueL,0xValueHThis will set the clock divisor. The TCK/SK always has a duty cycle of 50%, except between commands where it will remain in its initial state. The initial state is set using the Set Data Bits Low Byte command (0x80). For example, to use it in JTAG mode you would issue:-0x80 Set Data Bits Low Byte0x08 TCK/SK, TDI/D0 low, TMS/CS high0x0B TCK/SK, TDI/D0, TMS/CS output, TDO/DI and GPIOL0 -> GPIOL3 inputThe clock will then start low. When the MPSSE is sent a command to clock bits (or bytes) it will make the clock go high and then back low again as 1 clock period. For TMS/CS commands, a 0x4B command would be used for no read, and a 0x6B command for TMS/CS with read. For clocking data out on TDI/DO withno read of TDO/DI, a 0x19 command would be used for bytes and 0x1B for bits. To read from TDO/DIwith no data sent on TDI/DO a 0x28 command would be used for bytes and 0x2A for bits. To scan in and out at the same time a 0x39 command would be used for bytes and 0x3B for bits.The TCK/SK frequency can be worked out using the following algorithm:TCK/SK period = 12MHz / (( 1 +[(0xValueH * 256) OR 0xValueL] ) * 2)For example:Value TCK/SK Max0x0000 6 MHz0x0001 3 MHz0x0002 2 MHz0x0003 1.5 MHz0x0004 1.2 MHz............ ..............0xFFFF 91.553 HzDocument Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 3.8.2Set clk divisor (FT232H/FT2232H/FT4232H)The TCK/CK clock output pin has a front stage divide by 5 from the 60 MHz internal clock for backward compatibility with the FT2232D device. See command 0x8A for disabling the divide by 5.0x86,0xValueL,0xValueH,This will set the clock divisor.The TCK is always 50% duty cycle (except between commands where it will remain in its initial state).The initial state is set using the Set Data bits LowByte command. For example for using it in JTAG mode you would issue:0x80 Set Data Bits Low Byte0x08 TCK TDI low, TMS high0x0B TCK, TDI, TMS output, TDO and GPIOL0-> GPIOL3 inputThe clock will start low. When the MPSSE is sent a command to clock bits or bytes it will make the clockgo high and then back low again as 1 clock period. For TMS commands you would use command 0x4B for no read and 0x6B for TMS with read. For clocking data out on TDI with no read of TDO, you would use command 0x19 for bytes and 0x1B for bits. To read from TDO with no data sent on TDI you would use command 0x28 for bytes and 0x2A for bits. To scan in and out at the same time you would use command 0x39 for bytes and 0x3B for bits.For example with the divide by 5 set as on:The TCK frequency can be worked out by the following algorithm :TCK period = 12MHz / (( 1 +[ (0xValueH * 256) OR 0xValueL] ) * 2)value TCK max0x0000 6 MHz0x0001 3 MHz0x0002 2 MHz0x0003 1.5 MHz0x0004 1.2 MHz........0xFFFF 91.553 HzFor example with the divide by 5 set as off:The TCK frequency can be worked out by the following algorithm :TCK period = 60MHz / (( 1 +[ (0xValueH * 256) OR 0xValueL] ) * 2)value TCK max0x0000 30 MHz0x0001 15 MHz0x0002 10 MHz0x0003 7.5 MHz0x0004 6 MHz........0xFFFF 457.763 HzDocument Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 4Instructions for CPU mode4.1OverviewIn this mode the chip emulates a CPU style of interface with:a) a multiplexed 8 bit address and data busb) an extended 8 bit address busc) CS#, ALE, WR#, RD# and OSC signalsd) 2 I/O lines that can be used as extra I/O or to wait for IRQs4.2CPUMode Read Short Address0x90,0xAddrLowThis will read 1 byte from the target device.4.3CPUMode Read Extended Address0x91,0xAddrHigh0xAddrLowThis will read 1 byte from the target device.4.4CPUMode Write Short Address0x92,0xAddrLow,0xDataThis will write 1 byte from the target device.4.5CPUMode Write Extended Address0x93,0xAddrHigh,0xAddrLow,0xDataThis will write 1 byte from the target device.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 5Instructions for use in both MPSSE and MCU Host Emulation Modes 5.1Send Immediate0x87,This will make the chip flush its buffer back to the PC.5.2Wait On I/O High0x88,This will cause the MPSSE controller to wait until GPIOL1 (JTAG) or I/O1 (CPU) is high. Once it is detected as high, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes high.5.3Wait On I/O Low0x89,This will cause the controller to wait until GPIOL1 (JTAG) or I/O1 (CPU) is low. Once it is detected as low, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes low.Document Reference No.: FT_000109Command Processor for MPSSE and MCU Host Bus Emulation ModesApplication Note AN_108 Version 1.5Clearance No.: FTDI# 81 6FT232H, FT2232H & FT4232H ONLYThe commands in this section apply only to the FT232H, FT2232H and FT4232H devices.6.1Disable Clk Divide by 50x8AThis will turn off the divide by 5 from the 60 MHz clock.6.2Enable Clk Divide by 50x8BThis will turn on the divide by 5 from the 60 MHz clock to give a 12MHz master clock for backward compatibility with FT2232D designs.6.3Enable 3 Phase Data Clocking0x8CThis will give a 3 stage data shift for the purposes of supporting interfaces such as I2C which need the data to be valid on both edges of the clk. So it will appear asData setup for ½ clock period -> pulse clock for ½ clock period -> Data hold for ½ clock period.6.4Disable 3 Phase Data Clocking0x8DThis will give a 2 stage data shift which is the default state. So it will appear asData setup for ½ clock period -> Pulse clock for ½ clock period6.5Clock For n bits with no data transfer0x8ELength,This will pulse the clock for 1 to 8 times given by length. A length of 0x00 will do 1 clock and a length of 0x07 will do 8 clocks.6.6Clock For n x 8 bits with no data transfer0x8FLengthL,LengthH,This will pulse the clock for 8 to (8 x $10000) times given by length. A length of 0x0000 will do 8 clocks and a length of 0xFFFF will do 524288 clocks6.7Clk continuously and Wait On I/O High0x94,This will cause the controller to create CLK pulses until GPIOL1 or I/O1 (CPU mode of FT2232H) is low. Once it is detected as high, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes low.6.8Clk continuously and Wait On I/O Low0x95,This will cause the controller to create CLK pulses until GPIOL1 or I/O1 (CPU mode of FT2232H) is high. Once it is detected as low, it will move on to process the next instruction. The only way out of this will be to disable the controller if the I/O line never goes high.。
FT2232制作仿真器
FT2232制作仿真器制作FT2232仿真器的过程主要包括以下几个步骤：1.准备材料和工具：除了FT2232芯片外，还需要准备USB线，电容、电阻的元器件以及一块PCB板、焊接工具（锡焊台、焊锡、焊吸器等）和测试仪器（如万用表等）。
2.设计原理图：根据FT2232芯片的功能和规格，设计仿真器的原理图。
原理图中应包含电源电路、FT2232芯片的引脚接线、外部元器件的连接以及需要的调试接口（如LED指示灯等）。
3.PCB布局设计：根据原理图设计出仿真器的PCB布局，将各个元器件的位置和连接线路规划好，注意布局合理性和信号完整性。
4. 生成PCB文件：使用PCB设计软件将设计好的PCB布局生成对应的Gerber或其他格式的制造文件。
5.PCB制造和焊接：将PCB文件发送给PCB制造厂家，制造出PCB板。
收到PCB板后，进行焊接工作，将FT2232芯片和其他元器件焊接到PCB板上。
6.完成电路和外围连接：通过焊接完成的PCB板上的引脚，利用焊接工具将相关引脚连接到外围电路，如LED指示灯、按键开关等。
8.测试和调试：通过测试仪器和相关软件工具，对仿真器进行测试和调试。
包括验证串口和并口的通信功能、外围电路的工作状态以及与目标设备的通信能力等。
9.封装和外壳设计：通过加装外壳和封装，保护仿真器的电路部分，同时增加使用便捷性。
总之，制作FT2232仿真器是一个比较复杂的工程，需要有一定的电路设计和电子焊接经验。
了解FT2232芯片的规格和功能，并掌握PCB设计软件和相关测试工具的使用，是制作仿真器的基本要求。
制作完成后，可以将仿真器应用于串口通信、并口通信等领域，方便调试和测试其他电子设备。
ft232r eeprom编程
主题：FT232R EEPROM编程FT232R是一种通用的USB转串口芯片，广泛应用于USB转串口、USB转并口、USB转打印机等功能。
FT232R芯片内部集成了EEPROM存储器，用于存储设备的配置信息和序列号等数据。
在某些特定的应用场景下，需要对FT232R芯片的EEPROM进行编程，以实现特定的功能需求。
一、FT232R芯片的EEPROM概述FT232R芯片的EEPROM存储器容量为1KB，用于存储设备的配置信息、制造商信息、产品标识符和序列号等数据。
通过对EEPROM的编程，可以实现设备的定制功能，包括USB VID/PID设置、串口波特率设置、制造商信息修改、产品标识符编程等。
二、FT232R EEPROM编程工具1. FT_PROG工具FT_PROG是由芯片厂商FTDI提供的一款专门用于FT232R芯片EEPROM编程的工具软件，支持对FT232R芯片的EEPROM进行读取、编程、擦除等操作。
FT_PROG工具提供了直观的图形界面，用户可以通过简单的操作完成对EEPROM的编程，同时支持对FT232R芯片的其他配置参数进行设置。
2. FT232R EEPROM编程工具除了FT_PROG工具外，也有一些第三方软件和编程器可以用于对FT232R芯片的EEPROM进行编程。
这些工具通常提供了更加丰富的功能和自定义选项，适用于一些特定的应用场景和定制需求。
用户可以根据具体的需求选择合适的EEPROM编程工具。
三、FT232R EEPROM编程步骤进行FT232R EEPROM编程时，一般需要按照以下步骤进行操作：1. 连接FT232R芯片需要将FT232R芯片通过USB接口连接到计算机上，确保计算机可以正确识别FT232R设备。
2. 启动EEPROM编程工具打开FT_PROG或其他选择的EEPROM编程工具，选择对FT232R芯片的EEPROM进行编程操作。
3. 读取EEPROM数据在编程工具中选择读取FT232R芯片的EEPROM数据，可以对当前的EEPROM数据进行备份，以便在编程过程中出现问题时进行恢复。
DS_FT2232H
Future Technology Devices International Ltd FT2232H Dual High SpeedUSB to MultipurposeUART/FIFO ICThe FT2232H is FTDI‟s 5th generation of USB devices. The FT2232H is a USB 2.0 High Speed (480Mb/s) to UART/FIFO IC. It has the capability of being configured in a variety of industry standard serial or parallel interfaces. The FT2232H has the following advancedfeatures:Single chip USB to dual serial / parallel portswith a variety of configurations.Entire USB protocol handled on the chip. No USB specific firmware programming required. USB 2.0 High Speed (480Mbits/Second) and Full Speed (12Mbits/Second) compatible.Dual Multi-Protocol Synchronous Serial Engine (MPSSE) to simplify synchronous serial protocol (USB to JTAG, I 2C, SPI or bit-bang) design.Dual independent UART or FIFO ports configurable using MPSSEs.Independent Baud rate generators.RS232/RS422/RS485 UART Transfer Data Rate up to 12Mbaud. (RS232 Data Rate limited by external level shifter).USB to parallel FIFO transfer data rate up to 8 Mbyte/Sec.Single channel synchronous FIFO mode for transfers > 25 Mbytes/SecCPU-style FIFO interface mode simplifies CPU interface design.MCU host bus emulation mode configuration option.Fast Opto-Isolated serial interface option.FTDI‟s royalty -free Virtual Com Port (VCP) and Direct (D2XX) drivers eliminate the requirement for USB driver development in most cases.Adjustable receive buffer timeout.Option for transmit and receive LED drive signals on each channel.Enhanced bit-bang Mode interface option with RD# and WR# strobesFT245B-style FIFO interface option with bi-directional data bus and simple 4 wire handshake interface.Highly integrated design includes +1.8V LDO regulator for VCORE, integrated POR function and on chip clock multiplier PLL (12MHz – 480MHz).Asynchronous serial UART interface option with full hardware handshaking and modem interface signals.Fully assisted hardware or X-On / X-Off software handshaking.UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity.Auto-transmit enable control for RS485 serial applications using TXDEN pin.Operational configuration mode and USB Description strings configurable in external EEPROM over the USB interface.Configurable I/O drive strength (4, 8, 12 or 16mA) and slew rate.Low operating and USB suspend current.Supports bus powered, self powered and high-power bus powered USB configurations.UHCI/OHCI/EHCI host controller compatible. USB Bulk data transfer mode (512 byte packets in High Speed mode).+1.8V (chip core) and +3.3V I/O interfacing (+5V Tolerant).Extended -40°C to 85°C industrial operating temperature range.Compact 64-LD Lead Free LQFP or QFN package+3.3V single supply operating voltage range.ESD protection for FT2232H IO‟s : Human Body Model (HBM) ±2kV, Machine Mode (MM) ±200V,Charge Device Model (CDM) ±500V, Latch-up free.Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in any medical appliance, device or system in which the failure of the product might reasonably be expected to result in personal injury. This document provides preliminary information that may be subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC1366401Typical ApplicationsSingle chip USB to dual channel UART (RS232, RS422 or RS485).Single chip USB to dual channel FIFO.Single chip USB to dual channel JTAG.Single chip USB to dual channel SPI.Single chip USB to dual channel I2C.Single chip USB to dual channel Bit-Bang. Single chip USB to dual combination of any of above interfaces.Single chip USB to Fast Serial Optic Interface. Single chip USB to CPU target interface (as memory), double and independent. Single chip USB to Host Bus Emulation (as CPU).PDA to USB data transferUSB Smart Card ReadersUSB InstrumentationUSB Industrial ControlUSB MP3 Player InterfaceUSB FLASH Card Reader / WritersSet Top Box PC - USB interfaceUSB Digital Camera InterfaceUSB Bar Code Readers1.1Driver SupportThe FT2232H requires USB drivers (listed below) , available free from , which are used to make the FT2232H appear as a virtual COM port (VCP). This allows the user to communicate with the USB interface via a standard PC serial emulation port (for example TTY). Another FTDI USB driver, the D2XX driver, can also be used with application software to directly access the FT2232H through a DLL.Royalty free VIRTUAL COM PORT (VCP) DRIVERS for...Windows 2000, Server 2003, Server 2008 Windows XP and XP 64-bitWindows Vista and Vista 64-bitWindows XP EmbeddedWindows CE 4.2, 5.0, 5.2 and 6.0Mac OS-XLinux (2.6.9 or later)Windows 7 and Windows 7 64-bit Royalty free D2XX Direct Drivers (USB Drivers + DLL S/W Interface) Windows 2000, Server 2003, Server 2008 Windows XP and XP 64-bitWindows Vista and Vista 64-bitWindows XP EmbeddedWindows CE 4.2, 5.0, 5.2 and 6.0Linux (2.4 or later) and Linux x86_64Windows 7 and Windows 7 64-bitFor driver installation, please refer to the application note:AN_107, “Advanc ed Driver Options”.AN_103, “FTDI Drivers Installation Guide for VISTA”.AN_119, “FTDI Drivers Installation Guide for Windows7”.AN_104, “FTDI Drivers Installation Guide for WindowsXP”.The following additional installation guides application notes and technical notes are also available: AN_113, “Interfacing FT2232H Hi-Speed Devices To I2C Bus”.AN_109 –“Programming Guide for High Speed FTCI2C DLL”AN_110 –“Programming Guide for High Speed FTCJTAG DLL”AN_111 –“Programming Guide for High Speed FTCSPI DLL”AN 113 –“Interfacing FT2232H Hi-Speed Devices To I2C Bus”AN114 –“Interfacing FT2232H Hi-Speed Devices To SPI Bus”AN135 – MPSSE BasicsAN108 - Command Processor For MPSSE and MCU Host Bus Emulation ModesTN_104, “Guide to Debugging Customers Failed Driver Installation”1.2Part NumbersPart NumberNote: Packaging code for xxxx is:- Reel: Taped and Reel (LQFP =1000 pcs per reel, QFN =4000 pcs per reel)-Tray: Tray packing, (LQFP =160 pcs per tray, QFN =260 pcs per tray)Please refer to section 8 for all package mechanical parameters.1.3USB CompliantThe FT2232H is fully compliant with the USB 2.0 specification and has been given the USB-IF Test-ID (TID) 40720019.The timing of the rise/fall time of the USB signals is not only dependant on the USB signal drivers, it is also dependant system and is affected by factors such as PCB layout, external components and any transient protection present on the USB signals. For USB compliance these may require a slight adjustment. This timing can be modified through a programmable setting stored in the same external EEPROM that is used for the USB descriptors. Timing can also be changed by adding appropriate passive components to the USB signals.2FT2232H Block DiagramFigure 2.1 FT2232H Block DiagramFor a description of each function please refer to Section 4.Table of Contents1Typical Applications (2)1.1Driver Support (2)1.2Part Numbers (3)1.3USB Compliant (3)2FT2232H Block Diagram (4)3Device Pin Out and Signal Description (7)3.164-Pin LQFP and 64-Pin QFN Package Schematic Symbol (7)3.2FT2232H Pin Descriptions (8)3.3Common Pins (9)3.4Configured Pins (11)3.4.1FT2232H pins used in an RS232 interface (11)3.4.2FT2232H pins used in an FT245 Style Synchronous FIFO Interface (12)3.4.3FT2232H pins used in an FT245 Style Asynchronous FIFO Interface (13)3.4.4FT2232H pins used in a Synchronous or Asynchronous Bit-Bang Interface (14)3.4.5FT2232H pins used in an MPSSE (15)3.4.6FT2232H Pins used as a Fast Serial Interface (16)3.4.7FT2232H Pins Configured as a CPU-style FIFO Interface (17)3.4.8FT2232H Pins Configured as a Host Bus Emulation Interface (18)4Function Description (19)4.1Key Features (19)4.2Functional Block Descriptions (19)4.3Dual Port FT232 UART Interface Mode Description (21)4.3.1Dual Port RS232 Configuration (21)4.3.2Dual Port RS422 Configuration (22)4.3.3Dual Port RS485 Configuration (23)4.4FT245 Synchronous FIFO Interface Mode Description (24)4.4.1FT245 Synchronous FIFO Read Operation (25)4.4.2FT245 Synchronous FIFO Write Operation (25)4.5FT245 Asynchronous FIFO Interface Mode Description (26)4.6MPSSE Interface Mode Description. (28)4.6.1MPSSE Adaptive Clocking (29)4.7MCU Host Bus Emulation Mode (30)4.7.1MCU Host Bus Emulation Mode Signal Timing – Write Cycle (31)4.7.2MCU Host Bus Emulation Mode Signal Timing – Read Cycle (32)4.8Fast Opto-Isolated Serial Interface Mode Description (34)4.8.1Outgoing Fast Serial Data (35)4.8.2Incoming Fast Serial Data (35)4.8.3Fast Opto-Isolated Serial Data Interface Example ..........................................................4.9CPU-style FIFO Interface Mode Description (37)4.10Synchronous and Asynchronous Bit-Bang Interface Mode Description (39)4.11RS232 UART Mode LED Interface Description (41)4.12Send Immediate / Wake Up (SIWU#) (42)4.13FT2232H Mode Selection (43)4.13.1Do I need an EEPROM? (43)5Devices Characteristics and Ratings (44)5.1Absolute Maximum Ratings (44)5.2DC Characteristics (45)5.3ESD Tolerance (47)6FT2232H Configurations (48)6.1USB Bus Powered Configuration (48)6.2USB Self Powered Configuration (50)6.3Oscillator Configuration (52)7EEPROM Configuration (53)8Package Parameters (54)8.1FT2232HQ, QFN-64 Package Dimensions (55)8.2FT2232HL, LQFP-64 Package Dimensions (56)8.3Solder Reflow Profile (58)9Contact Information (60)Appendix A – List of Figures and Tables (61)List of Tables (61)Appendix B – Revision History (63)3Device Pin Out and Signal DescriptionThe 64-pin LQFP and 64-pin QFN have the same pin numbering for specific functions. This pin numbering is illustrated in the schematic symbol shown in Figure 3.1.3.164-Pin LQFP and 64-Pin QFN Package Schematic SymbolFigure 3.1 FT2232H Schematic Symbol3.2FT2232H Pin DescriptionsThis section describes the operation of the FT2232H pins. Both the LQFP and the QFN packages have the same function on each pin. The function of many pins is determined by the configuration of the FT2232H. The following table details the function of each pin dependent on the configuration of the interface. Each of the functions are described in the following table (Note: The convention used throughout this document for active low signals is the signal name followed by a #).Pins marked ** default to tri-stated inputs with an internal 75KΩ (approx) pull up resistor to VCCIO.62 EECLK61 EEDATA3.3Common PinsThe operation of the following FT2232H pins are the same regardless of the configured mode:-Pin No. Name3.4Configured PinsThe following sections describe the function of the configurable pins referred to in the table given in Section 3.2 which is determined by how the FT2232H is configured.3.4.1FT2232H pins used in an RS232 interfaceThe FT2232H channel A or channel B can be configured as an RS232 interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.4.3.4.2FT2232H pins used in an FT245 Style Synchronous FIFO InterfaceThe FT2232H only channel A can be configured as a FT245 style synchronous FIFO interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.5. To enter this mode the external EEPROM must be set to make port A 245 mode. A software command (Set Bit Mode option) is then sent by the application to the FTDI driver to tell the chip to enter single channel synchronous FIFO mod e. In this mode the …B‟ channel is not available as all resources have been switched onto channel A. In this mode, data is written or read on the rising edge of the CLKOUT.For a functional description of this mode, please refer to section 4.4 FT245 Synchronous FIFO Interface Mode Description3.4.3FT2232H pins used in an FT245 Style Asynchronous FIFO Interface The FT2232H channel A or channel B can be configured as a FT245 asynchronous FIFO interface. When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.6. To enter this mode the external EEPROM must be set to make port A or B or both 245 mode. In this mode, data is written or read on the falling edge of the RD# or WR# signals.3.4.4FT2232H pins used in a Synchronous or Asynchronous Bit-BangInterfaceThe FT2232H channel A or channel B can be configured as a synchronous or asynchronous bit-bang interface. Bit-bang mode is a special FTDI FT2232H device mode that changes the 8 IO lines on either (or both) channels into an 8 bit bi-directional data bus. There are two types of bit-bang modes: synchronous and asynchronous.When configured in any bit-bang mode, the pins used and the descriptions of the signals are shown in Table 3.7Table 3.7 Channel A and Channel B Synchronous or Asynchronous Bit-Bang Configured Pin Descriptions For a functional description of this mode, please refer to section 4.10 Synchronous and Asynchronous Bit-Bang Interface Mode Description.3.4.5FT2232H pins used in an MPSSEThe FT2232H channel A and channel B each have a Multi-Protocol Synchronous Serial Engine (MPSSE). Each MPSSE can be independently configured to a number of industry standard serial interface protocols such as JTAG, I2C or SPI, or it can be used to implement a proprietary bus protocol. For example, it is possible to use one of the FT2232H‟s channels to connect to an SRAM configur able FPGA such as supplied by Altera or Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use the MPSSE to download configuration data to the FPGA over USB. This data would define the hardware function on power up. The other FT2232H channel would be available for another function. Alternatively each MPSSE can be used to control a number of GPIO pins. When configured in this mode, the pins used and the descriptions of the signals are shown Table 3.6Table 3.8 Channel A and Channel B MPSSE Configured Pin DescriptionsFor a functional description of this mode, please refer to section 4.6 MPSSE Interface Mode Description.3.4.6FT2232H Pins used as a Fast Serial InterfaceThe FT2232H channel B can be configured for use with high-speed optical bi-directional isolated serial data transfer: Fast Serial Interface. (Not available on channel A). A proprietary FTDI protocol designed to allow galvanic isolated devices to communicate synchronously with the FT2232H using just 4 signal wires (over two dual opto-isolators), and two power lines. The peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. Maximum USB full speed data rates can be achieved. Both …A‟ and …B‟ channels can communicate over the same 4 wire interface if desired.When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.9.Table 3.9 Channel B Fast Serial Interface Configured Pin DescriptionsFor a functional description of this mode, please refer to section 4.8 Fast Opto-Isolated Serial Interface Mode Description3.4.7FT2232H Pins Configured as a CPU-style FIFO InterfaceThe FT2232H channel A or channel B can be configured in a CPU-style FIFO interface mode which allows a CPU to interface to USB via the FT2232H. This mode is enabled in the external EEPROM.When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.10Table 3.10 Channel A and Channel B CPU-style FIFO Interface Configured Pin DescriptionsFor a functional description of this mode, please refer to section 4.9 CPU-style FIFO Interface Mode Description3.4.8FT2232H Pins Configured as a Host Bus Emulation InterfaceThe FT2232H can be used to combine channel A and channel B to be configured as a host bus emulation interface mode which emulates a standard 8048 or 8051 MCU host.When configured in this mode, the pins used and the descriptions of the signals are shown in Table 3.11Table 3.11 Channel A and Channel B Host Bus Emulation Interface Configured Pin DescriptionsFor a functional description of this mode, please refer to section 4.7 MCU Host Bus Emulation Mode4Function DescriptionThe FT2232H USB 2.0 High Speed (480Mb/s) to UART/FIFO is one of FTDI‟s 5th generation of Ics. It has the capability of being configured in a variety of industry standard serial or parallel interfaces.The FT2232H has two independent configurable interfaces. Each interface can be configured as UART, FIFO, JTAG, SPI, I2C or bit-bang mode with independent baud rate generators. In addition to these, the FT2232H supports a host bus emulation mode, a CPU-Style FIFO mode and a fast opto-isolated serial interface mode.4.1Key FeaturesUSB High Speed to Dual Interface. The FT2232H is a USB 2.0 High Speed (480Mbits/s) to dual independent flexible and configurable parallel/serial interfaces.Functional Integration. The FT2232H integrates a USB protocol engine which controls the physical Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 High Speed interface. The FT222H includes an integrated +1.8V Low Drop-Out (LDO) regulator and 12MHz to 480MHz PLL. It also includes 4kbytes Tx and Rx data buffers per interface. The FT2232H effectively integrates the entire USB protocol on a chip with no firmware required.MPSSE.Multi-Purpose Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides flexible synchronous interface configurations.Data Transfer rate. The FT2232H supports a data transfer rate up to 12 Mbaud when configured as an RS232/RS422/RS485 UART interface or greater than 25 Mbytes/second over a synchronous parallel FIFO interface. Please note the FT2232H does not support the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud.Latency Timer. This is really a feature of the driver and is used to as a timeout to flush short packets of data back to the PC. The default is 16ms, but it can be altered between 0ms and 256ms. At 0ms latency you get a packet transfer on every high speed microframe.4.2Functional Block DescriptionsDual Multi-Purpose UART/FIFO Controllers. The FT2232H has two independent UART/FIFO Controllers. These control the UART data, 245 fifo data, opto isolation (Fast Serial) or control the Bit-Bang mode if selected by SETUP command. Each Multi-Purpose UART/FIFO Controller also contain an MPSSE (Multi Protocol Synchronous Serial Engine) which can be used independently of each other. Using this MPSSE, the Multi-Purpose UART/FIFO Controller can be configured, under software command, to have 1 MPSSE + 1 UART / 245 FIFO (each UART / 245 can be set to Bit Bang mode to gain extra I/O if required) or 2 MPSSE.USB Protocol Engine and FIFO control. The USB Protocol Engine controls and manages the interface between the UTMI PHY and the FIFOs of the chip. It also handles power management and the USB protocol specification.Dual Port FIFO TX Buffer (4Kbytes per interface). Data from the Host PC is stored in these buffers to be used by the Multi-purpose UART/FIFO controllers. This is controlled by the USB Protocol Engine and FIFO control block.Dual Port FIFO RX Buffer (4Kbytes per interface). Data from the Multi-purpose UART/FIFO controllers is stored in these blocks to be sent back to the the Host PC when requested. This is controlled by the USB Protocol Engine and FIFO control block.RESET Generator –The integrated Reset Generator Cell provides a reliable power-on reset to the device internal circuitry at power up. The RESET# input pin allows an external device to reset the FT2232H. RESET# should be tied to VCCIO (+3.3v) if not being used.Independent Baud Rate Generators –The Baud Rate Generators provides a x16 or a x10 clock input to the UART‟s from a 120MHz reference clock and consists of a 14 bit pre-scaler and 4 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 12 million baud. The FT2232H does not support the baud rates of 7 Mbaud 9 Mbaud, 10 Mbaud and 11 Mbaud.See FTDI application note AN232B-05 on the FTDI website () for more details.+1.8V LDO Regulator. The +1.8V LDO regulator generates the +1.8 volts for the core and the USB transceiver cell. Its input (VREGIN) must be connected to a +3.3V external power source. It is also recommended to add an external filtering capacitor to the VREGIN. There is no direct connection from the +1.8V output (VREGOUT) and the internal functions of the FT2232H. The PCB must be routed to connect VREGOUT to the pins that require the +1.8V including VREGIN.UTMI PHY. The Universal Transceiver Macrocell Interface (UTMI) physical interface cell. This block handles the Full speed / High Speed SERDES (serialise – deserialise) function for the USB TX/RX data. It also provides the clocks for the rest of the chip. A 12 MHz crystal should be connected to the OSCI and OSCO pins. A 12K Ohm resistor should be connected between REF and GND on the PCB.The UTMI PHY functions include:Supports 480 Mbit/s “High Speed” (HS)/ 12 Mbit/s “Full Speed” (FS), FS Only and “Low Speed”(LS)SYNC/EOP generation and checkingData and clock recovery from serial stream on the USB.Bit-stuffing/unstuffing; bit stuff error detection.Manages USB Resume, Wake Up and Suspend functions.Single parallel data clock output with on-chip PLL to generate higher speed serial data clocks.EEPROM Interface. When used without an external EEPROM the FT2232H defaults to a USB to dualasynchronous serial port device. Adding an external 93C46 (93C56 or 93C66) EEPROM allows each of the chip‟s channels to be independently configured as a serial UART (RS232 mode), parallel FIFO (245) mode or fast serial (opto isolation). The external EEPROM can also be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT2232H for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Soft Pull Down on Power-Off and I/O pin drive strength.The EEPROM should be a 16 bit wide configuration such as a Microchip 93LC46B or equivalent capable of a 1Mbit/s clock rate at VCC = +3.00V to 3.6V. The EEPROM is programmable in-circuit over USB using a utility program c alled MPROG available from FTDI‟s web site (). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process.If no EEPROM is connected (or the EEPROM is blank), the FT2232H will default to dual serial ports. The device uses its built-in default VID (0403) , PID (6010) Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor.4.3Dual Port FT232 UART Interface Mode DescriptionThe FT2232H can be configured in similar UART modes as the FTDI FT232 devices. The following examples illustrate how to configure the FT2232H with an RS232, RS422 or RS485 interface. The FT2232 can be configured as a mixture of these interfaces.4.3.1Dual Port RS232 ConfigurationFigure 4.1 illustrates how the FT2232H can be configured with an RS232 UART interface. This can be repeated for channel B to provide a dual RS232, but has been omitted for clarity.GND GNDGNDGNDFigure 4.1 RS232 Configuration4.3.2Dual Port RS422 ConfigurationFigure 4.2 illustrates how the FT2232H can be configured as a dual RS422 interface.Figure 4.2 Dual RS422 ConfigurationIn this case both channel A and channel B are configured as UART operating at TTL levels. The Sipex SP491 is used as a level converter to convert the TTL level signals from the FT2232H to RS422 levels. The PWREN# signal is used to power down the level shifters such that they operate in a low quiescent current when the USB interface is in suspend mode.4.3.3Dual Port RS485 ConfigurationFigure 4.3 illustrates how the FT2232H can be configured as a dual RS485 interface.Figure 4.3 Dual RS485 ConfigurationIn this case both channel A and channel B are configured as RS485 operating at TTL levels. This example uses two Sipex SP491 devices but there are similar parts available from Maxim and Analog Devices amongst others. The SP491 is a RS485 device in a compact 8 pin SOP package. It has separate enables on both the transmitter and receiver. With RS485, the transmitter is only enabled when a character is being transmitted from the UART. The TXDEN pins on the FT2232H are provided for exactly that purpose, and so the transmitter enables are wired to the TXDEN‟s. The receiver enable is a ctive low, so it is wired to the PWREN# pin to disable the receiver when in USB suspend mode.RS485 is a multi-drop network – i.e. many devices can communicate with each other over a single two wire cable connection. The RS485 cable requires to be terminated at each end of the cable. Links are provided to allow the cable to be terminated if the device is physically positioned at either end of the cable.In this example the data transmitted by the FT2232H is also received by the device that is transmitting. This is a common feature of RS485 and requires the application software to remove the transmitted data from the received data stream. With the FT2232H it is possible to do this entirely in hardware – simply modify the schematic so that RXD of the FT2232H is the logical OR of the SP481 receiver output with TXDEN using an HC32 or similar logic gate.4.4FT245 Synchronous FIFO Interface Mode DescriptionWhen channel A is configured in an FT245 Synchronous FIFO interface mode the IO timing of the signals used are shown in Figure 4.4, which shows details for read and write accesses. The timings are shown in Table 4.1. Note that only a read or a write cycle can be performed at any one time. Data is read or written on the rising edge of the CLKOUT clock.Figure 4.4 FT245 Synchronous FIFO Interface Signal WaveformsThis single channel mode uses a synchronous interface to get high data transfer speeds. The chip drives a 60 MHz CLKOUT clock for the external system to use.Note that Asynchronous FIFO mode must be selected on both channels before selecting the Synchronous FIFO mode in software.4.4.1FT245 Synchronous FIFO Read OperationA read operation is started when the chip drives RXF# low. The external system can then drive OE# low to turn around the data bus drivers before acknowledging the data with the RD# signal going low. The first data byte is on the bus after OE# is low. The external system can burst the data out of the chip by keeping RD# low or it can insert wait states in the RD# signal. If there is more data to be read it will change on the clock following RD# sampled low. Once all the data has been consumed, the chip will drive RXF# high. Any data that appears on the data bus, after RXF# is high, is invalid and should be ignored.4.4.2FT245 Synchronous FIFO Write OperationA write operation can be started when TXE# is low. WR# is brought low when the data is valid. A burst operation can be done on every clock providing TXE# is still low. The external system must monitor TXE# and its own WR# to check that data has been accepted. Both TXE# and WR# must be low for data to be accepted.。
DLP-2232M-G;中文规格书,Datasheet资料
DLP-2232M-G MODULE / EVALUATION KIT*LEAD-FREE*1.0 IntroductionThe DLP-2232M-G utilizes FTDI's third-generation USB UART/FIFO I.C., theFT2232D. This low-cost development tool features two Multi-Purpose UART/FIFO controllers that can be configured individually in several different modes. In addition to the UART interface, FIFO interface, and Bit-Bang IO modes of the second-generation FT232BM and FT245BM devices, the FT2232D offers a variety of additional modes of operation including a Multi-Protocol Synchronous Serial Engine interface designed specifically for synchronous serial protocols such as JTAG and SPI bus.The DLP-2232M-G features a quality four-layer printed circuit board with a solid ground plane, an integral 93C56 EEPROM on board for easy OEM customization and a standard 40-pin, 0.6in wide footprint. Integral power control and on-board MOSFET power switch make the DLP-2232M-G a perfect choice for USB bus-powered, high-power designs as well as self- and low-powered products.1.1 Features Summary• Single board, USB Dual Channel Serial / Parallel Ports with a variety of configurations • Entire USB protocol handled on-board. No USB-specific firmware programming required• DLP-USB232M-style UART interface option with full Handshaking & Modem interface signals• UART Interface supports 7/8 bit data, 1/2 stop bits, and Odd/Even/Mark/Space/No Parity• Transfer Data Rate 300 to 1 Mega Baud (RS232)• Transfer Data Rate 300 to 3 Mega Baud (TTL and RS422 / RS485)• Auto Transmit Enable control for RS485 serial applications using TXDEN pin• DLP-USB245M-style FIFO interface option with bi-directional data bus and simple 4- wire handshake interface• Transfer Data Rate up to 1 MegaByte / Second• Enhanced Bit-Bang Mode interface option• New Synchronous Bit-Bang Mode interface option• New CPU-Style FIFO Interface Mode option• New Multi-Protocol Synchronous Serial Engine (MPSSE) interface option• New MCU Host Bus Emulation Mode option• New Fast Opto-Isolated Serial Interface Mode option• Interface mode and USB Description strings configurable in on-board EEPROM• EEPROM Configurable in-circuit via USB• Support for USB Suspend and Resume conditions via PWREN#, and SI/WUx pins • Support for bus powered, self powered, and high-power bus powered USB configurations• Integrated Power-On-Reset circuit, with optional Reset input and Reset Output pins • 5V and 3.3V logic IO Interfacing with independent level conversion on each channel • USB Bulk or Isochronous data transfer modes• 4.35V to 5.25V single supply operating voltage range• UHCI / OHCI / EHCI host controller compatible• USB 2.0 Full Speed (12 Mbits / Second) compatible• Standard 40-pin, 0.6in wide footprintVIRTUAL COM PORT (VCP) DRIVERS APPLICATION AREAS• Windows 98 / 98 SE / 2000 / ME / XP • USB Dual Port RS232 Converters • Windows CE ** • USB Dual Port RS422 / RS485• MAC OS-8 and OS-9** • Upgrading Legacy Peripheral Designs • MAC OS-X** • USB Instrumentation• Linux 2.40 and greater** • USB JTAG Programming[ ** = In planning or under development ] • USB to SPI Bus Interfaces• USB Industrial ControlD2XX (Direct Drivers + DLL S/W • Field Upgradeable USB Products • Windows 98 / 98 SE / 2000 / ME / XP • Galvanically Isolated ProductsWith USB Interface1.2 General DescriptionThe DLP-2232M-G module is a USB interface that incorporates the functionality of two DLP-USB2xxM modules into a single 40-pin module. A single downstream USB port is converted to two IO channels that can each be individually configured as a DLP-USB232M-style UART interface, or a DLP-USB245M-style FIFO interface, without the need to add a USB hub.There are also several new modes which can be enabled in the external EEPROM, or by using DLL driver commands. These include Synchronous Bit-Bang Mode, a CPU-Style FIFO Interface Mode, a Multi-Protocol Synchronous Serial Engine Interface Mode, MCU Host Bus Emulation Mode, and Fast Opto-Isolated Serial Interface Mode. Additionally, a new high output drive level option means that the device UART / FIFO IO pins will drive out at around three times the normal power level, allowing the data bus to be shared by several devices.Classic BM-style Asynchronous Bit-Bang Mode is also supported, but has been enhanced to give the user access to the device’s internal RD# and WR# strobes.FTDI provides a royalty free Virtual Com Port (VCP) driver that makes the peripheral ports look like a standard COM port to the PC. Most existing software applications should be able interface with the Virtual Com Port simply by reconfiguring them to use the new ports created by the driver. Using the VCP drivers, an application programmer would communicate with the device in exactly the same way as they would a regular PC COM port - using the Windows VCOMM API calls or a COM port library.The FT2232D driver also incorporates the functions defined for FTDI’s D2XX drivers, allowing applications programmers to interface software directly to the device using a Windows DLL.2.0 Features and EnhancementsThe DLP-2232M-G incorporates all of the enhancements introduced for the second generation DLP-USB232M and DLP-USB245M modules, summarized here:• Two Individually Configurable IO ChannelsEach of the DLP-2232M-G’s Channels (A and B) can be individually configured as a DLP-USB232M-style UART interface, or as a DL-USB245M-style FIFO interface. Additionally, these channels can be configured in a number of special IO modes.• Integrated Power-On-Reset (POR) circuitThe module incorporates an internal POR function. A RESET# pin is available to allow external logic to reset the module where required, however for most applications this pin can simply be left disconnected as the RESET input to the FT2232D is pulled to VCC through a 47K resistor. A RSTOUT# pin is provided in order to allow the new POR circuit to provide a stable reset to external MCU and other devices.• Integrated level converter on UART / FIFO interface and control signalsEach channel of the DLP-2232M-G has its own independent VCCIO pin that can be supplied by between 3V to 5V. This allows each channel’s output voltage drive level to be individually configured. Thus allowing, for example, 3.3V logic to be interfaced to the device without the need for external level converter I.C.’s.• Improved power management control for high-power USB Bus Powered devicesThe PWREN# pin of the FT2232D directly drives a P-Channel MOSFET for applications where power switching of external circuitry is required. The BM pull down enable feature (configured in the external EEPROM) is also retained. This will make the module gently pull down on the FIFO / UART IO lines when the power is shut off (PWREN# is high). In this mode, any residual voltage on external circuitry is bled to GND when power is removed, thus ensuring that external circuitry controlled by PWREN# resets reliably when power is restored.• Support for Isochronous USB TransfersWhilst USB Bulk transfer is usually the best choice for data transfer, the scheduling time of the data is not guaranteed. For applications where scheduling latency takes priority over data integrity such as transferring audio and low bandwidth video data, the DLP-2232M-G offers the option of USB Isochronous transfer via configuration of bit in the EEPROM.• Send Immediate / Wake Up Signal Pin on each channelThere is a Send Immediate / Wake Up (SI/WU) signal pin on each of the two channels. These combine two functions on one pin. If USB is in suspend mode (and remote wakeup is enabled in the EEPROM), strobing this pin low will cause the device to request a resume from suspend (WakeUp) on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation, if this pin is strobed low any data in the device RX buffer will be sent out over USB on the next Bulk-IN request from thedrivers regardless of the packet size. This can be used to optimize USB transfer speed for applications that send small packets of data to the host PC.• Programmable Receive Buffer TimeoutThe TX buffer timeout is programmable over USB in 1ms increments from 1ms to255ms, thus allowing the module to be better optimized for protocols requiring faster response times from short data packets.• Baud Rate Pre-Scaler DivisorsThe DLP-2232M-G (UART mode) baud rate pre-scaler supports division by (n+0),(n+0.125), (n+0.25), (n+0.375), (n+0.5), (n+0.625), (n+0.75) and (n+0.875) where n is an integer between 2 and 16,384.• USB 2.0 (full speed option)An EEPROM based option allows the DLP-2232M-G to return a USB 2.0 device descriptor as opposed to USB 1.1. Note: The device would be a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s).For more details on these features please see the FT232BM and FT245BM datasheets and application notes.In addition to the DLP-USB2xxM module features, the DLP-2232M-G incorporates the following new features and interface modes:• Enhanced Asynchronous Bit-Bang InterfaceThe DLP-2232M-G supports FTDI’s BM chip Bit Bang mode. In Bit Bang mode, the eight FIFO data lines can be switched between FIFO interface mode and an 8-bit Parallel IO port. Data packets can be sent to the device and they will be sequentially sent to the interface at a rate controlled by an internal timer (equivalent to the baud rate prescaler). With the DLP-2232M-G module, this mode has been enhanced so that the internal RD# and WR# strobes are now brought out of the device which can be used to allow external logic to be clocked by accesses to the Bit-Bang IO bus.• Synchronous Bit-Bang InterfaceWith Synchronous Bit-Bang Mode, the device is only read when it is written to, as opposed to asynchronously by the data rate generator. This makes it easier for the controlling program to measure the response to an output stimulus, as the data returned is synchronous to the output data.• High Output Drive Level CapabilityThe IO interface pins can be made to drive out at 12 mA, instead of the normal 4 mA allowing multiple devices to be interfaced to the bus.• CPU-Style FIFO InterfaceThe CPU style FIFO interface is essentially the same function as the classic FT245 interface, however the bus signals have been redefined to make them easier to interface to a CPU bus.• Multi-Protocol Synchronous Serial Engine Interface (M.P.S.S.E.)The Multi-Protocol Synchronous Serial Engine (MPSSE) interface is a new option designed to interface efficiently with synchronous serial protocols such as JTAG and SPI Bus. It is very flexible in that it can be configured for different industry standards, or proprietary bus protocols. For instance, it is possible to connect one of the DLP-2232M-G’s channels to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA device would normally be un-configured (i.e. have no defined function) at power-up. Application software on the PC could use the MPSSE to download configuration data to the FPGA over USB. This data would define the hardware’s function and then, after the FPGA device is configured, the DLP-2232M-G can switch back into FIFO interface mode to allow the programmed FPGA device to communicate with the PC over USB. The other DLP-2232M-G channel would also be available for other devices.This approach would allow a customer to create a “generic” USB peripheral; who’s hardware function can be defined under control of the application software. The FPGA based hardware could be easily upgraded or totally changed simply by changing the FPGA configuration data file. (See the FTDI MORPH-IC or DLP-Design DLP-2232PB and DLP-2232SY development modules for practical examples)• MCU Host Bus EmulationThis new mode combines the ‘A’ and ‘B’ bus interface to make the DLP-2232M-G interface emulate a standard 8048 / 8051 style MCU bus. This allows peripheral devices for these MCU families to be directly attached to the DLP-2232M-G with IO being performed over USB with the help of MPSSE interface technology.• Fast Opto-Isolated Serial InterfaceA new proprietary FTDI protocol is designed to allow galvanically isolated devices to communicate synchronously with the DLP-2232M-G using just 4 wires (two dual opto-isolators). The peripheral circuitry controls the data transfer rate in both directions, whilst maintaining full data integrity. Maximum USB full speed data rates can be achieved. Both ‘A’ and ‘B’ channels can communicate over the same 4-wire interface if desired.3.0 DLP-2232M-G Module Simplified Block Diagram3.1 Functional Block Descriptions• 6MHz OscillatorThe 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz ceramic resonator.• Multi-Purpose UART / FIFO ControllersThe Multi-purpose UART / FIFO controllers handle the transfer of data between the Dual Port RX and TX buffers and the UART / FIFO transmit and receive registers. When configured as a UART it performs asynchronous 7/8 bit parallel to serial and serial to parallel conversion of the data on the RS232 (RS422 and RS485) interface. Control signals supported by UART mode include RTS, CTS, DSR, DTR, DCD and RI. There are also transmitter enable control signal pins (TXDEN) provided to assist with interfacing to RS485 transceivers. RTS/CTS, DSR/DTR and X-On/X-Off handshaking options are also supported. Handshaking, where required, is handled in hardware toensure fast response times. The UARTs also support the RS232 BREAK setting and detection conditions.• EEPROM InterfaceThe on-board 93C56 EEPROM allows each of the DLP-2232M-G module’s channels to be independently configured as a serial UART (232 mode), or a parallel FIFO (245 mode). The EEPROM is used to enable the CPU-style FIFO interface, and Fast Opto-Isolated Serial interface modes. The driver type selection (VCP or D2XX) is also stored in the EEPROM.The EEPROM can also be used to customize the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the DLP-2232M-G for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes.The EEPROM is programmable in-circuit via USB using the MPROG utility program available from both and FTDI’s web site ().4.0 Module Pin-Out402021Figure 2. Pin-Out (40 Pin DIP Header )4.1 Pin DefinitionsThis section describes the operation of the DLP-2232M-G pins. Common pins are defined in the first section and the I/O pins are defined by chip mode. More detailed descriptions of the operation of the I/O pins are provided in section x. (was 9)4.2 Common PinsThe operation of the following DLP-2232M-G pins stay the same, regardless of the operating mode.27 RSTIN# Input Can be used by an external device to reset the FT2232D. Ifnot required, can be left disconnected.26 RSTOUT# Output Output of the internal Reset Generator. Stays highimpedance for ~5ms after VCC > 3.5V and theinternal clock starts up, then clamps it’s output to the 3.3Voutput of the internal regulator.Taking RESET# low will also force RSTOUT# to drivelow. RSTOUT# is NOT affected by a USB Bus Reset.19 EXTVCC PWR +4.35 to +5.25 volt VCC to the device core, LDO and non-UART / FIFO controller interface pins.Device Analog Power Supply for the internal x8 clockmultiplier.18 VCCIOA PWR +3.0 to +5.25 volt VCC to the UART/FIFO Channel Ainterface pins. When interfacing with 3.3V external logicconnect VCCIO to the 3.3V supply of the external logic,otherwise connect to VCC to drive out at 5V CMOS level.17 VCCIOB PWR +3.0 volt to +5.25 volt VCC to the UART/FIFO Channel Binterface pins. When interfacing with 3.3V external logicconnect VCCIO to the 3.3V supply of the external logic,otherwise connect to VCC to drive out at 5V CMOS level.20 PORTVCC PWR Power from USB port. Connect to EXTVCC if module is tobe powered by the USB port (typical configuration).500mA maximum current available to USB adapter andtarget electronics if USB device is configured for highpower.16 VCCSW PWR Output of the MOSFET power switch, activated afterenumeration.21 VCCUSB PWR Filtered +3.0 volt to +5.25 volt EXTVCC from either thehost USB port or user supplied external power supply.4.3 IO Pin Definitions by Chip ModeThe definition of the following pins vary according to the module’s mode:*Note 2245*Note 4*Note 5TXD D0 D0 D0 TCK/SKAD0 *Note 3 ADBUS040RXD D1 D1 D1 TDI/DUAD1 ADBUS139AD2RTS# D2 D2 D2 TDO/D1 ADBUS238AD3CTS# D3 D3 D3 TMS/CS ADBUS337AD4DTR# D4 D4 D4 GPIOL0 ADBUS436DSR# D5 D5 D5 GPIOL1AD5 ADBUS535AD6DCD# D6 D6 D6 GPIOL2 ADBUS634RI# D7 D7 D7 GPIOL3AD7 ADBUS733*Note 6 GPIOH0 I/O032 ACBUS0 TXDEN RXF# CS# WR#*Note 6 GPIOH1 I/O131 ACBUS1 SLEEP# TXE# A0 RD#*Note 7 GPIOH2 IORDY#30 ACBUS2 RXLED# RD# RD# WR#*Note 7 GPIOH3 OSC29 ACBUS3 TXLED# WR WR# RD#28 SI/WUA SI/WUA SI/WUA SI/WUA分销商库存信息: DLP-DESIGNDLP-2232M-G。
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FT2232中文资料
1 FT2232C概述
1.1 电路概览
FT2232C是一款USB到UART/FIFO的转换电路，是FTDI公司继第二代FT232BM、FT245BM之后的第三代产品，集成了两片BM芯片的功能。
电路要用48-LD LQFP封装。
FT2232C具有两个多用途的UART/FIFO控制器，可分别配置成不同的工作模式。
一个USB下游端口转换成两个I/O通道，每个I/O通道相当一个FT232BM或FT245BM，可以单独配置成UART接口或者FIFO接口。
通过对外挂EEPROM的配置，FT2232C还提供一系列新的操作模式，如多协议同步串行机接口，这是专为同步串行协议如JTAG和SPI 总线设计的。
还有同步位宽模式、CPU风格的FIFO模式、多协议同步串行机接口模式、MCU主机总线竞争模式及快速光隔离串行机接口模式等。
此外，该电路的驱动能力有很大提高，能够输出较之通常电路3倍的功率，这使得多个电路可能共享总线。
使用FTDI公司提供的虚拟串口（VCP）驱动，对外围接口的使用就像使用PC的标准串口一样。
许多现有软件经过简单重新配置即哥与虚拟串口相接，应用程序与电路间的通信与PC的COM口通信相同。
1.2 电路的特征
●只需添加简单配置电路，便可实现由单电路到双通道串/并口的转换；
●芯片上集成了全部USB处理协议，使用时不需要另外编写USB固件程序；
●2个I/O通道（A/B）相互独立，可配置成2个5V、2个3.3V或一个5V、一个3.3V的逻辑I/O接口；
●UART接口支持7或8位数据位，1/2位停止位，奇校验/偶校验/标志位/空位/无奇偶校验；
●发送数据的速率为300~1Mb/s(RS-232)或3Mbs(TTL、RS-232/RS-485)；
●接口模式和USB描述字符可在外部EEPROM中进行配置，还可以在板子上通过USB对EEPROM进行配置；
●4.35V~5.25V的单电压工作范围。
1.3 简化功能框图
FT2232C的简化功能框图如图1所示，各单元的功能如下：
USB收发器单元：提供USB1.1、USB2.0到USB电缆的全速物理接口。
一个微分收发器和两个单独的终结收发器提供USB数据输入、SEO及USB复位条件检测。
USB DPLL单元：跟踪输入的NRZI USB数据，并单独恢复时钟及数据信号SIE模块。
SIE模块：执行USB数据从串行到并行及并行到串行的转换。
USB PE模块：管理从USB控制端接收的数据，负责处理USB主控器发出的低层USB协议请求和UART/FIFO控制器发出的控制命令。
RX Buffer和TX Buffer分别为384字节的接收缓冲和128字节的发送缓冲。
1.4 应用领域
由于集成了两片第二代BM的功能，因而FT2232C的应用场合十分广泛。
主要包括USB转换为双串口RS-232、USB转换为双串口
RS-422/RS-485、USB JTAG编程、USB转换为SPI总线接口、现场可升级的USB产品和带USB接口的交流隔离产品。
2 FT2232C的应用举例
在实际应用中，由于传统串口扩展方法相对比较繁锁，因此可使用该电路来扩展串口，实现时只需进行简单的外围电路配置即可得到一个由USB转换而来的两个COPMPORT。
具体的配置电路如图2所示。
设计是需要注意以下几点：
首先：FT2232C的USBDP、USBDM两个输入端的电阻器阻值必须相等，典型值为27Ω，而且必须是1%精度的电阻器，否则容易造成输入阻抗不匹配而使电路无法正常工作。
其次：该电路晶振两端的2个电容器的容值也必须相等，典型值为27pF。
由于设计要求是要得到2个串口，因此外挂的EEPROM可以不接，而直接将FT2232C的EEDATA端经由10kΩ的电阻器接到VCC上。
这样在上电复位时FT2232C不能从外挂的EEPROM中读取信息，工作在电路的缺省默认模式下，即由USB到双串口的转换。
将得到的2个串口通过电路的VCCIOA、VCCIOB进行配置，即将VCCIOA接3.3V，VCCIOB接5V，这样得到的串口A的工作电压为3.3V，串口B的工作电压为5V，可以分别接3.3V和5V的器件。
由于RS232电平一般为-9V~+9V，而FT2232C转换得到的2个串口通信前需要经过V或3.3V，因此在与RS232串口通信前需要经过电平转换。
以SP213EHCA电平转换电路为例，具体电路如图3所示。
除了常用的USB到RS-232串口的转换，FT2232C还可以转换成其他接口，如RS422、RS485及CPU风格的FIFO等。
其具体的电路分别如图4、图5、图6所示。
为方便起见，各图中仍仅以一个通道为例进行说明。