Verilog HDL 实验串行数据检测

Verilog HDL 实验报告（六）
系部名称：通信工程
专业名称：通信工程
班级：
班内序号：
学生姓名：
实验内容：串行数据检测一设计模块
源代码：
module check(clk,rst,in,out);
input clk,rst;
input in;
output out;
reg [3:0] state;
reg out;
parameter idle=3'b000,
state1=3'b001,
state2=3'b010,
state3=3'b011,
state4=3'b100,
state5=3'b101,
state6=3'b110,
state7=3'b111;
always @(posedge clk or negedge rst)
if (!rst)
begin
state<=idle;
end
else
case (state)
idle: if (in==1'b0)
state<=state1;
else state<=idle;
state1: if (in==1'b1)
state<=state2;
else state<=state1;
state2: if (in==1'b1)
state<=state3;
else state<=state1; state3: if (in==1'b0)
state<=state4;
else state<=idle;
state4: if (in==1'b1)
state<=state5;
else state<=state1;
state5: if (in==1'b0)
state<=state6;
else state<=state3;
state6: if (in==1'b1)
state<=state7;
else state<=state1;
state7: state<=idle;
default: state<=idle;
endcase
always @ (posedge clk or negedge rst) begin
if (!rst)
out<=1'b0;
else if (state==state7)
out<=1'b1;
else out<=1'b0;
end
endmodule
二测试模块
module jiance;
reg clk,rst;
reg [23:0]in;
wire out;
wire [2:0]state;
wire x,z;
check we(clk,rst,in,out);
assign x=in[23];
always #10 clk=~clk;
always @(posedge clk)
in={in[22:0],in[23]};
initial
begin
$monitor($time ,"out=%b",out);
clk=0;
rst=1;
#2 rst=0;
#50 rst=1;
#50 rst=0;
in='b0011_1111_1110_0101_1010;
#500 $stop;
end
endmodule
三输出结果。