HY57V283220LTP-7中文资料

0.2
0.3 0.4 0.5 0.6 0.7 0.8 0.9
Defined IDD Spec. Delited Preliminary. Changed IDD Spec. 133MHz Speed Added Changed FBGA Package Size from 11x13 to 8x13. 1) Changed VDD min from 3.135V to 3.0V. 2) Changed VIL min from VSSQ-0.3V to -0.3V. Modified of size erra. (Page15) (Equation : 13.00 ± 10 -> 13.00 ± 0.10)
元器件交易网
HY57V283220(L)T(P)/ HY5V22(L)F(P)
4 Banks x 1M x 32Bit Synchronous DRAM
DESCRIPTION
The Hynix HY57V283220(L)T(P) / HY5V22(L)F(P) is a 134,217,728-bit CMOS Synchronous DRAM, ideally suited for the memory applications which require wide data I/O and high bandwidth. HY57V283220(L)T(P) / HY5V22(L)F(P) is organized as 4banks of 1,048,576x32. HY57V283220(L)T(P) / HY5V22(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL. Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
8 6 p in T S O P II 4 0 0 m il x 8 7 5 m i l 0 .5 m m p i n p i t c h
PIN DESCRIPTION
PIN CLK CKE CS BA0, BA1 A0 ~ A11 Clock Clock Enable Chip Select Bank Address Address Row Address Strobe, Column Address Strobe, Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground No Connection PIN NAME DESCRIPTION The system clock input. All other inputs are registered to the SDRAM on the rising edge of CLK. Controls internal clock signal and when deactivated, the SDRAM will be one of the states among power down, suspend or self refresh Enables or disables all inputs except CLK, CKE and DQM Selects bank to be activated during RAS activity Selects bank to be read/written during CAS activity Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA7 Auto-precharge flag : A10 RAS, CAS and WE define the operation Refer function truth table for details Controls output buffers in read mode and masks input data in write mode Multiplexed data input / output pin Power supply for internal circuits and input buffers Power supply for output buffers No connection
FEATURES
• • • • • • JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3 • Internal four banks operation • Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks • • • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or full page for Sequential Burst - 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY57V283220(L)T(P)-5 HY5V22(L)F(P)-5 HY57V283220(L)T(P)-55 HY5V22(L)F(P)-55 HY57V283220(L)T(P)-6 HY5V22(L)F(P)-6 HY57V283220(L)T(P)-7 HY5V22(L)F(P)-7 HY57V283220(L)T(P)-H HY5V22(L)F(P)-H HY57V283220(L)T(P)-8 HY5V22(L)F(P)-8 HY57V283220(L)T(P)-P HY5V22(L)F(P)-P HY57V283220(L)T(P)-S HY5V22(L)F(P)-S
Clock Frequency
200MHz 183MHz 166MHz 143MHz
Organization
Interface
Package
4Banks x 1Mbits x32 133MHz 125MHz 100MHz 100MHz
LVTTL
86TSOP-II 90Ball FBGA
Note) Hynix supports lead free part for each speed grade with same specification.
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004
This document is a general product description and is subject to change without notice. Hynix Semiconductor Inc. does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.9 / July 2004
元器件交易网
HY57V283220(L)T(P) / HY5V22(L)F(P)
PIN CONFIGURATION ( HY57V283220(L)T(P) Series)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 /W E /C A S /R A S /C S A11 BA0 BA1 A 1 0 /A P A0 A1 A2 DQM2 VDD NC D Q 16 VSSQ D Q 17 D Q 18 VDDQ D Q 19 D Q 20 VSSQ D Q 21 D Q 22 VDDQ D Q 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS D Q 15 VSSQ D Q 14 D Q 13 VDDQ D Q 12 D Q 11 VSSQ D Q 10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC C LK CKE A9 A8 A7 A6 A5 A4 A3 DQM3 VSS NC D Q 31 VDDQ D Q 30 D Q 29 VSSQ D Q 28 D Q 27 VDDQ D Q 26 D Q 25 VSSQ D Q 24 VSS