THC63LVD103_LVDS

Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
4
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Electrical Characteristics CMOS/TTL DC Specifications
TD5 GND TD6 TE0 TE1 TE2 VCC TE3 TE4 GND TE5 CLK IN /PDWN PLL GND PLL VCC TE6
2
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Pin Description
Pin Name TA+, TATB+, TBTC+, TCTD+, TDTE+,TETCLK+, TCLKTA0 ~ TA6 TB0 ~ TB6 TC0 ~ TC6 TD0 ~ TD6 TE0 ~ TE6 /PDWN Pin # 30, 31 28, 29 24, 25 20, 21 18, 19 22, 23 33,34,35,36,37,38,40 41,42,44,45,46,48,49 50,52,53,54,55,57,58 59,61,62,63,64,1,3 Type LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT LVDS OUT IN IN IN IN Pixel Data Inputs. LVDS Clock Out. LVDS Data Out. Description
VCC = 3.0V ~ 3.6V, Ta = 0 ° C ~ +70 ° C Symbol VIH VIL VDDQ1 VREF VSH2 VSL2 IINC Parameter High Level Input Voltage Low Level Input Voltage Small Swing Voltage Input Reference Voltage Small Swing High Level Input Voltage Small Swing Low Level Input Voltage Input Current Small Swing (RS=VDDQ/2) VREF = VDDQ/2 VREF = VDDQ/2
PLL
TCLK +/(8 to 135MHz)
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
1
THine Electronics, Inc.
THC63LVD103 _Rev2.2
Pin Out
TB6 TC0 VCC TC1 TC2 TC3 TC4 GND TC5 TC6 TD0 R/F TD1 TD2 TD3 TD4
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
RS VCC
RS
43
IN
0.6 ~ 1.4V GND
a. VREF is Input Reference Voltage.
R/F VCC CLKIN GND LVDS VCC LVDS GND PLL VCC PLL GND
60 51, 7 12 2, 10, 39, 47, 56 27 17, 26, 32 15 14
TB5 GND TB4 TB3 TB2 RS TB1 TB0 TA6 GND TA5 TA4 TA3 TA2 TA1 TA0
LVDS GND TATA+ TBTB+ LVDS VCC LVDS GND TCTC+ TCLKTCLK+ TDTD+ TETE+ LVDS GND
Copyright 2001-2006 THine Electronics, Inc. All rights reserved.
4,5,6,8,9,11,16
13
IN
IN H: Normal operation, L: Power down (all outputs are Hi-Z) LVDS swing mode, VREF select.
LVDS Swing 350mV 350mV 200mV Small Swing Input Support N/A RS=VREFa N/A
1. “Absolute Maximum Ratings” are those valued beyond which the safety of the device can not be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Features
• Wide dot clock range: 8-135MHz suited for NTSC,
VGA, SVGA, XGA,SXGA and SXGA+
• • • • • • • • •
PLL requires no external components Supports spread spectrum clock generator On chip jitter filtering Clock edge selectable Supports reduced swing LVDS for low EMI Power down mode Low power single 3.3V CMOS design 64pin TQFP Backward compatible with THC63LVDM63R(18bits) / M83R(24bits)
IN Power IN Ground Power Ground Power Ground
Input Clock Triggering Edge Select. H: Rising edge, L: Falling edge Power Supply Pins for TTL inputs and digital circuitry. Clock in. Ground Pins for TTL inputs and digital circuitry. Power Supply Pins for LVDS Outputs. Ground Pins for LVDS Outputs. Power Supply Pin for PLL circuitry. Ground Pins for PLL circuitry.
0V ≤ V IN ≤ V CC
Conditions RS=VCC or GND RS=VCC or GND
Min. 2.0 GND 1.2
Typ.
Max. VCC 0.8 2.8
Units V V V
VDDQ/2 VDDQ/2 +100mV VDDQ/2 -100mV
± 10
V V μA
Notes: 1VDDQ voltage defines max voltage of small swing input. It is not an actual input voltage. 2 Small swing signal is applied to TA[6:0], TB[6:0], TC[6:0], TD[6:0], TE[6:0] and CLKIN.
THC63LVD103 _Rev2.2
THC63LVD103
135MHz 30Bits COLOR LVDS Transmitter
General Description
The THC63LVD103 transmitter is designed to support pixel data transmission between Host and Flat Panel Display from NTSC up to SXGA+ resolutions. The THC63LVD103 converts 35bits of CMOS/TTL data into LVDS(Low Voltage Differential Signaling) data stream. The transmitter can be programmed for rising edge or falling edge clocks through a dedicated pin. At a transmit clock frequency of 135MHz, 30bits of RGB data and 5bits of timing and control data (HSYNC, VSYNC, DE, CNTL1, CNTL2) are transmitted at an effective rate of 945Mbps per LVDS channel.
Block Diagram
CMOS/TTL INPUT
TA0-6 TB0-6 7 7 7
LVDS OUTPUT
TA +/TB +/TC +/TD +/TE +/-
TC0-6
TD0-6 TE0-6
7 7
PARALLEL TO SERIAL