tpq2ch12

10 SC C3 26 -
11 SC C4 27 TM R1
Interrupt Controller
12 - 7
Programming Model (4 of 4)
SIVEC - SIU Interrupt Vector Register 0 1 2 3 4 5 6 7 8 Interrupt Code 0 0 0 16 0 17 0 18 0 19 0 20 21 0 0 22 0 23 0 24 0 9 0 25 0 10 0 26 0 11 12 0 0 27 28 0 0 13 0 29 0 P. 4-23 14 15 0 0 30 0 31 0
Example
SWT
OR MCP Interrupt Controller
IRQ[0:7]
SIU Int. Sources
PPC INT
Port C[0:15]
CPM Int. Sources
SMI*
SIU Sources PIT TMCNT PCI
Description
1. The interrupt controller handles all the interrupt sources shown. 2. IRQ[0:7] can be individually programmed to be either edge or level sensitive. 3. Port C[0:15] can be individually programmed to be either negative edge sensitive or both edges. 4. There’ a separate input to the PPC for the NMI interrupt sources, SWT and s IRQ0. If one of these asserts and: If.. MSR[ME] HID0[EMCP] 0 0 1 0 1 1 Then.. Interrupt is ignored Core must terminate operation Interrupt is ignored Machine check exception occurs
SIPRR - SIU Interrupt Priority Register 0 1 2 3 4 5 6 7 8 XS1P XS2P XS3P 16 17 18 19 20 21 XS5P XS6P 22

9
10 11 XS4P
12
13
23 24 25 26 27 XS7P XS8P
SCPRR_H - CPM Interrupt Priority Register High 0 1 2 3 4 5 6 7 8 9 10 11 XC1P XC2P XC3P XC4P 16 17 18 19 20 21 XC5P XC6P 22 23 24 25 26 27 XC7P XC8P
SIPNR_H - SIU Interrupt Pending Register High 0 1 2 3 4 5 6 7 8 9 10 PC PC PC PC PC PC PC PC PC PC PC 0 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 21 22 23 24 25 26 IR IR IR IR IR IR IR IR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SIPNR_L - SIU Interrupt Pending Register Low 0 1 2 3 4 5 6 7 8 9 FC FC FC MC MC SC SC C1 C2 C3 C1 C2 C1 C2 16 17 18 19 20 21 22 23 24 25 I2 SP R- SM SM IDMIDMIDMIDM SD C I TT C1 C2 A1 A2 A3 A4 MA 10 SC C3 26 -
Interrupt Controller
12 - 3
What are the IRQ pins? (2 of 2)
How to Select IRQ If.. IRQ2* and not CI*/BADDR29 IRQ3* and not WT*/BADDR30 IRQ4* and not L2_HIT* IRQ5* and not CPU_BG*/BADDR31 IRQ7* and not APE*/INT_OUT* IRQ0* and not NMI_OUT* then.. SIUMCR[L2CPC] = 01 SIUMCR[APPC] <> 2 and SIUMCR[CDIS] = 0 SIUMCR[CDIS] = 0
12
13
Interrupt Controller
12 - 5
Programming Model (2 of 4)
SCPRR_L - CPM Interrupt Priority Register Low 0 1 2 3 4 5 6 7 8 9 10 11 12 YC1P YC2P YC3P YC4P 16 17 18 YC5P 19 20 21 YC6P 22 23 24 YC7P 25 26 27 28 YC8P 13 29 30 31 P. 4-19 14 15
How to Select IRQ
SIUMCR[DPPC] = 0
Comments
1. Most of the IRQ pins are shared with other functions. Also, in many cases, a particular IRQ is available on more than one pin. This gives the user significant flexibility in choosing the desired functions. 2. The decision to use data parity will eliminate 7 IRQ pins. 3. IRQ0 is a stand-alone pin. The shared function is NMI_OUT which is selected if the 8260 is a slave.
MPC8260 Interrupt Controller
What you will learn • What is the interrupt controller? • How the interrupt controller processes interrupts • What are the interrupt sources? • What is the priority of the interrupt sources? • How to prioritize the SCCs, FCCs, MCC, and SIU sources • How to set the highest priority interrupt • How to initialize the interrupt controller • How to write an interrupt handler
Comments
1. The decision to use L2 cache will eliminate 4 IRQs.
Interrupt Controller
12 - 4
Programming Model (1 of 4)
SICR - SIU Interrupt Configuration Register 0 1 2 3 4 5 6 7 8 9 HP 10 11 12 P. 4-17 13 14 15 GS SP IU S P. 4-18 14 15 28 29 P. 4-19 14 15 28 29 30 31 30 31
Interrupt Controller
12 - 2
What are the IRQ pins? (1 of 2)
Introduction IRQ Pins The following diagram summarizes the IRQ pins. IRQ0*/NMI_OUT IRQ1*/DP1/EXT_BG2 and IRQ1*/GBL* IRQ2*/DP2/TLBISYNC/EXT_DBG2 and IRQ2*/ABB* and IRQ2*/CI*/BADDR29 IRQ3*/DP3/CKSTP_OUT/EXT_BR3 and IRQ3*/DBB* and IRQ3*/WT*/BADDR30 IRQ4*/DP4/CORE_RESET/EXT_BG3 and IRQ4*/L2_HIT* IRQ5*/DP5/TBEN/EXT_DBG3 and IRQ5*/CPU_BG*/BADDR31 IRQ6*/DP6/CSE0 IRQ7*/DP7/CSE1 and IRQ7*/APE*/INT_OUT* If.. IRQ2,3* and not ABB*,DBB* IRQ1* and not GBL* IRQ1* and not DP1/EXT_BG2 IRQ2* and not DP2/TLBISYNC/EXT_ IRQ3* and not DP3/CKSTP_OUT/EX IRQ4* and not DP4/CORE_RESET/EX IRQ5* and not DP5/TBEN/EXT_DBG3 IRQ6* and not DP6/CSE0 IRQ7* and not DP7/CSE1 then.. SIUMCR[BBD] = 1 SIUMCR[ESE] = 0
11 PC 11 27
P. 4-21 12 13 14 15 PC PC PC PC 12 13 14 15 28 29 30 31 TM PI PC CNT T I 12 13 28 29 30 31 TM TM TM R2 R3 R4 P. 4-21 14 15
11 SC C4 27 TM R1