FPGA可编程逻辑器件芯片XC3S400A-4FT256I中文规格书

STAT_RX_PCSL_NUMBER_0[4:0]O RX_CLK The signal STAT_RX_PCSL_NUMBER_0[4:0] indicates which PCS lane is received on physical lane 0.There are a total of 20 separate STAT_RX_PCSL_NUMBER[4:0] buses This bus is only valid when the corresponding bit of be
STAT_RX_SYNCED[19:0] is a 1. These outputs are level sensitive.
STAT_RX_PCSL_NUMBER_1[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 1.
STAT_RX_PCSL_NUMBER_2[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 2.
STAT_RX_PCSL_NUMBER_3[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 3.
STAT_RX_PCSL_NUMBER_4[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 4.
STAT_RX_PCSL_NUMBER_5[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 5.
STAT_RX_PCSL_NUMBER_6[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 6.
STAT_RX_PCSL_NUMBER_7[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 7.
STAT_RX_PCSL_NUMBER_8[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 8.
STAT_RX_PCSL_NUMBER_9[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 9.
STAT_RX_PCSL_NUMBER_10[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 10.
STAT_RX_PCSL_NUMBER_11[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 11.
STAT_RX_PCSL_NUMBER_12[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 12.
STAT_RX_PCSL_NUMBER_13[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 13.
STAT_RX_PCSL_NUMBER_14[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 14.
STAT_RX_PCSL_NUMBER_15[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 15.
STAT_RX_PCSL_NUMBER_16[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 16.
STAT_RX_PCSL_NUMBER_17[4:0]O RX_CLK This signal indicates which PCS lane is
received on physical lane 17.
Name I/O Domain Description
STAT_RX_BIP_ERR_0O RX_CLK BIP8 error indicator for PCS lane 0. A
non-zero value indicates the BIP8 signature byte was in error for the corresponding PCS lane. A non-zero value is pulsed for one clock cycle. This output is pulsed for one clock cycle to indicate an error condition. Pulses can occur in back-to-back cycles.
STAT_RX_BIP_ERR_1O RX_CLK BIP8 error indicator for PCS lane 1. STAT_RX_BIP_ERR_2O RX_CLK BIP8 error indicator for PCS lane 2. STAT_RX_BIP_ERR_3O RX_CLK BIP8 error indicator for PCS lane 3. STAT_RX_BIP_ERR_4O RX_CLK BIP8 error indicator for PCS lane 4. STAT_RX_BIP_ERR_5O RX_CLK BIP8 error indicator for PCS lane 5. STAT_RX_BIP_ERR_6O RX_CLK BIP8 error indicator for PCS lane 6. STAT_RX_BIP_ERR_7O RX_CLK BIP8 error indicator for PCS lane 7. STAT_RX_BIP_ERR_8O RX_CLK BIP8 error indicator for PCS lane 8. STAT_RX_BIP_ERR_9O RX_CLK BIP8 error indicator for PCS lane 9. STAT_RX_BIP_ERR_10O RX_CLK BIP8 error indicator for PCS lane 10. STAT_RX_BIP_ERR_11O RX_CLK BIP8 error indicator for PCS lane 11. STAT_RX_BIP_ERR_12O RX_CLK BIP8 error indicator for PCS lane 12. STAT_RX_BIP_ERR_13O RX_CLK BIP8 error indicator for PCS lane 13. STAT_RX_BIP_ERR_14O RX_CLK BIP8 error indicator for PCS lane 14. STAT_RX_BIP_ERR_15O RX_CLK BIP8 error indicator for PCS lane 15. STAT_RX_BIP_ERR_16O RX_CLK BIP8 error indicator for PCS lane 16. STAT_RX_BIP_ERR_17O RX_CLK BIP8 error indicator for PCS lane 17. STAT_RX_BIP_ERR_18O RX_CLK BIP8 error indicator for PCS lane 18. STAT_RX_BIP_ERR_19O RX_CLK BIP8 error indicator for PCS lane 19.
STAT_RX_HI_BER O RX_CLK High Bit Error Rate (BER) indicator. When set to 1, the BER is too high as defined by the 802.3. Corresponds to MDIO register bit 3.32.1 as defined in Clause 82.3. This output is level sensitive.
Name I/O Domain Description
Chapter 2:Product Specification
Table 2-9:Statistics Interface – RX Path
Name I/O Domain Description
STAT_RX_TOTAL_BYTES[7:0]O RX_CLK Increment for the total number of bytes
received.
STAT_RX_TOTAL_PACKETS[3:0]O RX_CLK Increment for the total number of packets
received.
STAT_RX_TOTAL_GOOD_BYTES[13:0]O RX_CLK Increment for the total number of good bytes received. This value is only non-zero when a packet is received completely and contains no errors.
STAT_RX_TOTAL_GOOD_PACKETS O RX_CLK Increment for the total number of good packets received. This value is only non-zero when a packet is received completely and contains no errors.
STAT_RX_PACKET_BAD_FCS O RX_CLK Increment for packets between 64 and
ctl_rx_max_packet_len bytes that have FCS errors.
STAT_RX_PACKET_64_BYTES O RX_CLK Increment for good and bad packets received
that contain 64 bytes.
STAT_RX_PACKET_65_127_BYTES O RX_CLK Increment for good and bad packets received
that contain 65 to 127 bytes.
STAT_RX_PACKET_128_255_BYTES O RX_CLK Increment for good and bad packets received
that contain 128 to 255 bytes.
STAT_RX_PACKET_256_511_BYTES O RX_CLK Increment for good and bad packets received
that contain 256 to 511 bytes.
STAT_RX_PACKET_512_1023_BYTES O RX_CLK Increment for good and bad packets received
that contain 512 to 1,023 bytes.
STAT_RX_PACKET_1024_1518_BYTES O RX_CLK Increment for good and bad packets received
that contain 1,024 to 1,518 bytes.
STAT_RX_PACKET_1519_1522_BYTES O RX_CLK Increment for good and bad packets received
that contain 1,519 to 1,522 bytes.
STAT_RX_PACKET_1523_1548_BYTES O RX_CLK Increment for good and bad packets received
that contain 1,523 to 1,548 bytes.
STAT_RX_PACKET_1549_2047_BYTES O RX_CLK Increment for good and bad packets received
that contain 1,549 to 2,047 bytes.
STAT_RX_PACKET_2048_4095_BYTES O RX_CLK Increment for good and bad packets received
that contain 2,048 to 4,095 bytes.
STAT_RX_PACKET_4096_8191_BYTES O RX_CLK Increment for good and bad packets received
that contain 4,096 to 8,191 bytes.。