74CT2526资料

TL F 10684CGS74C2525
CGS74CT2525
CGS74C2526
CGS74CT2526 1-to-8 Minimum Skew Clock Driver
September1995
CGS74C2525 CGS74CT2525
CGS74C2526 CGS74CT2526
1-to-8Minimum Skew Clock Driver
The CGS’C CT2525is a minimum skew clock driver with
one input driving eight outputs specifically designed for sig-
nal generation and clock distribution applications The’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
t PLH and t PHL transitions The’2526is similar to the’2525
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented
Features
Y These CGS devices implement National’s FACT TM
family
Y Ideal for signal generation and clock distribution
Y Guaranteed pin to pin and part to part skew
Y Multiplexed clock input(’2526)
Y Guaranteed2kV minimum ESD protection
Y Symmetric output current drive of24mA for I OL I OH
Y’CT has TTL-compatible inputs
Y These products are identical to74AC ACT2525and
2526
Y Available as Mil Aero versions
54AC ACT2525
54AC ACT2526
Logic Symbols
’2525
TL F 10684–1
’2526
TL F 10684–2
Connection Diagrams
Pin Assignment
for DIP and SOIC
’2525
TL F 10684–3
’2526
TL F 10684–4
TRI-STATE is a registered trademark of National Semiconductor Corporation
FACT TM is a trademark of National Semiconductor Corporation
C1996National Semiconductor Corporation RRD-B30M106 Printed in U S A http www national com
Functional Description
On the multiplexed clock device the SEL pin is used to determine which CLKn input will have an active effect on the outputs of the circuit When SEL e 1 the CLK1input is selected and when SEL e 0 the CLK0input is selected The non-selected CLKn input will not have any effect on the logical output level of the circuit The output pins act as a single entity and will follow the state of the CLK or CLK1 CLK0pins when either the multiplexed (’2526)or the straight (’2525)clock distribution chip is selected
Pin Description
Pin Names Description CLK
Clock Input (’2525)CLK0 CLK1Clock Inputs (’2526)O 0–O 7Outputs
SEL
Clock Select (’2526)
Truth Tables
’2525
Inputs Outputs CLK O 0–O 7L L H
H ’2526Inputs
Outputs CLK0CLK1SEL O 0–O 7L X L L H X L H X L H L X
H
H
H
L e Low Voltage Level H e High Voltage Level X e Immaterial
’2525TL F 10684–7’2526
TL F 10684–8
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Absolute Maximum Ratings(Note1)
If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage(V CC)b0 5V to a7 0V DC Input Diode Current(I IK)
V I e b0 5V b20mA V I e V CC a0 5V a0 2mA DC Input Voltage(V I)b0 5V to(V CC a0 5V) DC Output Diode Current(I OK)
V O e0 5V b20mA V O e V CC a0 5V a20mA DC Output Voltage(V O)b0 5V to(V CC a0 5V) DC Output Source
or Sink Current(I O)g50mA DC V CC or Ground Current
per Output Pin(I CC or I GND)g50MA Storage Temperature(T STG)b65 C to a150 C Junction Temperature(i JA)
Plastic(N)14-Lead102 C W Plastic(M)14-Lead128 C W Plastic(N)16-Lead97 C W Plastic(M)16-Lead124 C W Recommended Operating Conditions
Supply Voltage(V CC)
‘C’2 0V to6 0V ‘CT’4 5V to5 5V Input Voltage(V I)0V to V CC Output Voltage(V O)0V to V CC Operating Temperature(T A)
CGS74C CT b40 C to a85 C 54AC ACT b55 C to a125 C Input Rise and Fall Times Devices
(30%to70%of V CC)
V CC e3 3V10 5ns max
4 5V14 4ns max
5 5V17 6ns max Input Rise and Fall Times Devices
(0 8V to2 0V)9 6ns max Note1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recom-mend operation of CGS circuits outside databook specifications
DC Electrical Characteristics for CGS74C and54AC Family Devices Over recommended operating conditions unless specified otherwise
CGS74C54AC CGS74C
Symbol Parameter V CC
T A e a25 C
T A e T A e
Units Conditions (V)b55 C to a125 C b40 C to a85 C
Typ Guaranteed Limits
V IH Minimum High Level3 01 52 12 12 1V OUT e0 1V Input Voltage4 52 253 153 153 15V or V CC b0 1V
5 52 753 853 853 85
V IL Maximum Low Level3 01 50 90 90 9V OUT e0 1V Input Voltage4 52 251 351 351 35V or V CC b0 1V
5 52 751 651 651 65
V OH Minimum High Level3 02 992 92 92 9I OUT e b50m A Output Voltage4 54 494 44 44 4V
(Note2)5 55 495 45 45 4
V IN e V IL or V IH
3 02 562 42 46b12mA
4 53 863 73 76V I OH b24mA
5 54 864 74 76b24mA
V OL Maximum Low Level3 00 0020 10 10 1I OUT e50m A Output Voltage4 50 0010 10 10 1V
(Note2)5 50 0010 10 10 1
V IN e V IL or V IH
3 00 360 400 4412mA
4 50 360 500 44V
I OL 24mA
5 50 360 500 4424mA
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DC Electrical Characteristics for CGS74C and 54AC Family Devices (Continued)
Over recommended operating conditions unless specified otherwise
CGS74C
54AC CGS74C Symbol
Parameter
V CC T A e a 25 C T A e
T A e
Units
Conditions
(V)
b 55 C to a 125 C
b 40 C to a 85 C
Typ
Guaranteed Limits
I IN
Maximum Input 5 5g 0 1
g 1 0
g 1 0
m A Leakage Current V I e V CC GND (Note 3)
I OLD Minimum Dynamic 5 550
75
mA V OLD e 1 65V Max I OHD Output Current 5 5
b 50
b 75
mA V OHD e 3 85V Min (Note 4)
I CC
Maximum Quiescent 5 58 080 080 0
m A
V IN e V CC Supply Current or GND
(Note 3)
DC Electrical Characteristics for CGS74CT and 54ACT Family Devices
Over recommended operating conditions unless specified otherwise
CGS74CT
54ACT CGS74CT Symbol
Parameter
V CC T A e a 25 C T A e
T A e
Units
Conditions
(V)
b 55 C to a 125 C
b 40 C to a 85 C
Typ
Guaranteed Limits V IH Minimum High Level 4 51 52 02 02 0V V OUT e 0 1V Input Voltage 5 51 52 02 02 0or V CC b 0 1V V IL Maximum Low Level 4 51 50 80 80 8V V OUT e 0 1V Input Voltage 5 51 50 80 80 8or V CC b 0 1V V OH
Minimum High Level 4 54 494 44 44 4V
I OUT e b 50m A Output Voltage 5 55 49
5 45 45 4(Note 2)
V IN e V IL or V IH
4 53 863 703 76V
I OH
b 24mA
5 5
4 864 704 76b 24mA V OL
Maximum Low Level 4 50 0010 10 10 1V
I OUT e 50m A Output Voltage 5 50 0010 10 10 1(Note 2)
V IN e V IL or V IH
4 50 360 500 44V
I OL
24mA
5 5
0 36
0 50
0 44
24mA I IN Maximum Input 5 5g 0 1
g 1 0
g 1 0
m A V I e V CC GND Leakage Current I CCT Maximum I CC Input 5 50 61 61 5mA V I e V CC b 2 1V I OLD Minimum Dynamic 5 550
75
mA V OLD e 1 65V Max I OHD Output Current 5 5
b 50
b 75
mA
V OHD e 3 85V Min (Note 4)
I CC
Maximum Quiescent 5 58 0160 080 0m A
V IN e V CC Supply Current or GND
(Note 5)
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AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise
(Note 6)Range V CC (V)CGS74C
54AC CGS74C T A e a 25 C T A e b 55 C T A e b 40 C Symbol Parameter
C L e 50pF to a 125 C to a 85 C Units
C L e 50pF C L e 50pF Min
Typ Max Min Max Min Typ
Max t PLH Propagation Delay 3 33 06 511 03 011 03 012 5ns t PHL CLK to O n (’2525)5 03 25 07 82 5
8 2
2 98 1t PLH Propagation Delay
3 33 07 013 03 01
4 0ns t PHL CLKn to O n (’2526)
5 03 65 57 83 38 6t PLH Propagation Delay 3 33 08 014 03 015 0ns t PHL SEL to O n (’2526)5 04 0
6 58 5
3 5
9 5t OSHL
Maximum Skew 3 30 31 5600
Common Edge
ps
Output-to-Output (Note 7)5 00 21 0500Variation
t OSLH
Maximum Skew 3 30 31 5600
Common Edge
ps
Output-to-Output (Note 7)5 0
0 2
1 0500
Variation
t OST
Maximum Skew 1 5
Opposite Edge
5 00 41 0
1 0ns
Output-to-Output (Note 7)1 0
Variation t PV
Maximum Skew ’C2525Part-to-Part
’CT25255 03 54 0ns Variation (Note 8)
’C2526’CT2526
5 05 0ns
t rise Maximum
t fall Rise Fall Time 5 0
3 0
4 03 75ns
(20%to 80%V CC )t rise Maximum
t fall
Rise Fall Time
0 91 1ns
(0 8V 2 0V and 2 0V 0 8V)
AC Electrical Characteristics Over recommended operating conditions unless specified otherwise
(Note 6)
Range V CC (V)CGS74CT
54ACT CGS74CT T A e a 25 C T A e b 55 C T A e b 40 C Symbol
Parameter
C L e 50pF
to a 125 C to a 85 C Units
C L e 50pF C L e 50pF Min
Typ Max Min
Max
Min Max t PLH Propagation Delay 5 04 66 59 04 010 1ns t PHL CLK to O n (’2525)t PLH Propagation Delay 5 0
5 8
8 5
11 1
5 1
12 4
ns t PHL
CLKn to O n (’2526)
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AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise (Continued)
(Note 6)
Range V CC (V)CGS74CT
54ACT CGS74CT T A e a 25 C T A e b 55 C T A e b 40 C Symbol
Parameter
C L e 50pF
to a 125 C to a 85 C Units
C L e 50pF C L e 50pF Min
Typ Max Min
Max
Min Typ
Max t PLH Propagation Delay 5 0
5 1
8 5
12 4
4 4
14 1
ns t PHL SEL to O n (’2526)t OSHL
Maximum Skew Common Edge
5 00 2550ps
Output-to-Output (Note 7)Variation
t OSLH
Maximum Skew Common Edge
5 00 2550ps
Output-to-Output (Note 7)Variation
t OST
Maximum Skew Opposite Edge
5 00 41 0ns
Output-to-Output (Note 7)Variation t PV
Maximum Skew AC2525Part-to-Part
ACT2525Variation (Note 8)
AC25265 03 5ns ACT2526
5 05 0ns t rise Maximum
t fall Rise Fall Time 5 0
3 0
3 75
ns
(20%to 80%V CC )t rise Maximum
t fall
Rise Fall Time
0 91 1ns
(0 8V 2 0V and 2 0V 0 8V)
Note 2 All outputs loaded thresholds on input associated with output under test Note 3 I IN and I CC 3 0V are guaranteed to be less than or equal to the respective limit
5 5V V CC
I CC for 54AC 25 C is identical to CGS74C 25 C Note 4 Maximum test duration 2 0ms one output loaded at a time Note 5 I CC for 54ACT 25 C is identical to CGS74CT 25 C
Note 6 Voltage Range 5 0is 5 0V g 0 5V voltage range 3 3is 3 3V g 0 3V
Note 7 Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device The specifications apply to any outputs switching in the same direction either HIGH to LOW (t OSHL )or LOW to HIGH (t OSLH )or in opposite directions both HL and LH (t OST ) t OSHL and t OSLH are characterized and guaranteed by design 1MHz
Note 8 Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device The parameter is specified for a given set of conditions (i e capacitive load V CC temperature of outputs switching etc ) Parameter guaranteed by design Note 9 Load capacitance includes the test jig
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Capacitance
Symbol Parameter Typ Units Conditions
C IN Input Capacitance4 5pF V CC e5 0V
C P
D Power Dissipation Capacitance(’2525)820pF–1 2x10b18(f) pF V CC e5 0V
C P
D Power Dissipation Capacitance(’2526)820pF–1 2x10b18(f) pF V CC e5 0V
f e frequency
Recommended Maximum Power Dissipation(W)
LFPM
T A e25 C T A e85 C
PDIP SOIC PDIP SOIC
01 1050 8580 5280 41
2251 4931 0550 7140 504
5001 711 2100 8200 578
Timing Diagrams
TL F 10684–27
TL F 10684–28
Test Circuit
TL F 10684–29
R L is500X
C L is50pF for all prop delays and skew measurements
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Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows
TL F 10684–26 Physical Dimensions inches(millimeters)unless otherwise noted
14-Lead Small Outline Integrated Circuit(M)
NS Package Number M14A
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Physical Dimensions inches(millimeters)unless otherwise noted(Continued)
16-Lead Small Outline Integrated Circuit(M)
NS Package Number M16A
14-Lead Plastic Dual-In-Line Package(N)
NS Package Number N14A
9
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C G S 74C 2525 C G S 74C T 2525 C G S 74C 2526 C G S 74C T 25261-t o -8M i n i m u m S k e w C l o c k
D r i v e r
Physical Dimensions inches (millimeters)unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (N)
NS Package Number N16E
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be reasonably expected to result in a significant injury to the user
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