MEMORY存储芯片MT45W8MW16BGX-708IT中文规格书

Table 22: MR6 Register Definition (Continued)
Data Rate Programming The device controller must program the correct data rate according to the operating fre-quency.
V REFDQ Calibration Enable
V REFDQ calibration is where the device internally generates its own V REFDQ to be used by the DQ input receivers. The V REFDQ value will be output on any DQ of DQ[3:0] for evalu-ation only. The device controller is responsible for setting and calibrating the internal V REFDQ level using an MRS protocol (adjust up, adjust down, and so on). It is assumed that the controller will use a series of writes and reads in conjunction with V REFDQ ad-justments to optimize and verify the data eye. Enabling V REFDQ calibration must be used whenever values are being written to the MR6[6:0] register.
V REFDQ Calibration Range
The device defines two V REFDQ calibration ranges: Range 1 and Range 2. Range 1 sup-ports V REFDQ between 60% and 92% of V DDQ while Range 2 supports V REFDQ between 45% and 77% of V DDQ , as seen in V REFDQ Specification table. Although not a restriction,Range 1 was targeted for module-based designs and Range 2 was added to target point-to-point designs.
V REFDQ Calibration Value
Fifty settings provide approximately 0.65% of granularity steps sizes for both Range 1and Range 2 of V REFDQ , as seen in V REFDQ Range and Levels table in the V REFDQ Calibra-tion section.
8Gb: x4, x8, x16 DDR4 SDRAM Mode Register 6
Figure 215: Rx Mask Without Write Training
CENTDQ,midpoint
V IL(DC)V IH(DC)Table 93: Rx Mask and t DS/t DH without Write Training
Note: 1.V IHL(AC), V diVW , and V ILH(DC) referenced to V CENTDQ,midpoint .
Connectivity Test (CT) Mode Input Levels
Table 94: TEN Input Levels (CMOS)
8Gb: x4, x8, x16 DDR4 SDRAM Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels
t RPRE Calculation
Figure 129: t RPRE Method for Calculating Transitions and Endpoints
CK_t
CK_c
Single-ended signal provided as background information
DDQ
Notes: 1.V sw1 = (0.3 - 0.04) × V DDQ .
2.V sw2 = (0.30 + 0.04) × V DDQ .
3.DQS_t and DQS_c low level = V DDQ /(50 + 34) × 34 = 0.4 × V DDQ
Driver impedance = RZQ/7 = 34˖
V TT test load = 50˖ to V DDQ .
8Gb: x4, x8, x16 DDR4 SDRAM READ Operation。