booth乘法器

Booth乘法器verilog代码（3：2）压缩
将每个模块的代码建一个.V文件，然后选中测试文件进行仿真。

本程序可仿真成功。

Booth编码规则
例子
测试文件
module tb_booth_mul();
reg signed [15:0] multiplicand;
reg signed [15:0] multiplier;
wire [31:0] product;
reg clock,reset;
initial
begin
reset<=0;
clock <= 1'b0 ;
forever
#5 clock <= ~clock ;
end
always @(posedge clock)
begin
#5
multiplicand <= $random($random);
multiplier <= $random($random);
end
//instantiation
booth_mul u_booth_mul (
.multiplicand(multiplicand),
.multiplier(multiplier), .product(product),
.clk(clock),
.reset(reset)
);
endmodule
booth乘法器主程序文件（不压缩）
module booth_mul(multiplicand,multiplier,product,clk,reset);
parameter BITWIDTH = 16;
input clk,reset;
input [BITWIDTH-1:0] multiplier;
input [BITWIDTH-1:0] multiplicand;
output [2*BITWIDTH-1:0] product;
reg [2*BITWIDTH-1:0] product;
reg [15:0] multiplicand1,multiplier1;
wire [8:0] ss;
wire a,e0,e1;
wire s0,s1,s2,s3,s4,s5,s6,s7,s8;
wire [2*BITWIDTH-1:0] tmp_prod;
wire [BITWIDTH+3:0] j0;
wire [BITWIDTH+2:0] j1,j2,j3,j4,j5,j6;
wire [BITWIDTH+1:0] j7;
wire [BITWIDTH:0] j8;
assign e0=multiplicand[15];
assign e1=multiplier[15];
assign a= e0|e1;
always@ (posedge clk or posedge reset or negedge clk)
begin
if(reset)
product <=0;
else
begin
if(a)
begin
if(multiplicand[15]) multiplicand1 <= ~multiplicand+1'b1;
else multiplicand1 <= multiplicand;
if(multiplier[15]) multiplier1 <= ~multiplier+1'b1;
else multiplier1 <= multiplier;
end
else
{multiplicand1,multiplier1}<={multiplicand,multiplier};
end
end
//partial product
bfj_9 j_9(
.multiplicand1(multiplicand1),
.multiplier1(multiplier1),
.s0(s0),.s1(s1),.s2(s2),.s3(s3),.s4(s4),
.s5(s5),.s6(s6),.s7(s7),.s8(s8),
.j0(j0),.j1(j1),
.j2(j2),.j3(j3),
.j4(j4),.j5(j5),
.j6(j6),.j7(j7),
.j8(j8)
);
assign
tmp_prod=j0000+{j1000[25:0],6'b000000}+{s7,1'b0,s6,1'b0,s5,1'b0,s4,1'b0,s3,1'b0,s2,1'b0,s1,1'b0,s0} ;
//partial product accumulator
assign tp1 = j0+{j1,1'b0,s0};
assign tp2 = tp1[BITWIDTH+5:2] + {j2,1'b0,s1};
assign tmp_prod[3:2] = tp2[1:0];
assign tp3 = tp2[BITWIDTH+5:2] + {j3,1'b0,s2};
assign tmp_prod[5:4] = tp3[1:0];
assign tp4 = tp3[BITWIDTH+5:2] + {j4,1'b0,s3};
assign tmp_prod[7:6] = tp4[1:0];
assign tp5 = tp4[BITWIDTH+5:2] + {j5,1'b0,s4};
assign tmp_prod[9:8] = tp5[1:0];
assign tp6 = tp5[BITWIDTH+5:2] + {j6,1'b0,s5};
assign tmp_prod[11:10] = tp6[1:0];
assign tp7 = tp6[BITWIDTH+5:2] + {j7,1'b0,s6};
assign tmp_prod[13:12] = tp7[1:0];
assign tp8 = tp7[BITWIDTH+5:2] + {j8[BITWIDTH-1],1'b0,s7};
assign tmp_prod[2*BITWIDTH-1:14] = tp8[BITWIDTH+1:0];
always@ (posedge clk or posedge reset or posedge clk)
if(reset) product <=0;
else if(e0^e1) product<={1'b1,~tmp_prod[2*BITWIDTH-2:0]+1'b1}; else product <= tmp_prod;
endmodule
booth乘法器3：2压缩文件
module booth_mul(multiplicand,multiplier,product,clk,reset); parameter BITWIDTH = 16;
input clk,reset;
input [BITWIDTH-1:0] multiplier;
input [BITWIDTH-1:0] multiplicand;
output [2*BITWIDTH-1:0] product;
reg [2*BITWIDTH-1:0] product;
reg [15:0] multiplicand1,multiplier1;
wire [8:0] ss;
wire a,e0,e1;
wire s0,s1,s2,s3,s4,s5,s6,s7,s8;
wire [2*BITWIDTH-1:0] tmp_prod;
wire [BITWIDTH+3:0] tp8;
wire [BITWIDTH+5:0] tp1,tp2,tp3,tp4,tp5,tp6,tp7;
wire [BITWIDTH+3:0] j0;
wire [BITWIDTH:0] j8;
assign e0=multiplicand[15];
assign e1=multiplier[15];
assign a= e0|e1;
always@ (posedge clk or posedge reset or negedge clk)
begin
if(reset)
product <=0;
else
begin
if(a)
begin
if(multiplicand[15]) multiplicand1 <= ~multiplicand+1'b1; else multiplicand1 <= multiplicand;
if(multiplier[15]) multiplier1 <= ~multiplier+1'b1;
else multiplier1 <= multiplier;
end
else
{multiplicand1,multiplier1}<={multiplicand,multiplier};
end
end
//partial product
bfj_9 j_9(
.multiplicand1(multiplicand1),
.multiplier1(multiplier1),
.s0(s0),.s1(s1),.s2(s2),.s3(s3),.s4(s4),
.s5(s5),.s6(s6),.s7(s7),.s8(s8),
.j0(j0),.j1(j1),
.j2(j2),.j3(j3),
.j4(j4),.j5(j5),
.j6(j6),.j7(j7),
.j8(j8)
);
//3:2 yasuo1:9->6
wire [21:0] j0_s,j1_s;
wire [19:0] j0_c,j1_c,j2_s;
wire [17:0] j2_c;
yasuo1 y9_6(
.j0(j0),.j1(j1),
.j6(j6),.j7(j7),
.j8(j8),
.j0_s(j0_s),.j0_c(j0_c),
.j1_s(j1_s),.j1_c(j1_c),
.j2_s(j2_s),.j2_c(j2_c)
);
//3:2 yasuo2:6->4
wire [23:0] j00_s,j00_c;
wire [22:0] j10_s;
wire [19:0] j10_c;
yasuo2 y6_4(
.j00(j0_s),.j01(j0_c),
.j10(j1_s),.j11(j1_c),
.j20(j2_s),.j21(j2_c),
.j00_s(j00_s),.j00_c(j00_c),
.j10_s(j10_s),.j10_c(j10_c)
);
//3:2 yasuo3:4->3
wire [28:0] j20_s;
wire [26:0] j20_c;
yasuo3 y4_3(
.j000(j00_s),.j100(j00_c),
.j200(j10_s),
.j20_s(j20_s),.j20_c(j20_c)
);
//3:2 yasuo4:3->2
wire [31:0] j0000;
wire [26:0] j1000;
yasuo4 y3_2(
.j10(j20_s),
.j20(j20_c),.j30(j10_c),
.j0000(j0000),.j1000(j1000)
);
assign
tmp_prod=j0000+{j1000[25:0],6'b000000}+{s7,1'b0,s6,1'b0,s5,1'b0,s4,1'b0,s3,1'b0,s2,1'b0,s1,1'b0,s0} ;
always@ (posedge clk or posedge reset or posedge clk)
if(reset) product <=0;
else if(e0^e1) product<={1'b1,~tmp_prod[2*BITWIDTH-2:0]+1'b1};
else product <= tmp_prod;
加法器
module add3(a,b,c,si,ci);
input a,b,c;
output si,ci;
wire si,ci;
assign si=a^b^c;
assign ci=a&b|(a^b)&c;
endmodule
booth 编码
module booth_recoder(
multiplicand,
code,
pp,
s
);
parameter BITWIDTH = 16;
input [BITWIDTH-1:0] multiplicand;
input [2:0] code;
output [BITWIDTH:0] pp;
output s;
reg [BITWIDTH:0] pp;
reg s;
always @ (multiplicand or code)
case(code)
3'b000:pp = {(BITWIDTH+1){1'b0}};//+0
3'b001:pp = {multiplicand[15],multiplicand}; //+M
3'b010:pp = {multiplicand[15],multiplicand}; //+M
3'b011:pp = {multiplicand,1'b0}; //+2M
3'b100:pp = {~multiplicand,1'b1};//-2M
3'b101:pp = {~multiplicand[15],(~multiplicand)};//-M 3'b110:pp = {~multiplicand[15],(~multiplicand)};//-M 3'b111:pp = {(BITWIDTH+1){1'b1}};//-0
endcase
always @ (multiplicand or code)
case(code[2])
1'b0:s = 1'b0;//+0,+M,+2M
1'b1:s = 1'b1;//-2M,-M,-0
endmodule
booth部分集产生
module bfj_9(multiplicand1,multiplier1,s0,s1,s2,s3,s4,s5,s6,s7,s8,j0,j1,j2,j3,j4,j5,j6,j7,j8);
parameter BITWIDTH = 16;
input [BITWIDTH-1:0]multiplicand1,multiplier1;
output s0,s1,s2,s3,s4,s5,s6,s7,s8;
output [BITWIDTH+3:0] j0;
output [BITWIDTH+2:0] j1,j2,j3,j4,j5,j6;
output [BITWIDTH+1:0] j7;
output [BITWIDTH:0] j8;
wire [BITWIDTH:0] pp0,pp1,pp2,pp3,pp4,pp5,pp6,pp7,pp8;
wire s0,s1,s2,s3,s4,s5,s6,s7,s8;
wire [BITWIDTH+3:0] j0;
wire [BITWIDTH+2:0] j1,j2,j3,j4,j5,j6;
wire [BITWIDTH+1:0] j7;
wire [BITWIDTH:0] j8;
booth_recoder #(BITWIDTH) br0(
.multiplicand(multiplicand1),
.code({multiplier1[1:0],1'b0}),
.pp(pp0),
.s(s0)
);
booth_recoder #(BITWIDTH) br1(
.multiplicand(multiplicand1),
.code(multiplier1[3:1]),
.pp(pp1),
.s(s1)
);
booth_recoder #(BITWIDTH) br2(
.multiplicand(multiplicand1),
.code(multiplier1[5:3]),
.pp(pp2),
.s(s2)
);
booth_recoder #(BITWIDTH) br3(
.multiplicand(multiplicand1),
.code(multiplier1[7:5]),
.pp(pp3),
.s(s3)
);
.multiplicand(multiplicand1), .code(multiplier1[9:7]),
.pp(pp4),
.s(s4)
);
booth_recoder #(BITWIDTH) br5(
.multiplicand(multiplicand1), .code(multiplier1[11:9]),
.pp(pp5),
.s(s5)
);
booth_recoder #(BITWIDTH) br6(
.multiplicand(multiplicand1), .code(multiplier1[13:11]),
.pp(pp6),
.s(s6)
);
booth_recoder #(BITWIDTH) br7(
.multiplicand(multiplicand1), .code(multiplier1[15:13]),
.pp(pp7),
.s(s7)
);
booth_recoder #(BITWIDTH) br8(
.multiplicand(multiplicand1), .code({2'b00,multiplier1[15]}), .pp(pp8),
.s(s8)
);
assign j0 = {~s0,s0,s0,pp0};
assign j1 = {1'b1,~s1,pp1};
assign j2 = {1'b1,~s2,pp2};
assign j3 = {1'b1,~s3,pp3};
assign j4 = {1'b1,~s4,pp4};
assign j5 = {1'b1,~s5,pp5};
assign j6 = {1'b1,~s6,pp6};
assign j7 = {~s7,pp7};
assign j8 = pp8[15:0];
endmodule
input [19:0] j0;
input [18:0] j1,j2,j3,j4,j5,j6;
input [17:0] j7;
input [16:0] j8;
output [21:0] j0_s,j1_s;
output [19:0] j0_c,j1_c,j2_s;
output [17:0] j2_c;
wire [21:0] j0_s,j1_s;
wire [19:0] j0_c,j1_c,j2_s;
wire [17:0] j2_c;
//j0_s,j0_c
assign j0_s[21]=j2[17];
assign j0_s[1]=j0[1];
assign j0_s[0]=j0[0];
assign j0_c[19]=j2[18];
add3 a1 (.a(1'b0), .b(j1[18]), .c(j2[16]), .si(j0_s[20]), .ci(j0_c[18])); add3 a2 (.a(j0[19]), .b(j1[17]), .c(j2[15]), .si(j0_s[19]), .ci(j0_c[17])); add3 a3 (.a(j0[18]), .b(j1[16]), .c(j2[14]), .si(j0_s[18]), .ci(j0_c[16])); add3 a4 (.a(j0[17]), .b(j1[15]), .c(j2[13]), .si(j0_s[17]), .ci(j0_c[15])); add3 a5 (.a(j0[16]), .b(j1[14]), .c(j2[12]), .si(j0_s[16]), .ci(j0_c[14])); add3 a6 (.a(j0[15]), .b(j1[13]), .c(j2[11]), .si(j0_s[15]), .ci(j0_c[13])); add3 a7 (.a(j0[14]), .b(j1[12]), .c(j2[10]), .si(j0_s[14]), .ci(j0_c[12])); add3 a8 (.a(j0[13]), .b(j1[11]), .c(j2[9]), .si(j0_s[13]), .ci(j0_c[11])); add3 a9 (.a(j0[12]), .b(j1[10]), .c(j2[8]), .si(j0_s[12]), .ci(j0_c[10])); add3 a10(.a(j0[11]), .b(j1[9]), .c(j2[7]), .si(j0_s[11]), .ci(j0_c[9])); add3 a11(.a(j0[10]), .b(j1[8]), .c(j2[6]), .si(j0_s[10]), .ci(j0_c[8])); add3 a12(.a(j0[9]), .b(j1[7]), .c(j2[5]), .si(j0_s[9]), .ci(j0_c[7])); add3 a13(.a(j0[8]), .b(j1[6]), .c(j2[4]), .si(j0_s[8]), .ci(j0_c[6])); add3 a14(.a(j0[7]), .b(j1[5]), .c(j2[3]), .si(j0_s[7]), .ci(j0_c[5])); add3 a15(.a(j0[6]), .b(j1[4]), .c(j2[2]), .si(j0_s[6]), .ci(j0_c[4])); add3 a16(.a(j0[5]), .b(j1[3]), .c(j2[1]), .si(j0_s[5]), .ci(j0_c[3])); add3 a17(.a(j0[4]), .b(j1[2]), .c(j2[0]), .si(j0_s[4]), .ci(j0_c[2])); add3 a18(.a(j0[3]), .b(j1[1]), .c(1'b0), .si(j0_s[3]), .ci(j0_c[1])); add3 a19(.a(j0[2]), .b(j1[0]), .c(1'b0), .si(j0_s[2]), .ci(j0_c[0]));
//j1_s,j1_c
assign j1_s[21]=j5[17];
assign j1_c[19]=j5[18];
add3 a20(.a(1'b0), .b(j4[18]), .c(j5[16]), .si(j1_s[20]), .ci(j1_c[18])); add3 a21(.a(1'b0), .b(j4[17]), .c(j5[15]), .si(j1_s[19]), .ci(j1_c[17])); add3 a22(.a(j3[18]), .b(j4[16]), .c(j5[14]), .si(j1_s[18]), .ci(j1_c[16])); add3 a23(.a(j3[17]), .b(j4[15]), .c(j5[13]), .si(j1_s[17]), .ci(j1_c[15])); add3 a24(.a(j3[16]), .b(j4[14]), .c(j5[12]), .si(j1_s[16]), .ci(j1_c[14])); add3 a25(.a(j3[15]), .b(j4[13]), .c(j5[11]), .si(j1_s[15]), .ci(j1_c[13])); add3 a26(.a(j3[14]), .b(j4[12]), .c(j5[10]), .si(j1_s[14]), .ci(j1_c[12])); add3 a27(.a(j3[13]), .b(j4[11]), .c(j5[9]), .si(j1_s[13]), .ci(j1_c[11])); add3 a28(.a(j3[12]), .b(j4[10]), .c(j5[8]), .si(j1_s[12]), .ci(j1_c[10])); add3 a29(.a(j3[11]), .b(j4[9]), .c(j5[7]), .si(j1_s[11]), .ci(j1_c[9])); add3 a30(.a(j3[10]), .b(j4[8]), .c(j5[6]), .si(j1_s[10]), .ci(j1_c[8])); add3 a31(.a(j3[9]), .b(j4[7]), .c(j5[5]), .si(j1_s[9]), .ci(j1_c[7])); add3 a32(.a(j3[8]), .b(j4[6]), .c(j5[4]), .si(j1_s[8]), .ci(j1_c[6])); add3 a33(.a(j3[7]), .b(j4[5]), .c(j5[3]), .si(j1_s[7]), .ci(j1_c[5])); add3 a34(.a(j3[6]), .b(j4[4]), .c(j5[2]), .si(j1_s[6]), .ci(j1_c[4])); add3 a35(.a(j3[5]), .b(j4[3]), .c(j5[1]), .si(j1_s[5]), .ci(j1_c[3])); add3 a36(.a(j3[4]), .b(j4[2]), .c(j5[0]), .si(j1_s[4]), .ci(j1_c[2])); add3 a37(.a(j3[3]), .b(j4[1]), .c(1'b0), .si(j1_s[3]), .ci(j1_c[1])); add3 a38(.a(j3[2]), .b(j4[0]), .c(1'b0), .si(j1_s[2]), .ci(j1_c[0]));
//j2_s,j2_c
assign j2_s[1]=j6[1];
assign j2_s[0]=j6[0];
add3 a39(.a(1'b0), .b(j7[17]), .c(j8[15]), .si(j2_s[19]), .ci(j2_c[17])); add3 a40(.a(j6[18]), .b(j7[16]), .c(j8[14]), .si(j2_s[18]), .ci(j2_c[16])); add3 a41(.a(j6[17]), .b(j7[15]), .c(j8[13]), .si(j2_s[17]), .ci(j2_c[15])); add3 a42(.a(j6[16]), .b(j7[14]), .c(j8[12]), .si(j2_s[16]), .ci(j2_c[14])); add3 a43(.a(j6[15]), .b(j7[13]), .c(j8[11]), .si(j2_s[15]), .ci(j2_c[13])); add3 a44(.a(j6[14]), .b(j7[12]), .c(j8[10]), .si(j2_s[14]), .ci(j2_c[12])); add3 a45(.a(j6[13]), .b(j7[11]), .c(j8[9]), .si(j2_s[13]), .ci(j2_c[11])); add3 a46(.a(j6[12]), .b(j7[10]), .c(j8[8]), .si(j2_s[12]), .ci(j2_c[10])); add3 a47(.a(j6[11]), .b(j7[9]), .c(j8[7]), .si(j2_s[11]), .ci(j2_c[9])); add3 a48(.a(j6[10]), .b(j7[8]), .c(j8[6]), .si(j2_s[10]), .ci(j2_c[8])); add3 a49(.a(j6[9]), .b(j7[7]), .c(j8[5]), .si(j2_s[9]), .ci(j2_c[7])); add3 a50(.a(j6[8]), .b(j7[6]), .c(j8[4]), .si(j2_s[8]), .ci(j2_c[6])); add3 a51(.a(j6[7]), .b(j7[5]), .c(j8[3]), .si(j2_s[7]), .ci(j2_c[5])); add3 a52(.a(j6[6]), .b(j7[4]), .c(j8[2]), .si(j2_s[6]), .ci(j2_c[4])); add3 a53(.a(j6[5]), .b(j7[3]), .c(j8[1]), .si(j2_s[5]), .ci(j2_c[3])); add3 a54(.a(j6[4]), .b(j7[2]), .c(j8[0]), .si(j2_s[4]), .ci(j2_c[2])); add3 a55(.a(j6[3]), .b(j7[1]), .c(1'b0), .si(j2_s[3]), .ci(j2_c[1])); add3 a56(.a(j6[2]), .b(j7[0]), .c(1'b0), .si(j2_s[2]), .ci(j2_c[0]));
endmodule
module yasuo2(j00,j01,j10,j11,j20,j21,j00_s,j00_c,j10_s,j10_c);
input [21:0] j00,j10;
input [19:0] j01,j11,j20;
input [17:0] j21;
output [23:0] j00_s,j00_c;
output [22:0] j10_s;
output [19:0] j10_c;
wire [23:0] j00_s,j00_c;
wire [22:0] j10_s;
wire [19:0] j10_c;
//j00_s,j00_c
assign j00_s[23]=j10[17];
assign j00_s[2]=j00[2];
assign j00_s[1]=j00[1];
assign j00_s[0]=j00[0];
assign j00_c[23]=j10[21];
assign j00_c[22]=j10[20];
assign j00_c[21]=j10[19];
assign j00_c[20]=j10[18];
add3 a1 (.a(1'b0), .b(j01[19]), .c(j10[16]), .si(j00_s[22]), .ci(j00_c[19]));
add3 a2 (.a(j00[21]), .b(j01[18]), .c(j10[15]), .si(j00_s[21]), .ci(j00_c[18])); add3 a3 (.a(j00[20]), .b(j01[17]), .c(j10[14]), .si(j00_s[20]), .ci(j00_c[17])); add3 a4 (.a(j00[19]), .b(j01[16]), .c(j10[13]), .si(j00_s[19]), .ci(j00_c[16])); add3 a5 (.a(j00[18]), .b(j01[15]), .c(j10[12]), .si(j00_s[18]), .ci(j00_c[15])); add3 a6 (.a(j00[17]), .b(j01[14]), .c(j10[11]), .si(j00_s[17]), .ci(j00_c[14])); add3 a7 (.a(j00[16]), .b(j01[13]), .c(j10[10]), .si(j00_s[16]), .ci(j00_c[13])); add3 a8 (.a(j00[15]), .b(j01[12]), .c(j10[9]), .si(j00_s[15]), .ci(j00_c[12])); add3 a9 (.a(j00[14]), .b(j01[11]), .c(j10[8]), .si(j00_s[14]), .ci(j00_c[11])); add3 a10(.a(j00[13]), .b(j01[10]), .c(j10[7]), .si(j00_s[13]), .ci(j00_c[10])); add3 a11(.a(j00[12]), .b(j01[9]), .c(j10[6]), .si(j00_s[12]), .ci(j00_c[9])); add3 a12(.a(j00[11]), .b(j01[8]), .c(j10[5]), .si(j00_s[11]), .ci(j00_c[8])); add3 a13(.a(j00[10]), .b(j01[7]), .c(j10[4]), .si(j00_s[10]), .ci(j00_c[7])); add3 a14(.a(j00[9]), .b(j01[6]), .c(j10[3]), .si(j00_s[9]), .ci(j00_c[6])); add3 a15(.a(j00[8]), .b(j01[5]), .c(j10[2]), .si(j00_s[8]), .ci(j00_c[5])); add3 a16(.a(j00[7]), .b(j01[4]), .c(j10[1]), .si(j00_s[7]), .ci(j00_c[4])); add3 a17(.a(j00[6]), .b(j01[3]), .c(j10[0]), .si(j00_s[6]), .ci(j00_c[3])); add3 a18(.a(j00[5]), .b(j01[2]), .c(1'b0), .si(j00_s[5]), .ci(j00_c[2])); add3 a19(.a(j00[4]), .b(j01[1]), .c(1'b0), .si(j00_s[4]), .ci(j00_c[1])); add3 a20(.a(j00[3]), .b(j01[0]), .c(1'b0), .si(j00_s[3]), .ci(j00_c[0]));
//j10_s,j10_c
assign j10_s[2]=j11[2];
assign j10_s[1]=j11[1];
assign j10_s[0]=j11[0];
add3 a21(.a(1'b0), .b(j20[19]), .c(j21[16]), .si(j10_s[22]), .ci(j10_c[19]));
add3 a22(.a(1'b0), .b(j20[18]), .c(j21[15]), .si(j10_s[21]), .ci(j10_c[18]));
add3 a23(.a(1'b0), .b(j20[17]), .c(j21[14]), .si(j10_s[20]), .ci(j10_c[17]));
add3 a24(.a(j11[19]), .b(j20[16]), .c(j21[13]), .si(j10_s[19]), .ci(j10_c[16])); add3 a25(.a(j11[18]), .b(j20[15]), .c(j21[12]), .si(j10_s[18]), .ci(j10_c[15])); add3 a26(.a(j11[17]), .b(j20[14]), .c(j21[11]), .si(j10_s[17]), .ci(j10_c[14])); add3 a27(.a(j11[16]), .b(j20[13]), .c(j21[10]), .si(j10_s[16]), .ci(j10_c[13])); add3 a28(.a(j11[15]), .b(j20[12]), .c(j21[9]), .si(j10_s[15]), .ci(j10_c[12])); add3 a29(.a(j11[14]), .b(j20[11]), .c(j21[8]), .si(j10_s[14]), .ci(j10_c[11])); add3 a30(.a(j11[13]), .b(j20[10]), .c(j21[7]), .si(j10_s[13]), .ci(j10_c[10])); add3 a31(.a(j11[12]), .b(j20[9]), .c(j21[6]), .si(j10_s[12]), .ci(j10_c[9])); add3 a32(.a(j11[11]), .b(j20[8]), .c(j21[5]), .si(j10_s[11]), .ci(j10_c[8])); add3 a33(.a(j11[10]), .b(j20[7]), .c(j21[4]), .si(j10_s[10]), .ci(j10_c[7])); add3 a34(.a(j11[9]), .b(j20[6]), .c(j21[3]), .si(j10_s[9]), .ci(j10_c[6])); add3 a35(.a(j11[8]), .b(j20[5]), .c(j21[2]), .si(j10_s[8]), .ci(j10_c[5])); add3 a36(.a(j11[7]), .b(j20[4]), .c(j21[1]), .si(j10_s[7]), .ci(j10_c[4])); add3 a37(.a(j11[6]), .b(j20[3]), .c(j21[0]), .si(j10_s[6]), .ci(j10_c[3])); add3 a38(.a(j11[5]), .b(j20[2]), .c(1'b0), .si(j10_s[5]), .ci(j10_c[2])); add3 a39(.a(j11[4]), .b(j20[1]), .c(1'b0), .si(j10_s[4]), .ci(j10_c[1])); add3 a40(.a(j11[3]), .b(j20[0]), .c(1'b0), .si(j10_s[3]), .ci(j10_c[0]));
endmodule
module yasuo3(j000,j100,j200,j20_s,j20_c);
input [23:0] j000,j100;
input [22:0] j200;
output [28:0] j20_s;
output [26:0] j20_c;
wire [28:0] j20_s;
wire [26:0] j20_c;
assign j20_s[28]=j200[19];
assign j20_s[3]=j000[3];
assign j20_s[2]=j000[2];
assign j20_s[1]=j000[1];
assign j20_s[0]=j000[0];
assign j20_c[26]=j200[22];
assign j20_c[25]=j200[21];
assign j20_c[24]=j200[20];
add3 a2 (.a(1'b0), .b(j100[22]), .c(j200[17]), .si(j20_s[26]), .ci(j20_c[22])); add3 a3 (.a(1'b0), .b(j100[21]), .c(j200[16]), .si(j20_s[25]), .ci(j20_c[21])); add3 a4 (.a(1'b0), .b(j100[20]), .c(j200[15]), .si(j20_s[24]), .ci(j20_c[20])); add3 a5 (.a(j000[23]), .b(j100[19]), .c(j200[14]), .si(j20_s[23]), .ci(j20_c[19])); add3 a6 (.a(j000[22]), .b(j100[18]), .c(j200[13]), .si(j20_s[22]), .ci(j20_c[18])); add3 a7 (.a(j000[21]), .b(j100[17]), .c(j200[12]), .si(j20_s[21]), .ci(j20_c[17])); add3 a8 (.a(j000[20]), .b(j100[16]), .c(j200[11]), .si(j20_s[20]), .ci(j20_c[16])); add3 a9 (.a(j000[19]), .b(j100[15]), .c(j200[10]), .si(j20_s[19]), .ci(j20_c[15])); add3 a10(.a(j000[18]), .b(j100[14]), .c(j200[9]), .si(j20_s[18]), .ci(j20_c[14])); add3 a11(.a(j000[17]), .b(j100[13]), .c(j200[8]), .si(j20_s[17]), .ci(j20_c[13])); add3 a12(.a(j000[16]), .b(j100[12]), .c(j200[7]), .si(j20_s[16]), .ci(j20_c[12])); add3 a13(.a(j000[15]), .b(j100[11]), .c(j200[6]), .si(j20_s[15]), .ci(j20_c[11])); add3 a14(.a(j000[14]), .b(j100[10]), .c(j200[5]), .si(j20_s[14]), .ci(j20_c[10])); add3 a15(.a(j000[13]), .b(j100[9]), .c(j200[4]), .si(j20_s[13]), .ci(j20_c[9])); add3 a16(.a(j000[12]), .b(j100[8]), .c(j200[3]), .si(j20_s[12]), .ci(j20_c[8])); add3 a17(.a(j000[11]), .b(j100[7]), .c(j200[2]), .si(j20_s[11]), .ci(j20_c[7])); add3 a18(.a(j000[10]), .b(j100[6]), .c(j200[1]), .si(j20_s[10]), .ci(j20_c[6])); add3 a19(.a(j000[9]), .b(j100[5]), .c(j200[0]), .si(j20_s[9]), .ci(j20_c[5])); add3 a20(.a(j000[8]), .b(j100[4]), .c(1'b0), .si(j20_s[8]), .ci(j20_c[4])); add3 a21(.a(j000[7]), .b(j100[3]), .c(1'b0), .si(j20_s[7]), .ci(j20_c[3])); add3 a22(.a(j000[6]), .b(j100[2]), .c(1'b0), .si(j20_s[6]), .ci(j20_c[2])); add3 a23(.a(j000[5]), .b(j100[1]), .c(1'b0), .si(j20_s[5]), .ci(j20_c[1])); add3 a24(.a(j000[4]), .b(j100[0]), .c(1'b0), .si(j20_s[4]), .ci(j20_c[0]));
endmodule
module yasuo4(j10,j20,j30,j0000,j1000);
input [28:0] j10;
input [26:0] j20;
input [19:0] j30;
output [31:0] j0000;
output [26:0] j1000;
wire [31:0] j0000;
wire [26:0] j1000;
assign j0000[4]=j10[4];
assign j0000[3]=j10[3];
assign j0000[2]=j10[2];
assign j0000[1]=j10[1];
assign j0000[0]=j10[0];
add3 a1 (.a(1'b0), .b(j20[26]), .c(j30[18]), .si(j0000[31]), .ci(j1000[26]));
add3 a3 (.a(1'b0), .b(j20[24]), .c(j30[16]), .si(j0000[29]), .ci(j1000[24])); add3 a4 (.a(j10[28]), .b(j20[23]), .c(j30[15]), .si(j0000[28]), .ci(j1000[23])); add3 a5 (.a(j10[27]), .b(j20[22]), .c(j30[14]), .si(j0000[27]), .ci(j1000[22])); add3 a6 (.a(j10[26]), .b(j20[21]), .c(j30[13]), .si(j0000[26]), .ci(j1000[21])); add3 a7 (.a(j10[25]), .b(j20[20]), .c(j30[12]), .si(j0000[25]), .ci(j1000[20])); add3 a8 (.a(j10[24]), .b(j20[19]), .c(j30[11]), .si(j0000[24]), .ci(j1000[19])); add3 a9 (.a(j10[23]), .b(j20[18]), .c(j30[10]), .si(j0000[23]), .ci(j1000[18])); add3 a10(.a(j10[22]), .b(j20[17]), .c(j30[9]), .si(j0000[22]), .ci(j1000[17])); add3 a11(.a(j10[21]), .b(j20[16]), .c(j30[8]), .si(j0000[21]), .ci(j1000[16])); add3 a12(.a(j10[20]), .b(j20[15]), .c(j30[7]), .si(j0000[20]), .ci(j1000[15])); add3 a13(.a(j10[19]), .b(j20[14]), .c(j30[6]), .si(j0000[19]), .ci(j1000[14])); add3 a14(.a(j10[18]), .b(j20[13]), .c(j30[5]), .si(j0000[18]), .ci(j1000[13])); add3 a15(.a(j10[17]), .b(j20[12]), .c(j30[4]), .si(j0000[17]), .ci(j1000[12])); add3 a16(.a(j10[16]), .b(j20[11]), .c(j30[3]), .si(j0000[16]), .ci(j1000[11])); add3 a17(.a(j10[15]), .b(j20[10]), .c(j30[2]), .si(j0000[15]), .ci(j1000[10])); add3 a18(.a(j10[14]), .b(j20[9]), .c(j30[1]), .si(j0000[14]), .ci(j1000[9])); add3 a19(.a(j10[13]), .b(j20[8]), .c(j30[0]), .si(j0000[13]), .ci(j1000[8])); add3 a20(.a(j10[12]), .b(j20[7]), .c(1'b0), .si(j0000[12]), .ci(j1000[7])); add3 a21(.a(j10[11]), .b(j20[6]), .c(1'b0), .si(j0000[11]), .ci(j1000[6])); add3 a22(.a(j10[10]), .b(j20[5]), .c(1'b0), .si(j0000[10]), .ci(j1000[5])); add3 a23(.a(j10[9]), .b(j20[4]), .c(1'b0), .si(j0000[9]), .ci(j1000[4])); add3 a24(.a(j10[8]), .b(j20[3]), .c(1'b0), .si(j0000[8]), .ci(j1000[3])); add3 a25(.a(j10[7]), .b(j20[2]), .c(1'b0), .si(j0000[7]), .ci(j1000[2])); add3 a26(.a(j10[6]), .b(j20[1]), .c(1'b0), .si(j0000[6]), .ci(j1000[1])); add3 a27(.a(j10[5]), .b(j20[0]), .c(1'b0), .si(j0000[5]), .ci(j1000[0]));
endmodule。