C052G102B5CX5CP中文资料
XC2005使用说明书V620资料
表 2 参数定义 说明
制袋 A 长度 ，单位：毫米。详见§ 3.2.2 。 制袋 B 长度 双步进 有效，单位：毫米。详见§ 3.2.2 。 整本数 。当累计到整本数时，计数清零，批数＋１ 色标跟踪 ，单位：脉冲步。搜索色标的最大步数， 0：无限制搜索色标直到超速。详见§ 3.2.3 。 最高频率 ，单位： Hz。详见§ 3.2.4 。 密码 。详见§ 3.2.1 。 脱料延时 ，单位： 0.1 秒。脱料动作的执行时间。 倍送（烫）。1：无倍送（烫）。2-4 ：倍送（烫）。 起始频率 ，单位： Hz。详见§ 3.2.4 。 点动频率 ，单位： Hz。详见§ 3.2.4 。 堵料一延时 ，单位： 0.1 秒 0 ：不检测堵料。 堵料二延时 ，单位： 0.1 秒 0 ：不检测堵料。 冲孔时间， 单位： 0.01 秒。 叠数设置， 到叠数后翻板脱料。 送料吹气时间， 单位： 0.1 秒。 软件版本号 。 机型 ，详见§ 3.2.5 。 机型选项 ，详见§ 3.2.5 。 胶辊直径 ，单位： 0.1 毫米。 后退步数 ，单位：脉冲步。热切机整本数后退步数。 色标补偿 ，单位：脉冲步。详见§ 3.2.3 。 启动延时 ，单位： 0.1 秒。启动前蜂鸣器预警时间。 脱料警告 。到达整本数前，提前警告的个数。 叠延长， 单位：步。在叠数状态下第一张料延长长度。 烫压后退步数： 单位：脉冲步。退送热切机退料步数。 冲孔滞后， 单位： 0.01 秒。 送料角度系数 （在自动调频状态有效）
HC-05蓝牙指令集
HC-05指今集HC-05嵌入式蓝牙串口通讯模块（以下简称模块）具有两种工作模式：命令响应工作模式和自动连接工作模式，在自动连接工作模式下模块又可分为主（Master）、从（Slave）和回环（Loopback）三种工作角色。
当模块处于自动连接工作模式时，将自动根据事先设定的方式连接的数据传输；当模块处于命令响应工作模式时能执行下述所有AT命令，用户可向模块发送各种AT指令，为模块设定控制参数或发布控制命令。
通过控制模块外部引脚（PIO11）输入电平，可以实现模块工作状态的动态转换。
串口模块用到的引脚定义：1、PIO8连接LED，指示模块工作状态，模块上电后闪烁，不同的状态闪烁间隔不同。
2、PIO9连接LED，指示模块连接成功，蓝牙串口匹配连接成功后，LED长亮。
3、PIO11模块状态切换脚，高电平-->AT命令响应工作状态，低电平或悬空-->蓝牙常规工4、模块上已带有复位电路，重新上电即完成复位。
设置为主模块的步骤：1、PIO11置高。
2、上电，模块进入AT命令响应状态。
3、超级终端或其他串口工具，设置波特率38400，数据位8位，停止位1位，无校验位，无流控制。
4、串口发送字符“AT+ROLE=1\r\n”，成功返回“OK\r\n”，其中\r\n为回车换行。
5、PIO置低，重新上电，模块为主模块，自动搜索从模块，建立连接。
指令详细说明（AT指令不区分大小写，均以回车、换行字符结尾：\r\n）1、测试指令：指令响应参数2、模块复位（重启）：指令响应参数AT+RESET OK无3、获取软件版本号：指令响应参数AT+VERSION？+VERSION：<Param> OKParam：软件版本号举例说明：at+version?\r\n+VERSION:2.0-20100601 OK4、恢复默认状态：指令响应参数AT+ORGL OK无出厂默认状态：①．设备类：0②．查询码：0x0009e8b333③．模块工作角色：SlaveMode④．连接模式：指定专用蓝牙设备连接模式⑤．串口参数：波特率—384000bits/s;停止位：1位；校验位：无⑥．配对码：“1234”⑦．设备名称：“H-C-2010-06-01”..5、获取模块蓝牙地址：指令响应参数AT+ADDR？+ADDR：<Param>OKParam：模块蓝牙地址蓝牙地址表示方法：NAP：UAP：LAP（十六进制）举例说明：模块蓝牙设备地址为：12：34：56：ab:cd:efat+addr?\r\n+ADDR:1234:56:abcdefOK6、设置/查询设备名称：指令响应参数AT+NAME=<Param>OKParam：蓝牙设备名称默认名称：“HC-05”AT+NAME？1、+NAME:<Param>OK——成功2、FAIL——失败例如：AT+NAME=HC-05\r\n——设置模块设备名为：“HC-05”OKAT+NAME=“HC-05”\r\n——设置模块设备名为：“HC-05”OKat+name=Beijin\r\n——设置模块设备名为：“Beijin”OKat+name=“Beijin”\r\n——设置模块设备名为：“Beijin”OKat+name?\r\n+NAME:Bei jinOK7、获取远程蓝牙设备名称：指令响应参数AT+RNAME？<Param1>1、+NAME:<Param2>OK——成功2、FAIL——失败Param1：远程蓝牙设备地址Param2：远程蓝牙设备地址蓝牙地址表示方法：NAP：UAP：LAP（十六进制）例如：模块蓝牙设备地址为：00:02:72:od:22:24，设备名称为：Bluetoothat+rname?0002，72，od2224\r\n+RNAME:BluetoothOK8、设置/查询—模块角色：指令响应参数AT+ROLE=<Param>OK Param：参数取值如下：0——从角色（Slave）1——主角色（Master）2——回环角色（Slave-Loop）默认值：0+ROLE:<Param>OK模块角色说明：Slave(从角色)——被动连接；Slave-Loop(回环角色)——被动连接，接收远程蓝牙主设备数据并将数据原样返回给远程蓝牙主设备；Master（主角色）——查询周围SPP蓝牙从设备，并主动发起连接，从而建立主、从蓝牙设备间的透明数据传输通道。
STC12C2052AD 系列单片机器件手册 说明书
ＳＴＣ１２Ｃ２０５２ＡＤ 系列单片机器件手册 －－－ １个时钟／机器周期８０５１ －－－无法解密 －－－低功耗，超低价 －－－高速，高可靠 －－－强抗静电，强抗干扰ＳＴＣ１２Ｃ０５５２，ＳＴＣ１２Ｃ０５５２ＡＤＳＴＣ１２Ｃ１０５２，ＳＴＣ１２Ｃ１０５２ＡＤＳＴＣ１２Ｃ２０５２，ＳＴＣ１２Ｃ２０５２ＡＤＳＴＣ１２Ｃ３０５２， ＳＴＣ１２Ｃ３０５２ＡＤＳＴＣ１２Ｃ４０５２， ＳＴＣ１２Ｃ４０５２ＡＤＳＴＣ１２Ｃ５０５２， ＳＴＣ１２Ｃ５０５２ＡＤＳＴＣ１２ＬＥ０５５２，ＳＴＣ１２ＬＥ０５５２ＡＤＳＴＣ１２ＬＥ１０５２，ＳＴＣ１２ＬＥ１０５２ＡＤＳＴＣ１２ＬＥ２０５２，ＳＴＣ１２ＬＥ２０５２ＡＤＳＴＣ１２ＬＥ３０５２，ＳＴＣ１２ＬＥ３０５２ＡＤＳＴＣ１２ＬＥ４０５２，ＳＴＣ１２ＬＥ４０５２ＡＤＳＴＣ１２ＬＥ５０５２，ＳＴＣ１２ＬＥ５０５２ＡＤ技术支援：宏晶科技（深圳） ｗｗｗ．ＭＣＵ－Ｍｅｍｏｒｙ．ｃｏｍ ｓｕｐｐｏｒｔ＠ＭＣＵ－Ｍｅｍｏｒｙ．ｃｏｍＵｐｄａｔｅ ｄａｔｅ： ２００５－１０－４ （草案，请随时注意更新）宏晶科技：专业单片机／存储器供应商 ｗｗｗ．ＭＣＵ－Ｍｅｍｏｒｙ．ｃｏｍ ＳＴＣ１２Ｃ２０５２ＡＤ系列 １Ｔ ８０５１单片机中文指南２领导业界革命 覆盖市场需求宏晶科技是新一代增强型８０５１单片机标准的制定者，致力于提供满足中国市场需求的世界级高性能单片机技术，在业内处于领先地位，销售网络覆盖全国。
在保证质量的基础上，以极低的价格和完善的服务赢得了客户的长期信赖。
目前，全力推出“１个时钟／机器周期”的单片机，全面提升８０５１单片机性能。
欢迎海内外厂家前来洽谈合作！新客户请直接联系深圳，以获得更好的技术支持与服务。
ＳＴＣ １２Ｃ２０５２ＡＤ系列 １Ｔ ８０５１ 单片机ＲＳＴ １ ２０ ＶＣＣＲｘＤ／Ｐ３．０ ２ １９ Ｐ１．７／ＳＣＬＫ／ＡＤＣ７ＴｘＤ／Ｐ３．１ ３ １８ Ｐ１．６／ＭＩＳＯ／ＡＤＣ６ＸＴＡＬ２ ４ １７ Ｐ１．５／ＭＯＳＩ／ＡＤＣ５ＩＮＴ０／Ｐ３．２ ６ １５ Ｐ１．３／ＡＤＣ３ＩＮＴ１／Ｐ３．３ ７ １４ Ｐ１．２／ＡＤＣ２ＥＣＩ／Ｔ０／Ｐ３．４ ８ １３ Ｐ１．１／ＡＤＣ１ＰＷＭ１／ＰＣＡ１／Ｔ１／Ｐ３．５ ９ １２ Ｐ１．０／ＡＤＣ０Ｇｎｄ １０ １１ Ｐ３．７／ＰＣＡ０／ＰＷＭ０ＸＴＡＬ１ ５ １６ Ｐ１．４／ＳＳ／ＡＤＣ４ＤＩＰ－２０，ＳＯＰ－２０，（超小封装ＴＳＳＯＰ－２０定货）ＳＴＣ１２Ｃ２０５２、ＳＴＣ１２Ｃ４０５２不带Ａ／Ｄ转换ＳＴＣ１２Ｃ２０５２ＡＤ、ＳＴＣ１２Ｃ４０５２ＡＤ带Ａ／Ｄ转换 新客户请直接联系深圳以获得更好的技术支持和服务 欢迎海内外厂家前来洽谈合作南京办：广州办： 传真至深圳申请ＳＴＣ单片机 样片及ＩＳＰ下载线／编程工具１个时钟／机器周期，超小封装８０５１单片机在系统可编程，无需编程器，可远程升级可送ＳＴＣ－ＩＳＰ下载编程器，１万片／人／天内部集成ＭＡＸ８１０专用复位电路，原复位电路可以保留，也可以不用，不用时ＲＥＳＥＴ脚直接短到地１个时钟／机器周期，可用低频晶振，大幅降低ＥＭＩ超低功耗：１、掉电模式： 典型功耗 ＜０．１μＡ２、空闲模式： 典型功耗 ＜１ｍＡ３、正常工作模式： 典型功耗 ４ｍＡ － ７ｍＡ４、掉电模式可由外部中断唤醒，适用于电池 供电系统，如水表、气表、便携设备等。
Polycom CX500 IP PHONE 产品说明书
The software included in this Product (including, without limitation, firmware and all updated thereto, including any software that may be downloaded electronically via the internet or otherwise (the “Software”) is licensed, not sold. Customer shall not reverse compile, disassemble, or otherwise reverse engineer, embed with any other software product, or modify in any manner with respect thereto, the software in whole or in part. LIMITED WARRANTY. Polycom warrants to the end user (“Customer”) that this product will be free from defects in workmanship and materials, under normal use and service, for one year from the date of purchase from Polycom or its authorized reseller. Polycom’s sole obligation under this express warranty shall be, at Polycom’s option and expense, to repair the defective product or part, deliver to Customer an equivalent product or part to replace the defective item, or if neither of the two foregoing options are reasonably available, Polycom may, in its sole discretion, refund to Customer the purchase price paid for the defective product. All products that are replaced will become the property of Polycom. Replacement products or parts may be new or reconditioned. Polycom warrants any replaced or repaired product or part for ninety (90) days from shipment, or the remainder of the initial warranty period, whichever is longer. Products returned to Polycom must be sent prepaid and packaged appropriately for safe shipment, and it is recommended that they be insured or sent by a method that provides for tracking of the package. Responsibility for loss or damage does not transfer to Polycom until the returned item is received by Polycom. The repaired or replaced item will be shipped to Customer, at Polycom’s expense, not later than thirty (30) days after Polycom receives the defective product, and Polycom will retain risk of loss or damage until the item is delivered to Customer. EXCLUSIONS. Polycom will not be liable under this limited warranty if its testing and examination disclose that the alleged defect or malfunction in the product does not exist or results from: • Failure to follow Polycom’s installation, operation, or maintenance instructions. • Unauthorized product repair, modification or alteration. • Unauthorized use of common carrier communication services accessed through the product. • Abuse, misuse, negligent acts or omissions of Customer and persons under Customer’s control; or • Acts of third parties, acts of God, accident, fire, lightning, power surges or outages, or other hazards. WARRANTY EXCLUSIVE. IF A POLYCOM PRODUCT DOES NOT OPERATE AS WARRANTED ABOVE, CUSTOMER’S SOLE REMEDY FOR BREACH OF THAT WARRANTY SHALL BE REPAIR, REPLACEMENT, OR REFUND OF THE PURCHASE PRICE PAID, AT POLYCOM’S OPTION. TO THE FULL EXTENT ALLOWED BY LAW, THE FOREGOING WARRANTIES AND REMEDIES ARE EXCLUSIVE AND ARE IN LIEU OF ALL OTHER WARRANTIES, TERMS, OR CONDITIONS, EXPRESS OR IMPLIED, EITHER IN FACT OR BY OPERATION OF LAW, STATUTORY OR OTHERWISE, INCLUDING WARRANTIES, TERMS, OR CONDITIONS OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, SATISFACTORY QUALITY, CORRESPONDENCE WITH DESCRIPTION, AND NON-INFRINGEMENT, ALL OF WHICH ARE EXPRESSLY DISCLAIMED. POLYCOM NEITHER ASSUMES NOR AUTHORIZES ANY OTHER PERSON TO ASSUME FOR IT ANY OTHER LIABILITY IN CONNECTION WITH THE SALE, INSTALLATION, MAINTENANCE OR USE OF ITS PRODUCTS.
C8051f020中文资料2
关于C8051F020系统概述C8051F020 器件是完全集成的混合信号系统级 MCU 芯片，具有 64 个数字I/O 引脚（C8051F020）。
下面列出了一些主要特性；有关某一产品的具体特性参见表 1.1；1. 高速、流水线结构的 8051 兼容的 CIP-51 内核（可达 25MIPS）2. 全速、非侵入式的在系统调试接口（片内）3. 真正 12 位（C8051F020）、 100 ksps 的8 通道 ADC，带 PGA和模拟多路开关4. 真正 8 位 500 ksps的 ADC，带 PGA和 8 通道模拟多路开关5. 两个 12 位 DAC，具有可编程数据更新方式6. 64K字节可在系统编程的 FLASH存储器7. 4352（4096+256）字节的片内 RAM8. 可寻址 64K字节地址空间的外部数据存储器接口9. 硬件实现的 SPI、SMBus/ I2C 和两个 UART 串行接口10. 5 个通用的 16 位定时器11. 具有 5 个捕捉/比较模块的可编程计数器/定时器阵列12. 片内看门狗定时器、VDD监视器和温度传感器具有片内 VDD 监视器、看门狗定时器和时钟振荡器的 C8051F020是真正能独立工作的片上系统。
所有模拟和数字外设均可由用户固件使能/禁止和配置。
FLASH 存储器还具有在系统重新编程能力，可用于非易失性数据存储，并允许现场更新 8051 固件。
片内 JTAG调试电路允许使用安装在最终应用系统上的产品 MCU进行非侵入式（不占用片内资源）、全速、在系统调试。
该调试系统支持观察和修改存储器和寄存器，支持断点、观察点、单步及运行和停机命令。
在使用 JTAG调试时，所有的模拟和数字外设都可全功能运行。
每个 MCU都可在工业温度范围（-45℃到+85℃）内用 2.7V-3.6V的电压工作。
端口 I/O、/RST 和 JTAG 引脚都容许 5V 的输入信号电压。
C8051F020 为100 脚 TQFP 封装见图 1.1）。
C052G102D2CX5CM中文资料
suitable for bypass or coupling applications or frequency discriminating circuits where Q and stability of capacitance characteristics are not of a major importance. Class II capacitors have temperature characteristics of ± 15% or less. They are made from materials which are ferro-electric, yielding higher volumetric efficiency but less stability. Class II capacitors are affected by temperature, voltage, frequency and time.
Mil-C-11015 (CK) & Mil-PRF-39014 (CKR) Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Part Number Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 - 31
JCB 3CX、4CX、5CX挖掘装载机维修手册说明书
ForewordThe Operator's ManualDo not operate the machine without an Operator's Manual, or if there is anything on the machine you do not understand.Treat the Operator's Manual as part of the machine.Keep it clean and in good condition. Replace the Operator's Manual immediately if it is lost, damaged or becomes unreadable.Contents01 - Machine03 - Attachments, Couplings and Load Handling06 - Body and Framework 09 - Operator Station12 - Heating, Ventilating andAir-Conditioning (HVAC)15 - Engine18 - Fuel and Exhaust System 21 - Cooling System 24 - Brake System 25 - Steering System 27 - Driveline30 - Hydraulic System 33 - Electrical System 72 - Fasteners and Fixings 75 - Consumable Products 78 - After SalesOperationLubricationOil is fed from the main gallery via five drillings, one to each of the main bearings. A groove around the diameter of the upper main bearing shell allows oil transfer to cross drillings in the crankshaft to feed each of the big end bearings. Crankshaft gear is 'splash' lubricated. Front and rear crankshaft oil seals prevent oil leakage from, and dirt ingress to, the engine.1Main gallery2Drillings (x5)3Main bearings4Big end bearings 5Cross drillings6Crankshaft gear 7Crankshaft oil seal8Crankshaft oil sealCheck (Condition)1.Check the main bearing surfaces for damage andexcessive wear.A Main bearing shells2.Measure the crankshaft diameters to confirmthey are within service limits, refer to Technical Data (PIL 15-12).B Crankshaft3.Check that the oil-way cross drillings in thecrankshaft are clear and free from debris.Blocked or restricted oil-ways will cause oil starvation at the big end bearings.4.Check that the piston cooling J-jets are clear. Ifthe J-jets cannot be cleared remove the fixing screws. Remove theJ-jets and discard them. 5.Install new J-jets.C J-jetsD Fixing screwsRemove and InstallConsumablesDescription Part No.Size Cleaner/Degreaser- General purposesolvent based partscleaner4104/15570.4LCAUTION This component is heavy. It must only be removed or handled using a suitable lifting method and device.Before Removal1.This procedure requires service parts. Makesure you have obtained the correct service parts before you start, refer to Parts Catalogue.2.Make sure that the engine is safe to work on. Ifthe engine has been running, let it cool before you start the service work.3.Remove the engine, refer to (PIL 15-00).4.Remove the drive belt, refer to (PIL 15-18).5.Remove the crankshaft pulley, refer to (PIL15-12).6.Remove the oil sump, refer to (PIL 15-45).7.Disconnect and remove the fuel pipes from theinjectors, refer to (PIL 18-96).8.Remove the rocker cover, refer to (PIL 15-42).9.Remove the fuel injectors, refer to (PIL 18-18).10.Remove the rocker assembly including the pushrods, refer to (PIL 15-42).11.It is not necessary to remove the cylinder headassembly to remove the crankshaft. If however the cylinder head needs to be removed for otherreasons (for piston and connecting rod removal for example) remove it now, refer to (PIL 15-06).12.Remove the fuel injection pump, refer to (PIL18-18).13.Remove the starter motor, refer to (PIL 15-75).14.Remove the high duty PTO device (if installed).15.Position the engine upside down in a suitable jigor fixture, supported at the front of the cylinder block.16.Remove the flywheel, refer to (PIL 15-54).17.Remove the flywheel housing, refer to (PIL15-54).18.Remove the fuel injection pump drive gear, referto (PIL 15-51).19.Remove the oil pump, refer to (PIL 15-60).20.Remove the high duty PTO idler drive gear (ifinstalled), refer to (PIL 15-51).21.Remove the crankshaft drive gear, refer to (PIL15-51).22.Remove the camshaft, refer to (PIL 15-15).23.Remove the rear timing case, refer to (PIL15-51).24.If the pistons and connecting rods have not beenremoved, undo and remove the main bearing caps, refer to (PIL 15-12).25.Remove the bedplate, refer to (PIL 15-09). Remove1.Remove the thrust washers between thecrankshaft and crankcase rear main bearing.A Thrust WashersB CrankshaftC Rear main bearing2.Put labels on the thrust washers to make surethat they are installed in the correct positions during assembly.e suitable lifting equipment to carefully lift thecrankshaft from the crankcase (if the crankshaft is lifted manually, two people will be required).4.Carefully lift out the bearing shells.D Main bearing shells5.It is recommended that the bearing shells arereplaced. If however they are to be used again, put label on the shells to make sure that they are installed in their original positions during assembly.6.Inspect the crankshaft and main bearings etc.for damage and excessive wear. Refer to Check Condition (PIL 15-12).Before Installation1.Clean off all traces of the old sealant compoundfrom the crankcase and bedplate mating faces.e a suitable degreasing agent to carefullyclean the main bearing saddles in the bedplate and crankcase. Take care not to block the oil ways or the piston cooling jets.Consumable: Cleaner/Degreaser - General purpose solvent based parts cleaner Important: Cleanliness is of the utmost importance. Blocked oil-ways or oil jets will cause engine failure. Before you install the crankshaft make sure that ALL oil-ways and jets are clear and free from debris. Install1.The installation procedure is the opposite of theremoval procedure. Additionally do the following steps.2.Make sure that all items are clean and free fromdamage and corrosion.3.If removed or a new crankcase is being installedthen install cooling J jets as follows:F Fixing screws3.1.Insert the cooling jets into the crankcase.3.2.Note: There are different types of coolingjets installed depending on the engineapplication. The jets are colour coded.3.3.Be sure to install the correct jets. Refer tothe relevant parts catalogue for the correctcooling jet identification.3.4.Tighten the retaining screws to the correcttorque value.4.Install the upper bearing shells as follows:D Main bearing shellsG Bearing location tabe a suitable degreasing agent to makesure that the surface of the upper bearingshells are clean.Consumable: Cleaner/Degreaser - Generalpurpose solvent based parts cleaner4.2.Assemble the bearing shells into thecrankcase bearing saddles. Make sure thatthe location tab engages into the slot asshown.4.3.Important: Make sure that the oil-way holesin the bearing saddles align with the holesin the bearing shell. If the holes are evenpartially misaligned the piston cooling oil jetwill be restricted, causing the engine to fail.4.4.Lubricate the upper bearing shells withclean engine oil.e suitable lifting equipment (if the crankshaftis lifted manually, two people will be required), to carefully lower the crankshaft into the crankcase.DO NOT rotate the crankshaft, the bearing shells can become dislodged, refer to step 4.6.Install the thrust washers as follows:A Thrust washersB CrankshaftC Rear main bearing H Oil slot - thrust washers6.1.Slide the thrust washers between thecrankshaft and the crankcase rear mainbearing.6.2.Make sure that they are installed in thecorrect positions, with the two slots facingoutwards from the bearing saddle.6.3.If necessary, push the crankshaft forwardand then backwards to obtain clearance toinstall the thrust washers.6.4.DO NOT rotate the crankshaft, the bearingshells can become dislodged, refer to step4.7.Check that the crankshaft end float is withinservice limits, refer to Technical Data (PIL 15-12).Table 115. Torque ValuesItem NmF2403 - Main BearingIntroduction .................................................... 15-66 Check (Condition) .......................................... 15-67 Remove and Install ....................................... 15-67IntroductionIn a piston engine, the main bearings are the bearings on which the crankshaft rotates.The bearings hold the crankshaft in place and prevent the forces created by the piston and transmitted to the crankshaft by the connecting rodsCheck (Condition)1.Check the bearing shell surfaces for signs ofdamage and excessive wear.2.Measure the crank pin diameters to confirm theyare within service limits.Refer to: PIL 15-12-00.3.Renew any parts that are worn or not within thespecified tolerances.Remove and Install Refer to: PIL 15-12-00.06 - Front Oil Seal Remove and InstallSpecial ToolsDescription Part No.Qty. Crankshaft Front OilSeal Installation Tool892/011571 Before Removal1.This procedure requires service parts. Makesure you have obtained the correct service parts before you start, refer to Parts Catalogue.2.Make sure that the engine is safe to work on. Ifthe engine has been running, let it cool before you start the service work.3.Get access to the engine.4.Remove the drive belt, refer to (PIL 15-18).5.Remove the crankshaft pulley, refer to (PIL15-12-12).Removee a suitable lever behind the lip of theseal, carefully prise out the oil seal from the counterbore in the crankcase. Take care not to scratch or damage the counterbore or the crankshaft hub. Damaged or dirty sealing faces will cause the oil seal to fail.A Crankshaft oil sealB CrankcaseC Crankshaft hubInstall1.Make sure that the counterbore and thecrankshaft hub are clean and free from damage and corrosion. Use a suitable degreasing agent to clean all traces of oil and grease from the counterbore. Important: The oil seal has a special coating and MUST be installed dry without lubricant.2.Dismantle the seal installation tool. Bolt thecentre body to the crankshaft hub, using the bolts. Refer to Figure 280.Special Tool: Crankshaft Front Oil Seal Installation Tool (Qty.: 1)3.Install the oil seal on to the centre body. Makesure that the seal is installed the correct way around. Assemble the outer sleeve on to the centre body and install the screw. Refer to Figure 280.A Crankshaft oil sealB CrankcaseC Crankshaft hubD Seal installation toolE Fixing bolts (x3)F Centre bodyG Outer sleeve H Screw4.Turn the screw to push the seal squarely intothe counterbore until the outer sleeve comes Array up against the front edge of the counterbore.When correctly installed, the front face of the sealshould be flush with the edge of the counterborewithin the specified tolerance. Refer to Figure281.Dimension: -0.5 -0/+0.5mmB CrankcaseC Crankshaft hubF Centre bodyG Outer sleeve5.Remove the seal installation tool.After Installation1.Install the crankshaft pulley, refer to (PIL15-12-12).2.Install the drive belt, refer to (PIL 15-18).09 - Rear Oil Seal Remove and InstallSpecial ToolsDescription Part No.Qty. Crankshaft Rear OilSeal Installation Tool892/011561Crankshaft Rear OilSeal Alignment Tool892/011581Note: The flywheel hub and crankshaft rear oil seal need to be replaced as a pair.Before Removal1.This procedure requires service parts. Makesure you have obtained the correct service parts before you start, refer to Parts Catalogue.2.Make sure that the engine is safe to work on. Ifthe engine has been running, let it cool before you start the service work.3.Get access to the engine.4.Remove the flywheel, refer to (PIL 15-54).Removee a suitable lever behind the lip of the sealto carefully prise out the rear oil seal from the counterbore in the flywheel housing. Take care not to scratch or damage the counterbore or the flywheel hub. Damaged or dirty sealing faces will cause the oil seal to fail.B Flywheel housingC Flywheel hubA Crankshaft rear oil sealB Flywheel housingC Flywheel hubE Fixing boltInstall (24mm Hub)1.Make sure that the counterbore and the flywheelhub are clean and free from damage and corrosion.A Crankshaft rear oil sealB Flywheel housingC Flywheel hubD Oil seal alignment tool2.To prevent the seal lip rolling over and becomingdamaged, make sure that you use the oil seal alignment tool to initially install the oil seal on to the flywheel hub. Locate the alignment tool over the end of the hub, then carefully push the oil seal over the alignment tool and on to the crankshaft diameter. Make sure that the oil seal is installed the correct way around.Special Tool: Crankshaft Rear Oil Seal Installation Tool (Qty.: 1)Special Tool: Crankshaft Rear Oil Seal Alignment Tool (Qty.: 1)3.Apply lubricant P80 around the seal outer rubberdiameter.4.Dismantle the oil seal installation tool. Bolt thecentre body to the flywheel hub, using the two flywheel bolts. Assemble the outer sleeve on to the centre body and install the screw.A Crankshaft rear oil sealB Flywheel housingC Outer sleeve E Oil seal installation tool F Flywheel bolts G Centre bodyH Flywheel hub J Screw5.Turn the screw to push the seal squarely intothe counterbore until the outer sleeve comes up against the front edge of the counterbore.When correctly installed, the front face of the seal should be flush with the edge of the counterbore within the tolerance specified.Length/Dimension/Distance: 0.5mm 6.Remove the oil seal installation tool.Install (15mm Hub)1.Make sure that the counterbore and the hub areclean and free from damage.**************************。
C55XCSL-LOWPOWER-2.01.00.00_Release_Notes_20100329
C55XCSL-LOWPOWER-2.01.00.00Release NotesTexas Instruments29 MAR 2010Table of Contents1.Purpose of Release (5)2.What’s New? (6)3.What is Being Released (7)4.Scope of this Release (7)5.Bug Fixes (7)6.Known Issues and Caveats (8)7.Installation Guide (8)8.Target Requirements for Testing (18)9.CSL Overview (19)9.1Introduction to CSL (19)9.1.1Benefits of CSL (19)9.1.2CSL Architecture (20)9.2Naming Conventions (21)9.3CSL Data Types (21)9.4CSL Functions (22)9.4.1Peripheral Initialization and Programming via Function Level CSL (23)9.4.2Example of DMA Control via Function Level CSL (24)9.5CSL Macros (27)9.6CSL Symbolic Constant Values (27)9.7Resource Management and the Use of CSL Handles (28)9.7.1Using CSL Handles (28)Figure 7-1 Opening and Building the CCS v3.3 Project (9)Figure 7-2 Connecting to Target and Loading CCS v3.3 Project Program (10)Figure 7-3 Running the CCS v3.3 Project Program (11)Figure 7-4 Selecting the CCS v4 Workspace (12)Figure 7-5 Starting the CCS v4 Workbench (12)Figure 7-6 Browsing for the CCS v4 Projects (13)Figure 7-7 Setting Active CCS v4 Project (14)Figure 7-8 Setting Active CCS v4 Build Configuration (15)Figure 7-9 Debugging the Active CCS v4 Project (16)Figure 7-10 Selecting the CCS v4 PLL Frequency (17)Figure 7-11 Running the CCS v4 Project’s Program on the Target (18)Figure 9-1 CSL Architecture (20)Table 9-1 CSL Modules and Include Files (20)Table 9-2 CSL Naming Conventions (21)Table 9-3 CSL Data Types (22)Table 9-4 Generic CSL Functions (22)Table 9-5 Using PER_init() (23)Table 9-6 Using PER_config (24)Table 9-7 Generic CSL Macros (27)Table 9-8 Generic CSL Symbolic Constants (28)1. Purpose of ReleaseThe purpose of this release is to add support in the Chip Support Library (CSL) software package forthe new TMS320C5504/05/14/15 DSPs now available as part of TI’s 55xx family of low power DSPs.This software is a modified version of that previously released for just the TMS320VC5504/05 DSPs. Thus, this version of CSL now supports all of the TMS320VC5504/05 and TMS320C5504/05/14/15DSPs. This version has been tested on both Code Composer Studio TM Ver3.3 and Code Composer Studio TM Ver4.0.This CSL release package contains the following modules. Beside the related CSL functions, each module also contains one or more “example” mini-applications that use and illustrate basic capabilities of the related CSL. These “examples” are listed under each module below.o DAT – Data Buffer Operations -- creating, filling, copying memory buffersCSL_DAT_Exampleo DMA – DMA Operations -- polled and interrupt-driven modes, even ping-pong buffers CSL_DMA_IntcExampleCSL_DMA_PingPongExampleCSL_DMA_PollExampleCSL_DMA_StopAPIExampleo drivers/SDIO – Secure Data IO Command and Data Functionssdio_drv_example.co GPIO – Control of General Purpose IOsCSL_GPIO_InputPinExampleCSL_GPIO_OutputPinExampleo GPT – Control of General Purpose TimersCSL_GPTExampleo I2C – Control of I2C PortsCSL_I2C_DmaExampleCSL_I2C_DmaWordSwapExampleCSL_I2C_IntcExampleCSL_I2C_LoopbackExampleCSL_I2C_PollExampleo I2S – Control of I2S PortsCSL_I2S_DMAExampaleCSL_I2S_INTCExampleCSL_I2S_PollExamplesyo INTC – Interrupt Control FunctionsCSL_INTC_Exampleo LCD - LCD Controller Setup & Control – initialize, write, and read LCD display via controllerCSL_LCDC_262kColorModeExampleCSL_LCDC_65kColorModeExampleCSL_LCDC_DiagramExampleCSL_LCDC_DmaIntcExampleCSL_LCDC_DmaPolledExampleCSL_LCDC_TextDisplayExampleo MEMORY – Basic Memory Control and ModesCSL_MEMORY_DARAM_PartialRetentionExampleCSL_MEMORY_DARAM_RetentionExampleCSL_MEMORY_SARAM_PartialRetentionExampleCSL_MEMORY_SARAM_RetentionExampleCSL_MSDRAM_ClockSwitchExampleo MMC_SD – Multi Media Card & Secure Data Card Interface ControlCSL_MMCSD_MmcCardExampleCSL_MMCSD_SdCardExampleCSL_MMCSD_SdCardFSExampleCSL_MMCSD_dmaExampleo NAND - Control of EMIF for Interfacing with NAND FlashCSL_NAND_DmaExampleCSL_NAND_DmaWordSwapExampleCSL_NAND_IntrExampleCSL_NAND_PollExampleo PLL – PLL Initialization and ControlCSL_PLL_Exampleo RTC – Real Time Clock ControlCSL_RTC_Compensation_ExampleCSL_RTC_Exampleo SAR – Initialization and Control of SAR AtoD IntpusCSL_SAR_DmaExampleCSL_SAR_IntcExampleCSL_SAR_PollExampleo SPI – Initialization and Control of SPI Serial PortsCSL_SPI_Exampleo UART – Initialization and Control of UART Serial PortsCSL_UART_IntExampleCSL_UART_dmaExampleCSL_UART_pollExampleo USB – USB Port Control – Basic USB operations plus Mass Storage Class (MSC) support CSL_USB_DmaExampleCSL_USB_ISO_fullSpeedExampleCSL_USB_ISO_highSpeedExampleCSL_USB_IntcExampleCSL_USB_MSC_dmaExampletCSL_USB_MSC_pollExampleCSL_USB_PollExamplesyo WDTIM – WatchDog Timer ControlCSL_WDT_Example2. What’s New?a.This release supports both VC5504/05 silicon (PG 1.4) and C5504/05/14/15 silicon (PG2.0). To generate a VC5504/5 build, in file c55x_csl\inc\csl_general.h near the top,simply uncomment “//#define CHIP_5505”. (Once done, the #define logic there ensuresthat CHIP_5505 is the only CHIP_xxxx macro defined.) On the other hand, to generate aC5504/05/14/15 build, comment out this same “#define CHIP_5505” near the top of filec55xx_csl\inc\csl_general.h. (e.g., with a beginning “//”). (Once done, the #define logicthere ensures that CHIP_5515 is the only CHIP_xxxx macro defined.) Note:csl_general.h is released in this latter state, with the #define CHIP_5505 commented out.Therefore, the default build target is the newer C5504/05/14/15 silicon.b. A new Secure Data IO (SDIO) driver has been added in this release within pathc55xx_csl\drivers\sdio. One SDIO Example application is also provided designed to workwith the SpecTec SDG-810 SDIO GPS Receiver ( /sdg810.htm).c.CSL 2.0 has added example functionality not found in CSL 1.0•DMAi.Extra/new example illustrating “ping pong” mode•LCDi.Extra/new example illustrating 56k color modeii.Extra/new example illustrating 252k color mode•Memoryi.Extra/new example illustrating DARAM partial* retention modeii.Extra/new example illustrating SARAM partial* retention modeiii.Extra/new example illustrating MSDRAM clock switchingd.CSL 2.0 has some new functions not found in CSL 1.0•MMCSDi.MMC_setEndianMode – sets endianess mode of MMCSD controller to little or big* “Partial” retention mode, new with C5504/05/14/15 (PG 2.0) silicon, allows finer-grained retention mode control than possible with VC5504/05 (PG 1.4) silicon. Specifically, any specific subset of the available memory banks can be placed in retention mode, not just all of them or none of them. More information is available in the C5504/05/14/15 data sheet.3. What is Being Released•Source code of all CSL Modules (as listed above in “Purpose of Release”). Source code is available in the path c55xx_csl\src and c55xx_csl\inc.•Sample applications, or “Examples,” which demonstrate basic CSL module functionalities. Examples for CCSv3.3 are available in the pathc55xx_csl\ccs_v3.3_examples. Examples for CCSv4.n are available in the pathc55xx_csl\ccs_v4.0_examples.•CSL API reference documentation. This documentation is available in the path c55xx_csl\doc\html_csl\. To begin, open file index.html with a browser.•Example application reference documentation. This documentation is available in the path c55xx_csl\doc\html_examples\. To begin, open file index.html with a browser.•Documentation on the new SDIO driver. This documentation is available in the path c55xx_csl\drivers\sdio\doc\html_sdio\.4. Scope of this ReleaseThis release provides the Chip Support Library (CSL), and related sample application Examples, forall the CSL modules listed in section 1 for both the TMS320VC5504/05 (PG 1.4) andTMS320C5504/05/14/15 (PG 2.0) DSPs.5. Bug FixesIn this release, the performance and robustness of the USB Mass Storage Class examples are improved. Within the CCS 3.3 projects, these are located under …/usb/example4/ as thecsl_usb_msc_dma_example and csl_usb_msc_poll_example. Within the CCS v4 projects, these are located within …/usb/CSL_USB_MSC_dmaExample and …/usb/CSL_USB_MSC_pollExample.6. Known Issues and Caveatsa.All LCD Examples for PG 2.0 silicon (C5504/05/14/15) are currently failingbecause of differences in the new C5515 EVM board’s LCD device versus that onthe older VC5505 EVM board.b.All NAND Examples for PG 2.0 silicon are currently failing because of differences inNAND chip selects used on the new C5515 EVM board versus the older VC5505EVM. This issue will be fixed in the next incremental release. Also, all NANDExamples, even for PG 1.4, currently are sensitive to NAND block size and willonly work for “big block” NAND devices. An example “small block” NAND devicewhich will not currently work is the Samsung K9F 1208 R0B.c.Even though now faster and more robust, some intermittent. enumerationproblems may occur with the USB MSC (Mass Storage Class) Examples. Weexpect this to be fixed completely by the next incremental release in mid April2010.d.As a whole, the set of Examples provided are currently designed to illustrate basicfunctionality of the related CSL functions upon which they call. As such, thecurrently provided Examples are, in general, not yet rigorously refined todemonstrate maximum system performance or robustness. In future releases, weplan to evolve these examples and/or add others that are specifically engineeredto showcase optimal power-and-performance behavior and high robustness.7. Installation GuideImportant Notes:For Running the Projects on VC5504/05 DSP:•Uncomment #define CHIP_5505 near the top of file c55xx_csl\inc\csl_general.h. (Once done, the #define logic there ensures that CHIP_5505 is the only CHIP_xxxx macro defined, which will cause your build to be tailored for VC5504/05 silicon.)•To run CCSv3.3 examples, configure your emulator target to use the gel filec55xx_csl\build\c5505evm.gel.•To run CCS v4 examples, first copy the contents of c55xx_csl\build\c5505evm.gel into c55xx_csl\ccs_v4.0_examples\c55xxevm.gel. Then, use this file c55xxevm.gel as yoursource of gel commands. (In your CCS v4 Example directories, your *.ccxml emulator target file is prebuilt to point to this gel file name.)For Running the Projects on C5504/05/14/15 DSP:•Make sure that #define CHIP_5505 near the top of file c55xx_csl\inc\csl_general.h. is commented out (e.g., with a beginning “//”). csl_general.h is released this way by default.With this line commented out, the #ifndef logic in csl_general.h #define’s the macroCHIP_5515 instead. This, in turn, causes your build, by default, to be tailored forC5504/05/14/15 silicon.•To run CCSv3.3 examples, configure your emulator target to use the gel filec55xx_csl\build\c5505evm_pg20.gel.• To run CCS v4 examples, first copy the contents of c55xx_csl\build\c5505evm_pg20.gel into c55xx_csl\ccs_v4.0_examples\c55xxevm.gel. Then, use this file c55xxevm.gel as your source of gel commands. (In your CCS v4 Example directories, your *.ccxml emulator target file is prebuilt to point to this gel file name.)Building and Running the CCSv3.3 Projects• For running the CCSv3.3 example projects, connect your 5505/5515 EVM, via a suitable emulator such as the “XDS510” or the EVM’s “Onboard” emulator, to CCS and load the .pjt file from c55xx_csl/ccs_v3.3_examples/<module>/<example#>. Build the project and load the program to the target. Run the program and observe the test result. Repeat the test at different PLL clock values. We recommend that you use CCS3.3.80.11 or newer on the host machine to build and run CSL examples. The “Update Advisor” in CCS v3.3 can help you update your version if needed.• The following figures illustrate the CCS v3.3 build and run process for the CCS v3.3 DMA “example1”. Begin by starting the CCSv3.3 IDE and browse to, select, and open, and build the project found in directory c55xx_csl\ccs_v3.3_examples\dma\example1\ .Figure 7-1 Opening and Building the CCS v3.3 Project The main DMA projectThe CSL library project.It is a dependent project of the main projectOpen the DMA project byProject Æ Open …• Connect to the target and load the project executable just built.Figure 7-2 Connecting to Target and Loading CCS v3.3 Project Program•Run the project executable and check the displayed results.Figure 7-3 Running the CCS v3.3 Project ProgramBuilding and Running the CCS v4 Projects• For running CCS v4 example projects connect your 5505/5515 EVM, via a suitable emulatorsuch as the “XDS510” or the EVM’s “Onboard” emulator, to CCS. To use the Onboardemulator, connect a USB A/B cable from your host PC’s USB port to port 'EMU USB'(J201) on the EVM. As released, all CCS v4 projects include at least an Onboard_xml file for using the Onboard emulator. (Other emulators, such as the XDS510, can also be used well but each requires a *.ccxml file specific to that emulator.)• Start the CCS4.0 IDE and select the c55xx_csl folder as the CCS work space while openingthen CCS v4 application.Execution result displayed hereExecute the DMA project byDebug Æ RunFigure 7-4 Selecting the CCS v4 Workspace•Click on the CCS logo (looks like a small Rubik’s cube) to start the CCS work benchFigure 7-5 Starting the CCS v4 Workbench•Select the menu Project/Import Existing CCS/CCE Eclipse Project. Browse for the c55xx_csl folder and click ok. All the CCS v4 projects will be displayed in the list of projects.Leave the “Copy projects into workspace” box unchecked. Click on “Finish”. Projects will be loaded to the CCS.Figure 7-6 Browsing for the CCS v4 Projects•Right click on the project that you want to test and select Set as Active Project.Figure 7-7 Setting Active CCS v4 Project•Right click on your active project and set the Active Build Configuration as either Debug or Release.(Both CCS v3.3 and CCS v4 support building programs in two distinct modes. Debug mode is used for building programs with little/no compiler optimization enabled. Resultantexecutables still retain full symbolic debugging information on variables and also linkage information between most points in the executable and the line(s) of source code from which each came. This information generally makes the code easier to debug but also makes it bigger and slower. Release mode, on the other hand, is used for building programs with high degrees of compiler optimization enabled. This eliminates much of the debug-supportive information described above from the executable but makes it smaller and faster.)Figure 7-8 Setting Active CCS v4 Build Configuration•Select the menu Target/Debug Active Project. Project will be built (if needed) and debugger will be opened.(The project will be (re)built here only if needed, as when a piece of involved source code has changed. If a (re)build does occur, you can monitor its progress in a special console sub-window that will open during the build. Any build errors will be reported there for your information. If the build completes without any issues, Figure 7-10, with the Debug view opened and the debugger ready to use, will appear next.)(Note that the menu Target/Debug Active Project recommended above includes an automatic project pre/re-build if needed before debug can commence. If you prefer, you can instead build the project in a separate step first by using menu Project/Build Active Project.)Figure 7-9 Debugging the Active CCS v4 Project•Select Scripts menu to set the PLL to the desired frequency. Note that, for VC5504/5 silicon, only speeds up to and including 100 MHz give reliable operation. For C5504/05/14/15 silicon, however, 120 MHz is also a reliable choice. (Also, under certain circumstances, we have noticed that the CCS v4 “Scripts” menu may remain unavailable until after you initially run the program once at the default PLL setting. Thereafter, it will be available for PLLadjustment.)Figure 7-10 Selecting the CCS v4 PLL Frequency•Select menu Target/Run to run the project.Figure 7-11 Running the CCS v4 Project’s Program on the Target8. Target Requirements for TestingOne important target specific requirement is to use a CSL build that is compatible with your silicon. For VC5504/05 silicon, uncomment #define CHIP_5505 near the top of filec55xx_csl\inc\csl_general.h. (Once done, the #define logic there ensures that CHIP_5505 is the only CHIP_xxxx macro defined, which will cause your build to be tailored for VC5504/05 silicon.) On the other hand, for C5504/05/14/15 silicon, make sure that #define CHIP_5505 near the top of filec55xx_csl\inc\csl_general.h. is commented out (e.g., with a beginning “//”). csl_general.h is, in fact,released this way by default. With this line commented out, the #ifndef logic in csl_general.h#define’s the macro CHIP_5515 instead. This, in turn, causes your build, by default, to be tailored for C5504/05/14/15 silicon.Additionally, it is recommended that you use versions of code gen tools and BIOS that are compatible with those used by us to test the CSL and Examples in this release. In general, we recommend that you use the following, or newer, versions. (If the comments in a particular example cite special tool version requirements, abide by those.)•CCS 3.3.80.11 “Platinum” using code generation tool v3.3.2 and DSP BIOS 5.33.05. The XDS510 USB Emulator is used to interact with the target to load and run the CCSv3.3 projects thereon.•CCS v4.0.2.01003 using code generation tool v4.3.2 and DSP BIOS 5.41.00.06. The EVM’s “Onboard” Emulator is used to interact with the target to load and run the CCS v4 projects thereon.9. CSL OverviewThis section introduces the Chip Support Library, describes its architecture, and provides an overview of the collection of functions, macros, and constants that help you program DSP peripherals.9.1 Introduction to CSLCSL is a collection of functions, macros, and symbols used to configure and control on-chip peripherals. It is fully scalable and functions much like a peripheral-specific layer of DSP/BIOS but does not require the use of specific DSP/BIOS components to operate.9.1.1 Benefits of CSLThe benefits of CSL include peripheral ease of use, shortened development time, portability, hardware abstraction, and a level of standardization and compatibility among devices. CSLcan be viewed as offering two fundamental levels of peripheral interface to users, a moreabstract function-level layer 1 offering a fairly high level of interfaces and protocols, and alower hardware-detailed register-level layer 2. offering direct symbolic access to allhardware control registers. These two layers are described below.1.Function Level CSL -- Higher level interfaces and protocols•Standard Protocol to Program Peripherals: CSL provides developers with a standard protocol to program on-chip peripherals. This protocol includes data types and macros todefine peripheral configurations, and functions to implement various operations of eachperipheral.•Basic Resource Management: Basic resource management is provided through the use of open and close functions for many of the peripherals. This is especially helpful forperipherals that support multiple channels.2.Register Level CSL -- Lower level register-manipulation interface•Symbolic Peripheral Descriptions: A complete symbolic detailed description of all peripheral registers and register fields has been created. It is suggested that developersuse the higher level protocols (of CSL layers b. and c.), as these are less device-specific,thus making it easier to migrate code to newer versions of DSPs.9.1.2 CSL ArchitectureCSL consists of modules that are built and archived into a library file. Each peripheral is coveredby a single module while additional modules provide general programming support. This architecture allows for future expansion because new modules can be added as new peripheralsemerge.Users have two levels of access to peripherals using CSL, register level access and function level access. All function CSL files have a name of the form csl_PER.c where PER is a placeholder for the specific peripheral. In a similar fashion, all register level files have a name of the form cslr_PER.h. The function level of CSL is implemented based on register level CSL. Users can use either level of CSL to build their applications. The following Figure 9-1 shows the architecture of CSL and its role in interfacing an application to the DSP hardware on which it executes.CSL APIDMA RTC SPI…USBDMAr RTCr SPIr…USBrVC5504/05 or C5504/05/14/15 DSP and peripheralsFigure 9-1 CSL ArchitectureTable 9-1 lists the key modules and related interface defining files within CSL.Table 9-1 CSL Modules and Include FilesPeripheralModule (PER)Description Include FileDAT A data copy/fill module based onthe DMA C5505csl_dat.hDMA DMAperipheral csl_dma.h GPIO General Purpose I/O csl_gpio.hGPT 32-bit General purpose timer csl_gpt.hI2C I2Cperipheral csl_i2c.h I2S I2Speripheral csl_i2s.h INTC InterruptController csl_intc.h LCDC LCDController csl_lcdc.hMEM Enable or Disable the Memorycsl_mem.hRetention Mode for SARAM andDARAMController csl_mmcsd.h MMC/SD MMC/SDMMC/SD ATAFS Interface to MMC/SD driver csl_mmcsd_at aIf.hflash csl_nand.h NAND NANDPLL PLL csl_pll.hRTC Real-timeclock csl_rtc.h SAR 10 bit SAR ADC csl_sar.hSDIO Secure Data I/O driver csl_sdio.hSPI SPI csl_spi.hUART UART csl_uart.hUSB USB core driver csl_usb.hUSB MSC USB MSC driver csl_msc.hUSB Audio USB Audio driver csl_audioClass.hTimer csl_wdt.hDogWDT Watch9.2 Naming ConventionsThe following conventions are used when naming CSL functions, macros, and data types. Note thatPER is used a placeholder for any of the specific module / peripheral names from Table 9-1 above.Table 9-2 CSL Naming ConventionsObject Type Naming ConventionFunction PER_funcName() Variable PER_varNameMacro PER_MACRO_NAMETypedef PER_TypenameFunction Argument funcArgStructure Member memberName•All functions, macros, and data types start with PER_ (where PER is the peripheral module name listed in Table 9-1) in uppercase letters.•Function names use all lowercase letters. Uppercase letters are used only if the function name consists of two separate words. For example, PER_getConfig().•Macro names use all uppercase letters; for example, DMA_DMPREC_RMK.•Data types start with an uppercase letter followed by lowercase letters, e.g., DMA_Handle.9.3 CSL Data TypesCSL provides its own set of data types that all begin with an uppercase letter. Table 9-3 lists CSLdata types as defined in the file …/c55xx_csl/inc/tistdtypes.h.Table 9-3 CSL Data TypesData Type DescriptionBool ShortInt ShortChar CharPtr void *String char *Uint32 unsigned longUint16 unsigned shortUint8 unsigned charInt32 LongInt16 ShortInt8 Char9.4 CSL FunctionsTable 9-4 provides a description of the most common CSL functions where PER indicates a peripheral module as listed in Table 9-1. Note that not all of the peripheral functions listed in the table are available for all modules / peripherals. Furthermore, some peripheral modules may offer additional peripheral-specific functions not listed in the table. Refer to the documentation in path c55xx_csl\doc\html_csl\index.html for a list of CSL functions offered for each module / peripheral.The following conventions are used in Table 9-4:•Italics indicate variable names.•Brackets [...] indicate optional parameters.o[handle] is required only for handle-based peripherals: such as DAT, DMA, SPI, MMC/SD and USB.CSL offers two fundamental ways to program peripherals•Directly write to hardware control registers using the lower CSLR layer• Use the more abstract functions (Table 9-4) of the higher CSL layer. For example, you can use PER_config() plus any other needed peripheral specific functions. See section 9.4.1 for more detail.Table 9-4 Generic CSL FunctionsFunction DescriptionPER_init(void) This function initializes and activates the SPImodule. It has to be called before any functioncallhandle = PER_open(…) Opens a peripheral channel and then performsthe operation indicated by the parameters;must be called before using a channel. Thereturn value is a unique device handle to use insubsequent API calls.PER_config([handle,] *configStructure) Initializes the peripheral based on thefunctional parameters included in theinitialization structure. Functional parametersare peripheral specific. This function may notbe supported in all peripherals. Please consultthe CSL API document for specific details.PER_start([handle,] … ) Starts the peripheral after it has beenconfigured using PER_config().PER_stop([handle,] …) Stops the peripheral after it has been startedusing PER_start().PER_reset([handle]) Resets the peripheral to its power-on defaultvalues.PER_close(handle) Closes a peripheral channel previously openedwith PER_open(). The registers for the channelare set to their power-on defaults, and anypending interrupt is cleared.PER_read(handle …) Read from the peripheral.PER_write(handle …) Write to the peripheral.9.4.1 Peripheral Initialization and Programming via Function Level CSLOn top of the register-level CSLR, CSL also provides higher level functions (Table 9-4) to initialize and to control peripherals. Using the CSL functional layer, relatively few function calls, each with appropriate parameters, can be used to control peripherals. This method provides a higher levelof abstraction than the direct register manipulation method of CSLR but generally at a cost oflarger code size and higher execution cycle count.Even though each CSL module may offer different parameter-based functions, PER_init() is the most commonly used. PER_init() initializes the parameters in the peripheral that are typically initialized only once in the application. PER_init() can then be followed by other module functions implementing other common run-time peripheral operations as shown in Table 9-5. Other parameter-based functions include module-specific functions such as the PER_config() function shown in Table 9-6.Table 9-5 Using PER_init()main() {...PER_init();...}Table 9-6 Using PER_configPER_config myConfig = {param_1, ..., param_n};main() {...PER_config (&myConfig);...}9.4.2 Example of DMA Control via Function Level CSLThe following example illustrates the use of CSL to initialize and use DMA channel 0 to copy a table from address 0x3000 to address 0x2000. Addresses and size of data to be moved are as follows.Source address: 2000h in data spaceDestination address: 3000h in data spaceTransfer size: Sixteen 16-bit single wordsThe example uses CSL functions DMA_init(), DMA_open(…), DMA_config(…), DMA_start(…),DMA_getStatus(…), and DMA_close(…). The next 9 steps illustrate the preparation and use of these functions in exercising control of the DMA operation.Step 1: Include the header file of the module/peripheral, use <csl_dma.h>. The different header files are shown in Table 2-1.#include "csl_dma.h"#include <stdio.h>Step 2: Define a DMA_Handle pointer and buffers. DMA_open will initialize this handle when a DMA channel is opened.#define CSL_DMA_BUFFER_SIZE 1024/* Declaration of the buffer */Uint16 dmaSRCBuff[CSL_DMA_BUFFER_SIZE];Uint16 dmaDESTBuff[CSL_DMA_BUFFER_SIZE];CSL_DMA_Handle dmaHandle;CSL_DMA_Config dmaConfig;CSL_DMA_Config getdmaConfig;CSL_DMA_ChannelObj dmaObj;status;CSL_StatusStep 3: Define and initialize the DMA channel configuration structure.dmaConfig.autoMode = CSL_DMA_AUTORELOAD_DISABLE;dmaConfig.burstLen = CSL_DMA_TXBURST_8WORD;dmaConfig.trigger = CSL_DMA_SOFTWARE_TRIGGER;。
CP2102中英文翻译
本科毕业设计（论文）外文翻译译文学生姓名：院（系）：电子信息工程学院专业班级：电信0901指导教师：严正国完成日期：2013 年04 月02日CP2102USB转UART芯片数据手册CP2102 SINGLE-CHIP USB TO UART BRIDGE作者：CYGNAL单芯片USB数据传输到UART-- 综合USB收发器无需外部电阻要求-- 集成的时钟无需外部晶振体要求-- 综合1024-Byte EEPROM用于产品的供应商ID,ID,序列号，电源描述，版本号和产品描述字符串-- 片上电复位电路-- 片上电压调节器：3.3v电压输出-- 100%引脚和软件兼容与CP2101USB功能控制器-- USB规范2.0标准：（全速12 Mbps）-- USB暂停支持国家通过悬浮pins异步串行数据总线（UART）-- 所有的握手和调制解调器借口信号-- 数据格式支持- 数据bits：5，6，7和8- 停止bits：1，1.5和2- 校验：奇，偶，标记，空间，无校验-- 波特率：300 bps到1兆位-- 567字节的接受缓冲区；640字节的发送缓冲区-- 支持硬件或X-On/X-Off 握手-- Event字符支持-- 输电线路中断虚拟设备驱动程序COM口-- 使用现有的COM端口的PC应用-- 免版税发行许可证于Windows Vista / XP / 服务器2003 / 2000 / 1998SE-- 苹果OS-X / 0S-9-- LinuxUSB Express 直接驱动器支持-- 免版税发行许可证-- 于Windows Vista / XP / 服务器2003 / 2000-- 视窗CE 5.0 和4.2应用实例-- 传统设备的RS-232升级到USB-- 蜂巢式电话USB接口电缆-- PDA USB 接口电缆-- USB到RS-232 串行适配器电源电压-- 自供电：3.0 v到3.6 vUSB总线供电：4.0 v到5.25 v包装-- 无铅28-pin QFN （5 * 5mm）订购零件编号-- CP2102-GM温度范围：-40到+85摄氏度图1. 系统功能电路1.系统概述该CP2102是一个高度集成的USB-UART桥控制器提供了一个简单的解决方案更新RS-232设计，USB使用的组件和PCB空间最小，该CP2102包括USB2.0全速功能控制器，USB收发器，振荡器和带有全部的调制解调器控制信号的异步串行数据总线（UART），全部功能集成在一个5 * 5 mm MIP-28封装的IC中，无需其他的外部USB元件，片内EEPROM可用于由原始设备制造商自定义USB 供应商代码、产品代码、产品描述文字、功率标牌、版本号和元件序列号等数据的存储空间。
PHOENIX CONTACT FKC 2,5 2-ST-5,08 10位插座插件商品说明书
Extract from the onlinecatalogFKC 2,5/ 2-ST-5,08Order No.: 1873058The figure shows a 10-position version of the producthttp://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=1873058Plug component, Nominal current: 12 A, Nom. voltage: 250 V, Pitch:5.08 mm, Number of positions: 2, Connection type: Spring-cage conn., Color: greenhttp://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataDimensions / positionsPitch 5.08 mmDimension a 5.08 mmNumber of positions2Technical dataInsulating material group IRated surge voltage (III/3) 4 kV Rated surge voltage (III/2) 4 kV Rated surge voltage (II/2) 4 kV Rated voltage (III/2)320 V Rated voltage (II/2)630 V Connection in acc. with standard EN-VDE Nominal current I N12 A Nominal voltage U N250 V Nominal cross section 2.5 mm²Maximum load current12 A Insulating material PA Inflammability class acc. to UL 94V0 Internal cylindrical gage A2 Stripping length10 mmConnection dataConductor cross section solid min.0.2 mm²Conductor cross section solid max. 2.5 mm²Conductor cross section stranded min.0.2 mm²Conductor cross section stranded max. 2.5 mm²Conductor cross section stranded, with ferrule0.25 mm²without plastic sleeve min.Conductor cross section stranded, with ferrule2.5 mm²without plastic sleeve max.Conductor cross section stranded, with ferrule0.25 mm²with plastic sleeve min.2.5 mm²Conductor cross section stranded, with ferrulewith plastic sleeve max.Conductor cross section AWG/kcmil min.24 Conductor cross section AWG/kcmil max120.5 mm²2 conductors with same cross section, stranded,TWIN ferrules with plastic sleeve, min.2 conductors with same cross section, stranded,1.5 mm²TWIN ferrules with plastic sleeve, max.Certificates / ApprovalsCertification CB, CUL, GOST, UL, VDE-PZICULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-12ULNominal voltage U N300 VNominal current I N10 AAWG/kcmil26-12AccessoriesItem Designation DescriptionAssembly1876880STZ 8-FKC-5,08Strain relief for snapping into the latching chambers of the plugcomponents, 8-pos.1876877STZ 4-FKC-5,08Strain relief for snapping into the latching chambers of the plugs,4-pos.Marking1051993B-STIFT Marker pen, for manual labeling of unprinted Zack strips, smear-proof and waterproof, line thickness 0.5 mm0804293SK 5,08/3,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 12 identicaldecades marked 1-10, 11-20 etc. up to 91-(99)100, sufficient for120 terminal blocks0805085SK 5,08/3,8:SO Marker card, special printing, self-adhesive, labeled acc. tocustomer requirements, 12 identical marker strips per card, max.25-position labeling per strip, color: white0805412SK 5,08/3,8:UNBEDRUCKT Marker cards, unprinted, with pitch divisions, self-adhesive, 10-section marker strips, 12 strips per card, can be labeled with theM-PENPlug/Adapter1734634CP-MSTB Keying profile, is inserted into the slot on the plug or invertedheader, red insulating material0201689MPS-IH BU Insulating sleeve, for MPS metal part, Color: blue0201702MPS-IH GN Insulating sleeve, for MPS metal part, Color: green0201676MPS-IH RD Insulating sleeve, Color: red0201663MPS-IH WH Insulating sleeve, for MPS metal part, Color: white0201744MPS-MT Metal part0201647RPS Reducing plug, Color: grayTools1205053SZS 0,6X3,5Screwdriver, bladed, matches all screw terminal blocks up to 4.0mm² connection cross section, blade: 0.6 x 3.5 mm, without VDEapprovalAdditional productsItem Designation DescriptionGeneral1859519EMSTBVA 2,5/ 2-G-5,08Header, Nominal current: 12 A, Nom. voltage: 200 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Press-in 1873359FKIC 2,5/ 2-ST-5,08Plug component, Nominal current: 12 A, Nom. voltage: 320 V,Pitch: 5.08 mm, Number of positions: 2, Connection type: Spring-cage conn., Color: green1823846ICC 2,5/ 2-STZ-5,08Plug component, Nominal current: 12 A, Nom. voltage: 250 V,Pitch: 5.08 mm, Number of positions: 2, Connection type: Crimpconnection, Color: green1762062MDSTB 2,5/ 2-G-5,08Header, Nominal current: 10 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 1763074MDSTBV 2,5/ 2-G-5,08Header, Nominal current: 10 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 1802430MDSTBW 2,5/ 2-G-5,08Header, Nominal current: 10 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 1770711MSTB 2,5/ 2-G-5,08-LA Header, Nominal current: 12 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Assembly: Soldering1757242MSTBA 2,5/ 2-G-5,08Header, Nominal current: 12 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 1770944MSTBA 2,5/ 2-G-5,08-LA Header, Nominal current: 12 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Assembly: Soldering1788729MSTBVK 2,5/ 2-G-5,08Plug component, Nominal current: 12 A, Nom. voltage: 320 V,Pitch: 5.08 mm, Number of positions: 2, Connection type: Screwconnection, Assembly: DIN rail, Color: green1788538MVSTBU 2,5/ 2-GB-5,08Plug component, Nominal current: 12 A, Nom. voltage: 320 V,Pitch: 5.08 mm, Number of positions: 2, Connection type: Screwconnection, Assembly: Direct mounting, Color: green1769463SMSTB 2,5/ 2-G-5,08Header, Nominal current: 12 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 1767371SMSTBA 2,5/ 2-G-5,08Header, Nominal current: 12 A, Nom. voltage: 250 V, Pitch: 5.08mm, Number of positions: 2, Color: green, Assembly: Soldering 3002034UK 3-MSTB-5,08Feed-through modular terminal block, Type of connection: Specialand hybrid connection, Screw connection, Cross section: 0.2mm² - 4 mm², AWG 24 - 12, Width: 5.08 mm, Color: gray,Mounting type: NS 32, NS 35/15, NS 35/7,53002076UK 3-MVSTB-5,08Feed-through modular terminal block, Nominal current: 12A, Nominal voltage: 250 V, Cross section: 0.2 mm² - 4 mm²,AWG: 24 - 12, Mounting type: NS 32, NS 35/15, NS 35/7,5,Pitch: 5.08 mm, Width: 5.1, Color: gray3002102UK 3-MVSTB-5,08-LA 24RD Feed-through modular terminal block, Nominal current: 12A, Nominal voltage: 250 V, Cross section: 0.2 mm² - 4 mm²,AWG: 24 - 12, Mounting type: NS 32, NS 35/15, NS 35/7,5,Pitch: 5.08 mm, Width: 5.08, Color: gray3002063UK 3-MVSTB-5,08/EK Feed-through modular terminal block, Nominal current: 12A, Nominal voltage: 250 V, Cross section: 0.2 mm² - 4 mm²,AWG: 24 - 12, Mounting type: NS 35/7,5, NS 35/15, NS 32,Pitch: 5.08 mm, Width: 5.1, Color: blue3002131UK 3D-MSTBV-5,08Feed-through modular terminal block, Type of connection: Specialand hybrid connection, Screw connection, Cross section: 0.2mm² - 4 mm², AWG 24 - 12, Width: 5.08 mm, Color: gray,Mounting type: NS 32, NS 35/15, NS 35/7,53002144UK 3D-MSTBV-5,08-LA 24RD Feed-through modular terminal block, Type of connection: Screwconnection, Screw connection, Number of positions: 1, Crosssection: 0.2 mm² - 4 mm², AWG 24 - 12, Width: 5.1 mm,Color: gray, Mounting type: NS 32, NS 35/15, NS 35/7,5 3002173UK 3D-MSTBV-5,08/EK Feed-through modular terminal block, Type of connection: Screwconnection, Screw connection, Cross section: 0.2 mm² - 4 mm²,AWG 24 - 12, Width: 5.1 mm, Color: blue, Mounting type: NS32, NS 35/15, NS 35/7,52770888UKK 3-MSTB-5,08End cover, Nominal current: 12 A, Nominal voltage: 250 V, Crosssection: 0.2 mm² - 4 mm², AWG: 24 - 12, Mounting type: NS35/7,5, NS 35/15, NS 32, Pitch: 5.08 mm, Width: 5.08, Color: gray 1876615UKK 3-MSTB-5,08-PE Feed-through modular terminal block, Nominal current: 12A, Nominal voltage: 320 V, Cross section: 0.2 mm² - 4 mm²,AWG: 24 - 12, Mounting type: NS 35/7,5, NS 35/15, NS 32,Pitch: 5.08 mm, Width: 5.08, Color: green-yellow2770846UKK 3-MSTBVH-5,08Feed-through modular terminal block, Nominal current: 12A, Nominal voltage: 250 V, Cross section: 0.2 mm² - 4 mm²,AWG: 24 - 12, Mounting type: NS 35/7,5, NS 35/15, NS 32,Pitch: 5.08 mm, Width: 5.08, Color: gray1788114UMSTBVK 2,5/ 2-G-5,08Plug component, Nominal current: 12 A, Nom. voltage: 320 V,Pitch: 5.08 mm, Number of positions: 2, Connection type: Screwconnection, Assembly: DIN rail, Color: greenDiagrams/Drawings Dimensioned drawingAddressPHOENIX CONTACT Deutschland GmbHFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 12000Fax +49 5235 3 41200http://www.phoenixcontact.de© 2010 Phoenix ContactTechnical modifications reserved;。
XCS05XL-4BG144C中文资料
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at /legal.htm .All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.IntroductionThe Spartan ™ and the Spartan-XL families are a high-vol-ume production FPGA solution that delivers all the key requirements for ASIC replacement up to 40,000 gates.These requirements include high performance, on-chip RAM, core solutions and prices that, in high volume,approach and in many cases are equivalent to mask pro-grammed ASIC devices.The Spartan series is the result of more than 14 years of FPGA design experience and feedback from thousands of customers. By streamlining the Spartan series feature set,leveraging advanced process technologies and focusing on total cost management, the Spartan series delivers the key features required by ASIC and other high-volume logic users while avoiding the initial cost, long development cycles and inherent risk of conventional ASICs. The Spar-tan and Spartan-XL families in the Spartan series have ten members, as shown in T able 1.Spartan and Spartan-XL FeaturesNote: The Spartan series devices described in this data sheet include the 5V Spartan family and the 3.3V Spartan-XL family. See the separate data sheet for the 2.5V Spartan-II family.•First ASIC replacement FPGA for high-volume production with on-chip RAM•Density up to 1862 logic cells or 40,000 system gates •Streamlined feature set based on XC4000 architecture •System performance beyond 80MHz•Broad set of AllianceCORE ™ and LogiCORE ™ predefined solutions available •Unlimited reprogrammability •Low cost•System level features-Available in both 5V and 3.3V versions -On-chip SelectRAM ™ memory -Fully PCI compliant-Full readback capability for program verificationand internal node observability -Dedicated high-speed carry logic -Internal 3-state bus capability-Eight global low-skew clock or signal networks -IEEE 1149.1-compatible Boundary Scan logic -Low cost plastic packages available in all densities -Footprint compatibility in common packages•Fully supported by powerful Xilinx development system -Foundation Series: Integrated, shrink-wrapsoftware-Alliance Series: Dozens of PC and workstationthird party development systems supported-Fully automatic mapping, placement and routing Additional Spartan-XL Features• 3.3V supply for low power with 5V tolerant I/Os •Power down input •Higher performance •Faster carry logic•More flexible high-speed clock network•Latch capability in Configurable Logic Blocks •Input fast capture latch•Optional mux or 2-input function generator on outputs •12 mA or 24 mA output drive •5V and 3.3V PCI compliant •Enhanced Boundary Scan •Express Mode configuration •Chip scale packagingSpartan and Spartan-XL Families Field Programmable Gate ArraysDS060 (v1.6) September 19, 2001Product Specification T able 1: Spartan and Spartan-XL Field Programmable Gate Arrays1.Max values of Typical Gate Range include 20-30% of CLBs used as RAM.2DS060 (v1.6) September 19, 2001General OverviewSpartan series FPGAs are implemented with a regular, flex-ible, programmable architecture of Configurable Logic Blocks (CLBs), interconnected by a powerful hierarchy of versatile routing resources (routing channels), and sur-rounded by a perimeter of programmable Input/Output Blocks (IOBs), as seen in Figure 1. They have generous routing resources to accommodate the most complex inter-connect patterns.The devices are customized by loading configuration data into internal static memory cells. Re-programming is possi-ble an unlimited number of times. The values stored in thesememory cells determine the logic functions and intercon-nections implemented in the FPGA. The FPGA can either actively read its configuration data from an external serial PROM (Master Serial mode), or the configuration data can be written into the FPGA from an external device (Slave Serial mode).Spartan series FPGAs can be used where hardware must be adapted to different user applications. FPGAs are ideal for shortening design and development cycles, and also offer a cost-effective solution for production rates well beyond 50,000 systems per month.Figure 1: Basic FPGA Block DiagramSpartan series devices achieve high-performance, low-cost operation through the use of an advanced architecture and semiconductor technology. Spartan and Spartan-XL devices provide system clock rates exceeding 80MHz and internal performance in excess of150MHz. In contrast to other FPGA devices, the Spartan series offers the most cost-effective solution while maintaining leading-edge per-formance. In addition to the conventional benefit of high vol-ume programmable logic solutions, Spartan series FPGAs also offer on-chip edge-triggered single-port and dual-port RAM, clock enables on all flip-flops, fast carry logic, and many other features.The Spartan/XL families leverage the highly successful XC4000 architecture with many of that family’s features and benefits. T echnology advancements have been derived from the XC4000XLA process developments.Logic Functional DescriptionThe Spartan series uses a standard FPGA structure as shown in Figure1, page2. The FPGA consists of an array of configurable logic blocks (CLBs) placed in a matrix of routing channels. The input and output of signals is achieved through a set of input/output blocks (IOBs) forming a ring around the CLBs and routing channels.•CLBs provide the functional elements for implementing the user’s logic.•IOBs provide the interface between the package pins and internal signal lines.•Routing channels provide paths to interconnect the inputs and outputs of the CLBs and IOBs.The functionality of each circuit block is customized during configuration by programming internal static memory cells. The values stored in these memory cells determine the logic functions and interconnections implemented in the FPGA.Configurable Logic Blocks (CLBs)The CLBs are used to implement most of the logic in an FPGA. The principal CLB elements are shown in the simpli-fied block diagram in Figure2. There are three look-up tables (LUT) which are used as logic function generators, two flip-flops and two groups of signal steering multiplexers. There are also some more advanced features provided by the CLB which will be covered in the Advanced Features Description, page13.Function GeneratorsTwo 16x1 memory look-up tables (F-LUT and G-LUT) are used to implement 4-input function generators, each offer-ing unrestricted logic implementation of any Boolean func-tion of up to four independent input signals (F1 to F4 or G1 to G4). Using memory look-up tables the propagation delay is independent of the function implemented.A third 3-input function generator (H-LUT) can implement any Boolean function of its three inputs. Two of these inputs are controlled by programmable multiplexers (see box "A" of Figure2). These inputs can come from the F-LUT or G-LUT outputs or from CLB inputs. The third input always comes from a CLB input. The CLB can, therefore, implement cer-tain functions of up to nine inputs, like parity checking. The three LUTs in the CLB can also be combined to do any arbi-trarily defined Boolean function of five inputs.4DS060 (v1.6) September 19, 2001A CLB can implement any of the following functions:•Any function of up to four variables, plus any second function of up to four unrelated variables, plus any third function of up to three unrelated variablesNote: When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two unregistered function generator outputs are available from the CLB.•Any single function of five variables•Any function of four variables together with some functions of six variables•Some functions of up to nine variables.Implementing wide functions in a single block reduces both the number of blocks required and the delay in the signal path, achieving both increased capacity and speed. The versatility of the CLB function generators significantly improves system speed. In addition, the design-software tools can deal with each function generator independently.This flexibility improves cell usage.Flip-FlopsEach CLB contains two flip-flops that can be used to regis-ter (store) the function generator outputs. The flip-flops and function generators can also be used independently (see Figure 2). The CLB input DIN can be used as a direct input to either of the two flip-flops. H1 can also drive either flip-flop via the H-LUT with a slight additional delay.The two flip-flops have common clock (CK), clock enable (EC) and set/reset (SR) inputs. Internally both flip-flops are also controlled by a global initialization signal (GSR) which is described in detail in Global Signals: GSR and GTS ,page 20.Latches (Spartan-XL only)The Spartan-XL CLB storage elements can also be config-ured as latches. The two latches have common clock (K)and clock enable (EC) inputs. Functionality of the storage element is described in Table 2.Figure 2: Spartan/XL Simplified CLB Logic Diagram (some features not shown)Clock InputEach flip-flop can be triggered on either the rising or falling clock edge. The CLB clock line is shared by both flip-flops.However, the clock is individually invertible for each flip-flop (see CK path in Figure 3). Any inverter placed on the clock line in the design is automatically absorbed into the CLB. Clock EnableThe clock enable line (EC) is active High. The EC line is shared by both flip-flops in a CLB. If either one is left discon-nected, the clock enable for that flip-flop defaults to the active state. EC is not invertible within the CLB. The clock enable is synchronous to the clock and must satisfy the setup and hold timing specified for the device.Set/ResetThe set/reset line (SR) is an asynchronous active High con-trol of the flip-flop. SR can be configured as either set or reset at each flip-flop. This configuration option determines the state in which each flip-flop becomes operational after configuration. It also determines the effect of a GSR pulse during normal operation, and the effect of a pulse on the SR line of the CLB. The SR line is shared by both flip-flops. If SR is not specified for a flip-flop the set/reset for that flip-flop defaults to the inactive state. SR is not invertible within the CLB.CLB Signal Flow ControlIn addition to the H-LUT input control multiplexers (shown in box "A" of Figure 2, page 4) there are signal flow control multiplexers (shown in box "B" of Figure 2) which select the signals which drive the flip-flop inputs and the combinatorial CLB outputs (X and Y).Each flip-flop input is driven from a 4:1 multiplexer which selects among the three LUT outputs and DIN as the data source.Each combinatorial output is driven from a 2:1 multiplexer which selects between two of the LUT outputs. The X output can be driven from the F-LUT or H-LUT, the Y output from G-LUT or H-LUT .Control SignalsThere are four signal control multiplexers on the input of the CLB. These multiplexers allow the internal CLB control sig-nals (H1, DIN, SR, and EC in Figure 2 and Figure 4) to be driven from any of the four general control inputs (C1-C4 in Figure 4) into the CLB. Any of these inputs can drive any of the four internal control signals.T able 2: CLB Storage Element FunctionalityLegend:XDon ’t careRising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Figure 3: CLB Flip-Flop Functional Block Diagram6DS060 (v1.6) September 19, 2001The four internal control signals are:•EC: Enable Clock•SR: Asynchronous Set/Reset or H function generator Input 0•DIN: Direct In or H function generator Input 2•H1: H function generator Input 1.Input/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide the interface between external package pins and the internal logic. Each IOB controls one package pin and can be con-figured for input, output, or bidirectional signals. Figure 6shows a simplified functional block diagram of the Spar-tan/XL IOB.IOB Input Signal PathThe input signal to the IOB can be configured to either go directly to the routing channels (via I1 and I2 in Figure 6) or to the input register. The input register can be programmed as either an edge-triggered flip-flop or a level-sensitive latch. The functionality of this register is shown in Table 3,and a simplified block diagram of the register can be seen in Figure 5.Figure 4: CLB Control Signal InterfaceFigure 5: IOB Flip-Flop/Latch Functional BlockDiagramTable 3: Input Register FunctionalityX Don ’t care.Rising edge (clock not inverted).SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)The register choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are also available. The clock signal inverter is also shown in Figure5 on the CK line.The Spartan IOB data input path has a one-tap delay ele-ment: either the delay is inserted (default), or it is not. The Spartan-XL IOB data input path has a two-tap delay ele-ment, with choices of a full delay, a partial delay, or no delay. The added delay guarantees a zero hold time with respect to clocks routed through the global clock buffers. (See Glo-bal Nets and Buffers, page12 for a description of the glo-bal clock buffers in the Spartan/XL families.) For a shorter input register setup time, with positive hold-time, attach a NODELAY attribute or property to the flip-flop.The output of the input register goes to the routing channels (via I1 and I2 in Figure6). The I1 and I2 signals that exit the IOB can each carry either the direct or registered input signal.The 5V Spartan input buffers can be globally configured for either TTL (1.2V) or CMOS (VCC/2) thresholds, using an option in the bitstream generation software. The Spartan output levels are also configurable; the two global adjust-ments of input threshold and output level are independent. The inputs of Spartan devices can be driven by the outputs of any 3.3V device, if the Spartan inputs are in TTL mode. Input and output thresholds are TTL on all configuration pins until the configuration has been loaded into the device and specifies how they are to be used. Spartan-XL inputs are TTL compatible and 3.3V CMOS compatible. Supported sources for Spartan/XL device inputs are shown in Table4.Spartan-XL I/Os are fully 5V tolerant even though the V CC is 3.3V. This allows 5V signals to directly connect to the Spar-tan-XL inputs without damage, as shown in Table4. In addi-tion, the 3.3V V CC can be applied before or after 5V signals are applied to the I/Os. This makes the Spartan-XL devices immune to power supply sequencing problems.Figure 6: Simplified Spartan/XL IOB Block Diagram8DS060 (v1.6) September 19, 2001Spartan-XL V CC ClampingSpartan-XL FPGAs have an optional clamping diode con-nected from each I/O to V CC . When enabled they clamp ringing transients back to the 3.3V supply rail. This clamping action is required in 3.3V PCI applications. V CC clamping is a global option affecting all I/O pins.Spartan-XL devices are fully 5V TTL I/O compatible if V CC clamping is not enabled. With V CC clamping enabled, the Spartan-XL devices will begin to clamp input voltages to one diode voltage drop above V CC . If enabled, TTL I/O com-patibility is maintained but full 5V I/O tolerance is sacrificed.The user may select either 5V tolerance (default) or 3.3V PCI compatibility. In both cases negative voltage is clamped to one diode voltage drop below ground.Spartan-XL devices are compatible with TTL, LVTTL, PCI 3V, PCI 5V and LVCMOS signalling. The various standards are illustrated in Table 5.Additional Fast Capture Input Latch (Spartan-XL only)The Spartan-XL IOB has an additional optional latch on the input. This latch is clocked by the clock used for the output flip-flop rather than the input clock. Therefore, two different clocks can be used to clock the two input storage elements.This additional latch allows the fast capture of input data,which is then synchronized to the internal clock by the IOB flip-flop or latch.T o place the Fast Capture latch in a design, use one of the special library symbols, ILFFX or ILFLX. ILFFX is a trans-parent-Low Fast Capture latch followed by an active High input flip-flop. ILFLX is a transparent Low Fast Capture latch followed by a transparent High input latch. Any of the clock inputs can be inverted before driving the library element,and the inverter is absorbed into the IOB.IOB Output Signal PathOutput signals can be optionally inverted within the IOB,and can pass directly to the output buffer or be stored in an edge-triggered flip-flop and then to the output buffer. The functionality of this flip-flop is shown in T able 6.T able 4: Supported Sources for Spartan/XL InputsT able 5: I/O Standards Supported by Spartan-XL FPGAsTable 6: Output Flip-Flop Functionality X Don ’t careRising edge (clock not inverted). SR Set or Reset value. Reset is default.0*Input is Low or unconnected (default value)1*Input is High or unconnected (default value)Z3-stateOutput Multiplexer/2-Input Function Generator (Spartan-XL only)The output path in the Spartan-XL IOB contains an addi-tional multiplexer not available in the Spartan IOB. The mul-tiplexer can also be configured as a 2-input function generator, implementing a pass gate, AND gate, OR gate, or XOR gate, with 0, 1, or 2 inverted inputs.When configured as a multiplexer, this feature allows two output signals to time-share the same output pad, effec-tively doubling the number of device outputs without requir-ing a larger, more expensive package. The select input is the pin used for the output flip-flop clock, OK.When the multiplexer is configured as a 2-input function generator, logic can be implemented within the IOB itself. Combined with a Global buffer, this arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in CLBs, and its output gated with a Read or Write Strobe driven by a global buffer. The user can specify that the IOB function generator be used by placing special library symbols beginning with the letter "O." For example, a 2-input AND gate in the IOB func-tion generator is called OAND2. Use the symbol input pin labeled "F" for the signal on the critical path. This signal is placed on the OK pin — the IOB input with the shortest delay to the function generator. Two examples are shown in Figure7.Output BufferAn active High 3-state signal can be used to place the out-put buffer in a high-impedance state, implementing 3-state outputs or bidirectional I/O. Under configuration control, the output (O) and output 3-state (T) signals can be inverted. The polarity of these signals is independently configured for each IOB (see Figure6, page7). An output can be config-ured as open-drain (open-collector) by tying the 3-state pin (T) to the output signal, and the input pin (I) to Ground.By default, a 5V Spartan device output buffer pull-up struc-ture is configured as a TTL-like totem-pole. The High driver is an n-channel pull-up transistor, pulling to a voltage one transistor threshold below V CC. Alternatively, the outputs can be globally configured as CMOS drivers, with additional p-channel pull-up transistors pulling to V CC. This option, applied using the bitstream generation software, applies to all outputs on the device. It is not individually programma-ble.All Spartan-XL device outputs are configured as CMOS drivers, therefore driving rail-to-rail. The Spartan-XL outputs are individually programmable for 12mA or 24mA output drive.Any 5V Spartan device with its outputs configured in TTL mode can drive the inputs of any typical 3.3V device. Sup-ported destinations for Spartan/XL device outputs are shown in Table7.Three-State Register (Spartan-XL Only)Spartan-XL devices incorporate an optional register control-ling the three-state enable in the IOBs. The use of the three-state control register can significantly improve output enable and disable time.Output Slew RateThe slew rate of each output buffer is, by default, reduced, to minimize power bus transients when switching non-criti-cal signals. For critical signals, attach a FAST attribute or property to the output buffer or flip-flop.Spartan/XL devices have a feature called "Soft Start-up," designed to reduce ground bounce when all outputs are turned on simultaneously at the end of configuration. When the configuration process is finished and the device starts up, the first activation of the outputs is automatically slew-rate limited. Immediately following the initial activation of the I/O, the slew rate of the individual outputs is deter-mined by the individual configuration option for each IOB. Pull-up and Pull-down NetworkProgrammable pull-up and pull-down resistors are used fortying unused pins to V CC or Ground to minimize power con-sumption and reduce noise sensitivity. The configurablepull-up resistor is a p-channel transistor that pulls to V CC.The configurable pull-down resistor is an n-channel transis-tor that pulls to Ground. The value of these resistors is typi-cally 20KΩ − 100KΩ (See "Spartan DC Characteristics Figure 7: AND and MUX Symbols in Spartan-XL IOB10DS060 (v1.6) September 19, 2001Over Operating Conditions" on page 43.). This high value makes them unsuitable as wired-AND pull-up resistors.After configuration, voltage levels of unused pads, bonded or unbonded, must be valid logic levels, to reduce noise sensitivity and avoid excess current. Therefore, by default,unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured with the pull-down resistor, or as a driven output, or to be driven by an external source. To activate the internal pull-up, attach the PULLUP library component to the net attached to the pad. To activate the internal pull-down, attach the PULL-DOWN library component to the net attached to the pad.Set/ResetAs with the CLB registers, the GSR signal can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property. The two flip-flops can be individually configured to set or clear on reset and after configuration. Other than the global GSR net, no user-con-trolled set/reset signal is available to the I/O flip-flops (Figure 5). The choice of set or reset applies to both the ini-tial state of the flip-flop and the response to the GSR pulse.Independent ClocksSeparate clock signals are provided for the input (IK) and output (OK) flip-flops. The clock can be independently inverted for each flip-flop within the IOB, generating eitherfalling-edge or rising-edge triggered flip-flops. The clock inputs for each IOB are mon Clock EnablesThe input and output flip-flops in each IOB have a common clock enable input (see EC signal in Figure 5), which through configuration, can be activated individually for the input or output flip-flop, or both. This clock enable operates exactly like the EC signal on the Spartan/XL CLB. It cannot be inverted within the IOB.Routing Channel DescriptionAll internal routing channels are composed of metal seg-ments with programmable switching points and switching matrices to implement the desired routing. A structured,hierarchical matrix of routing channels is provided to achieve efficient automated routing.This section describes the routing channels available in Spartan/XL devices. Figure 8 shows a general block dia-gram of the CLB routing channels. The implementation soft-ware automatically assigns the appropriate resources based on the density and timing requirements of the design.The following description of the routing channels is for infor-mation only and is simplified with some minor details omit-ted. For an exact interconnect description the designer should open a design in the FPGA Editor and review the actual connections in this tool.The routing channels will be discussed as follows;•CLB routing channels which run along each row and column of the CLB array.•IOB routing channels which form a ring (called a VersaRing) around the outside of the CLB array. It connects the I/O with the CLB routing channels.•Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew. Global routing can also be used for other high-fanout signals.CLB Routing ChannelsThe routing channels around the CLB are derived from three types of interconnects; single-length, double-length,and longlines. At the intersection of each vertical and hori-zontal routing channel is a signal steering matrix called a Programmable Switch Matrix (PSM). Figure 8 shows the basic routing channel configuration showing single-length lines, double-length lines and longlines as well as the CLBs and PSMs. The CLB to routing channel interface is shown as well as how the PSMs interface at the channel intersec-tions.T able 7: Supported Destinations for Spartan/XL OutputsNotes:1.Only if destination device has 5V tolerant inputs.CLB InterfaceA block diagram of the CLB interface signals is shown in Figure9. The input signals to the CLB are distributed evenly on all four sides providing maximum routing flexibility. In general, the entire architecture is symmetrical and regular. It is well suited to established placement and routing algo-rithms. Inputs, outputs, and function generators can freely swap positions within a CLB to avoid routing congestion during the placement and routing operation. The exceptions are the clock (K) input and CIN/COUT signals. The K input is routed to dedicated global vertical lines as well as four single-length lines and is on the left side of the CLB. The CIN/COUT signals are routed through dedicated intercon-nects which do not interfere with the general routing struc-ture. The output signals from the CLB are available to drive both vertical and horizontal channels.Programmable Switch MatricesThe horizontal and vertical single- and double-length lines intersect at a box called a programmable switch matrix (PSM). Each PSM consists of programmable pass transis-tors used to establish connections between the lines (see Figure10).For example, a single-length signal entering on the right side of the switch matrix can be routed to a single-length line on the top, left, or bottom sides, or any combination thereof, if multiple branches are required. Similarly, a dou-ble-length signal can be routed to a double-length line on any or all of the other three edges of the programmable switch matrix.Single-Length LinesSingle-length lines provide the greatest interconnect flexibil-ity and offer fast routing between adjacent blocks. There are eight vertical and eight horizontal single-length lines associ-ated with each CLB. These lines connect the switching matrices that are located in every row and column of CLBs. Single-length lines are connected by way of the program-mable switch matrices, as shown in Figure10. Routing con-nectivity is shown in Figure8.Single-length lines incur a delay whenever they go through a PSM. Therefore, they are not suitable for routing signals for long distances. They are normally used to conduct sig-nals within a localized area and to provide the branching for nets with fanout greater than one.Figure 8: Spartan/XL CLB Routing Channels and Interface Block DiagramFigure 9: CLB Interconnect Signals。
MIC45205评估板：26V 6A DC-到-DC电源模块，超轻负载和超速控制是Micrel公司的
MIC45205 Evaluation Board26V/6A DC-to-DC Power ModuleGeneral DescriptionMicrel’s MIC45205 is a synchronous step-down regulatormodule, featuring a unique adaptive ON-time controlarchitecture. The module incorporates a DC-to-DCcontroller, power MOSFETs, bootstrap diode, bootstrapcapacitor, and an inductor in a single package; simplifyingthe design and layout process for the end user.This highly integrated solution expedites system designand improves product time-to-market. The internalMOSFETs and inductor are optimized to achieve highefficiency at a low output voltage. The fully optimizeddesign can deliver up to 6A current under a wide inputvoltage range of 4.5V to 26V, without requiring additionalcooling.The MIC45205-1 uses Micrel’s HyperLight Load®(HLL)MIC45205-2 uses Micrel’s Hyper Speed Control™architecture which enables ultra-fast load transientresponse, allowing for a reduction of output capacitance.The MIC45205 offers 1% output accuracy that can beadjusted from 0.8V to 5.5V with two external resistors.The basic parameters of the evaluation board are:•Input: 4.5V to 26V•Output 0.8V to 5V at 6A•600kHz Switching Frequency−Adjustable 200kHz to 600kHzDatasheets and support documentation are available onMicrel’s web site at: .RequirementsThe MIC45205-1 and MIC45205-2 evaluation boardrequires only a single power supply with at least 10Acurrent capability. No external linear regulator is requiredto power the internal biasing of the IC because theMIC45205 has an internal PVDD LDO. In the applicationswith VIN < +5.5V, PVDD should be tied to VIN to bypassthe internal linear regulator. The output load can either bea passive or an active load.PrecautionsThe MIC45205 evaluation board does not have reversepolarity protection. Applying a negative voltage to the VINand GND terminals may damage the device. Themaximum VIN of the board is rated at 26V. Exceeding 30Von the VIN could damage the device.Getting Started1. VIN SupplyConnect a supply to the VIN and GND terminals,paying careful attention to the polarity and the supplyrange (4.5V < VIN < 26V). Monitor IIN with a currentmeter and monitor input voltage at VIN and GNDterminals with a voltmeter. Do not apply power untilStep 4.2. Connect Load and Monitor OutputConnect a load to the VOUT and GND terminals. Theload can be either a passive (resistive) or an active (asin an electronic load) type. A current meter may beplaced between the VOUT terminal and load tomonitor the output current. Ensure the output voltageis monitored at the VOUT terminal.3. Enable InputThe EN pin has an on board 100kΩpull-up resistor(R10) to VIN, which allows the output to be turned onwhen PVDD exceeds its UVLO threshold. An ENconnector is provided on the evaluation board forusers to easily access the enable feature. Applying anexternal logic signal on the EN pin to pull it low orusing a jumper to short the EN pin to GND will shut offthe output of the MIC45205 evaluation board.4. Turn PowerTurn on the VIN supply and verify that the outputvoltage is regulated to 5V.Ordering InformationPart Number DescriptionMIC45205-1YMP EV MIC45205-1 Evaluation BoardMIC45205-2YMP EV MIC45205-2 Evaluation BoardFeaturesFeedback ResistorsThe output voltage on the MIC45205 evaluation board, which is preset to 5.0V, is determined by the feedback divider, as illustrated in Equation 1:+×=BOTTOMREF OUT R R141V V Eq. 1where V REF = 0.8V, and R BOTTOM is one of R3 thru R9. Leaving the R BOTTOM open by removing all jumpers on the feedback headers gives a 0.8V output voltage. All other voltages not listed above can be set by modifying R BOTTOM value according to Equation 2:REFOUT REFBOTTOM V V V R1R −×=Eq. 2Note that the output voltage should not be set to exceed 5V.Table 1. Typical Values of Some Components V OUT VIN R14(Top Feedback Resistor)R(Bottom Feedback Resistor)C14 (C ff ) C OUT 1.0V 5V to 26V 10kΩ 40.2kΩ 2.2nF 100µF/6.3V 1.2V 5V to 26V 10kΩ 20.0kΩ 2.2nF 100µF/6.3V 1.5V 5V to 26V 10kΩ 11.5kΩ 2.2nF 100µF/6.3V 1.8V 5V to 26V 10kΩ 8.06kΩ 2.2nF 100µF/6.3V 2.5V 5V to 26V 10kΩ 4.75kΩ 2.2nF 100µF/6.3V 3.3V 5V to 26V 10kΩ 3.24kΩ 2.2nF 100µF/6.3V 5V7V to 26V10kΩ1.91kΩ2.2nF100µF/6.3VSW NodeA test pad is placed for monitoring the switching waveform, which is one of the most critical waveforms for the converter.Current LimitThe MIC45205 uses the R DS(ON) of the low-side MOSFET and external resistor connected from the ILIM pin to the SW node to decide the current limit.Figure 1. MIC45205 Current-Limiting CircuitIn each switching cycle of the MIC45205, the inductor current is sensed by monitoring the low-side MOSFET in the OFF period. The sensed voltage V(ILIM)is compared with the power ground (PGND) after a blanking time of 150ns. In this way the drop voltage over the resistor R15 (V CL) is compared with the drop over the bottom FET generating the short current limit. The small capacitor (C15) connected from ILIM pin to PGND filters the switching node ringing during the off-time allowing a better short-limit measurement. The time constant created by R15 and C15 should be much less than the minimum off time.The V CL drop allows programming of short limit through the value of the resistor (R15) if the absolute value of the voltage drop on the bottom FET is greater than V CL. In that case the V(ILIM)is lower than PGND and a short circuit event is triggered. A hiccup cycle to treat the short event is generated. The hiccup sequence including the soft-start reduces the stress on the switching FETs and protects the load and supply for severe short conditions. The short-circuit current limit can be programmed by using Equation 3:()CLCL)ON(DSPPLCLIMIVR)5.0II(R15+××D−=Eq. 3 where:I CLIM = Desired current limitR DS(ON) = On-resistance of low-side power MOSFET, 16mΩ typicallyV CL= Current-limit threshold (typical absolute value is 14mV per Electrical Characteristics in the MIC45205 data sheet)I CL= Current-limit source current (typical value is 80µA, per Electrical Characteristics in the MIC45205 data sheet). ΔI L(PP)= Inductor current peak-to-peak, since the inductor is integrated, use Equation 4 to calculate the inductor ripple current.The peak-to-peak inductor current ripple is:LfV)V(VVIswIN(MAX)OUTIN(MAX)OUTL(PP)××−×=D Eq. 4The MIC45205 has 1.0µH inductor integrated into the module. In case of hard short, the short limit is folded down to allow an indefinite hard short on the output without any destructive effect. It is mandatory to make sure that the inductor current used to charge the output capacitance during soft start is under the folded short limit; otherwise the supply will go in hiccup mode and may not be finishing the soft start successfully.The MOSFET R DS(ON) varies 30 to 40% with temperature. Therefore, it is recommended to add a 50% margin to I CLIM in the above equation to avoid false current limiting due to increased MOSFET junction temperature rise. With R15 = 1.37kΩ and C15 = 15pF, the typical output current limit is 8A.Setting the Switching FrequencyThe MIC45205 switching frequency can be adjusted by changing the value of resistors R1 and R2. The switching frequency also depends on VIN, V OUT and load conditions.Figure 2. Switching Frequency AdjustmentEquation 5 gives the estimated switching frequency:2R 1R 2R f f O SW +×=Eq. 5where: f O = 600kHzR1 = 100k Ω (recommended)R2 is selected to set the required switching frequency as shown in Figure 3:Figure 3. Switching Frequency vs. R2MIC45205 Evaluation Board SchematicFigure 4. Schematic of MIC45205 Evaluation BoardBill of MaterialsItem Part Number Manufacturer Description Qty. C1 B41125A7227M TDK(1)220µF/35V, ALE Capacitor (optional) 1 C1X, C6, C9,C10, C7, C13Open 6 C3 C3216X5R1H106M160AB TDK 10uF/50V, 1206, X5R, 10%, MLCC 1 C2, C4, C8 GRM188R71H104KA93D Murata(2)0.1µF/50V, X7R, 0603, 10%, MLCC 3 C5 C3216X5R0J107M160AB TDK 100µF/6.3V, X5R, 1206, 20%, MLCC 1 C12 C1608C0G1H222JT TDK 2.2nF/50V, NP0, 0603, 5%, MLCC 1 C11 GRM1885C1H150JA01D Murata 15pF/50V, NP0, 0603, 5%, MLCC 3 CON1, CON2,CON3, CON48174 Keystone(3)15A, 4-Prong Through-Hole Screw Terminal 4 J1 M50-3500742 Harwin(4)Header 2x7 1 J2, J3, J4,TP3 − TP590120-0122 Molex(5)Header 2 6 JPx1, JPx2 Open 2 R1, R10 CRCW0603100K0FKEA Vishay Dale(6)100kΩ, 1%, 1/10W, 0603, Thick Film 2 R2, R12,R13, R16Open 4 R3 CRCW060340K2FKEA Vishay Dale 40.2kΩ, 1%, 1/10W, 0603, Thick Film 1 R4 CRCW06020K0FKEA Vishay Dale 20kΩ, 1%, 1/10W, 0603, Thick Film 1 R5 CRCW060311K5FKEA Vishay Dale 11.5kΩ, 1%, 1/10W, 0603, Thick Film 1 R6 CRCW06038K06FKEA Vishay Dale 8.06kΩ, 1%, 1/10W, 0603, Thick Film 1 R7 CRCW06034K75FKEA Vishay Dale 4.75kΩ, 1%, 1/10W, 0603, Thick Film 1 R8 CRCW06033K24FKEA Vishay Dale 3.24kΩ, 1%, 1/10W, 0603, Thick Film 1 R9 CRCW06031K91FKEA Vishay Dale 1.91kΩ, 1%, 1/10W, 0603, Thick Film 1 R11 CRCW060349K9FKEA Vishay Dale 49.9kΩ, 1%, 1/10W, 0603, Thick Film 1 R14 CRCW060310K0FKEA Vishay Dale 10kΩ, 1%, 1/10W, 0603, Thick Film 1 R15 CRCW06031K37FKEA Vishay Dale 1.37kΩ, 1%, 1/10W, 0603, Thick Film 1 R17, R18, R19 RCG06030000Z0EA Vishay Dale 0Ω Resistor, 1%, 1/10W, 0603, Thick Film 3 TP6 − TP9,JPx3, JPx41502-2 Keystone Single-End, Through-Hole Terminal 6U1 MIC45205-1YMPMicrel, Inc.(7)26V/6A DC-to-DC Power Module 1 MIC45205-2YMPNotes:1. TDK: .2. Murata: .3. Keystone: .4. Harwin: 5. Molex: .6. Vishay-Dale: .7. Micrel: .PCB Layout RecommendationsMIC45205 Evaluation Board Top LayerMIC45205 Evaluation Board Copper Layer 2PCB Layout Recommendations (Continued)MIC45205 Evaluation Board Copper Layer 3MIC45205 Evaluation Board Bottom LayerMICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USATEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high-performance linear and power, LAN, and timing & communications markets. The Company’s products include advanced mixed-signal, analog & power semiconductors; high-performance communication, clock management, MEMs-based clock oscillators & crystal-less clock generators,Ethernet switches, and physical layer transceiver ICs. Company customers include leading manufacturers of enterprise, consumer, industrial, mobile, telecommunications, automotive, and computer products. Corporation headquarters and state-of-the-art wafer fabrication facilities are located in San Jose, CA, with regional sales and support offices and advanced technology design centers situated throughout the Americas, Europe, and Asia. Additionally, the Company maintains an extensive network of distributors and reps worldwide.Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this datasheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right.Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.© 2014 Micrel, Incorporated.。
hc05协议 (2)
hc05协议协议名称：HC05通信协议一、引言HC05通信协议旨在规范HC05蓝牙模块与其他设备之间的通信方式，确保数据传输的稳定性和可靠性。
本协议适合于各类设备之间的蓝牙通信，包括但不限于智能手机、电脑、单片机等。
二、协议范围本协议适合于使用HC05蓝牙模块进行通信的所有设备。
涉及到的通信方式包括串口通信、蓝牙配对、数据传输等。
三、术语定义1. HC05蓝牙模块：一种基于蓝牙技术的无线通信模块，用于实现设备之间的数据传输。
2. 串口通信：通过串行接口进行数据传输的通信方式，通常使用UART（通用异步收发传输）协议。
3. 蓝牙配对：蓝牙设备之间建立安全连接的过程，确保通信的私密性。
4. 数据传输：设备之间通过蓝牙模块传输数据的过程。
四、通信流程1. 初始化a. 确保HC05蓝牙模块已正确连接至设备的串口接口。
b. 设置串口通信参数，包括波特率、数据位、住手位、校验位等。
c. 配置HC05蓝牙模块的工作模式，包括主从模式、透明传输模式等。
2. 蓝牙配对a. 打开设备的蓝牙功能，并设置可被发现和可配对的状态。
b. 在另一设备上搜索可用的蓝牙设备，并选择与HC05蓝牙模块进行配对。
c. 输入配对码，确保配对的安全性。
3. 数据传输a. 在设备上建立蓝牙连接，并确保连接的稳定性。
b. 通过串口通信发送数据至HC05蓝牙模块。
c. HC05蓝牙模块将接收到的数据通过蓝牙信道传输至目标设备。
d. 目标设备接收到数据后进行相应的处理，如解析、存储等。
五、数据格式1. 串口通信数据格式a. 波特率：默认为9600bps，可根据实际需求进行调整。
b. 数据位：8位。
c. 住手位：1位。
d. 校验位：无。
2. 数据传输格式a. 数据包：每一个数据包由起始位、数据位、校验位和住手位组成。
b. 起始位：1个字节，表示数据包的起始标志。
c. 数据位：根据实际需求确定数据长度，可变长度。
d. 校验位：用于校验数据包的完整性和正确性。
M052_54 ARM中文资料
Cortex™-M032-位微控制器NuMicro M051™- 系列M052/54 微控制器简介The information described in this document is the exclusive intellectual property ofNuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton. Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based system design. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information or questions, please contact: Nuvoton Technology Corporation.目录-1概述 (3)2特性 (4)3管脚定义 (7)3.1QFN 32 (7)3.2LQFP 48 (8)3.3管脚功能描述 (9)4功能模块 (12)4.1绝对最大额定值 (13)4.2DC 电气特性 (14)4.3AC 电气特性 (17)4.3.1外部 XTAL1 晶振 (17)4.3.2典型晶振应用线路 (18)4.3.3内部 22.1184MHz RC 晶振 (19)4.3.4内部10KHz RC 晶振 (19)4.4模拟量特性 (20)4.4.11-MS/s 12-位 SARADC特性 (20)4.4.2LDO规格及电源管理 (21)4.4.3低压复位说明 (22)4.4.4欠压检测说明 (22)4.4.5上电复位说明(5V) (22)5应用电路 (23)6封装信息 (24)6.148L LQFP (7x7x1.4mm footprint 2.0mm) (24)6.2QFN 32L 5X5 mm^2, Thickness 0.8mm, Pitch 0.5 mm (25)7版本历史 (26)1 概述M052/54 系列为ARM® Cortex™-M0内核的32位微控制器，适用于工业控制应用领域，Cortex™-M0是ARM最新的32位嵌入式处理器，拥有可与传统8051单片机匹敌的价格优势。
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KEMET Electronics Corporation, P.O. Box 5928, Greenville, S.C. 29606, (864) 963-6300
3
the lowest volumetric efficiency.
元器件交易网 Class II: St-C-11015 (CK) & Mil-PRF-39014 (CKR) Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Part Number Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 - 31
NOTICE
Although the information in this catalog has been carefully checked for accuracy, and is believed to be correct and current, no warranty, either express or implied, is made as to either its applicability to, or its compatibility with, specific requirements; nor does KEMET Electronics Corporation assume any responsibility for correctness of this information, nor for damages consequent to its use. All design characteristics, specifications, tolerances, and the like are subject to change without notice.
suitable for bypass or coupling applications or frequency discriminating circuits where Q and stability of capacitance characteristics are not of a major importance. Class II capacitors have temperature characteristics of ± 15% or less. They are made from materials which are ferro-electric, yielding higher volumetric efficiency but less stability. Class II capacitors are affected by temperature, voltage, frequency and time.
Ceramic Molded Standard/Axial & Radial Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Part Number Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 - 19 Mil-PRF-20 Outline Drawings . . . . . Dimensions . . . . . . . . . Ordering Information . . Marking . . . . . . . . . . . . Part Number Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 - 25
Ceramic Axial Tape & Reel Packaging Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Ceramic Radial Tape & Reel Packaging Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Ceramic Leaded Packaging Quantities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Application Notes for Multilayer Ceramic Capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 - 39
temperature range of - 55°C to + 125°C (Also known as “NP0”). X7R: Class II, with a maximum capacitance change of ± 15% over an operating temperature range of - 55°C to + 125°C. Z5U: Class III, with a maximum capacitance change of + 22% - 56% over an operating temperature range of + 10°C to + 85°C. Specified electrical limits for these three temperature characteristics are shown in Table 1.