EM4-DINAV13DDR中文资料
维金Lite方向控制阀门值,G1 8,G1 4和G3 8说明书
3
Strategic Rationale
• To penetrate the global in-line valve market
• $100m addressable market
• Highly competitive product to address the in-line valve market in all regions of the world
• Overview • Specification • Design features • Options & accessories • Viking Lite & Xtreme – product differences
• Price & product positioning • Launch date • Summary
Viking Lite
Directional Control Valves
G1/8, G1/4 & G3/8 Body Ported
08 November 2019
Viking Lite
Table of contents
• Strategic rationale • Product information
Accessories
• Manifold bar - Anodised aluminium • Pressure bar - Anodised aluminium
10
Viking Lite
Table of contents
• Strategic rationale • Product information
EM4150A5WW11中文资料(EM Microelectronic)中文数据手册「EasyDatasheet - 矽搜」
EM微电子
- MARIN SA
EM4150 EM4350
1千比特读/写
非接触式识别装置
描述 该EM4150 / EM4350(以前称为P4150 / P4350) 是CMOS集成电路打算用于电子 读/写射频转发器.该芯片包含1千位 EEPROM,可以由用户来配置,允许写入禁止区,读出防 护护区,和一个连续地读区域输出功率上.存储器可以 通过使用所有写入和读防护护操作32位密码被固定. 密码可以被更新,但从来不看.固定代码序列号和设备标 识是激光编程尽一切芯片独一无二.
Control Word 0 - 7 First Word Read
8 - 15 Last Word Read 16 Password Check On/Off 17 Read After Write On/Off
18 - 31 User available
On means bit set to logic '1' Off means bit set to logic '0'
Device Identification Word & Serial Number Word Laser Programmed - Read Only
图. 6
4
芯片中文手册,看全文,戳
标准读模式
经过上电复位和一个完成时
命令,芯片将执行标准读
模式,将在其中通过连续发送数据,字
从第一之间限定存储器部分字
□ 场频位周期= 64或32学时 □ 170 pF±2%片上谐振电容 □ -40至+ 85°C温度范围 □ 100至150 kHz场频范围 □ 片上整流器和电压限制器 □ 由于无需外部电源缓冲电容
施耐德电气 MN4000 料位开关 振棒式 操作手册说明书
page 内容目录页码安全须知 / 技术支持2-----------------------------------------------------------------------------------------------------简介3-----------------------------------------------------------------------------------------------------技术参数4-----------------------------------------------------------------------------------------------------认证8-----------------------------------------------------------------------------------------------------可选项9-----------------------------------------------------------------------------------------------------安装10-----------------------------------------------------------------------------------------------------电气安装13-----------------------------------------------------------------------------------------------------信号输出16-----------------------------------------------------------------------------------------------------灵敏度设置16----------------------------------------------------------------------------------------------------- 维护17-----------------------------------------------------------------------------------------------------危险区域应用须知18-----------------------------------------------------------------------------------------------------组装 MN 404020-----------------------------------------------------------------------------------------------------废弃23-----------------------------------------------------------------------------------------------------技术如有更新,恕不另行通知。
EEV driver 4 EVD4 circuit diagram说明书
CVSTDUM0R0+050004150 - rel. 1.7 - 09.01.2013Tabella codici / Table of product codesEVD evolutioncode descriptionEVD0000E00EVD Evolution universal (tLAN)EVD0000E01EVD Evolution universal (tLAN),10 pz* (pcs)EVD0000E10EVD Evolution universal (pLAN)EVD0000E11EVD Evolution universal (pLAN),10 pz* (pcs)EVD0000E20EVD Evolution universal (RS485/Modbus®)EVD0000E21EVD Evolution universal (RS485/Modbus®), 10 pz* (pcs)EVD0000E30EVD Evolution for CAREL valves(tLAN)EVD0000E31EVD Evolution for CAREL valves(tLAN), 10 pz* (pcs)EVD0000E40EVD Evolution for CAREL valves(pLAN)EVD0000E41EVD Evolution for CAREL valves(pLAN), 10 pz* (pcs)EVD0000E50EVD Evolution for CAREL valves(RS485/Modbus®)EVD0000E51EVD Evolution for CAREL valves(RS485/Modbus®), 10 pz* (pcs)EVD0002E10EVD Evolution universaloptoisolated (pLAN)EVD0002E20EVD Evolution universaloptoisolated (RS485/Modbus®)(*) La confezione con imballo multiplo non è fornita di connettori / Th e multiple packages are not supplied with connectorsTabella compatibilità valvole / Table of valve compatibilityModel CAREL E*V****ALCOEX4; EX5; EX6; EX7; EX8 330 Hz (consigliato da CAREL/supported by CAREL ); EX8 500 Hz (da specifi che ALCO/from ALCO specifi cations )SPORLAN SEI 0.5-11; SER 1.5-20; SEI 30; SEI 50; SEH 100; SEH175Danfoss ETS 12.5-25B; ETS 50B; ETS 100B; ETS 250; ETS 400; CCM 10-20-30; CCM 40CAREL Due EXV CAREL collegate insieme / Two CAREL ExV connected together SPORLAN SER(I) G, J, K Montaggio scheda display D isplay board mountingC ompatibilità refrigeranti R efrigerant compatibilityR22; R134a; R404A; R407C; R410A; R507A; R290; R600; R600a; R717; R744; R728; R1270; R417A; R422D; R413A; R422A; R423A; R407A; R427A; R245Fa; R407F; R32; HTR01; HTR02For further information, see the “EEV system guide” (code +030220810) and the user manual (code +0300005EN) available at , under the“Literature” section.to be executed.Modalità di connessioni e alimentazione tL AN , pL AN e RS 485tL AN , pL AN and RS 485 connections and power supplyS chema elettrico per il controllo del surriscaldamento / W iring diagram for superheat controlCaso 1: applicazione di più driver collegati in rete, all’interno dello stesso quadro elettrico, alimentati dallo stesso trasformatore Case 1: a series of drivers is connected in a network, installed in the same electrical panel, powered by the same transformerCaso 2: applicazione di più driver collegati in rete, all’interno di quadri elettrici diversi, alimentati da trasformatori diversi (G0 non connesso a terra).Case 2: a series of drivers is connected in a network, installed in electrical diff erent panels, powered by diff erent transformers (G0 not connected to earth).punto di messa a terra.Case 3: a series of drivers is connected in a network, installed in electrical diff erent panels, powered by diff erent transformers with just one earth point.Per ulteriori informazioni, consultare la “Guida al sistema EEV” (codice +030220810) e il manuale d’uso (codice +03000005IT) disponibili sul sito, alla sezione “Documentazione”.procedura di prima messa in servizio.sovraccarico / Use a class 2 safety transformer, suitably protected against short-circuits and voltage surgesCASO 1/ CASE 1:alimentazione 230 Vac con modulo di emergenza/230 Vac power supply with emergency module CASO 3/ CASE 3:alimentazione 24 Vdc/ 24 Vdc power supplydisplay (accessorio/accessory)codedescriptionEVDIS00CN0Display (Chinese)EVDIS00CZ0Display (Czech)EVDIS00DE0Display (German)EVDIS00EN0Display (English)EVDIS00ES0Display (Spanish)EVDIS00FR0Display (French)EVDIS00IT0Display (Italian)EVDIS00JP0Display (Japanese)EVDIS00PL0Display (Polish)EVDIS00PT0Display (Portuguese)EVDIS00RU0Display (Russian)EVDIS00SE0Display (Swedish)altri accessori/other accessoriesEVDCON0021Kit connettori 10 pz*(connector kit 10 pcs)EVDCNV00E0Convertitore USB/tLAN(USB/tLAN converter)TRADRFE240trasformatore 35VA(35VA transformer)EVD0000UC0Modulo Ultracap(Ultracap module)C AREL INDUSTRIES HQsVia dell’Industria, 11 - 35020 Brugine - Padova (Italy)Tel.(+39)0499716611–Fax(+39)0499716600––e-mail:***************+050004150 - rel. 1.7 - 09.01.2013 CAREL si riserva la possibilità di apportare modifi che o cambiamenti ai propri prodotti senza alcun preavviso. / CAREL reserves the right to modify the features of its products without prior notice.。
n4000-13(SI)
- Fine-Line Multilayers - B ackplanes- S urface-Mount Multilayers - B GA Multilayers - M CM-Ls - CSP Attachment- W ireless Communication Infrastructure - H igh Speed Services - H igh Speed Storage Networks - I nternet Switching / Routing SystemsThe Nelco® N4000-13 series is an enhanced epoxy resin systemengineered to provide both outstanding thermal and high signal speed / low signal loss properties. N4000-13 SI ® is excellent for applications that require optimum signal integrity and precise impedance control, while maintaining high reliability through CAF2 and thermal resistance.Lead-Free Assembly Compatible- Ideally suited for assemblies with a maximum reflow temperature of 245°C1- Nelco N4000-13 has shown acceptable results in reflow conditions up to 260ºC1 depending on the PCB design and manufacturing processingTg >210ºC, outstanding thermal, electrical and signalloss properties- Excellent thickness control for tight tolerance impedance applications- Low Df and Dk allows for low signal distortion and faster signal propogation required by high frequency (1 - 10 GHz) and high reliability applications CAF 2 Resistant- The low Z-CTE and proven CAF resistance2 provide long-term reliability for both RF and digital applicationsSignal Integrity and Buried Capacitance TM Options- When used, SI glass provides enhanced electrical performance for even the most demanding applications - Approved ZBC-2000® substrate available for thinner, more reliable assemblies and increased board densities High-Tg FR-4 processing- Processes similar to traditional high Tg FR-4 materials - 90 min press at 193ºC and 275-350 psiAvailable in a variety of constructions - Vacuum laminated- Available in a wide variety of constructions, copper weights and glass styles including standard copper, double treat and RTFOIL ® laminate.- Meets UL 94V-0 and IPC-4101/29 specifications - All Nelco® materials are RoHS compliant.Global AvailabilityHigh-Speed Multifunctional Epoxy Laminate & PrepregNelco ® N4000-13Nelco ® N4000-13 SI ®Park’s UL file number: E36295ApplicationsNelco Products, Inc., California+1.714.879.4293Neltec, Inc., Arizona +1.480.967.5600Nelco Products Pte, Asia Pacific +65.6861.7117Neltec, SA, France + info@P A R KE L E C T R O C H E M I C A LC O R P .Rev 4-10Mechanical PropertiesN4000-13-13 SIU.S. Units N4000-13-13 SI MetricTest MethodPeel Strength - 1 oz. (35 micron) Cu After Solder Float7.57.5 lb / inch 1.31 1.31 N / mm IPC-TM-650.2.4.8 At Elevated Temperature8.1 8.1 lb / inch 1.42 1.42 N / mm IPC-TM-650.2.4.8.2a After Exposure to Process Solutions 9.0 9.0 lb / inch 1.58 1.58 N / mm IPC-TM-650.2.4.8X / Y CTE [-40°C to +125°C] 10 - 14 9 - 13 ppm / °C 10 - 14 9 - 13 ppm / °C IPC-TM-650.2.4.41Z Axis CTE Alpha 1 [50°C to Tg] 70 70 ppm / °C 70 70 ppm / °C IPC-TM-650.2.4.41Z Axis CTE Alpha 2 [Tg to 260°C] 280 280 ppm / °C 280 280 ppm / °C IPC-TM-650.2.4.41Z Axis Expansion [50°C to 260°C] 3.5 3.5 %3.5 3.5 %IPC-TM-650.2.4.41Young’s Modulus (X / Y) 4.2 / 3.3 2.4 / 2.3 psi x 106 28.5 / 22.4 16.5 / 15.9 GN / m 2 ASTM D3039Poisson’s Ratios (X / Y) 0.13 / 0.11 0.18 / 0.170.13 / 0.11 0.18 / 0.17ASTM D3039Thermal Conductivity 0.350 0.294 W / mK 0.350 0.294 W / mK ASTM E1461Specific Heat1.201.30J / gK1.20 1.30J / gKASTM E1461Electrical PropertiesDielectric Constant (50% resin content)@ 1 GHz (RF Impedance) 3.73.4 3.7 3.4 IPC-TM-650.2.5.5.9 @ 2.5 GHz (Split Post Cavity) 3.7 3.2 3.7 3.2 @ 10 GHz (Stripline)3.6 3.2 3.6 3.2IPC-TM-650.2.5.5.5@ 10 GHz (Split Post Cavity) 3.7 3.3 3.7 3.3Dissipation Factor (50% resin content) @ 2.5 GHz (Split Post Cavity) 0.009 0.008 0.009 0.008 @ 10 GHz (Stripline)0.009 0.008 0.009 0.008 IPC-TM-650.2.5.5.5@ 10 GHz (Split Post Cavity) 0.0080.0070.0080.007Volume Resistivity C - 96 / 35 / 90 108 108 M Ω - cm 108 108M Ω - cm IPC-TM-650.2.5.17.1 E - 24 / 125 107 108 M Ω - cm107 108 M Ω - cm IPC-TM-650.2.5.17.1Surface Resistivity C - 96 / 35 / 90 107 107 M Ω 107 107 M Ω IPC-TM-650.2.5.17.1E - 24 / 125 107 107 M Ω 107 107 M Ω IPC-TM-650.2.5.17.1Electric Strength 1200 1000 V / mil 4.7x104 3.9x104 V / mm IPC-TM-650.2.5.6.2Dielectric Breakdown >50 >50 kV >50 >50 kV IPC-TM-650.2.5.6Arc Resistance123 123seconds 123 123 seconds IPC-TM-650.2.5.1Thermal PropertiesGlass Transition Temperature (Tg) DSC (°C) 210 210 °C 210 210 °C IPC-TM-650.2.4.25c TMA (°C) 200 200 °C 200 200 °C IPC-TM-650.2.4.24c DMA (°C) (Tan d Peak)240 240 °C 240 240 °C IPC-TM-650.2.4.24.3Degradation Temp (TGA) (5% wt. loss) 350 350 °C 350 350 °C IPC-TM-650.2.4.24.6Pressure Cooker-60 min then solder dip IPC-TM-650.2.6.16 @288°C until failure (max 10 min.) Pass Pass Pass Pass (modified)T260 30+ 30+ minutes 30+ 30+ minutes IPC-TM-650.2.4.24.1T28810+ 10+ minutes 10+ 10+ minutes IPC-TM-650.2.4.24.1Chemical / Physical PropertiesMoisture Absorption 0.10.1 wt. % 0.10.1 wt. % IPC-TM-650.2.6.2.1Methylene Chloride Resistance 0.7 0.7 % wt. chg. 0.7 0.7 % wt. chg. IPC-TM-650.2.3.4.3Density [50% resin content]1.911.79g / cm 31.911.79g / cm 3 Internal MethodNelco N4000-13 and N4000-13 SI ®High-Speed Multifunctional Epoxy Laminate & PrepregP A R KE L E C T R O C H E M I C A LC O R P .Park Electrochemical Corp. is a global advanced materials company which develops and manufactures high-technology digital and RF/microwave printed circuit materials and advanced composite materials. The company operates under the Nelco ®, Nelcote ® and Nova™ names. All test data provided are typical values and not intended to be specification values. For review of critical specification tolerances, please contact a Nelco representative directly. Nelco reserves the right to change these typical values as a natural process of refining our testing equipment and techniques. Nelco reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Nelco does not assume any liability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights nor the rights of others. This disclaimer of warranty is in lieu of all warranties whether expressed, implied or statutory, including implied warranties of merchantability or fitness for a particular purpose.Nelco ®, Neltec ®, Nelcote ®, Nova™, RTFoil ®, SI ® , LD ® and EF ® are trademarks of Park Electrochemical Corp. BC ®, ZBC-2000® and Buried Capacitance™ are Trademarks of the Sanmina-SCI Corporation.1Refer to the N4000-13 Best Practices document and Contract Manufacturing Q&A for PCB processing recommendations. Visit for more information.2CAF resistance has been established to greater than 500 hours using a specific OEM coupon design and test procedure. Visit for more information.。
MEMORY存储芯片N25Q064A13ESE40F中文规格书
DDR3L SDRAMMT41K2G4 – 256 Meg x 4 x 8 banksMT41K1G8 – 128 Meg x 8 x 8 banksMT41K512M16 – 64 Meg x 16 x 8 banksDescriptionDDR3L (1.35V) SDRAM is a low voltage version of the DDR3 (1.5V) SDRAM. Refer to a DDR3 (1.5V) SDRAM data sheet specifications when running in 1.5V com-patible mode.Features•V DD = V DDQ = 1.35V (1.283–1.45V)•Backward compatible to V DD = V DDQ = 1.5V ±0.075V –Supports DDR3L devices to be backward com-patible in 1.5V applications•Differential bidirectional data strobe•8n-bit prefetch architecture•Differential clock inputs (CK, CK#)•8 internal banks•Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals •Programmable CAS (READ) latency (CL)•Programmable posted CAS additive latency (AL)•Programmable CAS (WRITE) latency (CWL)•Fixed burst length (BL) of 8 and burst chop (BC) of 4 (via the mode register set [MRS])•Selectable BC4 or BL8 on-the-fly (OTF)•Self refresh mode •T C of 0°C to +95°C–64ms, 8192-cycle refresh at 0°C to +85°C–32ms at +85°C to +95°C•Self refresh temperature (SRT)•Automatic self refresh (ASR)•Write leveling•Multipurpose register•Output driver calibrationOptions Marking •Configuration– 2 Gig x 42G4– 1 Gig x 81G8–512 Meg x 16512M16•FBGA package (Pb-free) – x4, x8–78-ball (9mm x 13.2mm)SN •FBGA package (Pb-free) – x16–96-ball (9mm x 14mm)HA •Timing – cycle time– 1.25ns @ CL = 11 (DDR3-1600)-125– 1.07ns @ CL = 13 (DDR3-1866)-107•Operating temperature–Commercial (0°C ≤ T C≤ +95°C)None–Industrial (–40°C ≤ T C≤ +95°C)IT •Revision:ATable 1: Key Timing ParametersNote: 1.Backward compatible to 1600, CL = 11 (-125).WRITE OperationWRITE bursts are initiated with a WRITE command. The starting column and bank ad-dresses are provided with the WRITE command, and auto precharge is either enabled ordisabled for that access. If auto precharge is selected, the row being accessed is pre-charged at the end of the WRITE burst. If auto precharge is not selected, the row willremain open for subsequent accesses. After a WRITE command has been issued, theWRITE burst may not be interrupted. For the generic WRITE commands used in Fig-ure 82 (page 163) through Figure 90 (page 168), auto precharge is disabled.During WRITE bursts, the first valid data-in element is registered on a rising edge ofDQS following the WRITE latency (WL) clocks later and subsequent data elements willbe registered on successive edges of DQS. WRITE latency (WL) is defined as the sum ofposted CAS additive latency (AL) and CAS WRITE latency (CWL): WL = AL + CWL. Thevalues of AL and CWL are programmed in the MR0 and MR2 registers, respectively. Priorto the first valid DQS edge, a full cycle is needed (including a dummy crossover of DQS,DQS#) and specified as the WRITE preamble shown in Figure 82 (page 163). The halfcycle on DQS following the last data-in element is known as the WRITE postamble.The time between the WRITE command and the first valid edge of DQS is WL clocks±t DQSS. Figure 83 (page 164) through Figure 90 (page 168) show the nominal casewhere t DQSS = 0ns; however, Figure 82 (page 163) includes t DQSS (MIN) and t DQSS(MAX) cases.Data may be masked from completing a WRITE using data mask. The data mask occurson the DM ball aligned to the WRITE data. If DM is LOW, the WRITE completes normal-ly. If DM is HIGH, that bit of data is masked.Upon completion of a burst, assuming no other commands have been initiated, the DQwill remain High-Z, and any additional input data will be ignored.Data for any WRITE burst may be concatenated with a subsequent WRITE command toprovide a continuous flow of input data. The new WRITE command can be t CCD clocksfollowing the previous WRITE command. The first data element from the new burst isapplied after the last element of a completed burst. Figure 83 (page 164) and Figure 84(page 164) show concatenated bursts. An example of nonconsecutive WRITEs is shownin Figure 85 (page 165).Data for any WRITE burst may be followed by a subsequent READ command after t WTRhas been met (see Figure 86 (page 165), Figure 87 (page 166), and Figure 88(page 167)).Data for any WRITE burst may be followed by a subsequent PRECHARGE command,providing t WR has been met, as shown in Figure 89 (page 168) and Figure 90(page 168).Both t WTR and t WR starting time may vary, depending on the mode register settings(fixed BC4, BL8 versus OTF).Figure 80: t WPRE TimingDQS - DQS#tt CKCK#。
HPMLDL系列服务器
HPMLDL系列服务器hpML系列服务器HP ProLiant ML110G7(C8R00A)参数规格差不多参数产品类型工作组级产品类别塔式产品结构4U处理器CPU类型奔腾双核CPU型号奔腾双核G860CPU频率3GHzHP ProLiant ML330 G6(600911-AA1)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强5600CPU型号Xeon E5620CPU频率 2.4GHz智能加速主2.666GHz频标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存12MB总线规格QPI 5.86GT/sCPU核心四核HP ProLiant ML330 G6(B9D22A)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强5600 CPU型号Xeon E5606CPU频率 2.13GHz标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存8MB总线规格QPI 4.8GT/sHP ProLiant ML330 G6(600911-AA1)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强5600CPU型号Xeon E5620CPU频率 2.4GHz智能加速主2.666GHz频标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存12MB总线规格QPI 5.86GT/sCPU核心四核HP ProLiant ML350 G6(638180-AA1)参数规格差不多参数产品类别塔式产品结构5U处理器CPU类型Intel 至强5600CPU型号Xeon E5606CPU频率 2.13GHz标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存8MB总线规格QPI 4.8GT/sCPU核心四核CPU线程四线程数主板HP ProLiant ML350 G6(600431-AA5)参数规格差不多参数产品类别塔式产品结构5U处理器CPU类型Intel 至强5600CPU型号Xeon E5620CPU频率 2.4GHz智能加速主2.666GHz频标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存12MB总线规格QPI 5.86GT/sCPU核心四核CPU线程八线程数HP ProLiant ML350 G6(594869-AA1)参数规格差不多参数产品类别塔式产品结构5U处理器CPU类型Intel 至强5600CPU型号Xeon E5620CPU频率 2.4GHz智能加速主2.666GHz频标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存12MB总线规格QPI 5.86GT/sCPU核心四核CPU线程八线程数HP ProLiant ML310e Gen8(686146-AA5)参数规格差不多参数产品类型企业级产品类别塔式产品结构4U处理器CPU类型Intel 至强E3-1200 v2 CPU型号Xeon E3-1220 v2CPU频率 3.1GHz标配CPU1颗数量最大CPU4颗数量制程工艺22nm三级缓存8MB总线规格DMI 5GT/sHP ProLiant ML310e Gen8(686147-AA5)参数规格差不多参数产品类型企业级产品类别塔式产品结构4U处理器CPU类型Intel 至强E3-1200 v2 CPU型号Xeon E3-1240 v2CPU频率 3.4GHz智能加速主3.8GHz频标配CPU1颗数量最大CPU4颗数量制程工艺22nm三级缓存8MBHP ProLiant ML350e Gen8(C3Q10A)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2400 CPU型号Xeon E5-2403CPU频率 1.8GHz标配CPU1颗数量最大CPU4颗数量制程工艺32nm三级缓存10MB总线规格QPI 6.4GT/sHP ProLiant ML350e Gen8(C3Q08A)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2400 CPU型号Xeon E5-2407CPU频率 2.2GHz标配CPU1颗数量最大CPU4颗数量制程工艺32nm三级缓存10MB总线规格QPI 6.4GT/sHP ProLiant ML350e Gen8(C3Q09A)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2400 CPU型号Xeon E5-2420CPU频率 1.9GHz标配CPU1颗数量最大CPU4颗数量制程工艺32nm三级缓存15MB总线规格QPI 6.4GT/sHP ProLiant ML350e Gen8(C3F91A)参数规格差不多参数产品类型企业级产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2400 CPU型号Xeon E5-2430CPU频率 2.2GHz标配CPU1颗数量最大CPU4颗数量制程工艺32nm三级缓存15MB总线规格QPI 6.4GT/sHP ProLiant ML350p Gen8(646675-AA1)参数规格差不多参数产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2600 CPU型号Xeon E5-2609CPU频率 2.4GHz标配CPU1颗数量最大CPU2颗数量制程工艺32nm三级缓存10MB总线规格QPI 6.4GT/sHP ProLiant ML350p Gen8(668271-AA5)参数规格差不多参数产品类别塔式产品结构5U处理器CPU类型Intel 至强E5-2600 CPU型号Xeon E5-2620CPU频率2GHz智能加速主2.5GHz频标配CPU1颗数量最大CPU2颗数量制程工艺32nm。
MT8KTF51264HZ-1G6E1
1.35V DDR3L SDRAM SODIMMMT8KTF12864HZ – 1GB MT8KTF25664HZ – 2GB MT8KTF51264HZ – 4GB Features•DDR3L functionality and operations supported as defined in the component data sheet•204-pin, small-outline dual in-line memory module (SODIMM)•Fast data transfer rates: PC3-14900, PC3-12800, or PC3-10600•1GB (128 Meg x 64), 2GB (256 Meg x 64), 4GB (512Meg x 64)•V DD = 1.35V (1.283–1.45V)•V DD = 1.5V (1.425–1.575V)•Backward compatible with standard 1.5V (±0.075V)DDR3 systems •V DDSPD = 3.0–3.6V•Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals •Single rank•Fixed burst chop (BC) of 4 and burst length (BL) of 8via the mode register set (MRS)•On-board I 2C serial presence-detect (SPD) EEPROM •Gold edge contacts •Halogen-free •Fly-by topology•Terminated control, command, and address bus Figure 1: 204-Pin SODIMM (MO-268 R/C B2, B4)Module height: 30mm (1.181in)OptionsMarking•Operating temperature–Commercial (0°C ≤ T A ≤ +70°C)None •Package–204-pin DIMM (halogen-free)Z •Frequency/CAS latency– 1.07ns @ CL = 13 (DDR3-1866)-1G9– 1.25ns @ CL = 11 (DDR3-1600)-1G6– 1.5ns @ CL = 9 (DDR3-1333)-1G4Table 1: Key Timing ParametersTable 2: AddressingTable 3: Part Numbers and Timing Parameters – 1GB Modules1Table 4: Part Numbers and Timing Parameters – 2GB Modules1Table 5: Part Numbers and Timing Parameters – 4GB Modules1Notes: 1.The data sheet for the base device can be found on Micron’s web site.2.All part numbers end with a two-place code (not shown) that designates component and PCB revisions.Consult factory for current revision codes. Example: MT8KSF51264HZ-1G9P1.Pin AssignmentsTable 6: Pin AssignmentsNotes: 1.Pin 78 is NF for 1GB and 2GB; A15 for 4GB.2.Pin 80 is NF for 1GB; A14 for 2GB and 4GB.Pin DescriptionsThe pin description table below is a comprehensive list of all possible pins for all DDR3modules. All pins listed may not be supported on this module. See Pin Assignments forinformation specific to this module.Table 7: Pin DescriptionsTable 7: Pin Descriptions (Continued)DQ MapsTable 8: Component-to-Module DQ Map, R/C B2 (PCB 1092)Table 9: Component-to-Module DQ Map, R/C B4 (PCB 1348)Functional Block Diagram Figure 2: Functional Block DiagramS0#A[15/14/13:0]RAS#WE#CKE0A[15/14/13:0]: DDR3 SDRAMWE#: DDR3 SDRAMCKE0: DDR3 SDRAMRESET#: DDR3 SDRAMCK0CK0#CK1CK1#V REFCAV SSV DDControl, command,and address terminationV DDSPDV TTV REFDQClock, control, command, and address line terminations:TTV DDNote: 1.The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistorthat is tied to ground. It is used for the calibration of the component’s ODT and outputdriver.1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMMFunctional Block DiagramGeneral DescriptionDDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-ules use DDR architecture to achieve high-speed operation. DDR3 architecture is essen-tially an 8n-prefetch architecture with an interface designed to transfer two data wordsper clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM mod-ule effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the inter-nal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfersat the I/O pins.DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CKand CK# to capture commands, addresses, and control signals. Differential clocks anddata strobes ensure exceptional noise immunity for these signals and provide precisecrossing points to capture input signals.Fly-By TopologyDDR3 modules use faster clock speeds than earlier DDR technologies, making signalquality more important than ever. For improved signal quality, the clock, control, com-mand, and address buses have been routed in a fly-by topology, where each clock, con-trol, command, and address pin on each DRAM is connected to a single trace and ter-minated (rather than a tree structure, where the termination is off the module near theconnector). Inherent to fly-by topology, the timing skew between the clock and DQS sig-nals can be easily accounted for by using the write-leveling feature of DDR3.Serial Presence-Detect EEPROM OperationDDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a256-byte EEPROM. The first 128 bytes are programmed by Micron to comply withJEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAMModules." These bytes identify module-specific timing parameters, configuration infor-mation, and physical attributes. The remaining 128 bytes of storage are available for useby the customer. System READ/WRITE operations between the master (system logic)and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, per-manently disabling hardware write protection. For further information refer to Microntechnical note TN-04-42, "Memory Module Serial Presence-Detect."Electrical SpecificationsStresses greater than those listed may cause permanent damage to the module. This is astress rating only, and functional operation of the module at these or any other condi-tions outside those indicated in each device's data sheet is not implied. Exposure to ab-solute maximum rating conditions for extended periods may adversely affect reliability. Table 10: Absolute Maximum RatingsTable 11: Operating ConditionsNotes: 1.Module is backward-compatible with 1.5V operation. Refer to device specification fordetails and operation guidance.2.V TT termination voltage in excess of the stated limit will adversely affect the commandand address signals’ voltage margin and will reduce timing margins.3.T A and T C are simultaneous requirements.4.For further information, refer to technical note TN-00-08: “Thermal Applications,”available on Micron’s web site.5.The refresh rate is required to double when 85°C < T C≤ 95°C.DRAM Operating ConditionsRecommended AC operating conditions are given in the DDR3 component data sheets.Component specifications are available at . Module speed grades correlatewith component speed grades, as shown below.Table 12: Module and Component Speed GradesDesign ConsiderationsSimulationsMicron memory modules are designed to optimize signal integrity through carefully de-signed terminations, controlled board impedances, routing topologies, trace lengthmatching, and decoupling. However, good signal integrity starts at the system level.Micron encourages designers to simulate the signal characteristics of the system'smemory bus to ensure adequate signal integrity of the entire memory system.PowerOperating voltages are specified at the DRAM, not at the edge connector of the module.Designers must account for any system voltage drops at anticipated power levels to en-sure the required supply voltage is maintained.I DD SpecificationsTable 13: DDR3 I DD Specifications and Conditions – 1GB (Die Revision J)Values are for the MT41K128M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 1GbTable 14: DDR3 I DD Specifications and Conditions – 2GB (Die Revision K)Values are for the MT41K256M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 2GbTable 15: DDR3 I DD Specifications and Conditions – 4GB (Die Revision E)Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4GbTable 16: DDR3 I DD Specifications and Conditions – 4GB (Die Revision N)Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4GbTable 17: DDR3 I DD Specifications and Conditions – 4GB (Die Revision P)Values are for the MT41K512M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 4GbSerial Presence-Detect EEPROMFor the latest SPD data, refer to Micron's SPD page: /spd .Table 18: Serial Presence-Detect EEPROM DC Operating ConditionsTable 19: Serial Presence-Detect EEPROM AC Operating ConditionsNotes:1.Guaranteed by design and characterization, not necessarily tested.2.To avoid spurious start and stop conditions, a minimum delay is placed between the fall-ing edge of SCL and the falling or rising edge of SDA.3.For a restart condition, or following a WRITE cycle.1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMMSerial Presence-Detect EEPROMModule DimensionsFigure 3: 204-Pin DDR3 SODIMM3.8 (0.150)1.8 (0.071)(2X)2.0 (0.079) RFront viewTYP45° 4XNotes:1.All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.2.The dimensional diagram is for reference only.8000 S. Federal Way, P .O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000/products/support Sales inquiries: 800-932-4992Micron and the Micron logo are trademarks of Micron Technology, Inc.All other trademarks are the property of their respective owners.This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.Although considered final, these specifications are subject to change, as further product development and data characterization some-times occur.1GB, 2GB, 4GB (x64, SR) 204-Pin DDR3L SODIMMModule DimensionsMouser ElectronicsAuthorized DistributorClick to View Pricing, Inventory, Delivery & Lifecycle Information:M icron Technology:MT8KTF25664HZ-1G6K1MT8KTF51264HZ-1G6P1MT8KTF51264HZ-1G9P1MT8KTF51264HZ-1G6N1。
MEMORY存储芯片N25Q512A13GSF40中文规格书
Output Electrical Characteristics and Operating Conditions Table 18: Differential AC Output ParametersNote: 1.The typical value of V OX(AC) is expected to be about 0.5 × V DDQ of the transmitting de-vice and V OX(AC) is expected to track variations in V DDQ . V OX(AC) indicates the voltage atwhich differential output signals must cross.Figure 15: Differential Output Signal LevelsV OXV SSQV DDQTable 19: Output DC Current DriveNotes: 1.For I OH(DC); V DDQ = 1.7V, V OUT = 1,420mV. (V OUT - V DDQ )/I OH must be less than 21˖ for val-ues of V OUT between V DDQ and V DDQ - 280mV.2.For I OL(DC); V DDQ = 1.7V, V OUT = 280mV. V OUT /I OL must be less than 21˖ for values of V OUT between 0V and 280mV.3.The DC value of V REF applied to the receiving device is set to V TT .4.The values of I OH(DC) and I OL(DC) are based on the conditions given in Notes 1 and 2. They are used to test device drive current capability to ensure V IH,min plus a noise margin and V IL,max minus a noise margin are delivered to an SSTL_18 receiver. The actual current val-ues are derived by shifting the desired driver operating point (see output IV curves)along a 21˖ load line to define a convenient driver current for measurement.2Gb: x4, x8, x16 DDR2 SDRAM Output Electrical Characteristics and Operating ConditionsExtended Mode Register (EMR)The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, output drive strength, on-die termination (ODT), posted AL, off-chip driver impedance calibration (OCD), DQS#enable/disable, RDQS/RDQS# enable/disable, and output disable/enable. These func-tions are controlled via the bits shown in Figure 38. The EMR is programmed via the LM command and will retain the stored information until it is programmed again or the de-vice loses power. Reprogramming the EMR will not alter the contents of the memory ar-ray, provided it is performed correctly.The EMR must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time t MRD before initiating any subsequent opera-tion. Violating either of these requirements could result in an unspecified operation.Figure 38: EMR Definition21Notes: 1.E16 (BA2) is only applicable for densities ุ1Gb, reserved for future use, and must be pro-grammed to 0.2.Mode bits (E n ) with corresponding address balls (A n ) greater than E12 (A12) are re-served for future use and must be programmed to 0.3.Not all listed AL options are supported in any individual speed grade.4.As detailed in the Initialization section notes, during initialization of the OCD operation,all three bits must be set to 1 for the OCD default state, then set to 0 before initializa-tion is finished.2Gb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR)Table 44: Truth Table – CKENotes: 1.CKE (n ) is the logic state of CKE at clock edge n ; CKE (n - 1) was the state of CKE at theprevious clock edge.2.Current state is the state of the DDR2 SDRAM immediately prior to clock edge n .mand (n ) is the command registered at clock edge n , and action (n ) is a result of command (n ).4.The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh (see ODT Timing (page 129) for more details and spe-cific restrictions).5.Power-down modes do not perform any REFRESH operations. The duration of power-down mode is therefore limited by the refresh requirements.6.“X” means “Don’t Care” (including floating around V REF ) in self refresh and power-down. However, ODT must be driven high or low in power-down if the ODT function is enabled via EMR.7.All states and sequences not shown are illegal or reserved unless explicitly described elsewhere in this document.8.Valid commands for power-down entry and exit are NOP and DESELECT only.9.On self refresh exit, DESELECT or NOP commands must be issued on every clock edge oc-curring during the t XSNR period. READ commands may be issued only after t XSRD (200clocks) is satisfied.10.Valid commands for self refresh exit are NOP and DESELECT only.11.Power-down and self refresh can not be entered while READ or WRITE operations,LOAD MODE operations, or PRECHARGE operations are in progress. See SELF REFRESH (page 117) and SELF REFRESH (page 78) for a list of detailed restrictions.12.Minimum CKE high time is t CKE = 3 × t CK. Minimum CKE LOW time is t CKE = 3 × t CK.This requires a minimum of 3 clock cycles of registration.13.Self refresh mode can only be entered from the all banks idle state.14.Must be a legal command, as defined in Table 37 (page 72).2Gb: x4, x8, x16 DDR2 SDRAM Power-Down Mode。
集成电路元件查询表
4 P1.3
14 (T0)P3.4
24 P2.3(A11)
34 P0.5(AD5)
5 P1.4
15 (T1)P3.5
25 P2.4(A12) 35 P0.4(AD4)
6 P1.5
16 (-WR)P3.6 26 P2.5(A13) 36 P0.3(AD3)
7 P1.6
17 (-RD)P3.7
27 P2.6(A14)
┌┴─┴─┴─┴─┴─┴─┴─┴─┴─┴┐
│20 19 18 17 16 15 14 13 12 11│
│)
UPD424256
Hale Waihona Puke ││1 2 3 4 5 6 7 8 9 10│
└┬─┬─┬─┬─┬─┬─┬─┬─┬─┬┘
I/O1 I/O2–WE–RAS NC A0 A1 A2 A3 VCC
X4 快速页模式 DRAM\n 同上
SNI 的串行网 1 COL
络接口
2 RXD
│
│ 1 2 3 4 5 6 7 8│
└┬─┬─┬─┬─┬─┬─┬─┬┘
IA IA OA 3SC OC IC IC GND
11 (TXD)P3.1 21 P2.0(A8)
31 -EA/VPP
编号
名称
AT89S52 9.
ATMEG16A 10.
CA3096E
11.
12. CA3140
集成电路元件查询表 No2
-CS
5 A3
12
VSS
19
A10
6 A2
13
I/O4
20
-OE
7 A1
14
I/O5
21
-WE
多通道光电耦合器与光电
JE第章DDRSDRAM引脚描述
Input
Bank组输入:BG0-BG1可以选择当前的ACT、RD、WRT或是PRE命令是对哪一个Bank组进行操作。在MRS命令中,BG0也参与模式寄存器的选择。在x4、x8系统中,有BG0与BG1,而x16系统中,仅有BG0。
A0-A17
Input
地址总线:在ACT命令中作为行地址,在读写命令中作为列地址,从而可定位到存储阵列中的确定位置。(A10/AP, A12/BC_n, RAS_n/A16, CAS_n/A15 与 WE_n/A14可作为额外的地址总线使用。在MRS命令中,地址总线还作为操作码使用,即写入模式寄存器的值。A17仅在x4系统中可用。
A10/AP
Input
自动刷新:此位可控制在完成读写操作好是否进行自动刷新操作,高电平为开启自动刷新,低电平为关闭自动刷新。在PRE命令中,A10为还可作为是否进行全bank操作的开关。如果仅有一个bank进行刷新,则由bank地址来确定哪个bank来进行操作。
A12/BC_n
Input
Burst选择:在选择On-The-Fly时,此位作为Burst长度的选择信号。具体细节参考命令真值表。
TDQS_t,TDQS_c
Output
终端数据选通:TDQS_t\TDQS_c仅在x8系统中应用。当MR1寄存器中的A11为高电平时,DRAM就会使能相似终端阻抗(same termination resistance)功能,同时TDQS_c与TDQS_t将会应用与DQS_t\DQS_c。当MR1寄存器中的A11为低电平时,DM\DBI\TDQS将会作为数据掩码或数据总线翻转功能使用,且A11、A12、A10与TDQS_c都不会使用。在x4与x16 DRAM中TDQS必须是禁止的,也就是MR1寄存器中的A11为永远为低电平。
MMSZ4xxxT1G系列和SZMMSZ4xxxT1G系列零点电阻电源器件的商品说明书
MMSZ4686T1G MMSZ4686T1G.MMSZ4xxxT1G Series, SZMMSZ4xxxT1G Series Zener Voltage Regulators 500 mW, Low I ZT SOD−123 Surface MountThree complete series of Zener diodes are offered in the convenient, surface mount plastic SOD−123 package. These devices provide a convenient alternative to the leadless 34−package style.Features•500 mW Rating on FR−4 or FR−5 Board•Wide Zener Reverse V oltage Range − 1.8 V to 43 V•Low Reverse Current (I ZT) − 50 m A•Package Designed for Optimal Automated Board Assembly •Small Package Size for High Density Applications•ESD Rating of Class 3 (>16 kV) per Human Body Model•SZ Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q101 Qualified and PPAP Capable•These Devices are Pb−Free and are RoHS Compliant*Mechanical Characteristics:CASE:V oid-free, transfer-molded, thermosetting plastic case FINISH:Corrosion resistant finish, easily solderableMAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 SecondsPOLARITY:Cathode indicated by polarity band FLAMMABILITY RATING:UL 94 V−0MAXIMUM RATINGSRating Symbol Max Units Total Power Dissipation on FR−5 Board,(Note 1) @ T L = 75°CDerated above 75°C P D5006.7mWmW/°CThermal Resistance, (Note 2) Junction−to−Ambient R q JA340°C/WThermal Resistance, (Note 2) Junction−to−Lead R q JL150°C/WJunction and Storage Temperature Range T J, T stg−55 to+150°CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.1.FR−5 = 3.5 X 1.5 inches, using the minimum recommended footprint.2.Thermal Resistance measurement obtained via infrared Scan Method.*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.Cathode AnodeSee specific marking information in the device marking column of the Electrical Characteristics table on page 3 of this data sheet.DEVICE MARKING INFORMATIONSOD−123CASE 425STYLE 1Device Package Shipping†ORDERING INFORMATIONMARKING DIAGRAM†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.MMSZ4xxxT1G SOD−123(Pb−Free)3,000 /Tape & ReelMMSZ4xxxT3G SOD−123(Pb−Free)10,000 /Tape & Reel xx= Device Code (Refer to page 3)M= Date CodeG= Pb−Free Package(Note: Microdot may be in either location)1SZMMSZ4xxxT1G SOD−123(Pb−Free)3,000 /Tape & ReelSZMMSZ4xxxT3G SOD−123(Pb−Free)10,000 /Tape & ReelELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted, V F = 0.9 V Max. @ I F = 10 mA)Symbol ParameterV Z Reverse Zener Voltage @ I ZTI ZT Reverse CurrentI R Reverse Leakage Current @ V RVR Reverse VoltageI F Forward CurrentV F Forward Voltage @ I FProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.ELECTRICAL CHARACTERISTICS (T A = 25°C unless otherwise noted, V F = 0.9 V Max. @ I F = 10 mA)Device*DeviceMarkingZener Voltage (Note 3)Leakage CurrentV Z (Volts)@ I ZT I R @ V RMin Nom Max m A m A VoltsMMSZ4678T1G CC 1.71 1.8 1.89507.51 MMSZ4679T1G CD 1.90 2.0 2.105051 MMSZ4680T1G CE 2.09 2.2 2.315041 MMSZ4681T1G CF 2.28 2.4 2.525021 MMSZ4682T1G CH 2.565 2.7 2.8355011 MMSZ4683T1G CJ 2.85 3.0 3.15500.81 MMSZ4684T1G CK 3.13 3.3 3.47507.5 1.5 MMSZ4685T1G CM 3.42 3.6 3.78507.52 MMSZ4686T1G CN 3.70 3.9 4.105052 MMSZ4687T1G CP 4.09 4.3 4.525042 SZMMSZ4687T1G CG6 4.09 4.3 4.525042 MMSZ4688T1G CT 4.47 4.7 4.9450103 MMSZ4689T1G CU 4.85 5.1 5.3650103 MMSZ4690T1G/T3G CV 5.32 5.6 5.8850104 MMSZ4691T1G CA 5.89 6.2 6.5150105 MMSZ4692T1G CX 6.46 6.87.145010 5.1 MMSZ4693T1G CY7.137.57.885010 5.7 MMSZ4694T1G CZ7.798.28.61501 6.2 MMSZ4695T1G DC8.278.79.14501 6.6 MMSZ4696T1G DD8.659.19.56501 6.9 MMSZ4697T1G DE9.501010.505017.6 MMSZ4698T1G DF10.451111.55500.058.4 MMSZ4699T1G DH11.401212.60500.059.1 MMSZ4700T1G DJ12.351313.65500.059.8 MMSZ4701T1G DK13.301414.70500.0510.6 MMSZ4702T1G DM14.251515.75500.0511.4 MMSZ4703T1G†DN15.201616.80500.0512.1 MMSZ4704T1G DP16.151717.85500.0512.9 MMSZ4705T1G DT17.101818.90500.0513.6 MMSZ4706T1G DU18.051919.95500.0514.4 MMSZ4707T1G DV19.002021.00500.0115.2 MMSZ4708T1G DA20.902223.10500.0116.7 MMSZ4709T1G DX22.802425.20500.0118.2 MMSZ4710T1G DY23.752526.25500.0119.0 MMSZ4711T1G†EA25.652728.35500.0120.4 MMSZ4712T1G EC26.602829.40500.0121.2 MMSZ4713T1G ED28.503031.50500.0122.8 MMSZ4714T1G EE31.353334.65500.0125.0 MMSZ4715T1G EF34.203637.80500.0127.3 MMSZ4716T1G EH37.053940.95500.0129.6 MMSZ4717T1G EJ40.854345.15500.0132.6 3.Nominal Zener voltage is measured with the device junction in thermal equilibrium at T L = 30°C ±1°C.*Include SZ-prefix devices where applicable.†MMSZ4703 and MMSZ4711 Not Available in 10,000/Tape & ReelTYPICAL CHARACTERISTICSV Z , T E M P E R A T U R E C O E F F I C I E N T (m V /C )°θV Z , NOMINAL ZENER VOLTAGE (V)Figure 1. Temperature Coefficients (Temperature Range −55°C to +150°C)V Z , T E M P E R A T U R E C O E F F I C I E N T (m V /C )°θ100101V Z , NOMINAL ZENER VOLTAGE (V)Figure 2. Temperature Coefficients (Temperature Range −55°C to +150°C)1.21.00.80.60.40.20T, TEMPERATURE (5C)Figure 3. Steady State Power Derating P p k, P E A K S U R G E P O W E R (W A T T S )PW, PULSE WIDTH (ms)Figure 4. Maximum Nonrepetitive Surge PowerP D , P O W E R D I S S I P A T I O N (W A T T S )V Z , NOMINAL ZENER VOLTAGEFigure 5. Effect of Zener Voltage onZener ImpedanceZ Z T , D Y N A M I C I M P E D A N C E ()ΩTYPICAL CHARACTERISTICSC , C A P A C I T A N C E (p F )V Z , NOMINAL ZENER VOLTAGE (V)Figure 6. Typical Capacitance 1000100101V Z , ZENER VOLTAGE (V)1001010.10.01I Z , Z EN E R C U R R E N T (m A )V Z , ZENER VOLTAGE (V)1001010.10.01I R , L E A K A G E C U R R E N T (A )μV Z , NOMINAL ZENER VOLTAGE (V)Figure 7. Typical Leakage Current10001001010.10.010.0010.00010.00001I Z , Z E N E R C U R R E N T (m A )Figure 8. Zener Voltage versus Zener Current(V Z Up to 12 V)Figure 9. Zener Voltage versus Zener Current(12 V to 91 V)SOD−123CASE 425−04ISSUE GDATE 07 OCT 2009SCALE 5:1NOTES:1.DIMENSIONING AND TOLERANCING PER ANSIY14.5M, 1982.2.CONTROLLING DIMENSION: INCH.DIM MIN NOM MAXMILLIMETERSINCHESA0.94 1.17 1.350.037A10.000.050.100.000b0.510.610.710.020c1.600.150.055D 1.40 1.80E 2.54 2.69 2.840.100---3.680.140L0.253.860.0100.0460.0020.0240.0630.1060.1450.0530.0040.0280.0710.1120.152MIN NOM MAX3.56H E---------0.006------------GENERICMARKING DIAGRAM**For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SOLDERING FOOTPRINT**This information is generic. Please refer to device datasheet for actual part marking. Pb−Free indicator, “G” ormicrodot “ G”, may or may not be present.XXX= Specific Device CodeM= Date CodeG= Pb−Free Package1STYLE 1:PIN 1. CATHODE2. ANODE0.910.036ǒmminchesǓSCALE 10:1------q001010°°°°(Note: Microdot may be in either location) MECHANICAL CASE OUTLINEPACKAGE DIMENSIONSON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor theON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.PUBLICATION ORDERING INFORMATIONTECHNICAL SUPPORTNorth American Technical Support:Voice Mail: 1 800−282−9855 Toll Free USA/Canada Phone: 011 421 33 790 2910LITERATURE FULFILLMENT :Email Requests to:*******************ON Semiconductor Website: Europe, Middle East and Africa Technical Support:Phone: 00421 33 790 2910For additional information, please contact your local Sales RepresentativeMMSZ4686T1G MMSZ4686T1G.。
莫贾V2416A系列迷你型无风扇、振动防护计算机产品介绍说明书
V2416A SeriesCompact,fanless,vibration-proof computers for rolling stock applicationsFeatures and Benefits•Intel Celeron/Core i7processor•Two hot-swappable2.5-inch HDD or SSD storage expansion trays•Dual independent DVI-I displays•2Gigabit Ethernet ports with M12X-coded connectors•2CFast sockets for OS backup•M12A-coded power connector•Compliant with EN50121-4•Complies with all EN50155mandatory test items1•IEC61373certified for shock and vibration resistance•Ready-to-run Debian7,Windows Embedded Standard7,and Windows10Embedded IoT Enterprise2016LTSB platforms•-40to70°C wide-temperature models available•Supports SNMP-based system configuration,control,and monitoring(Windows only)CertificationsIntroductionThe V2416A Series embedded computers are based on the Intel3rd Gen processor and feature4RS-232/422/485serial ports,dual LAN ports,and 3USB2.0hosts.In addition,the V2416A computers provide dual DVI-I outputs and comply with the mandatory test items of the EN50155 standard,making them suitable for a variety of industrial applications.The CFast socket,SATA connectors,and USB sockets provide the V2416A computers with the reliability needed for industrial applications that require data buffering and storage expansion.Most importantly,the V2416A computers come with2hot-swappable storage trays for inserting additional storage media,such as hard disk or solid-state drives,and support hot swapping for convenient,fast,and easy storage replacement. Each storage tray has its own LED to indicate whether or not a storage module is plugged in.The V2416A Series computers come preinstalled with a choice of Linux Debian7or Windows Embedded Standard7to provide programmers with a familiar environment in which to develop sophisticated,bug-free application software at a low cost.1.This product is suitable for rolling stock railway applications,as defined by the EN50155standard.For a more detailed statement,click here:/doc/specs/EN_50155_Compliance.pdfAppearanceFront View Rear ViewSpecificationsComputerCPU V2416A-C2Series:Intel®Celeron®Processor1047UE(2M cache,1.40GHz)V2416A-C7Series:Intel®Core™i7-3517UE Processor(4M cache,up to2.80GHz) System Chipset Mobile Intel®HM65Express ChipsetGraphics Controller Intel®HD Graphics4000(integrated)System Memory Pre-installed4GB DDR3System Memory Slot SODIMM DDR3/DDR3L slot x1Supported OS Linux Debian7Windows Embedded Standard7(WS7E)32-bitWindows Embedded Standard7(WS7E)64-bitStorage Slot CFast slot x2Computer InterfaceEthernet Ports Auto-sensing10/100/1000Mbps ports(M12X-coded)x2Serial Ports RS-232/422/485ports x4,software selectable(DB9male)USB2.0USB2.0hosts x1,M12D-coded connectorUSB2.0hosts x2,type-A connectorsAudio Input/Output Line in x1,Line out x1,M12D-codedDigital Input DIs x6Digital Output DOs x2Video Input DVI-I x2,29-pin DVI-D connectors(female)Digital InputsIsolation3k VDCConnector Screw-fastened Euroblock terminalDry Contact On:short to GNDOff:openI/O Mode DISensor Type Dry contactWet Contact(NPN or PNP)Wet Contact(DI to COM)On:10to30VDCOff:0to3VDCDigital OutputsConnector Screw-fastened Euroblock terminalCurrent Rating200mA per channelI/O Type SinkVoltage24to40VDCLED IndicatorsSystem Power x1Storage x1Hot-swappable2LAN2per port(10/100/1000Mbps)Serial2per port(Tx,Rx)Serial InterfaceBaudrate50bps to921.6kbpsFlow Control RTS/CTS,XON/XOFF,ADDC®(automatic data direction control)for RS-485,RTSToggle(RS-232only)Isolation N/AParity None,Even,Odd,Space,MarkData Bits5,6,7,8Stop Bits1,1.5,2Serial SignalsRS-232TxD,RxD,RTS,CTS,DTR,DSR,DCD,GNDRS-422Tx+,Tx-,Rx+,Rx-,GNDRS-485-2w Data+,Data-,GNDRS-485-4w Tx+,Tx-,Rx+,Rx-,GNDPower ParametersInput Voltage12to48VDCPower Connector M12A-coded male connectorPower Consumption(Max.) 3.3A@12VDC0.82A@48VDCPower Consumption40W(max.)Physical CharacteristicsHousing AluminumIP Rating IP30Dimensions(with ears)250x86x154mm(9.84x3.38x6.06in)Dimensions(without ears)275x92x154mm(10.83x3.62x6.06in)Weight4,000g(8.98lb)Installation DIN-rail mounting(optional),Wall mounting(standard) Protection-CT models:PCB conformal coating Environmental LimitsOperating Temperature Standard Models:-25to55°C(-13to131°F)Wide Temp.Models:-40to70°C(-40to158°F) Storage Temperature(package included)-40to85°C(-40to185°F)Ambient Relative Humidity5to95%(non-condensing)Standards and CertificationsEMC EN55032/24EMI CISPR32,FCC Part15B Class AEMS IEC61000-4-2ESD:Contact:6kV;Air:8kVIEC61000-4-3RS:80MHz to1GHz:20V/mIEC61000-4-4EFT:Power:2kV;Signal:2kVIEC61000-4-5Surge:Power:2kVIEC61000-4-6CS:10VIEC61000-4-8PFMFRailway EN50121-4,IEC60571Railway Fire Protection EN45545-2Safety EN60950-1,IEC60950-1Shock IEC60068-2-27,IEC61373,EN50155Vibration IEC60068-2-64,IEC61373,EN50155DeclarationGreen Product RoHS,CRoHS,WEEEMTBFTime332,173hrsStandards Telcordia(Bellcore),GBWarrantyWarranty Period3yearsDetails See /warrantyPackage ContentsDevice1x V2416A Series computerInstallation Kit8x screw,for storage installation2x storage key1x wall-mounting kit8x washer,for HDD/SSDDocumentation1x document and software CD1x quick installation guide1x warranty cardDimensionsOrdering InformationModel Name CPU Memory(Default)OS CFast(CTO)Backup CFast(CTO)Hot-SwappableSSD/HDD Tray(CTO)Operating Temp.ConformalCoatingV2416A-C2Celeron1047UE4GB or optional1(Optional)1(Optional)2(Optional)-25to55°C–V2416A-C2-T Celeron1047UE4GB or optional1(Optional)1(Optional)2(Optional)-40to70°C–V2416A-C2-CT-T Celeron1047UE4GB or optional1(Optional)1(Optional)2(Optional)-40to70°C✓V2416A-C7i7-3517UE4GB or optional1(Optional)1(Optional)2(Optional)-25to55°C–V2416A-C7-T i7-3517UE4GB or optional1(Optional)1(Optional)2(Optional)-40to70°C–V2416A-C7-CT-T i7-3517UE4GB or optional1(Optional)1(Optional)2(Optional)-40to70°C✓V2416A-C2-W7E Celeron1047UE4GB8GB1(Optional)2(Optional)-25to55°C–V2416A-C2-T-W7E Celeron1047UE4GB8GB1(Optional)2(Optional)-40to70°C–V2416A-C7-T-W7E Core i7-3517UE4GB8GB1(Optional)2(Optional)-40to70°C–Accessories(sold separately)Battery KitsRTC Battery Kit Lithium battery with built-in connectorCablesCBL-M12XMM8PRJ45-BK-100-IP67M12-to-RJ45Cat-5E UTP gigabit Ethernet cable,8-pin X-coded male connector,IP67,1mCBL-M12(FF5P)/Open-100IP67A-coded M12-to-5-pin power cable,IP67-rated5-pin female M12connector,1mConnectorsM12A-5PMM-IP685-pin male circular threaded D-coded M12USB connector,IP68M12X-8PMM-IP678-pin male X-coded circular threaded gigabit Ethernet connector,IP67M12A-5P-IP68A-coded screw-in sensor connector,female,IP68,4.05cmM12A-8PMM-IP678-pin male circular threaded A-codes M12connector,IP67-rated(for field-installation)Power AdaptersPWR-24270-DT-S1Power adapter,input voltage90to264VAC,output voltage24V with2.5A DC loadPower CordsPWC-C7AU-2B-183Power cord with Australian(AU)plug,2.5A/250V,1.83mPWC-C7CN-2B-183Power cord with two-prong China(CN)plug,1.83mPWC-C7EU-2B-183Power cord with Continental Europe(EU)plug,2.5A/250V,1.83mPWC-C7UK-2B-183Power cord with United Kingdom(UK)plug,2.5A/250V,1.83mPWC-C7US-2B-183Power cord with United States(US)plug,10A/125V,1.83mAntennasANT-WDB-ANF-0407 2.4/5GHz,omni-directional antenna,4/7dBi,N-type(male)Wall-Mounting KitsV2400Isolated Wall Mount Kit Wall-mounting kit with isolation protection,2wall-mounting brackets,4screwsDIN-Rail Mounting KitsDK-DC50131DIN-rail mounting kit,6screws©Moxa Inc.All rights reserved.Updated Jun12,2019.This document and any portion thereof may not be reproduced or used in any manner whatsoever without the express written permission of Moxa Inc.Product specifications subject to change without notice.Visit our website for the most up-to-date product information.。
AMD加速处理器列表
AMD加速处理器列表AMD Accelerated Processing Unit (APU)前称AMD Fusion,整合CPU和GPU。
目录•1 时程表•2 桌上型平台和笔电平台o 2.1 第一代AMD APU,基于AMD 10h(K10、K12/12h)▪ 2.1.1 Llanoo 2.2 第二代AMD APU,基于AMD Piledriver架构▪ 2.2.1 Trinity▪ 2.2.2 Richlando 2.3 第三代AMD APU,基于AMD Jagaur架构▪ 2.3.1 Kabinio 2.4 第四代AMD APU,基于AMD Steamroller架构▪ 2.4.1 Kaverio 2.5 第六代 AMD APU,基于 AMD Excavator 架构▪ 2.5.1 'Carrizo' (2015, 28 nm)o 2.6 第七代 AMD APU,基于 AMD Excavator 架构▪ 2.6.1 'Bristol Ridge' (2016, 28 nm)o 2.7 'Raven Ridge' (2017)•3 服务器核心o 3.1 Opteron X1100-series 'Kyoto' (28nm)o 3.2 Opteron X2100系列 'Kyoto' (2013, 28 nm)o 3.3 Opteron X3000系列 (2017, 28 nm) [26]•4 低功耗核心o 4.1 基于AMD Bobcat架构▪ 4.1.1 Brazos: 'Desna', 'Ontario', 'Zacate' (2011, 40nm)▪ 4.1.2 Brazos 2.0: 'Ontario', 'Zacate' (2012, 40 nm) ▪ 4.1.3 Brazos-T: 'Hondo' (2012, 40 nm)o 4.2 基于AMD Jagaur架构▪ 4.2.1 Temash▪ 4.2.2 Kabinio 4.3 第五代AMD APU 'Beema', 'Mullins',基于PUMA 核心 (2014, 28 nm)▪ 4.3.1 Mullins▪ 4.3.2 Beemao 4.4 'Carrizo-L' (2015, 28 nm)o 4.5 'Stoney Ridge' (2016,28nm)•5 嵌入式核心o 5.1 G系列▪ 5.1.1 Brazos: 'Ontario' and 'Zacate' (2011, 40 nm) ▪ 5.1.2 'Kabini' (2013, 28 nm)▪ 5.1.3 'Steppe Eagle' (2014, SoC,28nm)▪ 5.1.4 'Crowned Eagle' (2014, SoC,28nm)▪ 5.1.5 I家族: 'Brown Falcon' (2016, SoC,28nm)▪ 5.1.6 J家族: 'Prairie Falcon' (2016, SoC,28nm)▪ 5.1.7 LX家族 (2016, SoC,28nm)o 5.2 R系列▪ 5.2.1 Comal: 'Trinity' (2012, 32 nm)▪ 5.2.2 'Bald Eagle' (2014,28nm)▪ 5.2.3 'Merlin Falcon' (2015, SoC,28nm)•6 另见•7 备注•8 参考资料•9 外部链接时程表代号状态型号制程TDP 核心Radeon coresOntario 已发售C-30, C-50,C-60,C-7040nmbulk9W 1-2 Bobcat 80Zacate 已发售E-240, E-350,E-45040nmbulk18W 1-2 Bobcat 80Llano 已发售A6-3670, A8-3850等32nmSOI35W~100W2-4 K-10/Stars160~400Wichita 原定2012年上半年产品计划被取消28nmbulk~9W 1-2 Bobcat --Krishna 原定2012年上半年产品计划被取消28nmbulk~18W 2-4 Bobcat --Trinity 已发售A10-5800K 等32nmSOI17W~100W2-4Piledrivers128~384Richland 已发售A10-6800K 等32nmSOI17W~100W2-4Piledrivers128~384Kaveri 已发售A10-7850K等28nmSOI15W~95W2-4Steamrollers256~512Kabini 已发售Athlon5350 ,Sempron3850 等28nmSOI9~25W 2-4 Jaguar 128Beema 已发售A6 6410 ,A46310 等28nmSOI15W 2-4 Puma 128Mullins 已发售A10 Micro6700T , 等28nmSOI15W 2-4 Puma 128Carrizo 已发售Athlon X4 835,84528nmSOI 45W~65W2-4Excavator--Bristol Ridge 已出货A10-9700 等28nmSOI35W~65W2-4Excavator256~512桌上型平台和笔电平台第一代AMD APU,基于AMD 10h(K10、K12/12h)第一款Fusion处理器代号为“Swift”,最早将用于代号为“Shrike”笔记型电脑平台。
EM4-DINAV33DXR中文资料(List Unclassifed)中文数据手册「EasyDatasheet - 矽搜」
20(90) A (AV2)
频率
50到60赫兹
接口模块规范
RS422/RS485 (根据要求) Type
连接
地址 协议 数据(双向)
动态(只读) 静态(只写)
数据格式 波特率 隔离
2
AR2950模块
多点 双向(静 和动态变量)
2或4线,最大距离 1200米终止直接
模块上
255,由辅助键盘可选 MODBUS/JBUS
50%
0.1至100.0米
/ 脉冲
12V +辅助24VDC
逻辑状态:
OFF 2V, ON 10V
15mA最大值
1kΩ
1kΩ,亲密接触
100kΩ,开触点
通过光电耦合器方法,
2000 V 数字输入
测量输入,
2000 V 数字输入
电输入.
至5A)
每页最多4个变量 第1页:千瓦时,千乏 第2A:克瓦(T -t -t -t )
输出:2000伏
AQ2940模块
四种工作模式 可选:
完全和部分能源 米(千瓦时及无功电能) 无需使用数字 输入 完全和部分能源 米(千瓦时及无功电能) 按时间周期管理
(t -t -t -t );
总能量米
(千瓦时,千乏)和总 "日间/夜间"气 仪表;
总能量米
(千瓦时,千乏),GAS 和水表;
2
20Hz最大
1级累计.以EN61036 2级累计.以EN61268 Ib: 5A, Imax: 10A 0.1Ib: 500mA, 启动电流:20毫安 联合国:见附表"系列代码" Ib: 20A, Imax: 90A 0.1Ib: 2A, 启动电流:80毫安 联合国:见附表"系列代码"
ULN2004AIDRE4资料
PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package DrawingPins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)ULN2004AID ACTIVE SOIC D 1640Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM ULN2004AIDE4ACTIVE SOIC D 1640Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM ULN2004AIDR ACTIVE SOIC D 162500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM ULN2004AIDRE4ACTIVE SOIC D 162500Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM ULN2004AIN ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type ULN2004AINE4ACTIVE PDIP N 1625Pb-Free (RoHS)CU NIPDAU N /A for Pkg Type ULN2004AINSR ACTIVE SO NS 162000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM ULN2004AINSRE4ACTIVESONS162000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM5-Feb-2007Addendum-Page 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and todiscontinue any product or service without notice. Customers should obtain the latest relevant informationbefore placing orders and should verify that such information is current and complete. All products are soldsubject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extentTI deems necessary to support this warranty. Except where mandated by government requirements, testingof all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsiblefor their products and applications using TI components. To minimize the risks associated with customerproducts and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patentright, copyright, mask work right, or other TI intellectual property right relating to any combination, machine,or process in which TI products or services are used. Information published by TI regarding third-partyproducts or services does not constitute a license from TI to use such products or services or a warranty orendorsement thereof. Use of such information may require a license from a third party under the patents orother intellectual property of the third party, or a license from TI under the patents or other intellectualproperty of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices.Reproduction of this information with alteration is an unfair and deceptive business practice. TI is notresponsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI forthat product or service voids all express and any implied warranties for the associated TI product or serviceand is an unfair and deceptive business practice. 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KL03 芯片系列参考手册说明书
KL03 Sub-Family Reference Manual Supports: MKL03Z8VFG4(R), MKL03Z16VFG4(R), MKL03Z32VFG4(R), MKL03Z32CAF4R, MKL03Z8VFK4(R),MKL03Z16VFK4(R), and MKL03Z32VFK4(R)Document Number: KL03P24M48SF0RMRev 3, June, 2014ContentsSection number Title PageChapter 1About This Document1.1Overview (27)1.1.1Purpose (27)1.1.2Audience (27)1.2Conventions (27)1.2.1Numbering systems (27)1.2.2Typographic notation (28)1.2.3Special terms (28)Chapter 2Introduction2.1KL03 sub-family introduction (29)2.2Module functional categories (29)2.2.1ARM Cortex-M0+ core modules (30)2.2.2System modules (31)2.2.3Memories and memory interfaces (32)2.2.4Clocks (32)2.2.5Analog modules (32)2.2.6Timer modules (33)2.2.7Communication interfaces (33)2.2.8Human-machine interfaces (34)2.3Module to module interconnects (34)2.3.1Interconnection overview (34)2.3.2Analog reference options (35)2.4Orderable part numbers (36)Chapter 3Core Overview3.1ARM Cortex-M0+ core introduction (37)3.1.1Buses, interconnects, and interfaces (37)3.1.2System tick timer (37)3.1.3Debug facilities (37)3.1.4Core privilege levels (38)3.2Nested vectored interrupt controller (NVIC) (38)3.2.1Interrupt priority levels (38)3.2.2Non-maskable interrupt (38)3.2.3Interrupt channel assignments (38)3.3AWIC introduction (41)3.3.1Wake-up sources (41)Chapter 4Memory and Memory Map4.1Flash memory (43)4.1.1Flash memory map (43)4.1.2Flash security (44)4.1.3Flash modes (44)4.1.4Erase all flash contents (44)4.1.5FTFA_FOPT register (44)4.2SRAM (45)4.2.1SRAM sizes (45)4.2.2SRAM ranges (45)4.2.3SRAM retention in low power modes (46)4.3System Register file (46)4.4Memory map (47)4.4.1Introduction (47)4.4.2System memory map (47)4.4.3Flash memory map (48)4.4.4SRAM memory map (48)4.4.5Bit Manipulation Engine (49)4.4.6Peripheral bridge (AIPS-Lite) memory map (49)4.4.7Private Peripheral Bus (PPB) memory map (54)Chapter 5Clock Distribution5.1Introduction (55)5.2Programming model (55)5.3High-level device clocking diagram (55)5.4Clock definitions (56)5.4.1Device clock summary (57)5.5Internal clocking requirements (59)5.5.1Clock divider values after reset (59)5.5.2VLPR mode clocking (60)5.6Clock gating (60)5.7Module clocks (60)5.7.1PMC 1-kHz LPO clock (61)5.7.2COP clocking (62)5.7.3RTC clocking (62)5.7.4RTC_CLKOUT and CLKOUT32K clocking (63)5.7.5LPTMR clocking (63)5.7.6TPM clocking (64)5.7.7LPUART clocking (64)Chapter 6Reset and Boot6.1Introduction (67)6.2Reset (67)6.2.1Power-on reset (POR) (68)6.2.2System reset sources (68)6.2.3MCU resets (71)6.2.4RESET pin (72)6.3Boot (72)6.3.1Boot sources (72)6.3.2FOPT boot options (73)6.3.3Boot sequence (75)Chapter 7Power Management7.1Introduction (77)7.2Clocking modes (77)7.2.1Partial Stop (77)7.2.2Compute Operation (78)7.2.3Peripheral Doze (79)7.2.4Clock gating (79)7.3Power modes (80)7.4Entering and exiting power modes (82)7.5Module operation in low-power modes (82)Chapter 8Security8.1Introduction (87)8.1.1Flash security (87)8.1.2Security interactions with other modules (87)Chapter 9Debug9.1Introduction (89)9.2Debug port pin descriptions (89)9.3SWD status and control registers (90)9.3.1MDM-AP Control Register (91)9.3.2MDM-AP Status Register (92)9.4Debug resets (94)9.5Micro Trace Buffer (MTB) (94)9.6Debug in low-power modes (95)9.7Debug and security (96)Chapter 10Signal Multiplexing and Signal Descriptions10.1Introduction (97)10.2Signal multiplexing integration (97)10.2.1I/O Port control and interrupt module features (98)10.2.2Clock gating (98)10.2.3Signal multiplexing constraints (98)10.3Pinout (98)10.3.1KL03 signal multiplexing and pin assignments (98)10.3.2KL03 pinouts (100)10.4Module Signal Description Tables (101)10.4.1Core modules (101)10.4.2System modules (102)10.4.3Clock modules (102)10.4.4Memories and memory interfaces (103)10.4.5Analog (103)10.4.6Timer Modules (103)10.4.7Communication interfaces (104)10.4.8Human-machine interfaces (HMI) (105)Chapter 11Kinetis ROM Bootloader11.1Introduction (107)11.2Functional Description (108)11.2.1Memory Maps (108)11.2.2The Kinetis Bootloader Configuration Area (BCA) (109)11.2.3Start-up Process (110)11.2.4Clock Configuration (112)11.2.5Bootloader Entry Point (113)11.2.6Bootloader Protocol (114)11.2.7Bootloader Packet Types (117)11.2.8Bootloader Command API (123)11.2.9Bootloader Exit state (135)11.3Peripherals Supported (136)11.3.1I2C Peripheral (136)11.3.2SPI Peripheral (138)11.3.3UART Peripheral (140)11.4Get/SetProperty Command Properties (143)11.4.1Property Definitions (144)11.5Kinetis Bootloader Status Error Codes (145)Chapter 12Port Control and Interrupts (PORT)12.1Chip-specific PORT information (147)12.1.1GPIO instantiation information (147)12.1.2Port control and interrupt summary (148)12.2Introduction (149)12.3Overview (149)12.3.1Features (149)12.3.2Modes of operation (149)12.4External signal description (150)12.5Detailed signal description (150)12.6Memory map and register definition (151)12.6.1Pin Control Register n (PORT x_PCR n) (154)12.6.2Global Pin Control Low Register (PORT x_GPCLR) (156)12.6.3Global Pin Control High Register (PORT x_GPCHR) (157)12.6.4Interrupt Status Flag Register (PORT x_ISFR) (157)12.7Functional description (158)12.7.1Pin control (158)12.7.2Global pin control (159)12.7.3External interrupts (159)Chapter 13General-Purpose Input/Output (GPIO)13.1Chip-specific GPIO information (161)13.2Introduction (161)13.2.1Features (161)13.2.2Modes of operation (162)13.2.3GPIO signal descriptions (162)13.3Memory map and register definition (163)13.3.1Port Data Output Register (GPIO x_PDOR) (164)13.3.2Port Set Output Register (GPIO x_PSOR) (165)13.3.3Port Clear Output Register (GPIO x_PCOR) (165)13.3.4Port Toggle Output Register (GPIO x_PTOR) (166)13.3.5Port Data Input Register (GPIO x_PDIR) (166)13.3.6Port Data Direction Register (GPIO x_PDDR) (167)13.4FGPIO memory map and register definition (167)13.4.1Port Data Output Register (FGPIO x_PDOR) (168)13.4.2Port Set Output Register (FGPIO x_PSOR) (169)13.4.3Port Clear Output Register (FGPIO x_PCOR) (169)13.4.4Port Toggle Output Register (FGPIO x_PTOR) (170)13.4.5Port Data Input Register (FGPIO x_PDIR) (170)13.4.6Port Data Direction Register (FGPIO x_PDDR) (171)13.5Functional description (171)13.5.1General-purpose input (171)13.5.2General-purpose output (171)13.5.3IOPORT (172)Chapter 14System Integration Module (SIM)14.1Chip-specific COP information (173)14.2COP clocks (173)14.3COP watchdog operation (173)14.4Introduction (175)14.4.1Features (175)14.5Memory map and register definition (176)14.5.1System Options Register 1 (SIM_SOPT1) (177)14.5.2System Options Register 2 (SIM_SOPT2) (178)14.5.3System Options Register 4 (SIM_SOPT4) (180)14.5.4System Options Register 5 (SIM_SOPT5) (181)14.5.5System Options Register 7 (SIM_SOPT7) (182)14.5.6System Device Identification Register (SIM_SDID) (184)14.5.7System Clock Gating Control Register 4 (SIM_SCGC4) (186)14.5.8System Clock Gating Control Register 5 (SIM_SCGC5) (187)14.5.9System Clock Gating Control Register 6 (SIM_SCGC6) (189)14.5.10System Clock Divider Register 1 (SIM_CLKDIV1) (190)14.5.11Flash Configuration Register 1 (SIM_FCFG1) (192)14.5.12Flash Configuration Register 2 (SIM_FCFG2) (193)14.5.13Unique Identification Register Mid-High (SIM_UIDMH) (194)14.5.14Unique Identification Register Mid Low (SIM_UIDML) (194)14.5.15Unique Identification Register Low (SIM_UIDL) (195)14.5.16COP Control Register (SIM_COPC) (195)14.5.17Service COP (SIM_SRVCOP) (197)14.6Functional description (197)Chapter 15System Mode Controller (SMC)15.1Chip-specific SMC information (199)15.2Introduction (199)15.3Modes of operation (199)15.4Memory map and register descriptions (201)15.4.1Power Mode Protection register (SMC_PMPROT) (202)15.4.2Power Mode Control register (SMC_PMCTRL) (203)15.4.3Stop Control Register (SMC_STOPCTRL) (204)15.4.4Power Mode Status register (SMC_PMSTAT) (206)15.5Functional description (206)15.5.1Power mode transitions (206)15.5.2Power mode entry/exit sequencing (209)15.5.3Run modes (211)15.5.4Wait modes (212)15.5.5Stop modes (213)15.5.6Debug in low power modes (215)Chapter 16Power Management Controller (PMC)16.1Introduction (217)16.2Features (217)16.3Low-voltage detect (LVD) system (217)16.3.1LVD reset operation (218)16.3.2LVD interrupt operation (218)16.3.3Low-voltage warning (LVW) interrupt operation (218)16.4I/O retention (219)16.5Memory map and register descriptions (219)16.5.1Low Voltage Detect Status And Control 1 register (PMC_LVDSC1) (220)16.5.2Low Voltage Detect Status And Control 2 register (PMC_LVDSC2) (221)16.5.3Regulator Status And Control register (PMC_REGSC) (222)Chapter 17Miscellaneous Control Module (MCM)17.1Introduction (225)17.1.1Features (225)17.2Memory map/register descriptions (225)17.2.1Crossbar Switch (AXBS) Slave Configuration (MCM_PLASC) (226)17.2.2Crossbar Switch (AXBS) Master Configuration (MCM_PLAMC) (226)17.2.3Platform Control Register (MCM_PLACR) (227)17.2.4Compute Operation Control Register (MCM_CPO) (229)Chapter 18Crossbar Switch Lite (AXBS-Lite)18.1Introduction (231)18.1.1Features (231)18.2Memory Map / Register Definition (231)18.3Functional Description (232)18.3.1General operation (232)18.3.2Arbitration (233)18.4Initialization/application information (234)Chapter 19Low-Leakage Wakeup Unit (LLWU)19.1Chip-specific LLWU information (235)19.2Introduction (235)19.2.1Features (235)19.2.2Modes of operation (236)19.2.3Block diagram (237)19.3LLWU signal descriptions (238)19.4Memory map/register definition (238)19.4.1LLWU Pin Enable 1 register (LLWU_PE1) (239)19.4.2LLWU Pin Enable 2 register (LLWU_PE2) (240)19.4.3LLWU Module Enable register (LLWU_ME) (241)19.4.4LLWU Flag 1 register (LLWU_F1) (243)19.4.5LLWU Flag 3 register (LLWU_F3) (244)19.4.6LLWU Pin Filter 1 register (LLWU_FILT1) (246)19.4.7LLWU Pin Filter 2 register (LLWU_FILT2) (247)19.5Functional description (248)19.5.1VLLS modes (249)19.5.2Initialization (249)Chapter 20Peripheral Bridge (AIPS-Lite)20.1Introduction (251)20.1.1Features (251)20.1.2General operation (251)20.2Functional description (252)20.2.1Access support (252)Chapter 21Reset Control Module (RCM)21.1Introduction (253)21.2Reset memory map and register descriptions (253)21.2.1System Reset Status Register 0 (RCM_SRS0) (254)21.2.2System Reset Status Register 1 (RCM_SRS1) (255)21.2.3Reset Pin Filter Control register (RCM_RPFC) (256)21.2.4Reset Pin Filter Width register (RCM_RPFW) (257)21.2.5Force Mode Register (RCM_FM) (259)21.2.6Mode Register (RCM_MR) (259)21.2.7Sticky System Reset Status Register 0 (RCM_SSRS0) (260)21.2.8Sticky System Reset Status Register 1 (RCM_SSRS1) (261)Chapter 22Bit Manipulation Engine (BME)22.1Introduction (263)22.1.1Overview (264)22.1.2Features (264)22.1.3Modes of operation (265)22.2Memory map and register definition (265)22.3Functional description (266)22.3.1BME decorated stores (266)22.3.2BME decorated loads (273)22.3.3Additional details on decorated addresses and GPIO accesses (279)22.4Application information (280)Chapter 23Micro Trace Buffer (MTB)23.1Introduction (283)23.1.1Overview (283)23.1.2Features (286)23.1.3Modes of operation (287)23.2External signal description (287)23.3Memory map and register definition (288)23.3.1MTB_RAM Memory Map (288)23.3.2MTB_DWT Memory Map (301)23.3.3System ROM Memory Map (311)Chapter 24Multipurpose Clock Generator Lite (MCG_Lite)24.1Introduction (317)24.1.1Features (317)24.1.2Block diagram (317)24.2Memory map and register definition (318)24.2.1MCG Control Register 1 (MCG_C1) (319)24.2.2MCG Control Register 2 (MCG_C2) (319)24.2.3MCG Status Register (MCG_S) (320)24.2.4MCG Status and Control Register (MCG_SC) (321)24.2.5MCG Miscellaneous Control Register (MCG_MC) (321)24.3Functional description (322)24.3.1Clock mode switching (322)24.3.2LIRC divider 1 (323)24.3.3LIRC divider 2 (323)24.3.4Enable LIRC in Stop mode (324)24.3.5MCG-Lite in Low-power mode (324)Chapter 25Oscillator (OSC)25.1OSC modes of operation with MCG_Lite and RTC (325)25.2Introduction (325)25.3Features and Modes (325)25.4Block Diagram (326)25.5OSC Signal Descriptions (327)25.6External Crystal / Resonator Connections (327)25.7External Clock Connections (328)25.8Memory Map/Register Definitions (329)25.8.1OSC Memory Map/Register Definition (329)25.9Functional Description (330)25.9.1OSC module states (330)25.9.2OSC module modes (332)25.9.3Counter (333)25.9.4Reference clock pin requirements (333)25.10Reset (334)25.11Low power modes operation (334)25.12Interrupts (334)Chapter 26Flash Memory Controller (FMC)26.1Introduction (335)26.1.1Overview (335)26.1.2Features (335)26.2Modes of operation (336)26.3External signal description (336)26.4Memory map and register descriptions (336)26.5Functional description (336)Chapter 27Flash Memory Module (FTFA)27.1Introduction (339)27.1.1Features (339)27.1.2Block Diagram (340)27.1.3Glossary (341)27.2External Signal Description (342)27.3Memory Map and Registers (342)27.3.1Flash Configuration Field Description (342)27.3.2Program Flash IFR Map (343)27.3.3Register Descriptions (343)27.4Functional Description (352)27.4.1Flash Protection (352)27.4.2Interrupts (353)27.4.3Flash Operation in Low-Power Modes (354)27.4.4Functional Modes of Operation (354)27.4.5Flash Reads and Ignored Writes (354)27.4.6Read While Write (RWW) (355)27.4.7Flash Program and Erase (355)27.4.8Flash Command Operations (355)27.4.9Margin Read Commands (360)27.4.10Flash Command Description (361)27.4.11Security (375)27.4.12Reset Sequence (377)Chapter 28Analog-to-Digital Converter (ADC)28.1Chip-specific ADC information (379)28.1.1ADC0 connections/channel assignment (379)28.1.2ADC analog supply and reference connections (380)28.1.3ADC Reference Options (380)28.1.4Alternate clock (381)28.2Introduction (381)28.2.1Features (381)28.2.2Block diagram (382)28.3ADC signal descriptions (383)28.3.1Analog Power (VDDA) (384)28.3.2Analog Ground (VSSA) (384)28.3.3Analog Channel Inputs (ADx) (384)28.4Memory map and register definitions (384)28.4.1ADC Status and Control Registers 1 (ADC x_SC1n) (385)28.4.2ADC Configuration Register 1 (ADC x_CFG1) (389)28.4.3ADC Configuration Register 2 (ADC x_CFG2) (390)28.4.4ADC Data Result Register (ADC x_R n) (391)28.4.5Compare Value Registers (ADC x_CV n) (392)28.4.6Status and Control Register 2 (ADC x_SC2) (393)28.4.7Status and Control Register 3 (ADC x_SC3) (395)28.4.8ADC Offset Correction Register (ADC x_OFS) (397)28.4.9ADC Plus-Side Gain Register (ADC x_PG) (397)28.4.10ADC Plus-Side General Calibration Value Register (ADC x_CLPD) (398)28.4.11ADC Plus-Side General Calibration Value Register (ADC x_CLPS) (398)28.4.12ADC Plus-Side General Calibration Value Register (ADC x_CLP4) (399)28.4.13ADC Plus-Side General Calibration Value Register (ADC x_CLP3) (399)28.4.14ADC Plus-Side General Calibration Value Register (ADC x_CLP2) (400)28.4.15ADC Plus-Side General Calibration Value Register (ADC x_CLP1) (400)28.4.16ADC Plus-Side General Calibration Value Register (ADC x_CLP0) (401)28.5Functional description (401)28.5.1Clock select and divide control (402)28.5.2Voltage reference selection (403)28.5.3Hardware trigger and channel selects (403)28.5.4Conversion control (404)28.5.5Automatic compare function (411)28.5.6Calibration function (412)28.5.7User-defined offset function (414)28.5.8Temperature sensor (415)28.5.9MCU wait mode operation (416)28.5.10MCU Normal Stop mode operation (416)28.5.11MCU Low-Power Stop mode operation (417)28.6Initialization information (418)28.6.1ADC module initialization example (418)28.7Application information (420)28.7.1External pins and routing (420)28.7.2Sources of error (422)Chapter 29Comparator (CMP)29.1Chip-specific CMP information (427)29.1.1CMP input connections (427)29.1.2CMP external references (428)29.1.3CMP trigger mode (428)29.2Introduction (429)29.2.1CMP features (429)29.2.26-bit DAC key features (430)29.2.3ANMUX key features (430)29.2.4CMP, DAC and ANMUX diagram (430)29.2.5CMP block diagram (431)29.3Memory map/register definitions (432)29.3.1CMP Control Register 0 (CMP x_CR0) (433)29.3.2CMP Control Register 1 (CMP x_CR1) (434)29.3.3CMP Filter Period Register (CMP x_FPR) (435)29.3.4CMP Status and Control Register (CMP x_SCR) (436)29.3.5DAC Control Register (CMP x_DACCR) (437)29.3.6MUX Control Register (CMP x_MUXCR) (437)29.4Functional description (438)29.4.1CMP functional modes (438)29.4.2Power modes (442)29.4.3Startup and operation (443)29.4.4Low-pass filter (443)29.5CMP interrupts (445)29.6Digital-to-analog converter (446)29.7DAC functional description (446)29.7.1Voltage reference source select (446)29.8DAC resets (447)29.9DAC clocks (447)29.10DAC interrupts (447)29.11CMP Trigger Mode (447)Chapter 30Voltage Reference (VREF)30.1Chip specific VREF information (449)30.1.1Clock Gating (449)30.2Introduction (449)30.2.1Overview (450)30.2.2Features (450)30.2.3Modes of Operation (451)30.2.4VREF Signal Descriptions (451)30.3Memory Map and Register Definition (452)30.3.1VREF Trim Register (VREF_TRM) (452)30.3.2VREF Status and Control Register (VREF_SC) (453)30.4Functional Description (454)30.4.1Voltage Reference Disabled, SC[VREFEN] = 0 (455)30.4.2Voltage Reference Enabled, SC[VREFEN] = 1 (455)30.4.3Internal voltage regulator (456)30.5Initialization/Application Information (457)Chapter 31Timer/PWM Module (TPM)31.1Chip-specific TPM information (459)31.1.1Clock options (459)31.1.2Trigger options (460)31.1.3Global timebase (460)31.1.4TPM interrupts (460)31.2Introduction (461)31.2.1TPM Philosophy (461)31.2.2Features (461)31.2.3Modes of operation (462)31.2.4Block diagram (462)31.3TPM Signal Descriptions (463)31.3.1TPM_EXTCLK — TPM External Clock (463)31.3.2TPM_CHn — TPM Channel (n) I/O Pin (464)31.4Memory Map and Register Definition (464)31.4.1Status and Control (TPM x_SC) (465)31.4.2Counter (TPM x_CNT) (466)31.4.3Modulo (TPM x_MOD) (467)31.4.4Channel (n) Status and Control (TPM x_C n SC) (468)31.4.5Channel (n) Value (TPM x_C n V) (469)31.4.6Capture and Compare Status (TPM x_STATUS) (470)31.4.7Configuration (TPM x_CONF) (472)31.5Functional description (473)31.5.1Clock domains (474)31.5.2Prescaler (474)31.5.3Counter (475)31.5.4Input Capture Mode (478)31.5.5Output Compare Mode (478)31.5.6Edge-Aligned PWM (EPWM) Mode (480)31.5.7Center-Aligned PWM (CPWM) Mode (481)31.5.8Registers Updated from Write Buffers (483)31.5.9Output triggers (484)31.5.10Reset Overview (484)31.5.11TPM Interrupts (484)Chapter 32Low-Power Timer (LPTMR)32.1Chip-specific LPTMR information (487)32.1.1LPTMR pulse counter input options (487)32.1.2LPTMR prescaler/glitch filter clocking options (487)32.2Introduction (488)32.2.1Features (488)32.2.2Modes of operation (488)32.3LPTMR signal descriptions (489)32.3.1Detailed signal descriptions (489)32.4Memory map and register definition (489)32.4.1Low Power Timer Control Status Register (LPTMR x_CSR) (490)32.4.2Low Power Timer Prescale Register (LPTMR x_PSR) (491)32.4.3Low Power Timer Compare Register (LPTMR x_CMR) (493)32.4.4Low Power Timer Counter Register (LPTMR x_CNR) (493)32.5Functional description (494)32.5.1LPTMR power and reset (494)32.5.2LPTMR clocking (494)32.5.3LPTMR prescaler/glitch filter (494)32.5.4LPTMR compare (496)32.5.5LPTMR counter (496)32.5.6LPTMR hardware trigger (497)32.5.7LPTMR interrupt (497)Chapter 33Real Time Clock (RTC)33.1Chip-specific RTC information (499)33.1.1RTC_CLKOUT options (499)33.2Introduction (499)33.2.1Features (499)33.2.2Modes of operation (500)33.2.3RTC signal descriptions (500)33.3Register definition (500)33.3.1RTC Time Seconds Register (RTC_TSR) (501)33.3.2RTC Time Prescaler Register (RTC_TPR) (501)33.3.3RTC Time Alarm Register (RTC_TAR) (502)33.3.4RTC Time Compensation Register (RTC_TCR) (502)33.3.5RTC Control Register (RTC_CR) (504)33.3.6RTC Status Register (RTC_SR) (506)33.3.7RTC Lock Register (RTC_LR) (507)33.3.8RTC Interrupt Enable Register (RTC_IER) (508)33.4Functional description (509)33.4.1Power, clocking, and reset (509)33.4.2Time counter (510)33.4.3Compensation (510)33.4.4Time alarm (511)33.4.5Update mode (511)33.4.6Register lock (512)33.4.7Interrupt (512)Chapter 34Serial Peripheral Interface (SPI)34.1Chip-specific SPI information (513)34.2Introduction (513)34.2.1Features (513)34.2.2Modes of operation (514)34.2.3Block diagrams (515)34.3External signal description (517)34.3.1SPSCK — SPI Serial Clock (517)34.3.2MOSI — Master Data Out, Slave Data In (518)34.3.3MISO — Master Data In, Slave Data Out (518)34.3.4SS — Slave Select (518)34.4Memory map/register definition (519)34.4.1SPI Status Register (SPI x_S) (519)34.4.2SPI Baud Rate Register (SPI x_BR) (520)34.4.3SPI Control Register 2 (SPI x_C2) (521)34.4.4SPI Control Register 1 (SPI x_C1) (523)34.4.5SPI Match Register (SPI x_M) (524)34.4.6SPI Data Register (SPI x_D) (525)34.5Functional description (525)34.5.1General (525)34.5.2Master mode (526)34.5.3Slave mode (527)34.5.4SPI clock formats (529)34.5.5SPI baud rate generation (532)34.5.6Special features (532)34.5.7Error conditions (534)34.5.8Low-power mode options (535)34.5.9Reset (536)34.5.10Interrupts (537)34.6Initialization/application information (538)34.6.1Initialization sequence (538)34.6.2Pseudo-Code Example (539)Chapter 35Inter-Integrated Circuit (I2C)35.1Chip-specific I2C information (543)35.2Introduction (543)35.2.1Features (543)35.2.2Modes of operation (544)35.2.3Block diagram (544)35.3I2C signal descriptions (545)35.4Memory map/register definition (546)35.4.1I2C Address Register 1 (I2C x_A1) (546)35.4.2I2C Frequency Divider register (I2C x_F) (547)35.4.3I2C Control Register 1 (I2C x_C1) (548)35.4.4I2C Status register (I2C x_S) (549)35.4.5I2C Data I/O register (I2C x_D) (551)35.4.6I2C Control Register 2 (I2C x_C2) (552)35.4.7I2C Programmable Input Glitch Filter Register (I2C x_FLT) (553)35.4.8I2C Range Address register (I2C x_RA) (554)35.4.9I2C SMBus Control and Status register (I2C x_SMB) (555)35.4.10I2C Address Register 2 (I2C x_A2) (556)35.4.11I2C SCL Low Timeout Register High (I2C x_SLTH) (557)35.4.12I2C SCL Low Timeout Register Low (I2C x_SLTL) (557)35.4.13I2C Status register 2 (I2C x_S2) (558)35.5Functional description (558)35.5.1I2C protocol (558)35.5.210-bit address (564)35.5.3Address matching (565)35.5.4System management bus specification (566)35.5.5Resets (569)35.5.6Interrupts (569)35.5.7Programmable input glitch filter (571)35.5.8Address matching wake-up (572)35.5.9Double buffering mode (573)35.6Initialization/application information (574)Chapter 36Low Power Universal Asynchronous Receiver/Transmitter (LPUART)36.1Chip-specific LPUART information (579)36.2Introduction (579)36.2.1Features (579)36.2.2Modes of operation (580)36.2.3Signal Descriptions (581)36.2.4Block diagram (581)36.3Register definition (583)36.3.1LPUART Baud Rate Register (LPUART x_BAUD) (584)36.3.2LPUART Status Register (LPUART x_STAT) (586)36.3.3LPUART Control Register (LPUART x_CTRL) (590)36.3.4LPUART Data Register (LPUART x_DATA) (595)36.3.5LPUART Match Address Register (LPUART x_MATCH) (597)36.4Functional description (597)36.4.1Baud rate generation (597)36.4.2Transmitter functional description (598)36.4.3Receiver functional description (600)36.4.4Additional LPUART functions (605)36.4.5Interrupts and status flags (607)Chapter 1About This Document1.1Overview1.1.1PurposeThis document describes the features, architecture, and programming model of the Freescale microcontroller.1.1.2AudienceA reference manual is primarily for system architects and software application developers who are using or considering using a Freescale product in a system.1.2Conventions1.2.1Numbering systemsThe following suffixes identify different numbering systems:1.2.2Typographic notationThe following typographic notation is used throughout this document:1.2.3Special termsThe following terms have special meanings:Chapter 2Introduction2.1KL03 sub-family introductionThe device is highly-integrated, market leading ultra low-power 32-bit microcontroller based on the enhanced Cortex-M0+ (CM0+) core platform. The features of the KL03 family derivatives are as follows.•Core platform clock up to 48 MHz, bus clock up to 24 MHz•Memory option is up to 32 KB flash, 2 KB RAM and 8 KB ROM with build-in boot loader•Wide operating voltage ranges from 1.71–3.6 V with fully functional flash program/ erase/read operations•Multiple package options from 16-pin to 24-pin•Ambient operating temperature ranges from –40 °C to 85 °C for WLCSP package and –40 °C to 105 °C for all the other packages.The family acts as an ultra low-power, cost-effective microcontroller to provide developers an appropriate entry-level 32-bit solution. The family is the next-generation MCU solution for low-cost, low-power, high-performance devices applications. It’s valuable for cost-sensitive, portable applications requiring long battery life-time.2.2Module functional categoriesThe modules on this device are grouped into functional categories. Information found here describes the modules assigned to each category in more detail.2.2.1ARM Cortex-M0+ core modules The following core modules are available on this device.2.2.2System modulesThe following system modules are available on this device.2.2.3Memories and memory interfacesThe following memories and memory interfaces are available on this device.2.2.4ClocksThe following clock modules are available on this device.2.2.5Analog modulesThe following analog modules are available on this device:。
EM4-DINAV13BDR中文资料
D:
[1] Un: -20+15%
[2] Un: -30+15%
[4] Un: -10 +15%
Specifications are subject to change without notice
1
元器件交易网
EM4-DIN
Input specifications
Number of inputs Current Voltage Accuracy (display, RS485) 3 4 Ib: 5A, Imax: 10A Ib: 20A, Imax:90A Un: see “Range code” on previous page from 0.003Ib to 0.2Ib: ±(0.5%RDG +3DGT) from 0.2Ib to Imax: ±(0.5%RDG +1DGT) in the range Un: ±(0,5% RDG + 1DGT) ±0.1% RDG (50 to 60 Hz) ±(1% RDG +1DGT). PF 1, 0.1Ib to Imax, in the Un range; PF 0.5L, PF 0.8C, 0.2Ib to Imax, in the Un range Class 1 acc. to EN61036 Class 2 acc. to EN61268 Ib: 5A, Imax: 10A 0.1Ib: 500mA, Start up current: 20mA Un: see table “range code” Ib: 20A, Imax: 90A 0.1Ib: 2A, Start up current: 80mA Un: see table “range code” Acc. to EN61036, EN61268 <1% (3rd harmonic: 10%) < 0.5% (referred to Un) 0 (up to 0.5 mT) < 1% 0 Temperature drift Sampling rate Display Type Instantan. variables read-out Energies Max. and Min. indication Measurements Coupling type Crest factor Ib 5A Ib 20A Current overload 5(10) A, for 10ms 5(10) A, for 500ms 5(10) A, permanent 20(90) A, for 10ms 20(90) A, permanent Voltage overload Permanent For 1s Input impedance 400VL-L (AV1-AV5-AV9) 208VL-L (AV0-AV4-AV8-AV2) 660VL-L (AV3-AV7) 100VL-L (AV6) 5(10) A (AV4-AV5-AV6-AV7) 20(90) A (AV0-AV1-AV3-AV8-AV9) 20(90) A (AV2) Frequency ≤ 200ppm/°C 1000 samplings/s @ 50Hz Back-lighted LCD 31/2 DGT Total: 8 DGT + 71/2 DGT; Partial: 8 DGT + 71/2 DGT; Max. 1999 (99999999), Min. 0 Power, energy. TRMS measurements of distorted wave forms. Direct ≤3 (15A max. peak) ≤6 (127A max. peak) 300A max, @ 50Hz 200A max, @ 50Hz 10A, @ 50Hz 2700A max, @ 50Hz 90A, @ 50Hz 1.2 Un 2 Un > 720KΩ > 720KΩ > 1.97MΩ > 400KΩ < 0.3VA < 4VA < 4VA 50 to 60 Hz
MEMORY存储芯片MT46V64M8CY-5BIT J中文规格书
512Mb: x4, x8, x16 DDR SDRAM Pin and Ball Assignments and Descriptions E3E7E3511651DQS LDQS UDQS I/O Data strobe: Output with read data, input with write data. DQS is edge-aligned with read data, centered in write data. It is used to capture data. For the x16, LDQS is DQS for DQ[7:0] and UDQS is DQS for DQ[15:8]. Pin16 (E7) is NC on x4 and x8.F8, M7, A71, 18, 33V DD Supply Power supply: 2.5V ±0.2V. (2.6V ±0.1V for DDR400).B2, D2, C8, E8, A93, 9, 15, 55, 61V DDQ Supply DQ power supply: 2.5V ±0.2V (2.6V ±0.1V for DDR400). Isolated on the die for improved noise immunity.F149V REF Supply SSTL_2 reference voltage.A3, F2, M334, 48, 66V SS Supply Ground.A1, C2, E2, B8, D86, 12, 52, 58, 64V SSQ Supply DQ ground: Isolated on the die for improved noise immunity.–14, 17, 25, 43, 53NC –No connect for x16: These pins should be left unconnected.B1, B9, C1, C9, D1, D9, E1, E7, E9, F7 4, 7, 10,13, 14, 16,17, 20, 25,43, 53, 54,57, 60, 63NC –No connect for x8: These pins should be left unconnected.B1, B9, C1, C9, D1, D9, E1, E7, E9, F74, 7, 10, 13,14, 16, 17,20, 25, 43,53, 54, 57,60, 63NC –No connect for x4: These pins should be left unconnected.A2, A8, C3, C72, 8, 59, 65NF –No function for x4: These pins should be left unconnected.F9 19, 50DNU –Do not use: Must float to minimize noise on V REF .Table 5:Reserved NC Pin and Ball Descriptions NC pins not listed may also be reserved for other uses; this table defines NC pins of importance TSOP NumbersSymbol Type Description 17A13Input Address input A13 for 1Gb devices.Table 4:Pin and Ball Descriptions (continued)FBGA NumbersTSOP Numbers Symbol Type Description512Mb: x4, x8, x16 DDR SDRAMElectrical Specifications – I DDTable 7: I DD Specifications and Conditions (x16) Die Revision F OnlyV DDQ = 2.6V ±0.1V, V DD = 2.6V ±0.1V (-5B); V DDQ = 2.5V ±0.2V, V DD = 2.5V ±0.2V (-6, -6T, -75E, -75Z, -75);0°C d T A d 70°C; Notes: 1–5, 11, 13, 15, 47; Notes appear on pages 37–42; See also Table 10 on page 20Parameter/Condition Symbol-5B-6/6T-75E-75Z/-75Units NotesI DD0155130130115mA23, 48 Operating one-bank active-precharge current:t RC = t RC (MIN); t CK = t CK (MIN); DQ, DM, and DQS inputschanging once per clock cycle; Address and control inputschanging once every two clock cyclesI DD1195160160145mA23, 48 Operating one-bank active-read-precharge current:Burst = 4; t RC = t RC (MIN); t CK = t CK (MIN); I OUT = 0mA;Address and control inputs changing once per clock cycleI DD2P5555mA24, 33 Precharge power-down standby current: All banks idle;Power-down mode; t CK = t CK (MIN); CKE = (LOW)I DD2F55454540mA51 Idle standby current: CS# = HIGH; All banks are idle;t CK = t CK (MIN); CKE = HIGH; Address and other controlinputs changing once per clock cycle; V IN = V REF for DQ, DQS,and DMI DD3P45353530mA24, 33 Active power-down standby current: One bank active;Power-down mode; t CK = t CK (MIN); CKE = LOWI DD3N60505045mA23 Active standby current: CS# = HIGH; CKE = HIGH; One bankactive;t RC = t RAS (MAX); t CK = t CK (MIN); DQ, DM, and DQSinputs changing twice per clock cycle; Address and othercontrol inputs changing once per clock cycleI DD4R210165165145mA23, 48 Operating burst read current: Burst = 2; Continuousburst reads; One bank active; Address and control inputschanging once per clock cycle; t CK = t CK (MIN); I OUT = 0mAI DD4W215195160135mA23 Operating burst write current: Burst = 2; Continuous burstwrites;One bank active; Address and control inputs changingonce per clock cycle; t CK = t CK (MIN); DQ, DM, and DQS inputschanging twice per clock cycleAuto refresh burst current:t RFC = t RFC (MIN)I DD5345290290280mA50t RFC = 7.8µs IDD5A11101010mA28, 50t RFC = 1.95µs IDD5A16151515mA28, 50 Self refresh current: CKE d 0.2V Standard I DD66555mA12Low power (L)I DD6A4333mA12I DD7480405400350mA23, 49 Operating bank interleave read current: Four bankinterleaving READs (burst = 4) with auto precharge,t RC = minimum t RC allowed; t CK = t CK (MIN); Address andcontrol inputs change only during active READ or WRITEcommands。
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Product descriptionThree-phase energy meter with built-in configuration key-pad; particularly indicat-ed for the metering and the management of the energy in addition to the metering and the management of the signals coming from the water and gas meters.Housing for DIN-rail or wall-mounting, IP40 (front) pro-tection degree.Completely sealable housing.In case of direct connection up to 90A, the measuringinput terminals are suitable for cables with a cross-sec-tion area from 6 to 35 mm 2.The special design of the instrument’s housing allows to add at any time the inter-face modules, even when the instrument is already installed. The following mod-ules are available:-for all versions: pulse output;-only for the versions with auxiliary power supply:digital inputs, RS485 serial port.Energy ManagementEnergy Meter with plug-in Output Modules Type EM4-DINType selectionPower supplyFor all versions A:24VAC-15+10%, 50-60HzB:48VAC-15+10%, 50-60HzC:115VAC-15+10%, 50-60HzD:230VAC-15+10%, 50-60Hz4:18 to 60VDC 5:77 to 143VDC AV2, AV8 and AV9 only X:Self Power Supply400V L-L(-20+15%, 50-60Hz)208V L-L(-20+15%, 50-60Hz)220V L-L(-10+15%, 50-60Hz)Range CodeAuxiliary Power Supply:AV0:208V L-L /20(90)AAC [3]AV1:400V L-L /20(90)AAC [1]AV3:660V L-L /20(90)AAC [2]AV4:208V L-L /5(10)AAC [3]AV5:400V L-L /5(10)AAC [1]AV6:100V L-L /5(10)AAC [3]AV7:660V L-L /5(10)AAC [2]Self Power Supply:AV2:220V L-L /20(90)AAC [4]AV8:208V L-L /20(90)AAC [1]AV9:400V L-L /20(90)AAC [1]Slot A (retransmission)X:NoneO:AO2900 moduleDual open collector out-put. Three operating modes:•two pulse outputs (kWh and kvarh);•one alarm output (kW dmd)and one pulse output (kWh or kvarh) •one outputremotely controlled by a serial port and one pulseoutput (kWh or kvarh)D:AQ2940 module Two digital inputs for the management of water and gas metersSlot A (retransmission) cont.R:AO2910 module.One relay output + one open collector output.Operation modes like module AO2900Slot B (retransmission)Only with A-B-C-D-4 power supply XX:NoneS0:AR2950 module RS422/485serial portSystem 3:Three-phase,unbalanced load with or without neutral[1] Un: -20+15% [2] Un: -30+15% [3] Un: -20+20% [4] Un: -10 +15%•Class 1 (active energy)•Class 2 (reactive energy)•Three-phase multi-function energy meter •Back-lighted LCD display•31/2DGT instantaneous variables read-out •8DGT + 71/2DGT energy read-out•Measurements of system and phase variables: W, Wdmd •Measurements of total energies: kWh, kvarh •Measurements of partial energies: kWh, kvarh•Energy measurements according to EN61036 and EN61268•Energy measurements by time periods (t1-t2-t3-t4)selectable by input contacts•Measurements of m 3H 2O and m 3GAS by means of input contacts •TRMS measurements of distorted wave forms (voltages/currents)•Two basic models: direct connection 20(90)AAC,CT 5(10)AAC and VT connection•Self power supply (available for some models only) or auxiliary power supply: 24V , 48V , 115V , 230V , 50-60Hz; 18 to 60VDC, 77 to 143VDC•Degree of protection (front):IP 40•Front dimensions: 9 DIN modules•RS 422/485 Serial port by means of optional module •Dual pulse output by means of optional module•Alarm output (kW dmd) by means of optional module •Digital inputs for the management of the time periods and of the H 2O and GAS metersImportant note:•The models from AV0 to AV7 can be equipped with any type of available modules (slot A and B).•The models AV8 and AV9 can be equipped only with the “O” and “R” type modules.•The AV8 and AV9 models can measure all the parameters even if the three phase system being connected is missing one phase.•The AV2 model is suitable only for three-phase unbalanced system without neutral.EM4-DINRS422/RS485 (on request)AR2950 module T ype Multidropbidirectional (static and dynamic variables)Connections2 or 4 wires, max. distance 1200m, termination directly on the moduleAddresses 255, selectable by key-pad ProtocolMODBUS/JBUSData (bidirectional)Dynamic (reading only)Phase and system variables:see table “Display pages”Static (writing only )All the programming data, reset of energy, activation of static output.Stored energy (EEPROM) max. 99.999.999 kWh/kvarh Data format 1 start bit, 8 data bit, no parity,1stop bit Baud-rate 9600 bit/sInsulationBy means of optocouplers, 2000 V RMS output to measuring inputsInterface module specificationsInput specificationsEM4-DINV OFF 30 VDC max.Pulse duration220 ms (ON), ≥220 ms (OFF)According to DIN43864Alarm outputNumber of outputs 1Alarm typeUp alarm, down alarm.Setpoint adjustment0 to 100% of the electrical scaleHysteresis 0 to 100% of the electrical scaleOn-time delay 0 to 255 seconds Response time 700 msOutput type Open collector (transistor NPN)V ON 1.2 VDC / max. 100 mA V OFF 30 VDC max.InsulationBy means of optocouplers, 2000 V RMS outputs to measuring inputs,2000 V RMS output to supply input.Insulation between the two outputs: functional AO2910 module Relay + open collector output. Working mode like AO2900.Pulse output One static output+one relay output, other characteristics like AO2900.Alarm output Only relay output, other characteristics like AO2900.Output typeStatic type like module AO2900;Relay type: SPDT ,AC1, AC15: 1AAC @250VAC Insulation2000 V RMS outputs to measuring inputs,2000 V RMS output toInterface module specifications (cont.)to 5A)Display VariablesUp to 4 variables per page Page 1: k Wh-kvarh Page 2a: k Wh (t 1-t 2-t 3-t 4)k varh (t 1-t 2-t 3-t 4)Page 2b: GAS m 3day-time tariff,GAS m 3night tariffPage 2c: H 2O m 3,GAS m 3Page 3: W L1Page 4: W L2Page 5: W L3Page 6: W dmdErrorsPhase sequence, serialcommunication status, wrong connection of current measuring inputs.Software functionsEM4-DINVariables that can be displayedDisplay pagesGeneral SpecificationsSystem variablesEquivalent system voltageSystem reactive powerSystem active powerSystem apparent powerSystem power factor(TPF)Instantaneous effective voltageInstantaneous active powerInstantaneous power factor(TPF)Instantaneous effective currentInstantaneous apparent powerInstantaneous reactive powerNote:i = phase (L1, L2 or L3)P = active power Q = reactive powert 1,t 2=starting and ending time points of consumption recording n = time unit∆t= time interval of consumption recordingn 1,n 2=starting and ending discrete time points of consumption recordingRS422/RS485 “dynamic data”. The variables transmitted are the ones listed inthe table above and those mentioned in the “Display pages” of WM22-DIN data sheet except for: THD A ,THD V ,A max, W dmd max, and VA dmd max.EM4-DINAvailable modelsPossible module combinationsAvailable modulesEM4-DINWiring diagrams20(90)A model: three-phase unbalanced load Direct connection (3-phase system)Direct connection (3-phase system + N)5(10)A model:three-phase unbalanced load Direct connection (3-phase system + N)Direct connection (3-phase systemwith or without neutral)CT connection (3-phase system with neu tral)Self-power supplyFig. 45(10)A model: three-phase unbalanced load VT and CT connection (3-phase system)20(90)A model:three-phase unbalanced load Auxiliary power supplyFig. 2Auxiliary power supplyFig. 1Auxiliary power supplyFig. 5Auxiliary power supplyFig. 6Auxiliary power supplyFig. 9AC power supplyAC power supplyAC power supplyAC power supplyAC power supplyL O A DL O A DL O A DL O A DL O A DL O A DL O A DCT ARON connection (3-phase system)VT and CT ARON connection (3-phase system)Auxiliary power supplyFig. 8Auxiliary power supplyFig. 7AC power supplyAC power supplyL O A DL O A DEM4-DINWiring diagrams (optional modules)Only open collector outputs: the grounds of the outputs are separated, and therefore it’s possible to carry out, for the same module, two different connections. The load resistance (Rc) must be designed so that the closed contact current is lower than 100mA; the VDC voltage must be lower than or equal to 30V. VDC: power supply voltage output. Vo+: positive output contact (open collector transistor). GND: ground output contact (open collector transistor).PNP-NPN connections Contact and voltage connection2and 4-wire connectionDigital inputs Fig. 12Digital inputs Fig. 13RS485 Serial output Fig. 14AccuracyAccuracy (RDG) depending on the currentError10A (Imax)90A (Imax)10A (Imax)90A (Imax)5A (Ib)20A (Ib)5A (Ib)20A (Ib)0,5A2A1A4A0,25A1A0.5A2A+1%+4%-4%0%+1.5%-1%EN 61036/ IEC 61036 limits (Active energy)5(10A) Start-up current: 20mA20(90A) Start-up current: 80mA-1.5%Accuracy (RDG) depending on the currentError+2%+4%-4%0%+2.5%-2%EN 61268/ IEC 61268 limits (Reactive energy)5(6A) Start-up current: 20mA20(90A) Start-up current: 80mA-2.5%Relay + open coll. output Fig. 1110A (Imax)10A (Imax)90A (Imax)90A (Imax)5A (Ib)5A (Ib)20A (Ib)20A (Ib)0.25A0.5A2A4A0.1A0.25A1A2Asinϕ=1sinϕ=0.5sinϕ=1PF=1PF=L0.5or C0.8EM4-DINTerminal boardsDimensions and panel cut-outOpen collector dual output moduleRS485Serial output moduleA O 22900Relay output + open coll. output moduleA O 22910A R 22950Digital inputs moduleA Q 22940Keys for:- values programming;- function selection;- displaying the measuring pages.2.DisplayLCD with alphanumeric indications to:- display configuration parameters;- display all the measured variables.3.Removable labelIt shows the following information:- year of manufacturing - serial number- input voltages and currents - operating frequency - kWh measuring class - kvarh measuring class- symbols: electric system, attention and dual insulation.4.Hidden dip-switchEnable/disable the access to the programming procedure.Front panel description1.Key-padT o program configuration parameters and to display variables.S-key to enter programming and confirm selections;1234。