IDT7MB4045S15Z资料

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PD 0PD 1– GND – GND
GND CS 3A 16I/O 16I/O 17I/O 18I/O 19A 10A 11A 12A 13I/O 20I/O 21I/O 22I/O 23GND
I/O 0I/O 1I/O 2I/O 3V CC A 7A 8A 9I/O 4I/O 5I/O 6WE I/O 7CS 1PD 0A 14CS 4A 17OE I/O 24I/O 25I/O 26I/O 27A 3A 4A 5V CC A 6I/O 28I/O 29I/O 30I/O 31
PD 1GND I/O 8I/O 9I/O 10I/O 11A 0A 1A 2I/O 12I/O 13I/O 14I/O 15GND CS 2A 15
(IDT7MP4145 upgradeable to 4 megabyte, IDT7MP4120)•Low profile 64 pin ZIP (Zig-zag In-line vertical Package)or 64 pin SIMM (Single In-line Memory Module) for IDT7MP4045 and 72 pin SIMM (Single In-line Memory Module) for IDT7MP4145
•Very fast access time: 15ns (max.)
•Surface mounted plastic components on an epoxy laminate (FR-4) substrate
•Single 5V (±10%) power supply
•Multiple GND pins and decoupling capacitors for maxi-mum noise immunity
•Inputs/outputs directly TTL-compatible
2703 tbl 01
COMMERCIAL TEMPERATURE RANGE
SEPTEMBER 1996
©1996 Integrated Device Technology, Inc.
DSC-2703/7
The IDT logo is a registered trademark of Integrated Device Technology Inc.
NOTE:
1.Pins 2 and 3 (PD 0 and PD 1) are read by the user to determine the density
of the module. If PD 0 reads GND and PD 1 reads GND, then the module has a 256K depth.
constructed on an epoxy laminate (FR-4) substrate using 8256K x 4 static RAMs in plastic SOJ packages. Availability of four chip select lines (one for each group of two RAMs)provides byte access. The IDT7MP4045 is available with access time as fast as 10ns with minimal power consumption.The IDT7MP4045 is packaged in a 64 pin FR-4 ZIP (Zig-zag In-line vertical Package)or a 64 pin SIMM (Single In-line Memory Module) where as the 7MP4145 is packaged in a 72pin SIMM (Single In-line Memory Module). The 4045 ZIP configuration allows 64 pins to be placed on a package 3.65inches long and 0.365 inches wide. The 7MP4045 ZIP is only 0.585 inches high, this low profile package is ideal for systems with minimum board spacing while the SIMM configuration allows use of edge mounted sockets to secure the module.All inputs and outputs of the IDT7MP4045/4145 are TTL-compatible and operate from a single 5V supply. Full asyn-chronous circuitry requires no clocks or refresh for operation and provides equal access and cycle times for ease of use.Identification pins are provided for applications in which different density versions of the module are used. In this way,the target system can read the respective levels of PD pins to determine a 256K depth.
The contact pins are plated with 100 micro-inches of nickel covered by 30 micro-inches minimum of selective gold.
PIN CONFIGURATION – 7MP4045(1)
FUNCTIONAL BLOCK DIAGRAM
OE
WE 2703 drw 02
I/O 0-31
PD
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
A
NOTE:
2703 tbl 02
1.This parameter is guaranteed by design but not tested.
RECOMMENDED DC OPERATING NOTE:
2703 tbl 03
1.V IL (min) = –1.5V for pulse width less than 10ns.
(1)
NOTE:2703 tbl 061.Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
PIN CONFIGURATION – 7MP4145(1)
SIMM TOP VIEW
NOTE:
1.Pins 3,4,6,and 7 (PD 0-3) are read by the user to determine the density of
the module. If PD 0, PD 1 read GND and PD 2, PD 3 read OPEN, then the module has a 256K depth.
1 3 5 7 911131517192123252729313335373941434547495153555759616365676971
24681012141618202224262830323436384042444648505254565860626466687072
NC PD 2GND PD 1I/O 8I/O 9I/O 10I/O 11A 0A 1A 2I/O 12I/O 13I/O 14I/O 15GND A 15CS 2CS 4A 17OE I/O 24I/O 25I/O 26I/O 27A 3A 4A 5V CC A 6I/O 28I/O 29I/O 30I/O 31NC NC
NC PD 3PD 0I/O 0I/O 1I/O 2I/O 3V CC A 7A 8A 9I/O 4I/O 5I/O 6I/O 7WE A 14CS 1CS 3A 16GND I/O 16I/O 17I/O 18I/O 19A 10A 11A 12A 13I/O 20I/O 21I/O 22I/O 23GND NC NC
PD 0 - GND PD 1 - GND PD 2 - OPEN PD 3 - OPEN
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Figure 1. Output Load
*Includes scope and jig.Figure 2. Output Load
(for t OLZ ,t OHZ , t CHZ , t CLZ , t WHZ , t OW )
+5 V
480 Ω
30 pF*DATA OUT
255Ω
2703 drw 03+5 V
480 Ω
5 pF*
DATA OUT
255Ω
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2703 tbl 09
2703 tbl
2703 tbl 07
DC ELECTRICAL CHARACTERISTICS
AC ELECTRICAL CHARACTERISTICS
NOTE:2703 tbl 11 1.This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
TIMING WAVEFORM OF READ CYCLE NO. 2(1,2,4)
TIMING WAVEFORM OF READ CYCLE NO. 3(1,3,4)
OE
ADDRESS
CS
DATA OUT
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DATA OUT
ADDRESS
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DATA OUT
CS
NOTES:
1.WE is HIGH for Read Cycle.
2.Device is continuously selected. CS = V IL .
3.Address valid prior to or coincident with CS transition LOW.
4.OE = V IL .
5.Transition is measured ±200mV from steady state. This parameter is guaranteed by design, but not tested.
CS
DATA IN
ADDRESS
WE
DATA OUT
OE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED) (1, 2, 3, 7)
CS
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DATA IN
ADDRESS
WE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS CONTROLLED) (1, 2, 3, 5)
NOTES:
1.WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (t WP ) of a LOW CS and a LOW WE .
3.t WR is measured from the earlier of CS or WE going HIGH to the end of write cycle.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.Transition is measured ±200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7.If OE is LOW during a WE controlled write cycle, the write pulse width must be the larger of t WP or (t WHZ + t DW ) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t DW . If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t WP .
PACKAGE DIMENSIONS 7MP4045 ZIP VERSION
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7MP4045 SIMM VERSION
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SIDE VIEW
ORDERING INFORMATION
7MP4145 SIMM VERSION
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X Power
X Speed
X Package
X Process/Commercial (0°C to +70°C)
Z M
FR-4 ZIP (Zig-Zag In-line vertical Package,
7MP4045 only)
FR-4 SIMM (Single In-line Memory Module)
XXXXX
Device IDT Speed in Nanoseconds
S Standard Power
7MP40457MP4145
256K x 32 Static RAM Module 256K x 32 Static RAM Module
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