Method of reducing a critical dimension of a semic

专利名称：Method of reducing a critical dimension of a
semiconductor device
发明人：Yu Chao Lin,De-Fang Chen,Chia-Wei
Chang,Yih-Ann Lin,Chao-Cheng Chen,Ryan
Chia-Jen Chen,Weng Cheng
申请号：US12435552
申请日：20090505
公开号：US07759239B1
公开日：
20100720
专利内容由知识产权出版社提供
专利附图：
摘要：The present disclosure provides a method of fabricating a semiconductor
device. The method includes forming a gate layer over a substrate, forming a hard mask layer over a gate layer, forming a first material layer over the hard mask layer, forming a patterned photoresist layer having an opening over the first material layer, etching the first material layer through a cycle including forming a second material layer over the semiconductor device and etching the first and second material layers, repeating the cycle until the hard mask layer is exposed by a reduced opening, the reduced opening formed in a last cycle, etching the hard mask layer beneath the second opening to expose the gate layer, and patterning the gate layer using the hard mask layer. An etching selectivity of the first and second material layers is smaller than an etching selectivity of the second material layer and the photoresist layer.
申请人：Yu Chao Lin,De-Fang Chen,Chia-Wei Chang,Yih-Ann Lin,Chao-Cheng Chen,Ryan Chia-Jen Chen,Weng Cheng
地址：Rende Township, Tainan County TW,Lujhu Township, Taoyuan County
TW,Wufong Township, Taichung County TW,Jhudong Township, Hsinchu County TW,Shin-Chu TW,Chiayi TW,Hsin-Chu TW
国籍：TW,TW,TW,TW,TW,TW,TW
代理机构：Haynes and Boone, LLP
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