vga显示verilog代码

module vga_lena(iclk_50,irst,ovga_clock,ovga_hs,ovga_vs,ovga_blank,ovga_sync,ovga_r,ovga_g,ovga_b,ovga_r0,ovga_g0,ovga_b0);

parameter H_TA=96;
parameter H_TB=40;
parameter H_TC=8;
parameter H_TD=640;
parameter H_TE=8;
parameter H_TF=8;
parameter H_BLANK=H_TA+H_TB+H_TC;
parameter H_TOTAL=H_TA+H_TB+H_TC+H_TD+H_TE+H_TF;
parameter LENGTH=128,WIDTH=128;
parameter V_TA=2;
parameter V_TB=25;
parameter V_TC=8;
parameter V_TD=480;
parameter V_TE=8;
parameter V_TF=2;
parameter V_BLANK=V_TA+V_TB+V_TC;
parameter V_TOTAL=V_TA+V_TB+V_TC+V_TD+V_TE+V_TF;

(* chip_pin="AD15" *)input iclk_50;
(* chip_pin="AA23" *)input irst;
(* chip_pin="D24" *)output ovga_clock;
(* chip_pin="C15" *)output ovga_blank;
(* chip_pin="B15" *)output ovga_sync;
(* chip_pin="J19" *)output reg ovga_hs;
(* chip_pin="H19" *)output reg ovga_vs;
(* chip_pin="G20,E20,F20,H20,G21" *)output reg[4:0] ovga_r;
(* chip_pin="D19,C19,A19,B19,B18" *)output reg[4:0] ovga_b;
(* chip_pin="A14,B14,B13,C13,A12,B12" *)output reg[5:0] ovga_g;
(* chip_pin="H21,D22,E22,E23,D23" *)output [4:0] ovga_r0;
(* chip_pin="C18,B17,A17,C16,B16" *)output [4:0] ovga_b0;
(* chip_pin="C12,A11,B11,A10" *)output [3:0] ovga_g0;

reg iclk;wire vga_read;
reg[14:0] address;wire[15:0] q;
reg[10:0] h_cont,v_cont;
reg[9:0] xpos,ypos;
reg[1:0] ij;
wire[4:0] ired=q[15:11];
wire[5:0] igreen=q[10:5];
wire[4:0] iblue=q[4:0];

always @(posedge iclk_50)
begin iclk<=~iclk;end
assign ovga_blank=~((h_contassign ovga_clock=~iclk;
assign ovga_r0=5'h0;
assign ovga_g0=4'h0;
assign ovga_b0=5'h0;
always @(posedge iclk or posedge irst)
begin
if(irst)
begin
h_cont<=0;
ovga_hs<=1;
end
else
begin
if(h_conth_cont<=h_cont+1'b1;
else
h_cont<=1'b0;
if(h_contovga_hs=1'b0;
else
ovga_hs=1'b1;
end
end
always @(posedge ovga_hs or posedge irst)
begin
if(irst)
begin
v_cont<=0;
ovga_vs<=1;
end
else
begin
if(v_contv_cont<=v_cont+1;
else
v_cont<=0;
if(v_cont<=V_TA-1)
ovga_vs<=1'b0;
else
ovga_vs<=1'b1;
end
end
always @(posedge iclk)
begin
if(irst)
address<=15'h0;
else
begin
if((h_cont<(xpos+H_TA+H_TB+H_TC+LENGTH))&&(h_cont>=(xpos+H_TA+H_TB+H_TC))&&(v_cont<(ypos+V_TA+V_TB+V_TC+WIDTH))&&(v_cont>=(ypos+V_TA+V_TB+V_TC)))
begin
address<=address+1;
ovga_r<=ired;
ovga_g<=igreen;
ovga_b<=iblue;
end
else
begin
ovga_r<=5'h0;
ovga_g<=6'h0;
ovga_b<=5'h0;
end
end
end
always @(negedge ovga_vs)
begin
if(ij==2'b00)
begin
xpos<=xpos+1;
ypos<=ypos+1;
if(ypos+WIDTH==480)
ij<=2'b01;
else if(xpos+LENGTH==640)
ij<=2'b10;
end
else if(ij==2'b01)
begin
xpos<=xpos+1;
ypos<=ypos-1;
if(ypos==1)
ij<=2'b00;
else if(xpos+LENGTH==640)
ij<=2'b11;
end
else if(ij==2'b10)
begin
xpos<=xpos-1;
ypos<=ypos+1;
if(ypos+WIDTH==480)
ij<=2'b11;
else if(xpos==1)
ij<=2'b00;
end

else if(ij==2'b11)
begin
xpos<=xpos-1;
ypos<=ypos-1;
if(ypos==1)
ij<=2'b10;
else if(xpos==1)
ij<=2'b01;
end
end

vga_rom u1(.address(address),.clock(iclk),.q(q),);
endmodule