PLL锁相环的设置
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PLL锁相环的设置
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分类： xs1282011-11-10 22:39120人阅读评论(0)收藏举报
PLL锁相环的设置还是比较简单的，因为东西很死，完全可以照搬。主要配置的就是
REFDV （范围是0到63，CRG参考分频寄存器）和 SYNR（范围是0到15，CRG合成器
寄存器）。
计算公式是PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)，其中OSCCLK为系统
时钟，而PLLCLK为锁相环后的时钟。想要得到PLLCLK的时钟可以对SYNR和REFDV进行
一些配置。
#include "derivative.h"
//锁相环初始化函数
void Init_PLL_16M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(1+1)/(1+1)=32MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 1; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=32/2=16MHz
}
void Init_PLL_24M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(2+1)/(1+1)=48MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 2; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=48/2=24MHz
}
void Init_PLL_32M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(3+1)/(1+1)=64MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 3; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL =
0X80; //总线时钟=64/2=32MHz
}
void Init_PLL_48M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(5+1)/(1+1)=96MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 5; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=96/2=48MHz
}
void Init_PLL_64M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(7+1)/(1+1)=128MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 7; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=48/2=64MHz
}
void Init_PLL_72M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(8+1)/(1+1)=144MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 8; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=144/2=72MHz
}
void Init_PLL_80M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(9+1)/(1+1)=160MHz
REFDV = 1;
//REFDV范围为0~63
SYNR = 9; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=160/2=80MHz
}
void Init_PLL_88M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(10+1)/(1+1)=176MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 10; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=176/2=88MHz
}
void Init_PLL_96M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(11+1)/(1+1)=192MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 11; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=192/2=96MHz
}
void Init_PLL_104M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(12+1)/(1+1)=208MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 12; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=208/2=104MHz
}
vo
id Init_PLL_120M(void)
{
CLKSEL=0X00; // disengage PLL to system
PLLCTL_PLLON=1; // turn on PLL
//PLLCLK=2*OSCCLK*(SYNR+1)/(REFDV+1)
//锁相环时钟=2*16*(14+1)/(1+1)=240MHz
REFDV = 1; //REFDV范围为0~63
SYNR = 14; //SYNR范围为0~15
_asm(nop);
_asm(nop);
_asm(nop); //等待锁相环稳定
while(!(CRGFLG&0X08)); //when pll is steady ,then use it;
//选定锁相环位,Bus Clock=PLLCLK/2;
CLKSEL = 0X80; //总线时钟=240/2=120MHz
}