触摸屏控制芯片ADS7843中文文档

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触摸屏的驱动芯片ADS7843

触摸屏的驱动芯片ADS7843触摸屏由于其体积小、轻便和接口简单的特点，成为一种在嵌入式系统中应用广泛的输入设备。

S3C44B0X通过端口G模拟串行的SIO接口与触摸屏专门的控制芯片ADS7843（由Burr-Brown公司生产）开展数据传输，来完成对触摸屏触摸位置坐标的读取。

触摸屏接口专用芯片ADS7843要完成两件事：一是完成电极电压的切换；二是采集接触点处的电压值，并开展A/D转换。

触摸屏组成：触摸检测部件：安装在显示器屏幕前面，检测用户触摸位置，承受后送触摸屏控制器。

触摸屏控制器：接收触摸点检测装置信息，并将它转换成触点坐标，再送给CPU。

比方ADS7843。

ADS7843是TI 公司生产的4 线电阻触摸屏转换接口芯片。

ADS7843功能：（1）电极电压的切换。

（2）采集接触点处的电压值，并开展A/D转换。

ADS7843特性：（1）可编程控制8位或者12位A/D转换模式。

（2）低导通电阻模拟开关。

（3）实现触摸屏的驱动选择控制（X、Y通道）。

（4）供电电压为2.7~5V。

（5）参考电压VREF为1V~+Vcc。

（6）转换电压的输入范围为0~VREF。

（7）最高转换速率为125kHz。

编程说明：（1）S3C44B0X端口初始化：PCONG（2）S3C44B0X端口初始化：PUPG（3）触摸屏X坐标控制字（4）触摸屏Y坐标控制字（5）触摸点坐标读取过程（6）检测PENIRQ是否为低电平。

如果PENIRQ=0，则认为有接触。

（7）使ADS7843有效、无效（8）向ADS7843发送控制字（9）等待ADS7843 的BUSY管脚从高变低（10）从ADS7843接收数据。

ADS7843使用详解含时序图

CHYAD: MOV AD_CH,#CHY
LCALL AD_RUN
MOV CHYAdResultH,AD_RESULTH
MOV CHYAdResultL,AD_RESULTL
RET
; A/D转换子程序(AD_RUN)
;输入: AD_CH-模式和通道选择命令字
;输出: AD_RESULTH,L ;12 bit的A/D转换值
2 M68VZ328ADS Application Development System User's Manual. Revision 1.4. 2000
3 Burr-Brown IC Data Book
触摸屏的工作原理及典型应用
摘要简要介绍触摸屏的结构及工作原理,并以Burr-Brown公司的触摸屏控制芯片ADS7843为例,介绍触摸屏应用的典型电路和操作。由于ADS7843内置12位A/D,理论上触摸屏的输入坐标识别精度为有效长宽的1/4096。
关键词触摸屏ITO ADS7843嵌入式系统
1触摸屏的基本原理
RL A
DJNZ R2,AD_LOOP
NOP
NOP
NOP
NOP
ADW0: JNB BUSY,AD_WAIT ;等待转换完成
SJMP ADW1
AD_WAIT:
LCALL WATCHDOG
NOP
SJMP ADW0
CLR DIN
ADW1: MOV R2,#12 ;开始读取12bit结果
SETB DCLK
CLR DCLK
CHYAdResultL EQU 3BH
;采集通道CHX+的程序段(CHXAD)
CHXAD: MOV AD_CH,#CHX
LCALL AD_RUN

触摸屏控制器驱动程序设计

触摸屏控制器驱动程序设计在便携式的电子类产品中 ,触摸屏由于其便、灵活、占用空间少等优点 ,已经逐渐取代键盘成为嵌入式计算机系统常选用的人机交互输入设备。

触摸屏输入系统由触摸屏、触摸屏控制器、微控制器及其相应的驱动程序构成。

本文从触摸屏控制器的驱动程序设计着手 ,介绍触摸屏控制器 ADS7843 的内部结构及工作原理和在嵌入式 Linux 操作系统中基于PXA255微处理器的ADS784羽驱动程序设计。

1触摸屏控制器ADS7843的介绍1.1ADS7843的内部结构ADS7843内驻一个多路低导通电阻模拟开关组成的供电-测量电路网络、12bit逐次逼近A/D转换器和异步串行数据输入输出，ADS7843艮据微控制器发来的不同测量命令导通相应的模拟开关 ,以便向触摸屏电极对提供电压 ,并把相应电极上的触点坐标位置所对应的电压模拟量引入A/D转换器，图1为ADS7843内部结构图。

X+、Y+ X-、丫为触摸屏电极模拟电压输入；CS为ADS7843的片选输入信号，低电平有效；DCLK接外部时钟输入 ,为芯片进行 A/D 转换和异步串行数据输入 /输出提供时钟;DIN串行数据输入端，当CS低电平时，输入数据在时钟的上升沿将串行数据锁存；DOUT串行数据输出端，在时钟下降沿数据由此移位输出，当 CS 为高电平时，DOUT呈高阻态。

BUSY为系统忙标志端，当CS为低电平, 且BUSY为高电平时，表示ADS7843正在进行数据转换;VREF参考电压输入端，电压值在+1V到+VCC之间变化；PENIRC为笔触中断，低电平有效;IN3、IN4为辅助ADC转换输入通道；+VCC为电源输入。

图1ADS7843内部结构1.2ADS7843的转换时序ADS7843完成一次数据转换需要与微控制器进行3次通信，第一次微处理器通过异步数据传送向 ADS843 发送控制字 ,其中包括起始位、通道选择、 8/12 位模式、差分 /单端选择和掉电模式选择 ,其后的两次数据传送则是微控制器从 ADS7843 取出 16bitA/D 转换结果数据（最后四位自动补零）,每次通信需要 8 个时钟周期 ,完成一次数据转换共需 24 个时钟周期周2为ADS7843转换时序。

第十八节：ADS7843驱动的320240电阻型触摸屏：

资料范本本资料为word版本，可以直接编辑和打印，感谢您的下载第十八节：ADS7843驱动的320240电阻型触摸屏：地点：__________________时间：__________________说明：本资料适用于约定双方经过谈判，协商而共同承认，共同遵守的责任与义务，仅供参考，文档可直接下载或修改，不需要的部分可直接删除，使用时请详细阅读内容第十八节：ADS7843驱动的320240电阻型触摸屏（1）开场白：320240的触摸屏是由320240液晶显示屏和320240电阻触摸薄膜组成。

320240液晶显示屏披上一层触摸膜的皮就是触摸屏了。

显示和读取触摸信息是各自独立的，我们通过编写程序，两者有机结合起来，让客户产生错觉，以为触摸和显示是一体的。

320240液晶屏的程序在第十五节已经讲过。

现在重点介绍一下电阻触摸薄膜的原理。

它的本质是利用电阻分压的原理。

假如我在桌面上放了一条很长的裸露电阻，我们的手触摸到电阻的某点时，就相当于可调电阻的中间移动点，按到哪一点位置，我们只要通过AD把被分压后的电压读取出来，就知道你的手按到了哪个位置。

一张触摸膜相当于在X轴和Y轴都放了一个很宽很长的裸露电阻，手按到哪一点，只要把该点的X轴和Y轴的分压通过AD读取出来，就可以得到被触摸的X轴和Y轴坐标。

驱动电阻型触摸屏，就相当于单片机驱动一个外部AD转换芯片，这个AD芯片就是ADS7843。

编程技巧：我们要在显示屏上先做一个显示程序，专门用来显示按下去的X轴坐标和Y轴坐标，这样方便我们记录按键的位置信息。

有了具体某个按键的位置信息，我们才可以针对此按键进行后续的触发程序编写。

（2）功能需求：在触摸屏上按下一个矩形按键，此按键马上反显，表示被触发。

同时把相对应的X轴和Y轴坐标数据在液晶屏上显示出来。

（3）硬件原理：跟320240液晶显示屏的接线请参考第十五节。

然后用单片机的4个IO口分别跟ADS7843的DCLK, CS, DIN, DOUT连接。

51单片机程序触摸屏芯片ADS7843驱动

51单片机程序触摸屏芯片ADS7843驱动#include "reg51.h"#include "intrins.h"sbit DCLK=P1^6;sbit CS=P2^2;sbit DIN=P2^3;sbit DOUT=P2^4;sbit BUSY=P2^5;delay(unsigned char i--){while(i--);}void start() //SPI开始{DCLK=0;CS=1;DIN=1;DCLK=1;CS=0;}WriteCharTo7843(unsigned char num) //SPI写数据{unsigned char count=0;DCLK=0;for(count=0;count<8;count++){num<<=1;DIN=CY;DCLK=0; _nop_();_nop_();_nop_(); //上升沿有效DCLK=1; _nop_();_nop_();_nop_();}}ReadFromCharFrom7843() //SPI 读数据{unsigned char count=0;unsigned int Num=0;for(count=0;count<12;count++){Num<<=1;DCLK=1; _nop_();_nop_();_nop_(); //下降沿有效DCLK=0; _nop_();_nop_();_nop_();if(DOUT) Num++;}return(Num);}void ZhongDuan() interrupt 0 //外部中断0 用来接受键盘发来的数据{unsigned int X=0,Y=0;delay(10000); //中断后延时以消除抖动，使得采样数据更准确start(); //启动SPI// while(BUSY); //如果BUSY信号不好使可以删除不用delay(2);WriteCharTo7843(0x90); //送控制字 10010000 即用差分方式读X坐标详细请见有关资料// while(BUSY); //如果BUSY信号不好使可以删除不用delay(2);DCLK=1; _nop_();_nop_();_nop_();_nop_();DCLK=0; _nop_();_nop_();_nop_();_nop_();X=ReadFromCharFrom7843(); //读X轴坐标WriteCharTo7843(0xD0); //送控制字 11010000 即用差分方式读Y坐标详细请见有关资料DCLK=1; _nop_();_nop_();_nop_();_nop_();DCLK=0; _nop_();_nop_();_nop_();_nop_();Y=ReadFromCharFrom7843(); //读Y轴坐标CS=1;}main(){TMOD=0x11; // 记数器0 计数器1 都以 16 位记数TCON=0x00;IE=0x83; //1000 0001 EA=1中断允许,IP=0x01;while(1);//等待触摸中断}。

基于PXA255的触摸屏控制器ADS7843程序设计

基于PXA255的触摸屏控制器ADS7843程序设计来源:网络作者:李外云胡文静刘锦高发布时间:2011-01-25 点击: 121次摘要:在研发具有操作系统的设备时,高质量的设备驱动程序可以大大提高设备的稳定性与可靠性。

本文以触摸屏控制器ADS7843为例,介绍了其内部结构、工作原理,并详细阐述了在Linux操作系统的设备文件系统机制中编写设备驱动程序的过程与方法,同时给出基于PXA255微外理器的触摸屏控制器ADS7843中断方式的驱动程序。

关键词:嵌入式Linux;触摸屏;ADS7843;PXA255微处理器在便携式的电子类产品中,触摸屏由于其便、灵活、占用空间少等优点,已经逐渐取代键盘成为嵌入式计算机系统常选用的人机交互输入设备。

触摸屏输入系统由触摸屏、触摸屏控制器、微控制器及其相应的驱动程序构成。

本文从触摸屏控制器的驱动程序设计着手,介绍触摸屏控制器ADS7843的内部结构及工作原理和在嵌入式Linux操作系统中基于PXA255微处理器的ADS7843驱动程序设计。

1触摸屏控制器ADS7843的介绍1.1ADS7843的内部结构ADS7843内驻一个多路低导通电阻模拟开关组成的供电-测量电路网络、12bit逐次逼近A/D 转换器和异步串行数据输入输出,ADS7843根据微控制器发来的不同测量命令导通相应的模拟开关,以便向触摸屏电极对提供电压,并把相应电极上的触点坐标位置所对应的电压模拟量引入A/D转换器,图1为ADS7843内部结构图。

X+、Y+、X-、Y-为触摸屏电极模拟电压输入;CS为ADS7843的片选输入信号,低电平有效;DCLK接外部时钟输入,为芯片进行A/D转换和异步串行数据输入/输出提供时钟;DIN串行数据输入端,当CS低电平时,输入数据在时钟的上升沿将串行数据锁存;DOUT串行数据输出端,在时钟下降沿数据由此移位输出,当CS 为高电平时,DOUT呈高阻态。

BUSY为系统忙标志端,当CS为低电平,且BUSY为高电平时,表示ADS7843正在进行数据转换;VREF参考电压输入端,电压值在+1V到+VCC之间变化;PENIRQ为笔触中断,低电平有效;IN3、IN4为辅助ADC转换输入通道;+VCC为电源输入。

基于ADS7843的触摸屏控制系统设计

Science &Technology Vision科技视界0引言在电子产品及工业产品的设计中,触摸屏由于其轻便、占用空间少、方便灵活等优点越来越受到设计师及用户的青睐。

触摸屏可作为模拟键盘,使用起来比普通键盘灵活,因为键的位置可根据需要进行改变,并且省去了按键所占用的空间。

触摸屏分为电阻、电容、表面声波、红外线扫描和矢量压力传感等,其中四线电阻触摸屏应用广泛。

1ADS7843简介ADS7843是一款专为四线电阻触摸屏设计的带SPI 接口的12位AD 转换器,内部含模拟电子开关和逐次比较型AD 转换器。

当要采样Y 方向的AD 值时,通过将Y+、Y 一端施加电压,将X+送入AD 转换器得到Y 方向的AD 值;同理可得X 方向的AD 值。

而这些转换均由MCU 通过SPI 方式向ADS7843发送命令来完成。

ADS7843的引脚功能如表1所示。

表1ADS7843的引脚功能ADS7843之所以能实现对触摸屏的控制,是因为其内部结构很容易实现电极电压的切换,并能进行快速A/D 转换。

内部结构如图1所示,A2~A0和SER 为控制寄存器中的控制位,用来进行开关切换和参考电压的选择。

图1ADS7843内部结构2触摸屏控制系统设计以应用广泛的STC89C52作为主控制器,进行触摸控制系统设计。

2.1硬件接口电路设计ADS7843串行接口的一次完整操作需要3×8=24个DCLK 时钟周期,前8个脉冲接收8位的命令,并在第6个脉冲的上升沿开始A/D 转换器进入采样阶段,从第9个脉冲开始进入转换阶段,输出,输出12位采样值,转换结束进入空闲阶段。

直到24个DCLK 结束,CS 置高电平,一次测量结束。

ADS7843采用、转换时序如图2所示。

图2ADS7843采用、转换时序ADS7843与STC89C52的连接图如图3所示。

图3ADS7843与STC89C52的连接图2.2软件设计当用户在触摸屏上的有效区域内点击时,触摸屏的X 方向、Y 方向输出电阻分别随X 和Y 呈线性变化,ADS7843控制器将其分别转换为12位数据,通过中断告知STC89C52需要接收数据,STC89C52接收到数据后进行处理;首先进行触点数据是否有效判断,包括两方面:一是判断是否误操作,即是否是由于人的抖动产生的错误数据;二是ADS7843传过来得数据是否有效,由于刚开始的传过来的第一个基于ADS7843的触摸屏控制系统设计薛大为杨春兰(蚌埠学院机械与电子工程系,安徽蚌埠233030)【摘要】触摸屏在现代电子设备中广泛使用。

半导体传感器AD7683ARMZ中文规格书

AD7680Rev. A | Page 17 of 24SERIAL INTERFACEFigure 20 shows the detailed timing diagram for serialinterfacing to the AD7680. The serial clock provides the conversion clock and also controls the transfer of information from the AD7680 during conversion.The CS signal initiates the data transfer and conversion process. The falling edge of CS puts the track-and-hold into hold mode, takes the bus out of three-state, and samples the analog input. The conversion is also initiated at this point and requires at least 20 SCLK cycles to complete. Once 17 SCLK falling edges have elapsed, the track-and-hold goes back into track mode on the next SCLK rising edge. Figure 20 shows a 24 SCLK transfer that allows a 100 kSPS throughput rate. On the 24th SCLK falling edge, the SDATA line goes back into three-state. If the rising edge of CS occurs before 24 SCLKs have elapsed, the conversion terminates and the SDATA line goes back into three-state; otherwise SDATA returns to three-state on the 24th SCLK falling edge as shown in Figure 20. A minimum of 20 serial clock cycles are required to perform the conversion process and to access data from the AD7680. CS going low provides the first leading zero to be read in by the microcontroller or DSP . The remaining data is then clocked out by subsequent SCLK falling edges beginning with the second leading zero; thus the first falling clock edge on the serial clock has the first leading zero provided and also clocks out the second leading zero. If a 24 SCLK transfer is used as in Figure 20, the data transfer consists of four leading zeros followed by the 16 bits of data, followed by four trailing zeros. The final bit (fourth trailing zero) in the data transfer is valid on the 24th falling edge, having been clocked out on the previous (23rd) falling edge. If a 20 SCLK transfer is used as shown in Figure 21, the data output stream consists of only four leading zeros followed by 16 bits of data with the final bit valid on the 20th SCLK falling edge. A 20 SCLK transfer allows for a shorter cycle time and therefore a faster throughput rate is achieved.03643-0-013SCLK SDATACSFigure 20. AD7680 Serial Interface Timing Diagram—24 SCLK Transfer03643-0-014SCLK SDATA CSFigure 21. AD7680 Serial Interface Timing Diagram—20 SCLK TransferAD7680Rev. A | Page 18 of 24It is also possible to take valid data on each SCLK rising edge rather than falling edge, since the SCLK cycle time is long enough to ensure the data is ready on the rising edge of SCLK. However, the first leading zero is still driven by the CS falling edge, and so it can be taken on only the first SCLK falling edge. It may be ignored and the first rising edge of SCLK after the CS falling edge would have the second leading zero provided and the 23rd rising SCLK edge would have the final trailing zero provided. This method may not work with mostmicrocontrollers/DSPs but could possibly be used with FPGAs and ASICs. AD7680 TO ADSP-218x The ADSP-218x family of DSPs can be interfaced directly to theAD7680 without any glue logic required. The SPORT control register should be set up as follows:TFSW = RFSW = 1, Alternate FramingINVRFS = INVTFS = 1, Active Low Frame SignalDTYPE = 00, Right Justify DataSLEN = 0111, 8-Bit Data-WordsISCLK = 1, Internal Serial ClockTFSR = RFSR = 0, Frame First WordIRFS = 0ITFS = 1To implement the power-down mode, SLEN should be set to 0111 to issue an 8-bit SCLK burst. The connection diagram is shown in Figure 22. The ADSP-218x has the TFS and RFS of the SPORT tied together, with TFS set as an output and RFS set as an input. The DSP operates in alternate framing mode and the SPORT control register is set up as described. Transmit and receive autobuffering is used in order to get a 24 SCLK transfer. Each buffer contains three 8-bit words. The frame synchroniza-tion signal generated on the TFS is tied to CS , and as with all signal processing applications, equidistant sampling is necessary. In this example, the timer interrupt is used to control the sampling rate of the ADC. 03643-0-015*ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. Interfacing to the ADSP-218x The timer register is loaded with a value that provides an interrupt at the required sample interval. When an interrupt is received, the values in the transmit autobuffer start to be transmitted and TFS is generated. The TFS is used to control the RFS and therefore the reading of data. The data is stored in the receive autobuffer for processing or to be shifted later. The frequency of the serial clock is set in the SCLKDIV register. When the instruction to transmit with TFS is given, i.e., TX0 = AX0, the state of the SCLK is checked. The DSP waits until the SCLK has gone high, low, and high again before transmission starts. If the timer and SCLK values are chosen such that the instruction to transmit occurs on or near the rising edge of SCLK, the data may be transmitted or it may wait until the next clock edge.。

ads7843中文资料

•’—•p 应用与设计¡¤³—˜”“触摸屏接口解放军信息工程大学胡冰吴升艳岳春生Touch Scre e n Inte r f a ce Ch i p ADS7843¨Õ¢ÉÎÇ·Õ³ÈÅÎÇÙÁÎ¹ÕÅ£ÈÕÎÓÈÅÎÇ摘要š简单介绍了¡¤³—˜”“的功能特点和工作原理Œ探讨了¡¤³—˜”“触摸屏接口芯片的模式选择和应用技巧Œ最后给出了基于该系统的一个实际使用方案"关键词š触摸屏控制器›嵌入式系统›¡¤³—˜”“分类号š´°’—“文献标识码š¢文章编号š‘••–•–™——ˆ’••’‰•—•••’—••“图‘¡¤³—˜”“的连接关系¡¤³—˜”“触摸屏接口‘前言随着生活中类似于°¤¡的手持设备的越来越多Œ彩色¬£¤触摸屏也变得越来越普及Œ并逐渐成为当今的主流配置"触摸屏分为电阻!电容!表面声波!红外线扫描和矢量压力传感等Œ其中使用最多的是四线或五线电阻触摸屏"四线电阻触摸屏是由两个透明电阻膜构成的Œ在它的水平和垂直电阻网上施加电压Œ就可通过¡•¤转换面板在触摸点测量出电压Œ从而对应出坐标值"本文除了简单介绍¡¤³—˜”“的特点和原理之外Œ主要讨论触摸屏控制器的使用技巧Œ同时给出了具体的应用连接图"’¡¤³—˜”“的功能特性¡¤³—˜”“是´©公司生产的”线电阻触摸屏转换接口芯片"它是一款具有同步串行接口的‘’位取样模数转换器"在‘’•Ë¨Ú吞吐速率和’Ž—¶电压下的功耗为—••L ·Œ而在关闭模式下的功耗仅为•Ž•L ·"因此Œ¡¤³—˜”“以其低功耗和高速率等特性Œ被广泛应用在采用电池供电的小型手持设备上"¡¤³—˜”“采用³³¯°•‘–引脚封装形式Œ温度范围是•”•*‹˜•e "¡¤³—˜”“具有两个辅助输入ˆ©®“!©®”‰Œ可设置为˜位或‘’位模式"其外部连接电路如图‘所示Œ该电路的工作电压¶ÃÃ在’Ž—*•Ž’•¶之间Œ基准电压¶ÒÅÆ介于‘¶*‹¶ÃÃ"该电路的基准电压确定了转换器的输入范围Œ输出数据中每个数字位代表的模拟电压等于基准电压除以”•™–"平均基准输入电流由¡¤³—˜”“的转换率来确定"以下是¡¤³—˜”“的主要引脚功能š¸‹!¹‹!¸•!¹•š转换器模拟输入端Œ实际上是一个”通道多路器›¤£¬«š外部时钟输入引脚›£³š片选端›参考文献‘Ž张芳兰Ž´-³“’•£’ØØ用户指南Ž电子工业出版社Œ‘™™™Ž–’Ž赵保经Ž¡•¤和¤•¡转换器应用手册Ž上海科学普及出版社Œ‘™™•“Ž-ÁØÉÍŽ‹•¶³ÉÎÇÌÅ•³ÕÐÐÌÙŒ‘-ÓÐÓŒ‘–•¢ÉÔ³ÅÌÆ•£ÁÌÉÂÒÁÔÉÎÇ¡¤£Œ’•••”Ž闻亭公司Ž´-³“’•£’¸¸高速数字信号处理器原理与应用Ž‘™™˜Œ”•Ž´ÅØÁÓ©ÎÓÔÒÕÍÅÎÔÓ©ÎÃŽ´-³“’•£’•ØµÓÅÒ‡Ó§ÕÉÄÅŒ‘™™™收稿日期š’••‘•‘’•’‘咨询编号š•’•—‘•海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ　为您提供各种ＩＣ中文资料•’˜•5国外电子元器件6’••’年第—期’••’年—月¤©®š串行输入Œ其控制数据通过该引脚输入›¤¯µ´š串行数据输出Œ用于输出转换后的触摸位置数据Œ最大数为二进制的”•™•›©®“!©®”š辅助输入引脚›°¥®©²±š°¥®中断引脚Œ可用于在触摸显示屏后引发一个中断"“工作原理¡¤³—˜”“是一款连续近似记录ˆ³¡²‰的¡•¤转换器"可通过连结触摸屏¸‹将触摸信号输入到¡•¤转换器Œ同时打开¹‹和¹•驱动Œ然后数字化¸‹的电压Œ从而得到当前¹位置的测量结果"同理也可得到¸方向的坐标"具体设置和使用方法可查阅´©公司的¡¤³—˜”“数据手册Œ下面主要介绍¡¤³—˜”“的模式设置!°¥®中断引脚的使用和软件编程方法"“Ž‘模式设置¡¤³—˜”“有差分ˆ¤©¦¦¥²¥®´©¡¬‰和单端ˆ³©®2§¬¥•¥®¤¥¤-¯¤¥‰两种工作模式"这两种模式对转换后的精度和可靠性有一些影响"如果将¡•¤转换器配置为读绝对电压ˆ单端模式‰方式Œ那么驱动ˆ¤²©¶¥²‰电压的下降将导致转换输入数据的错误"而如果配置为差分模式Œ则可以避免上述错误"当触摸屏被按下时Œ有两种情况可影响接触点的电压š一种是当触摸到显示屏时Œ会导致触摸屏外层振动›另一种是触摸屏顶层和低层之间的寄生电容引起的电流振荡以及在¡¤³—˜”“输入引脚上引起的电压振荡"这两种情况都可导致触摸屏上的电压发生振荡以及增加¤£值稳定的时间"在单端模式中Œ一旦在触摸屏上检测到一次触摸事件Œ电路系统将发送一串控制字节给¡¤³—˜”“Œ并要求它进行一次转换"然后¡¤³—˜”“将在获取周期的起始点通过内部¦¥´开关给面板提供电压Œ而这将导致触摸点电压的升高"正如上面所介绍的Œ上升的电压在最终稳定之前会振荡一段时间"当获取周期结束后Œ所有的¦¥´开关关闭Œ¡•¤转换器进入转换周期"如果在转换周期期间Œ没有发出下一个控制字节Œ¡¤³—˜”“将进入低功耗模式并等待下一条指令"由于面板上分布有大量电容Œ特别是滤波噪音Œ因此Œ应该注意设置好对应于¸坐标或¹坐标上的电压"在单端模式中Œ输入电压必须在¤ÁÔÁ©Î×ÏÒÄ的最后三个时钟周期期间设置Œ否则将产生错误"除了内部¦¥´开关从获取周期开始到转换周期结束期间一直保持打开状态以外Œ差分模式的操作类似于单端模式"加在面板上的电压将成为¡•¤转换器的基准电压Œ提供一个度量比操作"这意味着如果加在面板上的电压发生变化ˆ由于电源!驱动电阻!温度或触摸屏电阻等原因‰Œ¡•¤转换器的度量比操作将对这种变化进行补偿"如果在当前转换周期发向¡¤³—˜”“的下一个控制字节所选择的通道与前一个控制字节相同Œ那么在当前转换完成后开关仍然不会关闭"在这两种模式中Œ¡¤³—˜”“只有“个时钟周期可以从触摸屏上获取ˆ取样‰输入模拟电压Œ因此Œ为了¡¤³—˜”“可以获取正确的电压Œ输入电压必须在“个时钟周期的时间范围内设置好"打开驱动将引起触摸屏的电压快速升高到最终值"为了得到正确的转换数据Œ获取必须在触摸屏完全设置好时完成"获取的方式有两种š一种是采用单端模式Œ即采用相对较慢的时钟扩展获取时间ˆ三个时钟周期‰›二是采用差分模式Œ即用相对较快的时钟在第一个转换周期内设置电压Œ在第二个转换周期获取准确电压"该方式的两个控制字节相同Œ且内部¸•¹开关在首次转换后不会关闭"由于首次转换期间电压还不稳定Œ因此应当丢弃首次转换的结果"使用第二种方式的另一个优点是功耗低"因为在全部转换后Œ¡¤³—˜”“会进入低功耗模式来等待下一次取样周期›对于慢时钟Œ下一次取样可能在当前转换结束后立即进入取样周期Œ而没有时间进入低功耗模式"实际在单端模式下不能使用快速时钟"差分模式还具有以下两个优点š第一个优点是能够在不扩展转换器获取时间的条件下用很长的设置时间处理触摸屏Œ即触摸屏电压可以有足够的时间稳定下来"第二个优点是¡¤³—˜”“通过快速时钟可以进入低功耗模式Œ从而可以节约电池能量"因此Œ通常建议使用差分模式"“Ž’°¥®中断引脚的使用°¥®中断引脚的主要作用是让设计者可以完全控制¡¤³—˜”“的低功耗操作模式"图’所示是其模式操作连接示意图"图中Œ©•¯‘和©•¯’是引自¥°—’‘’的通用目的输入•输出口"当电源加入系统且转换器被设置ˆ°¤‘Œ°¤••••‰之后Œ器件进入低功耗模式"而当未触摸面板时Œ¡¤³—˜”“内部的二极海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ　为您提供各种ＩＣ中文资料•’™•¡¤³—˜”“触摸屏接口图“采用判断两次的方法来克服触摸屏信号的抖动图”采用最后的结果来克服触摸屏信号的抖动图’¡¤³—˜”“ˆ°¤•Œ°¤‘•••‰下的示意图管没有偏压Œ因此没有电流流过ˆ忽略漏流‰›当触摸面板时Œ¹•将提供一条电流ˆ©‰通路Œ这时¸‹!¸•和¹‹处于高阻状态Œ电流经过‘••Ë8电阻和中断二极管Œ°¥®©²±被拉低Œ从而通过©•¯’上一个不超过•Ž–•¶的电压唤醒£°µŒ然后¥°—’‘’再拉低©•¯‘和©•¯’上的电位Œ同时对¡¤³—˜”“控制寄存器写一个字节以进行转换初始化"为了转换°¥®©²±二极管上的偏置电压Œ¥°—’‘’必须拉低©•¯‘和©•¯’上的电压"否则Œ如果在转换期间二极管上有一个前向偏压Œ那么附加的电流将引起错误的输入数据"“Ž“错误触发由于¸‹输入引脚与°¥®中断输出相连Œ因此在¸‹上的噪声可能引起触摸屏的错误触发"设计时可以在°¥®中断输出引脚上连结一个²£滤波器ˆ可对地连结一个‘8的电阻和一个•Ž•‘L ¦的电容‰Œ以过滤噪声脉冲并避免错误触发"“Ž”差分模式下的软件流程图“和图”所示的两种算法假设¡¤³—˜”“配置成差分模式Œ每次转换为‘–个时钟Œ¸轴坐标的结果在¤¡´¡¸中Œ¹轴的坐标在¤¡´¡¹中"其中图“的例子采用的是判断两次的方法来克服触摸屏信号的抖动"¤¡´¡‘用于存储当前转换的结果Œ¤¡´¡’用于存储上一次转换的结果Œ当两次结果相同时Œ转换数据有效"但是Œ应当注意š当输入电压的振动频率和取样频率相近时Œ可能会漏掉正确结果"图”的例子是将最后的转换结果ˆ第Î次‰作为有效转换"可以看出š该方式更加简单Œ但该方法只对某一类触摸屏有效Œ且/Î0的具体值依赖于¡¤³—˜”“输入电压的设置时间Œ同时Œ在确定/Î0值以前还需要对一些触摸屏进行测试"参考文献‘Ž刘永智Œ杨开愚Ž液晶显示技术Ž电子科技大学出版社’Ž¡¤³—˜”“¤ÁÔÁÓÈÅÅÔ´©Œªµ¬¹Œ’••‘收稿日期š’••‘•‘’•’•咨询编号š•’•—‘‘海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ　为您提供各种ＩＣ中文资料。

ADS7843简介及应用

ADS7843簡介及應用
1
OUTLINE
1.ADS7843特性 2.ADS7843腳位定義 3.ADS7843方塊圖 4.ADS7843廠內之應用
2
1.ADS7843特性
a.4-WIRE T/P INTERFACE b.SINGLE SUPPLY：2.7V~5.0V c.SERIAL INTERFACE d.PROGRAMMABLE 8-OR 12-BIT RESOLUTION e.2 AUXILIARY ANALOG INPUTS
HandIN為讀取I18_Bit，ADS7843應用為8_Bit，試問TFT Control Box上可變電阻在軟體上需做幾階調的變化較適當?
2^8=256 可變化總階調 2^6=64 RGB各佔6_Bit 256/64=4 故軟體應做每調四階實際輸出變化一次較適當
開關控制腳
Out to control A/D 階數變化值
10
3. Timing characteristics diagram
11
Timing characteristics diagram SPI (System Interface)
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
6
4-WIRE T/P 動作原理
7
TOUCH PANEL軟體
int runTP(void) { while (PENIRQ); 中斷指令 Xdata=HandShack(scanX_comm); Ydata=HandShack(scanY_comm); if(((Xdata>=0x0ddd)&&(Xdata<=0x0fff))&&((Ydata>=0x0000)&&(Ydata<=0x0333))) return 1; else if(((Xdata>=0x0444)&&(Xdata<=0x0777))&&((Ydata>=0x0000)&&(Ydata<=0x0444))) return 2; else if(((Xdata>=0x0444)&&(Xdata<=0x0777))&&((Ydata>=0x0ccc)&&(Ydata<=0x0fff))) return 3; else if(((Xdata>=0x0ddd)&&(Xdata<=0x0fff))&&((Ydata>=0x0ddd)&&(Ydata<=0x0fff))) return 4; else if(((Xdata>=0x0555)&&(Xdata<=0x0aaa))&&((Ydata>=0x0555)&&(Ydata<=0x0aaa))) return 5; else return 0; } X+

ADS7843EG4中文资料

FEATURESq 4-WIRE TOUCH SCREEN INTERFACE q RATIOMETRIC CONVERSION q SINGLE SUPPLY: 2.7V to 5V q UP TO 125kHz CONVERSION RATE q SERIAL INTERFACEq PROGRAMMABLE 8- OR 12-BIT RESOLUTION q 2 AUXILIARY ANALOG INPUTS qFULL POWER-DOWN CONTROLDESCRIPTIONThe ADS7843 is a 12-bit sampling Analog-to-Digital Con-verter (ADC) with a synchronous serial interface and low on-resistance switches for driving touch screens. Typical power dissipation is 750µW at a 125kHz throughput rate and a +2.7V supply. The reference voltage (V REF ) can be varied between 1V and +V CC , providing a corresponding input voltage range of 0V to V REF . The device includes a shutdown mode which reduces typical power dissipation to under 0.5µW. The ADS7843 is specified down to 2.7V operation.Low power, high speed, and onboard switches make the ADS7843 ideal for battery-operated systems such as per-sonal digital assistants with resistive touch screens and other portable equipment. The ADS7843 is available in an SSOP-16 package and is specified over the –40°C to +85°C temperature range.APPLICATIONSq PERSONAL DIGITAL ASSISTANTS q PORTABLE INSTRUMENTS q POINT-OF-SALES TERMINALS q PAGERSqTOUCH SCREEN MONITORSTOUCH SCREEN CONTROLLERCSDIN DOUTBUSYDCLKX+PENIRQX –Y+Y –IN3IN4V REFADS7843SBAS090B – SEPTEMBER 2000 – REVISED MAY 2002PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Copyright © 2001, Texas Instruments IncorporatedPlease be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.US Patent No. 6246394ADS78432SBAS090BPIN NAME DESCRIPTION1+V CC Power Supply, 2.7V to 5V.2X+X+ Position Input. ADC input Channel 1.3Y+Y+ Position Input. ADC input Channel 2.4X –X – Position Input 5Y –Y – Position Input 6GND Ground7IN3Auxiliary Input 1. ADC input Channel 3.8IN4Auxiliary Input 2. ADC input Channel 4.9V REF Voltage Reference Input 10+V CC Power Supply, 2.7V to 5V.11PENIRQ Pen Interrupt. Open anode output (requires 10k Ωto 100k Ω pull-up resistor externally).12DOUTSerial Data Output. Data is shifted on the falling edge of DCLK. This output is high impedance when CS is HIGH.13BUSY Busy Output. This output is high impedance when CS is HIGH.14DIN Serial Data Input. If CS is LOW, data is latched on rising edge of DCLK.15CS Chip Select Input. Controls conversion timing and enables the serial input/output register.16DCLKExternal Clock Input. This clock runs the SAR con-version process and synchronizes serial data I/O.ABSOLUTE MAXIMUM RATINGS (1)+V CC to GND ........................................................................–0.3V to +6V Analog Inputs to GND ............................................–0.3V to +V CC + 0.3V Digital Inputs to GND .............................................–0.3V to +V CC + 0.3V Power Dissipation..........................................................................250mW Maximum Junction Temperature...................................................+150°C Operating Temperature Range ........................................–40°C to +85°C Storage Temperature Range .........................................–65°C to +150°C Lead Temperature (soldering, 10s)...............................................+300°C NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings ”may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.This integrated circuit can be damaged by ESD. Texas Instru-ments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.12345678+V CC X+Y+X –Y –GND IN3IN4DCLK CS DIN BUSY DOUT PENIRQ +V CC V REF161514131211109ADS7843PIN CONFIGURATIONTop ViewSSOPPIN DESCRIPTIONMAXIMUM INTEGRAL SPECIFIED LINEARITY PACKAGE TEMPERATUREPACKAGE ORDERING TRANSPORT PRODUCT ERROR (LSB)PACKAGE-LEADDESIGNATOR (1)RANGE MARKING NUMBER MEDIA, QUANTITY ADS7843E±2SSOP-16DBQ–40°C to +85°CADS7843E ADS7843E Rails, 100"""""ADS7843EADS7843E/2K5Tape and Reel, 2500NOTES: (1) For the most current specifications and package information, refer to our web site at .PACKAGE/ORDERING INFORMATIONADS78433SBAS090BPARAMETER CONDITIONSMIN TYPMAX UNITS ANALOG INPUTFull-Scale Input Span Positive Input – Negative Input0V REF V Absolute Input Range Positive Input –0.2+V CC +0.2V Negative Input–0.2+0.2V Capacitance 25pF Leakage Current0.1µA SYSTEM PERFORMANCE Resolution12Bits No Missing Codes 11Bits Integral Linearity Error ±2LSB (1)Offset Error±6LSB Offset Error Match 0.1 1.0LSB Gain Error±4LSB Gain Error Match 0.1 1.0LSB Noise30µVrms Power-Supply Rejection 70dB SAMPLING DYNAMICS Conversion Time 12Clk Cycles Acquisition Time 3Clk CyclesThroughput Rate125kHz Multiplexer Settling Time 500ns Aperture Delay 30ns Aperture Jitter100ps Channel-to-Channel Isolation V IN = 2.5Vp-p at 50kHz100dBSWITCH DRIVERS On-Resistance Y+, X+5ΩY –, X –6ΩREFERENCE INPUT Range 1.0+V CC V Resistance CS = GND or +V CC 5G ΩInput Current1340µA f SAMPLE = 12.5kHz2.5µA CS = +V CC0.0013µADIGITAL INPUT/OUTPUT Logic FamilyCMOSLogic Levels, Except PENIRQ V IH | I IH | ≤ +5µA +V CC • 0.7+V CC +0.3V IL | I IL | ≤ +5µA –0.3+0.8V V OH I OH = –250µA +V CC • 0.8V V OL I OL = 250µA0.4V PENIRQ V OLT A = 0°C to +85°C, 100k Ω Pull-Up0.8VData FormatStraight BinaryPOWER-SUPPLY REQUIREMENTS +V CCSpecified Performance 2.73.6V Quiescent Current280650µA f SAMPLE = 12.5kHz 220µA Shutdown Mode with 3µA DCLK = DIN = +V CCPower Dissipation +V CC = +2.7V1.8mW TEMPERATURE RANGE Specified Performance–40+85°CELECTRICAL CHARACTERISTICSAt T A = –40°C to +85°C, +V CC = +2.7V, V REF = +2.5V, f SAMPLE = 125kHz, f CLK = 16 • f SAMPLE = 2MHz, 12-bit mode, and digital inputs = GND or +V CC , unless otherwise noted.ADS7843ENOTE: (1) LSB means Least Significant Bit. With V REF equal to +2.5V, 1LSB is 610µV.ADS78434SBAS090BTYPICAL CHARACTERISTICSAt T A = +25°C, +V CC = +2.7V, V REF = +2.5V, f SAMPLE = 125kHz, and f CLK = 16 • f SAMPLE = 2MHz, unless otherwise noted.SUPPLY CURRENT vs +V CC3.5252.54+V CC (V)S u p p l y C u r r e n t (µA )3203002802602402202001804.53MAXIMUM SAMPLE RATE vs +V CC3.5252.54+V CC (V)S a m p l e R a t e (H z )1M100k10k1k4.53SUPPLY CURRENT vs TEMPERATURE20–40100–2040Temperature (°C)S u p p l y C u r r e n t (µA )4003503002502001501006080CHANGE IN GAIN vs TEMPERATURE20–40100–2040Temperature (°C)D e l t a f r o m +25˚C (L S B )0.150.100.050.00–0.05–0.10–0.156080CHANGE IN OFFSET vs TEMPERATURE20–40100–2040Temperature (°C)D e l t a f r o m +25˚C (L S B )0.60.40.20.0–0.2–0.4–0.66080POWER-DOWN SUPPLY CURRENTvs TEMPERATURE20–40100–2040Temperature (°C)S u p p l y C u r r e n t (n A )140120100806040206080ADS78435SBAS090BTYPICAL CHARACTERISTICS (Cont.)At T A = +25°C, +V CC = +2.7V, V REF = +2.5V, f SAMPLE = 125kHz, and f CLK = 16 • f SAMPLE= 2MHz, unless otherwise noted.REFERENCE CURRENT vs SAMPLE RATE751252550100Sample Rate (kHz)R e f e r e n c e C u r r e n t (µA )14121086420REFERENCE CURRENT vs TEMPERATURE20–40100–2040Temperature (°C)R e f e r e n c e C u r r e n t (µA )1816141210866080SWITCH-ON RESISTANCE vs +V CC (X+, Y+: +V CC to Pin; X –, Y –: Pin to GND)3.5252.54+V CC (V)R O N (Ω)18765432 4.53SWITCH-ON RESISTANCE vs TEMPERATURE (X+, Y+: +V CC to Pin; X –, Y –: Pin to GND)20–40100–2040Temperature (°C)R O N (Ω)18765432608021.81.61.41.210.80.60.40.20L S B E r r o r20406080100120140160180200Sampling Rate (kHz)MAXIMUM SAMPLING RATE vs RINTHEORY OF OPERATIONThe ADS7843 is a classic Successive Approximation Regis-ter (SAR) ADC. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µs CMOS process.The basic operation of the ADS7843 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 1V and +V CC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7843.The analog input to the converter is provided via a four-channel multiplexer. A unique configuration of low on-resis-tance switches allows an unselected ADC input channel to provide power and an accompanying pin to provide ground for an external device. By maintaining a differential input to the converter and a differential reference architecture, it is pos-sible to negate the switch’s on-resistance error (should this be a source of error for the particular measurement).ANALOG INPUTSee Figure 2 for a block diagram of the input multiplexer on the ADS7843, the differential input of the ADC, and the converter’s differential reference. Table I and Table II show the relation-ship between the A2, A1, A0, and SER/DFR control bits and the configuration of the ADS7843. The control bits are pro-vided serially via the DIN pin—see the Digital Interface section of this data sheet for more details.When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs (see Figure 2) is captured on the internal capacitor array. The input current on the analog inputs depends on the conversion rate of the device. During the sample period, the source must charge the internal sampling capacitor (typically 25pF). After the capacitor has been fully charged, there is no further input current. The rate of charge transfer from the analog source to the converter is a function of conversion rate.TABLE I. Input Configuration, Single-Ended Reference Mode (SER/DFR HIGH).NOTE: (1) Internal node, for clarification only—not directly accessible by the user.A2A1A0X+Y+IN3IN4–IN(1)X SWITCHES Y SWITCHES+REF(1)–REF(1) 001+IN–Y OFF ON+Y–Y 101+IN–X ON OFF+X–X 010+IN GND OFF OFF+V REF GND 110+IN GND OFF OFF+V REF GND NOTE: (1) Internal node, for clarification only—not directly accessible by the user.TABLE II. Input Configuration, Differential Reference Mode (SER/ LOW).ADS7843 6SBAS090BFIGURE 2. Simplified Diagram of Analog Input.REFERENCE INPUTThe voltage difference between +REF and –REF (shown in Figure 2) sets the analog input range. The ADS7843 will operate with a reference in the range of 1V to +V CC. There are several critical items concerning the reference input and its wide voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 4096. Any offset or gain error inherent in the ADC will appear to increase, in terms of LSB size, as the reference voltage is reduced. For example, if the offset of a given converter is 2LSBs with a 2.5V reference, it will typically be 5LSBs with a 1V reference. In each case, the actual offset of the device is the same, 1.22mV. With a lower reference voltage, more care must be taken to provide a clean layout including adequate bypassing, a clean (low noise, low ripple) power supply, a low-noise reference, and a low-noise input signal.The voltage into the V REF input is not buffered and directly drives the Capacitor Digital-to-Analog Converter (CDAC) por-tion of the ADS7843. Typically, the input current is 13µA with V REF = 2.7V and f SAMPLE = 125kHz. This value will vary by a few microamps depending on the result of the conversion. The reference current diminishes directly with both conversion rate and reference voltage. As the current from the reference is drawn on each bit decision, clocking the converter more quickly during a given conversion period will not reduce overall current drain from the reference.There is also a critical item regarding the reference when making measurements where the switch drivers are on. For this discussion, it’s useful to consider the basic operation of the ADS7843 as shown in Figure 1. This particular applica-tion shows the device being used to digitize a resistive touch screen. A measurement of the current Y position of the pointing device is made by connecting the X+ input to the ADC, turning on the Y+ and Y– drivers, and digitizing the voltage on X+ (shown in Figure 3). For this measurement, the resistance in the X+ lead does not affect the conversion (it does affect the settling time, but the resistance is usually small enough that this is not a concern).FIGURE 3.Simplified Diagram of Single-Ended Reference (SER/DFR HIGH, Y Switches Enabled, X+ isAnalog Input).ADS78437 SBAS090B ADS78438SBAS090BFIGURE 5. Conversion Timing, 24 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with DedicatedSerial Port.However, since the resistance between Y+ and Y – is fairly low,the on-resistance of the Y drivers does make a small differ-ence. Under the situation outlined so far, it would not be possible to achieve a 0V input or a full-scale input regardless of where the pointing device is on the touch screen because some voltage is lost across the internal switches. In addition,the internal switch resistance is unlikely to track the resistance of the touch screen, providing an additional source of error.This situation can be remedied as shown in Figure 4. By setting the SER/DFR bit LOW, the +REF and –REF inputs are connected directly to Y+ and Y –. This makes the A/D conver-sion ratiometric. The result of the conversion is always a percentage of the external resistance, regardless of how it changes in relation to the on-resistance of the internalFIGURE 4. Simplified Diagram of Differential Reference (SER/DFR LOW, Y Switches Enabled, X+ is Analog Input).switches. Note that there is an important consideration regard-ing power dissipation when using the ratiometric mode of operation, see the Power Dissipation section for more details.As a final note about the differential reference mode, it must be used with +V CC as the source of the +REF voltage and cannot be used with V REF . It is possible to use a high precision reference on V REF and single-ended reference mode for mea-surements which do not need to be ratiometric. Or, in some cases, it could be possible to power the converter directly from a precision reference. Most references can provide enough power for the ADS7843, but they might not be able to supply enough current for the external load (such as a resistive touch screen).DIGITAL INTERFACEFigure 5 shows the typical operation of the ADS7843’s digital interface. This diagram assumes that the source of the digital signals is a microcontroller or digital signal processor with a basic serial interface. Each communication between the pro-cessor and the converter consists of eight clock cycles. One complete conversion can be accomplished with three serial communications, for a total of 24 clock cycles on the DCLK input.The first eight clock cycles are used to provide the control byte via the DIN pin. When the converter has enough information about the following conversion to set the input multiplexer,switches, and reference inputs appropriately, the converter enters the acquisition (sample) mode and, if needed, the internal switches are turned on. After three more clock cycles,the control byte is complete and the converter enters the conversion mode. At this point, the input sample-and-hold goes into the hold mode and the internal switches may turn off. TheADS78439SBAS090B1DCLKCS8111DOUT BUSYSDIN CONTROL BITSSCONTROL BITS109876543210111098118next 12th clock cycles accomplish the actual A/D conversion.If the conversion is ratiometric (SER/DFR LOW), the internal switches are on during the conversion. A 13th clock cycle is needed for the last bit of the conversion result. Three more clock cycles are needed to complete the last byte (DOUT will be LOW). These will be ignored by the converter.Control ByteSee Figure 5 for the placement and order of the control bits within the control byte. Tables III and IV give detailed informa-tion about these bits. The first bit, the ‘S ’ bit, must always be HIGH and indicates the start of the control byte. The ADS7843will ignore inputs on the DIN pin until the start bit is detected.The next three bits (A2-A0) select the active input channel or channels of the input multiplexer (see Tables I and II and Figure 2). The MODE bit determines the number of bits for each conversion, either 12 bits (LOW) or 8 bits (HIGH).The SER/DFR bit controls the reference mode: either single-ended (HIGH) or differential (LOW). (The differential mode is also referred to as the ratiometric conversion mode.) In single-ended mode, the converter ’s reference voltage is always the difference between the V REF and GND pins. In differential mode, the reference voltage is the difference between the currently enabled switches. See Tables I and II and Figures 2through 4 for more information. The last two bits (PD1-PD0)select the power-down mode as shown in Table V. If both inputs are HIGH, the device is always powered up. If both inputs are LOW, the device enters a power-down mode between conversions. When a new conversion is initiated, the device will resume normal operation instantly —no delay is needed to allow the device to power up and the very first conversion will be valid. There are two power-down modes:one where PENIRQ is disabled and one where it is enabled.PD1PD0PENIRQ DESCRIPTIONEnabledPower-down between conversions. When each conversion is finished, the converter enters a low power mode. At the start of the next conversion,the device instantly powers up to full power.There is no need for additional delays to assure full operation and the very first conversion is valid. The Y – switch is on while in power-down.01Disabled Same as mode 00, except PENIRQ is disabled.The Y – switch is off while in power-down mode.10Disabled Reserved for future use.11DisabledNo power-down between conversions, device is always powered.TABLE V. Power-Down Selection.FIGURE 6. Conversion Timing, 16 Clocks per Conversion, 8-bit Bus Interface. No DCLK Delay Required with DedicatedSerial Port.BIT NAME DESCRIPTION7SStart Bit. Control byte starts with first HIGH bit on DIN. A new control byte can start every 16th clock cycle in 12-bit conversion mode or every 12th clock cycle in 8-bit conversion mode.6-4A2-A0Channel Select Bits. Along with the SER/DFR bit,these bits control the setting of the multiplexer input,switches, and reference inputs, see Tables I and II.3MODE12-Bit/8-Bit Conversion Select Bit. This bit controls the number of bits for the following conversion: 12bits (LOW) or 8 bits (HIGH).2 SER/DFRSingle-Ended/Differential Reference Select Bit. Along with bits A2-A0, this bit controls the setting of the multiplexer input, switches, and reference inputs, see Tables I and II.1-0PD1-PD0Power-Down Mode Select Bits. See Table V for details.TABLE IV. Descriptions of the Control Bits within the ControlByte.Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0(MSB)(LSB)SA2A1A0MODE SER/DFRPD1PD0TABLE III. Order of the Control Bits in the Control Byte.16-Clocks per ConversionThe control bits for conversion n + 1 can be overlapped with conversion ‘n ’ to allow for a conversion every 16 clock cycles,as shown in Figure 6. This figure also shows possible serial communication occurring with other serial peripherals between each byte transfer between the processor and the converter.ADS784310SBAS090BFIGURE 8. Ideal Input Voltages and Output Codes.This is possible provided that each conversion completes within 1.6ms of starting. Otherwise, the signal that has been captured on the input sample-and-hold may droop enough to affect the conversion result. Note that the ADS7843 is fully powered while other serial communications are taking place during a conversion.Digital TimingFigure 7 and Table VI provide detailed timing for the digital interface of the ADS7843.SYMBOL DESCRIPTION MIN TYPMAXUNITS t ACQ Acquisition Time1.5µs t DS DIN Valid Prior to DCLK Rising 100ns t DH DIN Hold After DCLK HIGH 10ns t DO DCLK Falling to DOUT Valid 200ns t DV CS Falling to DOUT Enabled 200ns t TR CS Rising to DOUT Disabled 200ns t CSS CS Falling to First DCLK Rising 100ns t CSH CS Rising to DCLK Ignored0ns t CH DCLK HIGH 200ns t CL DCLK LOW200ns t BD DCLK Falling to BUSY Rising 200ns t BDV CS Falling to BUSY Enabled 200ns t BTRCS Rising to BUSY Disabled200nsTABLE VI. Timing Specifications (+V CC = +2.7V and Above,T A = –40°C to +85°C, C LOAD = 50pF).FIGURE 7. Detailed Timing Diagram.Data FormatThe ADS7843 output data is in Straight Binary format, as shown in Figure 8. This figure shows the ideal output code for the given input voltage and does not include the effects of offset, gain, or noise.8-Bit ConversionThe ADS7843 provides an 8-bit conversion mode that can be used when faster throughput is needed and the digital result is not as critical. By switching to the 8-bit mode, a conversion is complete four clock cycles earlier. This could be used in conjunction with serial interfaces that provide 12-bit transfers or two conversions could be accomplished with three 8-bit transfers. Not only does this shorten each conversion by four bits (25% faster throughput), but each conversion can actu-ally occur at a faster clock rate. This is because the internal settling time of the ADS7843 is not as critical —settling to better than 8 bits is all that is needed. The clock rate can be as much as 50% faster. The faster clock rate and fewer clock cycles combine to provide a 2x increase in conversion rate.POWER DISSIPATIONThere are two major power modes for the ADS7843: full power (PD1-PD0 = 11B ) and auto power-down (PD1-PD0 = 00B ).When operating at full speed and 16 clocks per conversion ( see Figure 6), the ADS7843 spends most of its time acquiring or converting. There is little time for auto power-down, assuming that this mode is active. Therefore, the difference between full power mode and auto power-down is negligible. If the conver-sion rate is decreased by simply slowing the frequency of the DCLK input, the two modes remain approximately equal. How-ever, if the DCLK frequency is kept at the maximum rate during a conversion but conversions are simply done less often, the difference between the two modes is dramatic.Figure 9 shows the difference between reducing the DCLK frequency (“scaling ” DCLK to match the conversion rate) or maintaining DCLK at the highest frequency and reducing the number of conversions per second. In the later case, the converter spends an increasing percentage of its time in power-down mode (assuming the auto power-down mode is active).Another important consideration for power dissipation is the reference mode of the converter. In the single-ended refer-ence mode, the converter ’s internal switches are on only when the analog input voltage is being acquired (see Figure 5). Thus, the external device, such as a resistive touch screen, is only powered during the acquisition period. In the differential reference mode, the external device must be powered throughout the acquisition and conversion periods (see Figure 5). If the conversion rate is high, this could substantially increase power dissipation.devices have fairly “clean ” power and grounds because most of the internal components are very low power. This situation would mean less bypassing for the converter ’s power and less concern regarding grounding. Still, each situation is unique and the following suggestions should be reviewed carefully.For optimum performance, care should be taken with the physical layout of the ADS7843 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Thus, during any single conversion for an ‘n-bit ’SAR converter, there are n ‘windows ’ in which large external transient voltages can easily affect the conversion result.Such glitches might originate from switching power supplies,nearby digital logic, and high-power devices. The degree of error in the digital output depends on the reference voltage,layout, and the exact timing of the external event. The error can change if the external event changes in time with respect to the DCLK input.With this in mind, power to the ADS7843 should be clean and well bypassed. A 0.1µF ceramic bypass capacitor should be placed as close to the device as possible. A 1µF to 10µF capacitor may also be needed if the impedance of the connection between +V CC and the power supply is high.The reference should be similarly bypassed with a 0.1µF capacitor. If the reference voltage originates from an op amp,make sure that it can drive the bypass capacitor without oscillation. The ADS7843 draws very little current from the reference on average, but it does place larger demands on the reference circuitry over short periods of time (on each rising edge of DCLK during a conversion).The ADS7843 architecture offers no inherent rejection of noise or voltage variation in regards to the reference input.This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high frequency noise can be filtered out, voltage variation due to line fre-quency (50Hz or 60Hz) can be difficult to remove.The GND pin should be connected to a clean ground point.In many cases, this will be the “analog ” ground. Avoid connections which are too near the grounding point of a microcontroller or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply entry or battery connection point. The ideal layout will include an analog ground plane dedicated to the converter and associated analog circuitry.In the specific case of use with a resistive touch screen, care should be taken with the connection between the converter and the touch screen. Since resistive touch screens have fairly low resistance, the interconnection should be as short and robust as possible. Longer connections will be a source of error, much like the on-resistance of the internal switches.Likewise, loose connections can be a source of error when the contact resistance changes with flexing or vibrations.FIGURE 9. Supply Current versus Directly Scaling the Fre-quency of DCLK with Sample Rate or Keeping DCLK at the Maximum Possible Frequency.LAYOUTThe following layout suggestions should provide the most optimum performance from the ADS7843. However, many portable applications have conflicting requirements concern-ing power, cost, size, and weight. In general, most portable元器件交易网。

触摸屏控制芯片ADS中文资料

触摸屏控制芯片ADS中文资料随着科技的日新月异，触摸屏已经成为我们生活中不可或缺的一部分。

而实现触摸屏功能的核心设备就是触摸屏控制芯片（Touch Screen Controller）。

其中，由美国德州仪器（Texas Instruments）公司出品的ADS触摸屏控制器，因其高效、稳定等特点广受好评。

本文将介绍关于ADS触摸屏控制芯片的中文资料，以帮助读者更好地了解和应用。

一、ADS触摸屏控制芯片的基本介绍ADS是DeTexAS（德州仪器）电容式触摸屏控制芯片，是一款高性能和低功耗的控制芯片，用于对电容式触摸屏的数据采集和处理。

其主要优点包括：1.高精度采集：ADS可以在高灵敏度、高准确度的状态下，快速采集有关电容式触摸屏各种触摸信息。

可支持4线、5线电阻式触摸屏以及电容式触摸屏。

2.强大的报告处理：ADS的报告率可达200Hz，符合市场上各种不同需求的触摸屏设备。

3.低功耗：ADS的低功耗设计可最大程度延长设备的电池续航能力。

除此之外，ADS还融入了多种先进的电路设计技术，如多点触控、自动进入低功耗模式、广泛的温度范围和高速传输技术，保证了它在功能方面的完备性以及出色的性能表现。

二、ADS触摸屏控制芯片的应用场景ADS广泛应用于智能手机、平板电脑、护航摄影、手持终端和医疗设备等领域，在其中扮演了非常重要的角色。

在智能手机和平板电脑市场，例如三星S6，华为P9和苹果iPhone，都采用了德州仪器的ADS控制器来实现更加完美的触摸体验。

同时，ADS还被广泛应用于工业自动化、家庭娱乐等领域。

三、ADS触摸屏控制芯片相关中文资料随着ADS触摸屏控制芯片的逐渐普及和应用，越来越多的人希望了解该芯片的相关资料。

以下是几种常见的中文资料：1. ADS芯片数据手册ADS芯片数据手册是一份详细的技术文档，可以提供ADS触摸屏控制芯片各项技术指标、功能及接口的详细描述。

此外，数据手册还包含了ADS的软件和硬件架构方案，以及使用提示和设计建议。

半导体传感器AD7683BRMZ中文规格书

AD7710PIN FUNCTION DESCRIPTIONSPin Mnemonic Function1SCLK Serial Clock. Logic input/output, depending on the status of the MODE pin. When MODE is high, the device is in its self-clocking mode, and the SCLK pin provides a serial clock output. This SCLK becomesactive when RFS or TFS goes low, and it goes high impedance when either RFS or TFS returns high or whenthe device has completed transmission of an output word. When MODE is low, the device is in its externalclocking mode, and the SCLK pin acts as an input. This input serial clock can be a continuous clock with alldata transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock with theinformation being transmitted to the AD7710 in smaller batches of data.2MCLK IN Master Clock Signal for the Device. This can be provided in the form of a crystal or external clock. A crystal can be tied across the MCLK IN and MCLK OUT pins. Alternatively, the MCLK IN pin can be driven witha CMOS compatible clock and MCLK OUT left unconnected. The clock input frequency is nominally 10MHz. 3MCLK OUT When the master clock for the device is a crystal, the crystal is connected between MCLK IN and MCLK OUT. 4A0Address Input. With this input low, reading and writing to the device is to the control register. With this input high, access is to either the data register or the calibration registers.5SYNC Logic Input. Allows for synchronization of the digital filters when using a number of AD7710s. It resets the nodes of the digital filter.6MODE Logic Input. When this pin is high, the device is in its self-clocking mode; with this pin low, the device is in its external clocking mode.7AIN1(+)Analog Input Channel 1. Positive input of the programmable gain differential analog input. The AIN1(+) input is connected to an output current source that can be used to check that an external transducer hasburned out or gone open circuit. This output current source can be turned on/off via the control register.8AIN1(–)Analog Input Channel 1. Negative input of the programmable gain differential analog input.9AIN2(+)Analog Input Channel 2. Positive input of the programmable gain differential analog input.10AIN2(–)Analog Input Channel 2. Negative input of the programmable gain differential analog input.11V SS Analog Negative Supply, 0 V to –5 V. Tied to AGND for single-supply operation. The input voltage on AIN1 or AIN2 should not go > 30 mV negative w.r.t. V SS for correct operation of the device.12AV DD Analog Positive Supply Voltage, 5 V to 10 V.13V BIAS Input Bias Voltage. This input voltage should be set such that V BIAS + 0.85 × V REF < AV DD and V BIAS –0.85 × V REF > V SS where V REF is REF IN(+) – REF IN(–). Ideally, this should be tied halfway betweenAV DD and V SS. Thus with AV DD = 5 V and V SS = 0 V, it can be tied to REF OUT; with AV DD = 5 Vand V SS = –5 V, it can be tied to AGND; with AV DD = 10 V, it can be tied to 5 V.14REF IN(–)Reference Input. The REF IN(–) can lie anywhere between AV DD and V SS provided REF IN(+) is greater than REF IN(–).15REF IN(+)Reference Input. The reference input is differential providing that REF IN(+) is greater than REF IN(–).REF IN(+) can lie anywhere between AV DD and V SS.16REF OUT Reference Output. The internal 2.5 V reference is provided at this pin. This is a single-ended output which is referred to AGND. It is a buffered output which is capable of providing 1 mA to an external load.17I OUT Compensation Current Output. A 20 µA constant current is provided at this pin. This current can be used in association with an external thermistor to provide cold junction compensation in thermocouple applications.This current can be turned on or off via the control register.18AGND Ground Reference Point for Analog Circuitry.REV. G–7–AD7710Pin Mnemonic Function19TFS Transmit Frame Synchronization. Active low logic input used to write serial data to the device with serial data expected after the falling edge of this pulse. In the self-clocking mode, the serial clock becomes active afterTFS goes low. In the external clocking mode, TFS must go low before the first bit of the data-word is writtento the part.20RFS Receive Frame Synchronization. Active low logic input used to access serial data from the device. In the self-clocking mode, the SCLK and SDATA lines both become active after RFS goes low. In the externalclocking mode, the SDATA line becomes active after RFS goes low.21DRDY Logic Output. A falling edge indicates that a new output word is available for transmission. The DRDY pin will return high upon completion of transmission of a full output word. DRDY is also used to indicate whenthe AD7710 has completed its on-chip calibration sequence.22SDATA Serial Data. Input/output with serial data being written to either the control register or the calibration regis-ters, and serial data being accessed from the control register, calibration registers, or the data register.During an output data read operation, serial data becomes active after RFS goes low (provided DRDY is low).During a write operation, valid serial data is expected on the rising edges of SCLK when TFS is low. Theoutput data coding is natural binary for unipolar inputs and offset binary for bipolar inputs.23DV DD Digital Supply Voltage, 5 V. DV DD should not exceed AV DD by more than 0.3 V in normal operation.24DGND Ground Reference Point for Digital Circuitry.Terminology Integral NonlinearityThis is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale (not to be con-fused with bipolar zero), a point 0.5 LSB below the first code transition (000 . . . 000 to 000 . . . 001) and full scale, a point 0.5LSB above the last code transition (111 . . . 110 to 111 . . . 111). The error is expressed as a percentage of full scale. Positive Full-Scale ErrorPositive full-scale error is the deviation of the last code transi-tion (111 . . . 110 to 111 . . . 111) from the ideal AIN(+) voltage (AIN(–) + V REF/GAIN – 3/2 LSBs). It applies to both unipolar and bipolar analog input ranges.Unipolar Offset ErrorUnipolar offset error is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) + 0.5 LSB) when oper-ating in the unipolar mode.Bipolar Zero ErrorThis is the deviation of the midscale transition (0111 . . . 111 to 1000 . . . 000) from the ideal AIN(+) voltage (AIN(–) – 0.5LSB) when operating in the bipolar mode.Bipolar Negative Full-Scale ErrorThis is the deviation of the first code transition from the ideal AIN(+) voltage (AIN(–) – V REF/GAIN + 0.5 LSB) when operat-ing in the bipolar mode.Positive Full-Scale OverrangePositive full-scale overrange is the amount of overhead available to handle input voltages on AIN(+) input greater than AIN(–) + V REF/GAIN (for example, noise peaks or excess voltages due to system gain errors in system calibration routines) without intro-ducing errors due to overloading the analog modulator or tooverflowing the digital filter.Negative Full-Scale OverrangeThis is the amount of overhead available to handle voltages onAIN(+) below AIN(–) –V REF/GAIN without overloading theanalog modulator or overflowing the digital filter. Note that the analog input will accept negative voltage peaks even in the uni-polar mode provided that AIN(+) is greater than AIN(–) andgreater than V SS – 30mV.Offset Calibration RangeIn the system calibration modes, the AD7710 calibrates its offset with respect to the analog input. The offset calibration rangespecification defines the range of voltages that the AD7710 can accept and still calibrate offset accurately.Full-Scale Calibration RangeThis is the range of voltages that the AD7710 can accept in the system calibration mode and still calibrate full scale correctly.Input SpanIn system calibration schemes, two voltages applied in sequence to the AD7710’s analog input define the analog input range.The input span specification defines the minimum and maxi-mum input voltages from zero- to full-scale that the AD7710 can accept and still calibrate gain accurately.REV. G –8–。

dsp与触摸屏

DSP芯片与触摸屏的接口控制摘要：简述了液晶触摸屏控制产品的工作原理以及用于触摸屏控制的专用芯片ADS7843的工作原理。

无线数字扩频通信平台是无线扩频通信的一种开放式平台，在此基础上增加液晶触摸屏控制，可实现文字和图形的编辑和无线传送，使该产品用途更加广泛。

关键词：电阻式触摸屏 DSP ADS7843以DSP (数字信号处理)芯片和FPGA(现场可编程逻辑门阵列)为核心的无线数字扩频通信平台是无线扩频通信的一个开放式平台，可用于无线接入、无线图像和音频传送、移动INTERNET、精确区域定位LPS、智能遥控探测等高科技领域。

我们在此基础上增加了液晶显示和触摸屏控制，从而实现文字和图形信息的编辑和无线传送，使该产品用途更加广泛。

ADS7843是专用于4线电阻式触摸屏的12位模/数采样转换器，具有单一电源供电、完全降功耗模式、转换速度快的特点。

ADS7843大量用在电池供电PDA(Personal Digital Assistants和手持便携式装置中。

1 液晶触摸屏控制产品设计简介液晶采用Microtips Technology Inc．公司的型号为MTG－32240X的中小规模液晶显示器(图形方式为3 20x240点)。

触摸屏控制器采用香港BURR－BROWN公司的 ADS7843。

对FPGA进行逻辑编程可实现液晶显示控制器的功能。

用FPGA定时中断DSP(约占DSP工作时间的5%)获取外部RAM的显示数据，然后FPGA 内部逻辑将显示数据送到液晶屏上进行显示。

DSP对触摸屏的转换信号进行处理和计算以及完成各种文字和图形的编辑任务，然后将需要显示的数据送入显示缓冲区(外部数据RAM)。

也就是说，用DSP和FP GA来控制液晶的显示和文字、图形信息的编辑处理，并能接收触摸屏信号，从而实现笔输入掌上电脑的功能。

再结合无线数字扩频通信平台就能实现文字和图形信息的无线传送。

该产品能用于记者在通讯不便的现场进行文字和图形的实时编辑和采访报道以及在移动过程中需要进行文字和图形信息无线传送的地方。

四线电阻式触摸屏接口技术

--电容式触摸屏,无需压力 --精度好，无需校准 --屏幕强度高，不易损坏 2023年6月:苹果推出iPhone电容式全屏多点触摸手机 --免触笔无按键全屏触摸令世人惊艳 --进入从单点到多点触摸旳新时代近期，微软正式推出旳Windows 7带起PC市场多点触摸旳需求，并联合多家 PC业者推出多点触摸台式计算机及笔记本电脑。
红外式触摸屏
简朴简介：红外式触摸屏以光束阻断技术为基本原理，构造非常简朴，在屏幕前框架旳左边（Y轴）和下边（X轴）分别装有红外发射管，各自旳对边又装有相应旳接受管，进而形成一种横竖交叉旳红外线网。管旳排列密度与其辨别率有关。工作时在屏幕前形成纵横交叉旳红外线矩阵，只有有物体触摸屏上任何一点时，便会阻挡该位置旳红外线，控制器即时算出触摸点旳位置坐标。
表面声波触摸屏
简朴简介：
表面声波触摸屏旳触摸屏部分能够是一块平面、球面或是柱面旳玻璃平板，安装在CRT、LED、LCD或是等离子显示屏屏幕旳前面。玻璃屏旳左上角和右下角各固定了竖直和水平方向旳超声波发射换能器，右上角则固定了两个相应旳超声波接受换能器。玻璃屏旳四个周围则刻有45°角由疏到密间隔非常精密旳反射条纹。
四线制电阻触摸屏
四线电阻式触摸屏旳应用性能：（1）.耐用性不够，长时间旳触按施压会使器件损坏。因为每次触按，上层旳PET和ITO都会发生形变，而ITO材质较脆，在形变经常发生时轻易损坏。一旦ITO层断裂，导电旳均匀性也就被破坏，上面推导坐标时旳百分比等效性也就不再存在，所以四线电阻触摸屏旳寿命不长。（2）.四线式旳触控面板因成本及技术层面较为成熟等原因，几乎是全部触控面板业者最基本旳生产规格，合用于有固定顾客旳公共场合，如工业控制现场、办公室、家庭等。所以，以电阻式旳技术来说，四线式旳规格约占了50％以上旳市场拥有率。

基于ILI9320和ADS7843的触摸显示屏控制系统设计

基于ILI9320和ADS7843的触摸显示屏控制系统设计陈章宝;邓运生【摘要】Medium and small touch and display screen was widely used in portable network terminal,and it gave the design in this paper of 2.8 inch TFT-LCD touch and display screen module,design of circuit withSTC12C5A60S2 as main chip,system includes display screen and touch screen interface circuit,FPC interface circuit,SD card interface circuit,and the driving program and application program design method were given.The experimental results showed that the system is stable and all the functions are realized.%结合中小型触摸显示屏在手持式网络终端中的广泛应用,给出了一种2.8寸TFT-LCD触摸显示屏模块的设计方法,以STC12C5A60S2为主控芯片,包括显示屏和触摸屏接口电路、FPC接口电路、SD卡接口电路等,给出驱动程序及其应用程序的设计方法.实验结果表明,系统运行稳定,能够实现模块的全部功能.【期刊名称】《蚌埠学院学报》【年(卷),期】2017(006)002【总页数】5页(P12-16)【关键词】显示触摸屏;薄膜场效应晶体管显示器;驱动程序【作者】陈章宝;邓运生【作者单位】蚌埠学院电子与电气工程学院,安徽蚌埠 233030;蚌埠学院电子与电气工程学院,安徽蚌埠 233030【正文语种】中文【中图分类】TP274随着电子信息技术的发展，平面显示技术被广泛应用于日常的生产和生活当中，而液晶显示(LCD：Liquid Crystal Display)器件由于具有功耗低、重量轻、价格低以及优越的字符和图形显示功能，在智能仪器仪表、手持网络设备、物联网终端设备中得到了广泛的应用。

基于LPC2478与ADS7843的电阻触摸屏设计方案

基于LPC2478与ADS7843的电阻触摸屏设计方案触摸屏具有坚固耐用、反应速度快、节省空间、易于交流等许多优点，相比键盘输入，触摸屏技术更简单、直观、快捷，且具有丰富多彩的表现能力。

设计触摸屏时，最重要的问题是准确定位触摸点的坐标位置。

本文详细介绍了利用工业级芯片LPC2478 与ADS7843 设计四线电阻触摸屏的实际方案。

1 硬件设计1．1 硬件选择LPC2478 芯片内部集成了LCD 接口，它的工作范围为-40～+80℃，其宽温的特点特别适合工业领域。

ADS7843 芯片是一款专为触摸采样设计的芯片，12 位可编程精度。

外部参考电压范围从1V～Vcc 均可，Vcc 最高电压为5 V，高速低功耗使得ADS7843 非常适用于电阻触摸屏的手持设备。

1．2 硬件电路笔者设计了ADS7843 的硬件接口电路(如图1 所示)。

该电路中采取了利用LPC2478 的GPIO 管脚模拟SPI 时序的方式，将DCLK，CS，DIN，BUS-Y，DOUT 接到LPC2478 的5 个GPIO 引脚上。

将ADS7843 的引脚接到LPC2478 的中断1 上的方式。

采用的四线电阻触摸屏，分别接到ADS7843 的X+，Y+，X-，Y-引脚上。

1．3 采集方式ADS7843 有2 种参考电压模式：单端模式和差分模式。

在单端模式中，参考输入电压选取的是Vcc 和GND。

由于内部的开关电阻压降影响转换结果带来误差，所以转换器内部的低阻开关对转换精度有一定影响。

差分模式参考输入由未选中的输入通道Y+，Y-，X+，X-提供参考电源和地。

不管内部开关电阻如何变化，其转换结果总与触摸屏的电阻成比例，克服了内部开关电阻的影响，但当转换频率很高时则增加了功耗，需要考虑低功耗设计。

笔者基于采样精度的原因在程序中采用了差分方式。

ADS7843 的引脚是一个PIN 中断引脚，在触摸显示屏时可产生一个低电平，触发LPC2478 的中断，采。